[llvm] [TableGen][SchedModel] Add repeat rate to block buffered resources (PR #202775)

[Jay Foad via llvm-commits]

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@@ -548,6 +600,177 @@ def : HWWriteRes<WriteVALUDummy, [HWVALU],  5>;
 def : HWWriteRes<WriteSALUDummy, [HWSALU],  2>;
 }
 
+// VALU RepeatRate = 2 instructions
+// F32 transcendentals
+def : InstRW<[Trans32Repeat2], (instregex "^V_EXP_F32_e(32|64)$",
+                                          "^V_LOG_F32_e(32|64)$",
+                                          "^V_RCP_F32_e(32|64)$",
+                                          "^V_RCP_IFLAG_F32_e(32|64)$",
+                                          "^V_RSQ_F32_e(32|64)$",
+                                          "^V_SQRT_F32_e(32|64)$",
+                                          "^V_SIN_F32_e(32|64)$",
+                                          "^V_COS_F32_e(32|64)$")>;
+// BF16 transcendentals
+def : InstRW<[Trans32Repeat2], (instregex "^V_EXP_BF16_e(32|64)$",
+                                          "^V_LOG_BF16_e(32|64)$",
+                                          "^V_RCP_BF16_e(32|64)$",
+                                          "^V_RSQ_BF16_e(32|64)$",
+                                          "^V_SQRT_BF16_e(32|64)$",
+                                          "^V_SIN_BF16_e(32|64)$",
+                                          "^V_COS_BF16_e(32|64)$")>;
+// F16 transcendentals
+def : InstRW<[Trans32Repeat2], (instregex "^V_EXP_F16_e(32|64)$",
+                                          "^V_LOG_F16_e(32|64)$",
+                                          "^V_RCP_F16_e(32|64)$",
+                                          "^V_RSQ_F16_e(32|64)$",
+                                          "^V_SQRT_F16_e(32|64)$",
+                                          "^V_SIN_F16_e(32|64)$",
+                                          "^V_COS_F16_e(32|64)$")>;
+// TANH instructions
+def : InstRW<[Trans32Repeat2], (instregex "^V_TANH_BF16_e(32|64)$",
+                                          "^V_TANH_F16_e(32|64)$",
+                                          "^V_TANH_F32_e(32|64)$")>;
+// 64-bit shifts and moves
+def : InstRW<[Write64BitRepeat2], (instregex "^V_LSHLREV_B64_e64$",
+                                             "^V_LSHRREV_B64_e64$",
+                                             "^V_ASHRREV_I64_e64$",
+                                             "^V_MOV_B64_e(32|64)$",
+                                             "^V_TRIG_PREOP_F64_e64$")>;
+
+def : InstRW<[Write32BitRepeat2],  (instregex "^V_LSHL_ADD_U64_e64$")>;
+
+// 64-bit integer comparisons
+def : InstRW<[Write64BitRepeat2], (instregex "^V_CMP_EQ_I64_e(32|64)$",
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jayfoad wrote:

It's a regex so you don't need to list all the comparison predicates explicitly.

https://github.com/llvm/llvm-project/pull/202775