[llvm] [RISCV] Fix incorrect fixed vector lowering for VECTOR_DEINTERLEAVE (PR #207254)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 2 12:00:47 PDT 2026
https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/207254
Partially address #207136
Previously this part of the logic simply converts each operand into scalable vector and pass on. This will run into problem when the scalable vector container is larger than the actual fixed vector.
This patch fixes this issue by (1) concat each fixed vector operands into a larger, legal fixed vector, then (2) turn it into a scalable vector before extracting the (scalable) sub-vectors as operands for the new VECTOR_DEINTERLEAVE.
-----
Since we don't run DAGCombiner right after this legalization, we will have code like this, generated by the new approach, hanging around
```
t2: nxv1i32,ch = CopyFromReg t0, Register:nxv1i32 %0
t4: v16i32 = extract_subvector t2, Constant:i64<0>
t49: v4i32 = extract_subvector t4, Constant:i64<8>
t47: v4i32 = extract_subvector t4, Constant:i64<4>
t23: v4i32 = extract_subvector t4, Constant:i64<0>
t66: v16i32 = concat_vectors t23, t47, t49, undef:v4i32
t67: nxv1i32 = insert_subvector undef:nxv1i32, t66, Constant:i64<0>
t68: nxv1i32,nxv1i32,nxv1i32 = vector_deinterleave t67, undef:nxv1i32, undef:nxv1i32
```
before some of the extract/insert_subvector got turned into vslideup/down prematurely. Which is likely where all the uglier codegen in this patch came from.
I think we could either do some simple combine when legalizing CONCAT_VECTORS, or write some `RISCVISD::VSLIDEDOWN_VL` / `RISCVISD::VSLIDEUP_VL` aware combine rules.
>From 856f926b7e2c1025bc40d6cb641e1f13421da72a Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Wed, 1 Jul 2026 19:38:25 -0700
Subject: [PATCH] [RISCV] Fix incorrect fixed vector lowering for
VECTOR_DEINTERLEAVE
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 96 ++++-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 405 ++++++++++--------
2 files changed, 314 insertions(+), 187 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 23497ac58ba46..6083b72dd8531 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13123,25 +13123,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
if (VecVT.getVectorElementType() == MVT::i1)
return widenVectorOpsToi8(Op, DL, DAG);
- // Convert to scalable vectors first.
- if (VecVT.isFixedLengthVector()) {
- MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
- SmallVector<SDValue, 8> Ops(Factor);
- for (unsigned i = 0U; i < Factor; ++i)
- Ops[i] = convertToScalableVector(ContainerVT, Op.getOperand(i), DAG,
- Subtarget);
-
- SmallVector<EVT, 8> VTs(Factor, ContainerVT);
- SDValue NewDeinterleave =
- DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, VTs, Ops);
-
- SmallVector<SDValue, 8> Res(Factor);
- for (unsigned i = 0U; i < Factor; ++i)
- Res[i] = convertFromScalableVector(VecVT, NewDeinterleave.getValue(i),
- DAG, Subtarget);
- return DAG.getMergeValues(Res, DL);
- }
-
// If concatenating would exceed LMUL=8, we need to split.
if ((VecVT.getSizeInBits().getKnownMinValue() * Factor) >
(8 * RISCV::RVVBitsPerBlock)) {
@@ -13167,6 +13148,83 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
return DAG.getMergeValues(Res, DL);
}
+ // Convert to scalable vectors.
+ if (VecVT.isFixedLengthVector()) {
+ ElementCount OrigEC = VecVT.getVectorElementCount();
+ // Note that we cannot just convert individual operands to scalable vectors
+ // and call it a day: as scalable vector container is always equal or
+ // larger than the fixed vector subject, in the case where it is larger
+ // than fixed vector, this approach will create "padded" lanes in the
+ // conceptually concated vector created by VECTOR_DEINTERLEAVE per its
+ // semantics.
+
+ // First, concat operands into a larger (fixed) vector.
+ // There are two ways to do this: insert each operands into a larger
+ // (legal) vector one by one, or concat_vectors with additional
+ // operands to pad to legal type. The first way seems to lead to
+ // worse codegen primarily because we don't run DAGCombiner to
+ // simplify stuffs before some of the insert_subvector got
+ // lower into vslideup/down prematurely.
+ EVT ConcatVecEVT = EVT(VecVT).changeVectorElementCount(
+ *DAG.getContext(), OrigEC.multiplyCoefficientBy(Factor));
+ SmallVector<SDValue, 8> ConcatOps(Op->op_begin(), Op->op_end());
+ MVT ConcatVecVT;
+ if (!isTypeLegal(ConcatVecEVT)) {
+ // SplitVector should already be handled above.
+ assert(getTypeAction(*DAG.getContext(), ConcatVecEVT) ==
+ TargetLowering::TypeWidenVector);
+ ConcatVecVT =
+ getTypeToTransformTo(*DAG.getContext(), ConcatVecEVT).getSimpleVT();
+ ElementCount WidenedConcatEC = ConcatVecVT.getVectorElementCount();
+ // Both OrigEC and WidenedConcatEC are both derived from legal fixed
+ // vector types. A legal fixed vector's element count is always power of
+ // two, so WidenedConcatEC will always be a multiple of OrigEC.
+ assert(WidenedConcatEC.hasKnownScalarFactor(OrigEC));
+ unsigned NumTotalConcatOps = WidenedConcatEC.getKnownScalarFactor(OrigEC);
+ assert(NumTotalConcatOps > Factor);
+ ConcatOps.append(NumTotalConcatOps - Factor, DAG.getUNDEF(VecVT));
+ } else {
+ ConcatVecVT = ConcatVecEVT.getSimpleVT();
+ }
+
+ SDValue ConcatVec =
+ DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVecVT, ConcatOps);
+ MVT ConcatContainerVT = getContainerForFixedLengthVector(ConcatVecVT);
+ ElementCount ConcatContainerEC = ConcatContainerVT.getVectorElementCount();
+ ConcatVec =
+ convertToScalableVector(ConcatContainerVT, ConcatVec, DAG, Subtarget);
+
+ MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
+ ElementCount ContainerEC = ContainerVT.getVectorElementCount();
+
+ SmallVector<SDValue, 8> Ops(Factor);
+ // Then, we extract the new scalable sub-vectors.
+ for (unsigned i = 0U; i < Factor; ++i) {
+ ElementCount Idx = ContainerEC.multiplyCoefficientBy(i);
+ // Index might be out-of-bound. This usually happens on large
+ // VLEN where a single or a few VR registers is enough to caputre
+ // the entire concat vector. In this case we can just use poison
+ // on other VECTOR_DEINTERLEAVE operands -- semantically
+ // VECTOR_DEINTERLEAVE will just concat them back together later
+ // anyway.
+ if (ElementCount::isKnownGE(Idx, ConcatContainerEC))
+ Ops[i] = DAG.getUNDEF(ContainerVT);
+ else
+ Ops[i] = DAG.getExtractSubvector(DL, ContainerVT, ConcatVec,
+ Idx.getKnownMinValue());
+ }
+
+ SmallVector<EVT, 8> VTs(Factor, ContainerVT);
+ SDValue NewDeinterleave =
+ DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, VTs, Ops);
+
+ SmallVector<SDValue, 8> Res(Factor);
+ for (unsigned i = 0U; i < Factor; ++i)
+ Res[i] = convertFromScalableVector(VecVT, NewDeinterleave.getValue(i),
+ DAG, Subtarget);
+ return DAG.getMergeValues(Res, DL);
+ }
+
if (Subtarget.hasStdExtZvzip() && Factor == 2) {
MVT VT = Op->getSimpleValueType(0);
MVT NewVT = VT.getDoubleNumVectorElementsVT();
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 07fb8675d85e8..5236e5eea4c60 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -190,11 +190,15 @@ define {<2 x i32>, <2 x i32>, <2 x i32>} @vector_deinterleave3_v2i32_v6i32(<6 x
; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 2
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 2
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a0
-; CHECK-NEXT: vmv1r.v v9, v10
+; CHECK-NEXT: vslidedown.vx v10, v8, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -217,12 +221,15 @@ define {<3 x i32>, <3 x i32>, <3 x i32>} @vector_deinterleave3_v3i32_v9i32(<9 x
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v8, 8
+; CHECK-NEXT: vmv2r.v v16, v8
; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 4
-; CHECK-NEXT: vmv1r.v v9, v10
-; CHECK-NEXT: vmv2r.v v10, v12
+; CHECK-NEXT: vslidedown.vi v8, v8, 4
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v16, v8, 4
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vslideup.vi v16, v12, 8
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs4r.v v8, (a0)
+; CHECK-NEXT: vs4r.v v16, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vlseg3e32.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -241,17 +248,6 @@ define {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @vector_deinterleave4_v2i32_
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 6
-; CHECK-NEXT: vslidedown.vi v12, v8, 4
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 2
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v12, v10, a0
-; CHECK-NEXT: vslideup.vx v8, v9, a0
-; CHECK-NEXT: vmv.v.v v9, v12
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -273,20 +269,31 @@ define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @vector_deinterle
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 8
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 6
-; CHECK-NEXT: vslidedown.vi v11, v8, 4
-; CHECK-NEXT: vslidedown.vi v12, v8, 2
+; CHECK-NEXT: vslidedown.vi v12, v8, 4
+; CHECK-NEXT: vslidedown.vi v13, v8, 2
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v9, 2
+; CHECK-NEXT: vslideup.vi v8, v13, 2
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 4
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: srli a1, a0, 3
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vslidedown.vx v11, v8, a0
+; CHECK-NEXT: vslidedown.vx v12, v8, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
+; CHECK-NEXT: vslideup.vx v11, v10, a1
; CHECK-NEXT: vslideup.vx v8, v12, a1
-; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vmv1r.v v9, v10
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -308,7 +315,6 @@ define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @vecto
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 10
; CHECK-NEXT: vslidedown.vi v12, v8, 8
@@ -316,14 +322,30 @@ define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @vecto
; CHECK-NEXT: vslidedown.vi v9, v8, 6
; CHECK-NEXT: vslidedown.vi v11, v8, 4
; CHECK-NEXT: vslidedown.vi v13, v8, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
-; CHECK-NEXT: vslideup.vx v8, v13, a1
-; CHECK-NEXT: vslideup.vx v12, v10, a1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v11, v9, 2
+; CHECK-NEXT: vslideup.vi v8, v13, 2
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v11, 4
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 8
+; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vslidedown.vx v11, v8, a0
+; CHECK-NEXT: vslidedown.vx v12, v8, a1
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v11, v10, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vmv1r.v v9, v12
+; CHECK-NEXT: vslidedown.vx v10, v9, a1
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v10, a1
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -352,22 +374,42 @@ define {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} @v
; CHECK-NEXT: vslidedown.vi v13, v8, 4
; CHECK-NEXT: vmv1r.v v14, v8
; CHECK-NEXT: vslidedown.vi v8, v8, 6
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: srli a2, a0, 3
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vx v14, v12, a2
-; CHECK-NEXT: add a3, a1, a2
-; CHECK-NEXT: vslideup.vx v10, v9, a2
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v14, v12, 2
+; CHECK-NEXT: vslideup.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v14, v13, 4
+; CHECK-NEXT: vslideup.vi v10, v11, 4
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v14, v8, 6
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v14, v10, 8
+; CHECK-NEXT: srli a1, a0, 3
+; CHECK-NEXT: srli a2, a0, 1
+; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v8, v14, a3
+; CHECK-NEXT: vslidedown.vx v9, v14, a2
+; CHECK-NEXT: srli a3, a0, 2
+; CHECK-NEXT: sub a0, a0, a3
+; CHECK-NEXT: vslidedown.vx v10, v14, a0
+; CHECK-NEXT: vslidedown.vx v11, v14, a1
+; CHECK-NEXT: vslidedown.vx v12, v14, a3
+; CHECK-NEXT: add a0, a3, a1
+; CHECK-NEXT: vmv1r.v v13, v14
+; CHECK-NEXT: vslidedown.vx v14, v14, a0
; CHECK-NEXT: vsetvli zero, a3, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vx v14, v13, a1
-; CHECK-NEXT: vslideup.vx v10, v11, a1
+; CHECK-NEXT: vslideup.vx v13, v11, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; CHECK-NEXT: vslideup.vx v13, v12, a3
+; CHECK-NEXT: vslideup.vx v9, v10, a3
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v14, v8, a3
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v14, v10, a0
+; CHECK-NEXT: vslideup.vx v13, v14, a0
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v13, v9, a2
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs1r.v v14, (a0)
+; CHECK-NEXT: vs1r.v v13, (a0)
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vlseg7e8.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -384,30 +426,6 @@ define {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 10
-; CHECK-NEXT: vslidedown.vi v10, v8, 8
-; CHECK-NEXT: vslidedown.vi v11, v8, 12
-; CHECK-NEXT: vslidedown.vi v12, v8, 14
-; CHECK-NEXT: vslidedown.vi v13, v8, 2
-; CHECK-NEXT: vslidedown.vi v14, v8, 4
-; CHECK-NEXT: vslidedown.vi v15, v8, 6
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: srli a2, a0, 3
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vx v10, v9, a2
-; CHECK-NEXT: vslideup.vx v8, v13, a2
-; CHECK-NEXT: add a2, a1, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vx v10, v11, a1
-; CHECK-NEXT: vslideup.vx v8, v14, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v12, a2
-; CHECK-NEXT: vslideup.vx v8, v15, a2
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
@@ -605,11 +623,15 @@ define {<2 x float>, <2 x float>, <2 x float>} @vector_deinterleave3_v6f32_v2f32
; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 2
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v9, 2
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a0
-; CHECK-NEXT: vmv1r.v v9, v10
+; CHECK-NEXT: vslidedown.vx v10, v8, a0
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -634,17 +656,6 @@ define {<2 x float>, <2 x float>, <2 x float>, <2 x float>} @vector_deinterleave
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
-; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 6
-; CHECK-NEXT: vslidedown.vi v12, v8, 4
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 2
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v12, v10, a0
-; CHECK-NEXT: vslideup.vx v8, v9, a0
-; CHECK-NEXT: vmv.v.v v9, v12
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -670,20 +681,31 @@ define {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} @vector_dein
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 8
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 6
-; CHECK-NEXT: vslidedown.vi v11, v8, 4
-; CHECK-NEXT: vslidedown.vi v12, v8, 2
+; CHECK-NEXT: vslidedown.vi v12, v8, 4
+; CHECK-NEXT: vslidedown.vi v13, v8, 2
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v9, 2
+; CHECK-NEXT: vslideup.vi v8, v13, 2
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 4
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: srli a1, a0, 3
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vslidedown.vx v11, v8, a0
+; CHECK-NEXT: vslidedown.vx v12, v8, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
+; CHECK-NEXT: vslideup.vx v11, v10, a1
; CHECK-NEXT: vslideup.vx v8, v12, a1
-; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vmv1r.v v9, v10
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -709,20 +731,31 @@ define {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>} @v
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 8
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 6
-; CHECK-NEXT: vslidedown.vi v11, v8, 4
-; CHECK-NEXT: vslidedown.vi v12, v8, 2
+; CHECK-NEXT: vslidedown.vi v12, v8, 4
+; CHECK-NEXT: vslidedown.vi v13, v8, 2
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v9, 2
+; CHECK-NEXT: vslideup.vi v8, v13, 2
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 4
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: srli a1, a0, 3
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vslidedown.vx v11, v8, a0
+; CHECK-NEXT: vslidedown.vx v12, v8, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
+; CHECK-NEXT: vslideup.vx v11, v10, a1
; CHECK-NEXT: vslideup.vx v8, v12, a1
-; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vmv1r.v v9, v10
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -748,7 +781,6 @@ define {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>}
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 10
; CHECK-NEXT: vslidedown.vi v12, v8, 8
@@ -756,14 +788,30 @@ define {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>}
; CHECK-NEXT: vslidedown.vi v9, v8, 6
; CHECK-NEXT: vslidedown.vi v11, v8, 4
; CHECK-NEXT: vslidedown.vi v13, v8, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
-; CHECK-NEXT: vslideup.vx v8, v13, a1
-; CHECK-NEXT: vslideup.vx v12, v10, a1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v11, v9, 2
+; CHECK-NEXT: vslideup.vi v8, v13, 2
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v11, 4
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 8
+; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vslidedown.vx v11, v8, a0
+; CHECK-NEXT: vslidedown.vx v12, v8, a1
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v11, v10, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vmv1r.v v9, v12
+; CHECK-NEXT: vslidedown.vx v10, v9, a1
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v10, a1
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -789,7 +837,6 @@ define {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 10
; CHECK-NEXT: vslidedown.vi v12, v8, 8
@@ -797,14 +844,30 @@ define {<2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2 x bfloat>, <2
; CHECK-NEXT: vslidedown.vi v9, v8, 6
; CHECK-NEXT: vslidedown.vi v11, v8, 4
; CHECK-NEXT: vslidedown.vi v13, v8, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
-; CHECK-NEXT: vslideup.vx v8, v13, a1
-; CHECK-NEXT: vslideup.vx v12, v10, a1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v11, v9, 2
+; CHECK-NEXT: vslideup.vi v8, v13, 2
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v11, 4
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v12, 8
+; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vslidedown.vx v11, v8, a0
+; CHECK-NEXT: vslidedown.vx v12, v8, a1
+; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v11, v10, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v8, v11, a0
-; CHECK-NEXT: vmv1r.v v9, v12
+; CHECK-NEXT: vslidedown.vx v10, v9, a1
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v10, a1
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -830,25 +893,36 @@ define {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>,
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 3
-; CHECK-NEXT: vslidedown.vi v11, v8, 2
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vslidedown.vi v12, v8, 1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
-; CHECK-NEXT: vslideup.vx v10, v12, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 5
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vslideup.vx v10, v11, a0
; CHECK-NEXT: vslidedown.vi v11, v8, 4
+; CHECK-NEXT: vslidedown.vi v12, v8, 6
+; CHECK-NEXT: vslidedown.vi v13, v8, 1
+; CHECK-NEXT: vslidedown.vi v14, v8, 2
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vslidedown.vi v8, v8, 3
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v10, v13, 1
+; CHECK-NEXT: vslideup.vi v11, v9, 1
+; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v10, v14, 2
+; CHECK-NEXT: vslideup.vi v11, v12, 2
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 3
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v11, 4
+; CHECK-NEXT: srli a1, a0, 3
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v8, v10, a2
+; CHECK-NEXT: vslidedown.vx v9, v10, a0
+; CHECK-NEXT: vslidedown.vx v11, v10, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vslideup.vx v10, v11, a1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v8, 6
-; CHECK-NEXT: vslideup.vx v11, v8, a0
+; CHECK-NEXT: vslideup.vx v10, v9, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v10, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -874,25 +948,36 @@ define {<1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 3
-; CHECK-NEXT: vslidedown.vi v11, v8, 2
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vslidedown.vi v12, v8, 1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
-; CHECK-NEXT: vslideup.vx v10, v12, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 5
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vslideup.vx v10, v11, a0
; CHECK-NEXT: vslidedown.vi v11, v8, 4
+; CHECK-NEXT: vslidedown.vi v12, v8, 6
+; CHECK-NEXT: vslidedown.vi v13, v8, 1
+; CHECK-NEXT: vslidedown.vi v14, v8, 2
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vslidedown.vi v8, v8, 3
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v10, v13, 1
+; CHECK-NEXT: vslideup.vi v11, v9, 1
+; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; CHECK-NEXT: vslideup.vi v10, v14, 2
+; CHECK-NEXT: vslideup.vi v11, v12, 2
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 3
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v11, 4
+; CHECK-NEXT: srli a1, a0, 3
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v8, v10, a2
+; CHECK-NEXT: vslidedown.vx v9, v10, a0
+; CHECK-NEXT: vslidedown.vx v11, v10, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v9, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vslideup.vx v10, v11, a1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v8, 6
-; CHECK-NEXT: vslideup.vx v11, v8, a0
+; CHECK-NEXT: vslideup.vx v10, v9, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v10, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -918,26 +1003,18 @@ define {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>,
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 7
-; CHECK-NEXT: vslidedown.vi v11, v8, 6
-; CHECK-NEXT: vslidedown.vi v12, v8, 5
-; CHECK-NEXT: vslidedown.vi v9, v8, 4
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v10, a1
-; CHECK-NEXT: vslideup.vx v9, v12, a1
-; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v11, a0
-; CHECK-NEXT: vslidedown.vi v10, v8, 3
-; CHECK-NEXT: vslidedown.vi v11, v8, 2
-; CHECK-NEXT: vslidedown.vi v12, v8, 1
+; CHECK-NEXT: vslidedown.vx v9, v8, a1
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: add a2, a1, a0
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vslidedown.vx v11, v8, a0
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v10, a1
-; CHECK-NEXT: vslideup.vx v8, v12, a1
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v10, a0
; CHECK-NEXT: vslideup.vx v8, v11, a0
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
@@ -963,26 +1040,18 @@ define {<1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1 x bfloat>, <1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a1, a0, 3
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 7
-; CHECK-NEXT: vslidedown.vi v11, v8, 6
-; CHECK-NEXT: vslidedown.vi v12, v8, 5
-; CHECK-NEXT: vslidedown.vi v9, v8, 4
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v10, a1
-; CHECK-NEXT: vslideup.vx v9, v12, a1
-; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v11, a0
-; CHECK-NEXT: vslidedown.vi v10, v8, 3
-; CHECK-NEXT: vslidedown.vi v11, v8, 2
-; CHECK-NEXT: vslidedown.vi v12, v8, 1
+; CHECK-NEXT: vslidedown.vx v9, v8, a1
+; CHECK-NEXT: srli a0, a0, 3
+; CHECK-NEXT: add a2, a1, a0
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vslidedown.vx v11, v8, a0
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v11, v10, a1
-; CHECK-NEXT: vslideup.vx v8, v12, a1
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v10, a0
; CHECK-NEXT: vslideup.vx v8, v11, a0
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs2r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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