[llvm] [InstCombine] Simplify (A >= 0) & ((A & INT_MAX) != 0) to A > 0 (PR #207209)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 2 11:56:08 PDT 2026
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/207209
>From c4f3ea5ac54aa2c1fdb21a7b718c4fc9ef0e9ef9 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 2 Jul 2026 11:28:17 -0400
Subject: [PATCH 1/6] [InstCombine] Precommit tests for PR112390
---
llvm/test/Transforms/InstCombine/pr112390.ll | 93 ++++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 llvm/test/Transforms/InstCombine/pr112390.ll
diff --git a/llvm/test/Transforms/InstCombine/pr112390.ll b/llvm/test/Transforms/InstCombine/pr112390.ll
new file mode 100644
index 0000000000000..74669f35f0246
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/pr112390.ll
@@ -0,0 +1,93 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+define i1 @test_and(i32 %A) {
+; CHECK-LABEL: @test_and(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[RES:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: ret i1 [[RES]]
+;
+ %cmp1 = icmp sge i32 %A, 0
+ %and = and i32 %A, 2147483647
+ %cmp2 = icmp ne i32 %and, 0
+ %res = and i1 %cmp1, %cmp2
+ ret i1 %res
+}
+
+define i1 @test_or(i32 %A) {
+; CHECK-LABEL: @test_or(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
+; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[RES:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: ret i1 [[RES]]
+;
+ %cmp1 = icmp slt i32 %A, 0
+ %and = and i32 %A, 2147483647
+ %cmp2 = icmp eq i32 %and, 0
+ %res = or i1 %cmp1, %cmp2
+ ret i1 %res
+}
+
+define i1 @test_and_logical(i32 %A) {
+; CHECK-LABEL: @test_and_logical(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[RES:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: ret i1 [[RES]]
+;
+ %cmp1 = icmp sge i32 %A, 0
+ %and = and i32 %A, 2147483647
+ %cmp2 = icmp ne i32 %and, 0
+ %res = select i1 %cmp1, i1 %cmp2, i1 false
+ ret i1 %res
+}
+
+define i1 @test_or_logical(i32 %A) {
+; CHECK-LABEL: @test_or_logical(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
+; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[RES:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: ret i1 [[RES]]
+;
+ %cmp1 = icmp slt i32 %A, 0
+ %and = and i32 %A, 2147483647
+ %cmp2 = icmp eq i32 %and, 0
+ %res = select i1 %cmp1, i1 true, i1 %cmp2
+ ret i1 %res
+}
+
+define <2 x i1> @test_and_vec(<2 x i32> %A) {
+; CHECK-LABEL: @test_and_vec(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt <2 x i32> [[A:%.*]], splat (i32 -1)
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A]], splat (i32 2147483647)
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ne <2 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT: [[RES:%.*]] = and <2 x i1> [[CMP1]], [[CMP2]]
+; CHECK-NEXT: ret <2 x i1> [[RES]]
+;
+ %cmp1 = icmp sge <2 x i32> %A, zeroinitializer
+ %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
+ %cmp2 = icmp ne <2 x i32> %and, zeroinitializer
+ %res = and <2 x i1> %cmp1, %cmp2
+ ret <2 x i1> %res
+}
+
+define i1 @test_and_commuted(i32 %A) {
+; CHECK-LABEL: @test_and_commuted(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[RES:%.*]] = and i1 [[CMP2]], [[CMP1]]
+; CHECK-NEXT: ret i1 [[RES]]
+;
+ %cmp1 = icmp sge i32 %A, 0
+ %and = and i32 %A, 2147483647
+ %cmp2 = icmp ne i32 %and, 0
+ %res = and i1 %cmp2, %cmp1
+ ret i1 %res
+}
+
>From 21b277a3b6047c7bd8d87820660143c0eb7c5564 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 2 Jul 2026 11:30:40 -0400
Subject: [PATCH 2/6] [InstCombine] Simplify (A >= 0) & ((A & INT_MAX) != 0) to
A > 0
This patch implements simplifications for bitwise and logical AND/OR combinations of sign-bit checks and lower-bits checks.
---
.../InstCombine/InstCombineAndOrXor.cpp | 28 +++++++++++++++++
llvm/test/Transforms/InstCombine/pr112390.ll | 30 ++++---------------
2 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index b6f4a55c07e8a..591802b77178c 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -3533,6 +3533,34 @@ Value *InstCombinerImpl::foldAndOrOfICmps(ICmpInst *LHS, ICmpInst *RHS,
}
}
+ // (icmp sge X, 0) & (icmp ne (X & INT_MAX), 0) -> (icmp sgt X, 0)
+ // (icmp slt X, 0) | (icmp eq (X & INT_MAX), 0) -> (icmp sle X, 0)
+ {
+ bool TrueIfSigned;
+ if (isSignBitCheck(PredL, *LHSC, TrueIfSigned) &&
+ PredR == (IsAnd ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ) &&
+ match(RHS1, m_Zero()) &&
+ match(RHS0, m_And(m_Specific(LHS0), m_MaxSignedValue()))) {
+ if (IsAnd && !TrueIfSigned)
+ return Builder.CreateICmpSGT(
+ LHS0, ConstantInt::getNullValue(LHS0->getType()));
+ if (!IsAnd && TrueIfSigned)
+ return Builder.CreateICmpSLE(
+ LHS0, ConstantInt::getNullValue(LHS0->getType()));
+ }
+ if (isSignBitCheck(PredR, *RHSC, TrueIfSigned) &&
+ PredL == (IsAnd ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ) &&
+ match(LHS1, m_Zero()) &&
+ match(LHS0, m_And(m_Specific(RHS0), m_MaxSignedValue()))) {
+ if (IsAnd && !TrueIfSigned)
+ return Builder.CreateICmpSGT(
+ RHS0, ConstantInt::getNullValue(RHS0->getType()));
+ if (!IsAnd && TrueIfSigned)
+ return Builder.CreateICmpSLE(
+ RHS0, ConstantInt::getNullValue(RHS0->getType()));
+ }
+ }
+
// Match naive pattern (and its inverted form) for checking if two values
// share same sign. An example of the pattern:
// (icmp slt (X & Y), 0) | (icmp sgt (X | Y), -1) -> (icmp sgt (X ^ Y), -1)
diff --git a/llvm/test/Transforms/InstCombine/pr112390.ll b/llvm/test/Transforms/InstCombine/pr112390.ll
index 74669f35f0246..2b404e56c58fc 100644
--- a/llvm/test/Transforms/InstCombine/pr112390.ll
+++ b/llvm/test/Transforms/InstCombine/pr112390.ll
@@ -3,10 +3,7 @@
define i1 @test_and(i32 %A) {
; CHECK-LABEL: @test_and(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
-; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND]], 0
-; CHECK-NEXT: [[RES:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp sgt i32 [[A:%.*]], 0
; CHECK-NEXT: ret i1 [[RES]]
;
%cmp1 = icmp sge i32 %A, 0
@@ -18,10 +15,7 @@ define i1 @test_and(i32 %A) {
define i1 @test_or(i32 %A) {
; CHECK-LABEL: @test_or(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
-; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: [[RES:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp slt i32 [[A:%.*]], 1
; CHECK-NEXT: ret i1 [[RES]]
;
%cmp1 = icmp slt i32 %A, 0
@@ -33,10 +27,7 @@ define i1 @test_or(i32 %A) {
define i1 @test_and_logical(i32 %A) {
; CHECK-LABEL: @test_and_logical(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
-; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND]], 0
-; CHECK-NEXT: [[RES:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp sgt i32 [[A:%.*]], 0
; CHECK-NEXT: ret i1 [[RES]]
;
%cmp1 = icmp sge i32 %A, 0
@@ -48,10 +39,7 @@ define i1 @test_and_logical(i32 %A) {
define i1 @test_or_logical(i32 %A) {
; CHECK-LABEL: @test_or_logical(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
-; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND]], 0
-; CHECK-NEXT: [[RES:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp slt i32 [[A:%.*]], 1
; CHECK-NEXT: ret i1 [[RES]]
;
%cmp1 = icmp slt i32 %A, 0
@@ -63,10 +51,7 @@ define i1 @test_or_logical(i32 %A) {
define <2 x i1> @test_and_vec(<2 x i32> %A) {
; CHECK-LABEL: @test_and_vec(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt <2 x i32> [[A:%.*]], splat (i32 -1)
-; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A]], splat (i32 2147483647)
-; CHECK-NEXT: [[CMP2:%.*]] = icmp ne <2 x i32> [[AND]], zeroinitializer
-; CHECK-NEXT: [[RES:%.*]] = and <2 x i1> [[CMP1]], [[CMP2]]
+; CHECK-NEXT: [[RES:%.*]] = icmp sgt <2 x i32> [[A:%.*]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[RES]]
;
%cmp1 = icmp sge <2 x i32> %A, zeroinitializer
@@ -78,10 +63,7 @@ define <2 x i1> @test_and_vec(<2 x i32> %A) {
define i1 @test_and_commuted(i32 %A) {
; CHECK-LABEL: @test_and_commuted(
-; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 2147483647
-; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND]], 0
-; CHECK-NEXT: [[RES:%.*]] = and i1 [[CMP2]], [[CMP1]]
+; CHECK-NEXT: [[RES:%.*]] = icmp sgt i32 [[A:%.*]], 0
; CHECK-NEXT: ret i1 [[RES]]
;
%cmp1 = icmp sge i32 %A, 0
>From a8ddfe7c78b7ddd49773be847a0b71cdb82cbcfc Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 2 Jul 2026 11:31:24 -0400
Subject: [PATCH 3/6] Rename
---
.../Transforms/InstCombine/{pr112390.ll => sign-bitwise-check.ll} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename llvm/test/Transforms/InstCombine/{pr112390.ll => sign-bitwise-check.ll} (100%)
diff --git a/llvm/test/Transforms/InstCombine/pr112390.ll b/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
similarity index 100%
rename from llvm/test/Transforms/InstCombine/pr112390.ll
rename to llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
>From 9167402adcee88fc70ea7fc8500de94b5957a462 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 2 Jul 2026 12:07:34 -0400
Subject: [PATCH 4/6] Generalize to computeNumBits
---
.../InstCombine/InstCombineAndOrXor.cpp | 35 ++++++++++++-------
.../InstCombine/sign-bitwise-check.ll | 20 +++++++++++
2 files changed, 43 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 591802b77178c..ba7bb64df7f95 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -3533,31 +3533,42 @@ Value *InstCombinerImpl::foldAndOrOfICmps(ICmpInst *LHS, ICmpInst *RHS,
}
}
- // (icmp sge X, 0) & (icmp ne (X & INT_MAX), 0) -> (icmp sgt X, 0)
- // (icmp slt X, 0) | (icmp eq (X & INT_MAX), 0) -> (icmp sle X, 0)
+ // (icmp sge X, 0) & (icmp ne (X & Mask), 0) -> (icmp sgt X, 0)
+ // (icmp slt X, 0) | (icmp eq (X & Mask), 0) -> (icmp sle X, 0)
+ // Valid if Mask covers all potentially non-zero positive bits of X.
{
bool TrueIfSigned;
+ const APInt *MaskC;
+ auto IsValidMask = [&](Value *X, const APInt &Mask) {
+ APInt SignBit = APInt::getSignMask(Mask.getBitWidth());
+ APInt RequiredMask = ~Mask & ~SignBit;
+ return RequiredMask.isZero() ||
+ (RequiredMask & ~computeKnownBits(X, &I, 0).Zero).isZero();
+ };
+
if (isSignBitCheck(PredL, *LHSC, TrueIfSigned) &&
PredR == (IsAnd ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ) &&
match(RHS1, m_Zero()) &&
- match(RHS0, m_And(m_Specific(LHS0), m_MaxSignedValue()))) {
+ match(RHS0, m_And(m_Specific(LHS0), m_APInt(MaskC))) &&
+ IsValidMask(LHS0, *MaskC)) {
if (IsAnd && !TrueIfSigned)
- return Builder.CreateICmpSGT(
- LHS0, ConstantInt::getNullValue(LHS0->getType()));
+ return Builder.CreateICmpSGT(LHS0,
+ ConstantInt::getNullValue(LHS0->getType()));
if (!IsAnd && TrueIfSigned)
- return Builder.CreateICmpSLE(
- LHS0, ConstantInt::getNullValue(LHS0->getType()));
+ return Builder.CreateICmpSLE(LHS0,
+ ConstantInt::getNullValue(LHS0->getType()));
}
if (isSignBitCheck(PredR, *RHSC, TrueIfSigned) &&
PredL == (IsAnd ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ) &&
match(LHS1, m_Zero()) &&
- match(LHS0, m_And(m_Specific(RHS0), m_MaxSignedValue()))) {
+ match(LHS0, m_And(m_Specific(RHS0), m_APInt(MaskC))) &&
+ IsValidMask(RHS0, *MaskC)) {
if (IsAnd && !TrueIfSigned)
- return Builder.CreateICmpSGT(
- RHS0, ConstantInt::getNullValue(RHS0->getType()));
+ return Builder.CreateICmpSGT(RHS0,
+ ConstantInt::getNullValue(RHS0->getType()));
if (!IsAnd && TrueIfSigned)
- return Builder.CreateICmpSLE(
- RHS0, ConstantInt::getNullValue(RHS0->getType()));
+ return Builder.CreateICmpSLE(RHS0,
+ ConstantInt::getNullValue(RHS0->getType()));
}
}
diff --git a/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll b/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
index 2b404e56c58fc..d2dcfa3d4d6bc 100644
--- a/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
+++ b/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
@@ -73,3 +73,23 @@ define i1 @test_and_commuted(i32 %A) {
ret i1 %res
}
+
+define i1 @test_known_bits(i32 %A) {
+ ; clear bit 30
+ %A_and = and i32 %A, -1073741825
+ %cmp1 = icmp sge i32 %A_and, 0
+ %and = and i32 %A_and, 1073741823
+ %cmp2 = icmp ne i32 %and, 0
+ %res = and i1 %cmp1, %cmp2
+ ret i1 %res
+}
+
+define i1 @test_known_bits_or(i32 %A) {
+ ; clear bit 30
+ %A_and = and i32 %A, -1073741825
+ %cmp1 = icmp slt i32 %A_and, 0
+ %and = and i32 %A_and, 1073741823
+ %cmp2 = icmp eq i32 %and, 0
+ %res = or i1 %cmp1, %cmp2
+ ret i1 %res
+}
>From 89a227c6f43456ff83b4ef8fb017665ce56754d7 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 2 Jul 2026 14:04:12 -0400
Subject: [PATCH 5/6] Update sign-bitwise-check.ll
---
llvm/test/Transforms/InstCombine/sign-bitwise-check.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll b/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
index d2dcfa3d4d6bc..5e31e1dc168c1 100644
--- a/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
+++ b/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
@@ -73,7 +73,6 @@ define i1 @test_and_commuted(i32 %A) {
ret i1 %res
}
-
define i1 @test_known_bits(i32 %A) {
; clear bit 30
%A_and = and i32 %A, -1073741825
>From 1feebc7f264ef1a4c08df2f774efeab7cb66680f Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 2 Jul 2026 14:55:54 -0400
Subject: [PATCH 6/6] Update sign-bitwise-check.ll
---
.../Transforms/InstCombine/sign-bitwise-check.ll | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll b/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
index 5e31e1dc168c1..04f0d4457552c 100644
--- a/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
+++ b/llvm/test/Transforms/InstCombine/sign-bitwise-check.ll
@@ -75,6 +75,13 @@ define i1 @test_and_commuted(i32 %A) {
define i1 @test_known_bits(i32 %A) {
; clear bit 30
+; CHECK-LABEL: @test_known_bits(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 1073741823
+; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT: [[RES:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: ret i1 [[RES]]
+;
%A_and = and i32 %A, -1073741825
%cmp1 = icmp sge i32 %A_and, 0
%and = and i32 %A_and, 1073741823
@@ -85,6 +92,13 @@ define i1 @test_known_bits(i32 %A) {
define i1 @test_known_bits_or(i32 %A) {
; clear bit 30
+; CHECK-LABEL: @test_known_bits_or(
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], 1073741823
+; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT: [[RES:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT: ret i1 [[RES]]
+;
%A_and = and i32 %A, -1073741825
%cmp1 = icmp slt i32 %A_and, 0
%and = and i32 %A_and, 1073741823
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