[llvm] [TableGen][SchedModel] Add repeat rate to block buffered resources (PR #202775)

[Jeffrey Byrnes via llvm-commits]

jrbyrnes wrote:

> ```
> let ReleaseAtCycles = [4, 1], ForceReserved = true in
> def : WriteRes<SC1, [Res0, Res1]>;
> ```
> 
> where `ForceReserved` is the new property I was talking about here. The name could also be something like `AlwaysReserved` or even `AlwaysUnbuffered`.
> 
> what do you think?

Thanks for the proposal and valuable feedback - I have been considering it. 

Given the modelling requirements, I think your proposal makes a lot of sense.

The main problem I have is that, in the shorter term, I am also looking for a way to express this property that is consumable for our target specific schedulers & heuristics, while also having minimal impact on the heuristics defined in MachineScheduler.cpp. After more thought, I think it is best to explore different approaches for this shorter term need, to avoid polluting the SchedModel.

As a longer term effort, we will need to express this property in the SchedModel in some way if we want accurate modelling for AMDGPU. Though, I am not fully convinced we want to stick with the current modelling requirements (e.g. I would like to reconsider whether we should truly be using BufferSize 1 instead of trying to find a solution with BufferSize 0). So, for the moment, I think we should pause the conversation (while I look into different avenues for short term + rethink long term modelling) -- unless you feel this property is generally useful across all targets.

https://github.com/llvm/llvm-project/pull/202775