[llvm] dab5d92 - [X86] haddsub-2.ll - sync scalar "not" hsub tests between the middle-end and backend (#207192)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 2 07:58:24 PDT 2026
Author: Simon Pilgrim
Date: 2026-07-02T14:58:20Z
New Revision: dab5d92f36fff2149f55e8dd7108522f4104cb62
URL: https://github.com/llvm/llvm-project/commit/dab5d92f36fff2149f55e8dd7108522f4104cb62
DIFF: https://github.com/llvm/llvm-project/commit/dab5d92f36fff2149f55e8dd7108522f4104cb62.diff
LOG: [X86] haddsub-2.ll - sync scalar "not" hsub tests between the middle-end and backend (#207192)
Replace the codegen scalar tests with the IR that middle-end actually generates
Help towards #143000
Added:
Modified:
llvm/test/CodeGen/X86/haddsub-2.ll
llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/haddsub-2.ll b/llvm/test/CodeGen/X86/haddsub-2.ll
index c060b6b708302..f71bd0cbc737d 100644
--- a/llvm/test/CodeGen/X86/haddsub-2.ll
+++ b/llvm/test/CodeGen/X86/haddsub-2.ll
@@ -1,164 +1,78 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+sse3 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+sse3,+ssse3 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse3 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse3,fast-hops | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2,fast-hops | FileCheck %s --check-prefixes=AVX
; Verify that we don't select horizontal subs in the following functions.
define <4 x i32> @not_a_hsub_1(<4 x i32> %A, <4 x i32> %B) {
; SSE-LABEL: not_a_hsub_1:
; SSE: # %bb.0:
-; SSE-NEXT: movd %xmm0, %eax
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,1,1]
-; SSE-NEXT: movd %xmm2, %ecx
-; SSE-NEXT: subl %ecx, %eax
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
-; SSE-NEXT: movd %xmm2, %ecx
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; SSE-NEXT: movd %xmm0, %edx
-; SSE-NEXT: subl %edx, %ecx
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; SSE-NEXT: movd %xmm0, %edx
-; SSE-NEXT: movd %xmm1, %esi
-; SSE-NEXT: subl %esi, %edx
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3]
-; SSE-NEXT: movd %xmm0, %esi
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
-; SSE-NEXT: movd %xmm0, %edi
-; SSE-NEXT: subl %edi, %esi
-; SSE-NEXT: movd %esi, %xmm0
-; SSE-NEXT: movd %edx, %xmm1
-; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; SSE-NEXT: movd %ecx, %xmm2
-; SSE-NEXT: movd %eax, %xmm0
-; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE-NEXT: movaps %xmm0, %xmm2
+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
+; SSE-NEXT: psubd %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: not_a_hsub_1:
; AVX: # %bb.0:
-; AVX-NEXT: vmovd %xmm0, %eax
-; AVX-NEXT: vpextrd $1, %xmm0, %ecx
-; AVX-NEXT: subl %ecx, %eax
-; AVX-NEXT: vpextrd $2, %xmm0, %ecx
-; AVX-NEXT: vpextrd $3, %xmm0, %edx
-; AVX-NEXT: subl %edx, %ecx
-; AVX-NEXT: vpextrd $1, %xmm1, %edx
-; AVX-NEXT: vmovd %xmm1, %esi
-; AVX-NEXT: subl %esi, %edx
-; AVX-NEXT: vpextrd $3, %xmm1, %esi
-; AVX-NEXT: vpextrd $2, %xmm1, %edi
-; AVX-NEXT: subl %edi, %esi
-; AVX-NEXT: vmovd %eax, %xmm0
-; AVX-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
-; AVX-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
-; AVX-NEXT: vpinsrd $3, %esi, %xmm0, %xmm0
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,2],xmm1[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
+; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm0
; AVX-NEXT: retq
- %vecext = extractelement <4 x i32> %A, i32 0
- %vecext1 = extractelement <4 x i32> %A, i32 1
- %sub = sub i32 %vecext, %vecext1
- %vecinit = insertelement <4 x i32> undef, i32 %sub, i32 0
- %vecext2 = extractelement <4 x i32> %A, i32 2
- %vecext3 = extractelement <4 x i32> %A, i32 3
- %sub4 = sub i32 %vecext2, %vecext3
- %vecinit5 = insertelement <4 x i32> %vecinit, i32 %sub4, i32 1
- %vecext6 = extractelement <4 x i32> %B, i32 1
- %vecext7 = extractelement <4 x i32> %B, i32 0
- %sub8 = sub i32 %vecext6, %vecext7
- %vecinit9 = insertelement <4 x i32> %vecinit5, i32 %sub8, i32 2
- %vecext10 = extractelement <4 x i32> %B, i32 3
- %vecext11 = extractelement <4 x i32> %B, i32 2
- %sub12 = sub i32 %vecext10, %vecext11
- %vecinit13 = insertelement <4 x i32> %vecinit9, i32 %sub12, i32 3
- ret <4 x i32> %vecinit13
+ %x = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 2, i32 5, i32 7>
+ %y = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 4, i32 6>
+ %r = sub <4 x i32> %x, %y
+ ret <4 x i32> %r
}
define <4 x float> @not_a_hsub_2(<4 x float> %A, <4 x float> %B) {
; SSE-LABEL: not_a_hsub_2:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
-; SSE-NEXT: movaps %xmm0, %xmm3
-; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3],xmm0[3,3]
-; SSE-NEXT: subss %xmm3, %xmm2
-; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; SSE-NEXT: subss %xmm3, %xmm0
-; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; SSE-NEXT: movaps %xmm1, %xmm2
-; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm1[3,3]
-; SSE-NEXT: movaps %xmm1, %xmm3
-; SSE-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1]
-; SSE-NEXT: subss %xmm3, %xmm2
-; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
-; SSE-NEXT: subss %xmm3, %xmm1
-; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
-; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,3]
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,2]
+; SSE-NEXT: subps %xmm0, %xmm2
+; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: not_a_hsub_2:
; AVX: # %bb.0:
-; AVX-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm0[3,3,3,3]
-; AVX-NEXT: vsubss %xmm3, %xmm2, %xmm2
-; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX-NEXT: vsubss %xmm3, %xmm0, %xmm0
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3]
-; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[3,3,3,3]
-; AVX-NEXT: vshufpd {{.*#+}} xmm3 = xmm1[1,0]
-; AVX-NEXT: vsubss %xmm3, %xmm2, %xmm2
-; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
-; AVX-NEXT: vsubss %xmm3, %xmm1, %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,2],xmm1[0,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,2]
+; AVX-NEXT: vsubps %xmm0, %xmm2, %xmm0
; AVX-NEXT: retq
- %vecext = extractelement <4 x float> %A, i32 2
- %vecext1 = extractelement <4 x float> %A, i32 3
- %sub = fsub float %vecext, %vecext1
- %vecinit = insertelement <4 x float> undef, float %sub, i32 1
- %vecext2 = extractelement <4 x float> %A, i32 0
- %vecext3 = extractelement <4 x float> %A, i32 1
- %sub4 = fsub float %vecext2, %vecext3
- %vecinit5 = insertelement <4 x float> %vecinit, float %sub4, i32 0
- %vecext6 = extractelement <4 x float> %B, i32 3
- %vecext7 = extractelement <4 x float> %B, i32 2
- %sub8 = fsub float %vecext6, %vecext7
- %vecinit9 = insertelement <4 x float> %vecinit5, float %sub8, i32 3
- %vecext10 = extractelement <4 x float> %B, i32 0
- %vecext11 = extractelement <4 x float> %B, i32 1
- %sub12 = fsub float %vecext10, %vecext11
- %vecinit13 = insertelement <4 x float> %vecinit9, float %sub12, i32 2
- ret <4 x float> %vecinit13
+ %x = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 7>
+ %y = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> <i32 1, i32 3, i32 5, i32 6>
+ %r = fsub <4 x float> %x, %y
+ ret <4 x float> %r
}
define <2 x double> @not_a_hsub_3(<2 x double> %A, <2 x double> %B) {
; SSE-LABEL: not_a_hsub_3:
; SSE: # %bb.0:
-; SSE-NEXT: movapd %xmm1, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
-; SSE-NEXT: subsd %xmm2, %xmm1
; SSE-NEXT: movapd %xmm0, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
-; SSE-NEXT: subsd %xmm0, %xmm2
-; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE-NEXT: shufpd {{.*#+}} xmm2 = xmm2[1],xmm1[0]
+; SSE-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE-NEXT: subpd %xmm1, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: not_a_hsub_3:
; AVX: # %bb.0:
-; AVX-NEXT: vshufpd {{.*#+}} xmm2 = xmm1[1,0]
-; AVX-NEXT: vsubsd %xmm2, %xmm1, %xmm1
-; AVX-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
-; AVX-NEXT: vsubsd %xmm0, %xmm2, %xmm0
-; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1],xmm1[0]
+; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
+; AVX-NEXT: vsubpd %xmm0, %xmm2, %xmm0
; AVX-NEXT: retq
- %vecext = extractelement <2 x double> %B, i32 0
- %vecext1 = extractelement <2 x double> %B, i32 1
- %sub = fsub double %vecext, %vecext1
- %vecinit = insertelement <2 x double> undef, double %sub, i32 1
- %vecext2 = extractelement <2 x double> %A, i32 1
- %vecext3 = extractelement <2 x double> %A, i32 0
- %sub2 = fsub double %vecext2, %vecext3
- %vecinit2 = insertelement <2 x double> %vecinit, double %sub2, i32 0
- ret <2 x double> %vecinit2
+ %x = shufflevector <2 x double> %A, <2 x double> %B, <2 x i32> <i32 1, i32 2>
+ %y = shufflevector <2 x double> %A, <2 x double> %B, <2 x i32> <i32 0, i32 3>
+ %r = fsub <2 x double> %x, %y
+ ret <2 x double> %r
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/hsub.ll b/llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
index e41021281e269..24b1a4c4af405 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
@@ -1740,3 +1740,73 @@ define <4 x double> @sub_v4f64_0022(<4 x double> %a) {
%shuf = shufflevector <4 x double> %ins2, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
ret <4 x double> %shuf
}
+
+define <4 x i32> @not_a_hsub_1(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: @not_a_hsub_1(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> <i32 0, i32 2, i32 5, i32 7>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[B]], <4 x i32> <i32 1, i32 3, i32 4, i32 6>
+; CHECK-NEXT: [[TMP3:%.*]] = sub <4 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret <4 x i32> [[TMP3]]
+;
+ %vecext = extractelement <4 x i32> %A, i32 0
+ %vecext1 = extractelement <4 x i32> %A, i32 1
+ %sub = sub i32 %vecext, %vecext1
+ %vecinit = insertelement <4 x i32> undef, i32 %sub, i32 0
+ %vecext2 = extractelement <4 x i32> %A, i32 2
+ %vecext3 = extractelement <4 x i32> %A, i32 3
+ %sub4 = sub i32 %vecext2, %vecext3
+ %vecinit5 = insertelement <4 x i32> %vecinit, i32 %sub4, i32 1
+ %vecext6 = extractelement <4 x i32> %B, i32 1
+ %vecext7 = extractelement <4 x i32> %B, i32 0
+ %sub8 = sub i32 %vecext6, %vecext7
+ %vecinit9 = insertelement <4 x i32> %vecinit5, i32 %sub8, i32 2
+ %vecext10 = extractelement <4 x i32> %B, i32 3
+ %vecext11 = extractelement <4 x i32> %B, i32 2
+ %sub12 = sub i32 %vecext10, %vecext11
+ %vecinit13 = insertelement <4 x i32> %vecinit9, i32 %sub12, i32 3
+ ret <4 x i32> %vecinit13
+}
+
+define <4 x float> @not_a_hsub_2(<4 x float> %A, <4 x float> %B) {
+; CHECK-LABEL: @not_a_hsub_2(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i32> <i32 0, i32 2, i32 4, i32 7>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[B]], <4 x i32> <i32 1, i32 3, i32 5, i32 6>
+; CHECK-NEXT: [[TMP3:%.*]] = fsub <4 x float> [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret <4 x float> [[TMP3]]
+;
+ %vecext = extractelement <4 x float> %A, i32 2
+ %vecext1 = extractelement <4 x float> %A, i32 3
+ %sub = fsub float %vecext, %vecext1
+ %vecinit = insertelement <4 x float> undef, float %sub, i32 1
+ %vecext2 = extractelement <4 x float> %A, i32 0
+ %vecext3 = extractelement <4 x float> %A, i32 1
+ %sub4 = fsub float %vecext2, %vecext3
+ %vecinit5 = insertelement <4 x float> %vecinit, float %sub4, i32 0
+ %vecext6 = extractelement <4 x float> %B, i32 3
+ %vecext7 = extractelement <4 x float> %B, i32 2
+ %sub8 = fsub float %vecext6, %vecext7
+ %vecinit9 = insertelement <4 x float> %vecinit5, float %sub8, i32 3
+ %vecext10 = extractelement <4 x float> %B, i32 0
+ %vecext11 = extractelement <4 x float> %B, i32 1
+ %sub12 = fsub float %vecext10, %vecext11
+ %vecinit13 = insertelement <4 x float> %vecinit9, float %sub12, i32 2
+ ret <4 x float> %vecinit13
+}
+
+define <2 x double> @not_a_hsub_3(<2 x double> %A, <2 x double> %B) {
+; CHECK-LABEL: @not_a_hsub_3(
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret <2 x double> [[TMP3]]
+;
+ %vecext = extractelement <2 x double> %B, i32 0
+ %vecext1 = extractelement <2 x double> %B, i32 1
+ %sub = fsub double %vecext, %vecext1
+ %vecinit = insertelement <2 x double> undef, double %sub, i32 1
+ %vecext2 = extractelement <2 x double> %A, i32 1
+ %vecext3 = extractelement <2 x double> %A, i32 0
+ %sub2 = fsub double %vecext2, %vecext3
+ %vecinit2 = insertelement <2 x double> %vecinit, double %sub2, i32 0
+ ret <2 x double> %vecinit2
+}
More information about the llvm-commits
mailing list