[llvm] [AArch64][DAG] Port adde and sube combine to AArch64 (PR #202227)

[via llvm-commits]

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@@ -22867,6 +22867,41 @@ static SDValue foldADCToCINC(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(AArch64ISD::CSINC, DL, VT, LHS, LHS, CC, Cond);
 }
 
+static SDValue performAddSubCarryCombine(SDNode *N, SelectionDAG &DAG) {
+  SDValue RHS = N->getOperand(1);
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
+    int64_t Imm = C->getSExtValue();
+    if (Imm < 0) {
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zip-stack-debug wrote:

> The case for supporting negative values other than -1 seems thin, but I'm happy to accept the reasoning. That said, I do think this should be something like `Imm == -1 || (Imm < 0 and C->hasOneUse())` because otherwise you run the risk of increasing the number of generated immediates.
> 
> This will require a dedicated test, but I suspect you can just copy an existing test and insert `call void (...) @llvm.fake.use(i64 ????)`.

Done!

https://github.com/llvm/llvm-project/pull/202227