[llvm] [AArch64] NFCI: Simplify LowerVectorFP_TO_INT_SAT (part 1) (PR #207198)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Sander de Smalen (sdesmalen-arm)

<details>
<summary>Changes</summary>

The lowering code tries to implement splitting by keeping two source values SrcVal and SrcVal2 for the Lo/Hi part respectively.

This is a bit awkward, because SrcVal2 may not be set. It makes more sense to generating new DAG nodes that will be lowered separately by the lowering mechanism, which revisits the newly added (split sourceval) nodes for lowering.

---
Full diff: https://github.com/llvm/llvm-project/pull/207198.diff


1 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+17-25) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c4c52dbe395e8..910740bbcf04c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5208,7 +5208,6 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
 
   // In the absence of FP16 support, promote f16 to f32 and saturate the result.
   SDLoc DL(Op);
-  SDValue SrcVal2;
   if ((SrcElementVT == MVT::f16 &&
        (!Subtarget->hasFullFP16() || DstElementWidth > 16)) ||
       SrcElementVT == MVT::bf16) {
@@ -5217,8 +5216,17 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
     // If we are extending to a v8f32, split into two v4f32 to produce legal
     // types.
     if (F32VT.getSizeInBits() > 128) {
+      SDValue SrcVal2;
       std::tie(SrcVal, SrcVal2) = DAG.SplitVector(SrcVal, DL);
-      F32VT = F32VT.getHalfNumVectorElementsVT();
+      EVT IntVT = SrcVal.getValueType().changeVectorElementTypeToInteger();
+      SDValue Lo =
+          DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal, Op.getOperand(1));
+      SDValue Hi =
+          DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal2, Op.getOperand(1));
+      EVT HalfDstVT = DstVT.getHalfNumVectorElementsVT(*DAG.getContext());
+      Lo = DAG.getNode(ISD::TRUNCATE, DL, HalfDstVT, Lo);
+      Hi = DAG.getNode(ISD::TRUNCATE, DL, HalfDstVT, Hi);
+      return DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Lo, Hi);
     }
     SrcVT = F32VT;
     SrcElementVT = MVT::f32;
@@ -5237,16 +5245,9 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
     SrcElementWidth = 64;
   }
   // Cases that we can emit directly.
-  if (SrcElementWidth == DstElementWidth && SrcElementWidth == SatWidth) {
-    SDValue Res = DAG.getNode(Op.getOpcode(), DL, DstVT, SrcVal,
-                              DAG.getValueType(DstVT.getScalarType()));
-    if (SrcVal2) {
-      SDValue Res2 = DAG.getNode(Op.getOpcode(), DL, DstVT, SrcVal2,
-                                 DAG.getValueType(DstVT.getScalarType()));
-      return DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Res, Res2);
-    }
-    return Res;
-  }
+  if (SrcElementWidth == DstElementWidth && SrcElementWidth == SatWidth)
+    return DAG.getNode(Op.getOpcode(), DL, DstVT, SrcVal,
+                       DAG.getValueType(DstVT.getScalarType()));
 
   // Otherwise we emit a cvt that saturates to a higher BW, and saturate the
   // result. This is only valid if the legal cvt is larger than the saturate
@@ -5255,35 +5256,26 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
   if (SrcElementWidth < SatWidth || SrcElementVT == MVT::f64)
     return SDValue();
 
+  assert((SrcElementWidth > DstElementWidth) ||
+         (SrcElementWidth == DstElementWidth && SatWidth < DstElementWidth));
+
   EVT IntVT = SrcVT.changeVectorElementTypeToInteger();
   SDValue NativeCvt = DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal,
                                   DAG.getValueType(IntVT.getScalarType()));
-  SDValue NativeCvt2 =
-      SrcVal2 ? DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal2,
-                            DAG.getValueType(IntVT.getScalarType()))
-              : SDValue();
-  SDValue Sat, Sat2;
+  SDValue Sat;
   if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) {
     SDValue MinC = DAG.getConstant(
         APInt::getSignedMaxValue(SatWidth).sext(SrcElementWidth), DL, IntVT);
     SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC);
-    SDValue Min2 = SrcVal2 ? DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt2, MinC) : SDValue();
     SDValue MaxC = DAG.getConstant(
         APInt::getSignedMinValue(SatWidth).sext(SrcElementWidth), DL, IntVT);
     Sat = DAG.getNode(ISD::SMAX, DL, IntVT, Min, MaxC);
-    Sat2 = SrcVal2 ? DAG.getNode(ISD::SMAX, DL, IntVT, Min2, MaxC) : SDValue();
   } else {
     SDValue MinC = DAG.getConstant(
         APInt::getAllOnes(SatWidth).zext(SrcElementWidth), DL, IntVT);
     Sat = DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt, MinC);
-    Sat2 = SrcVal2 ? DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt2, MinC) : SDValue();
   }
 
-  if (SrcVal2)
-    Sat = DAG.getNode(ISD::CONCAT_VECTORS, DL,
-                      IntVT.getDoubleNumVectorElementsVT(*DAG.getContext()),
-                      Sat, Sat2);
-
   return DAG.getNode(ISD::TRUNCATE, DL, DstVT, Sat);
 }
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/207198