[llvm] [CodeGen] Merge TargetRegClass into MCRegClass (PR #207168)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 2 05:42:53 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-regalloc
Author: Alexis Engelke (aengelke)
<details>
<summary>Changes</summary>
Both data types store primitive information only and TargetRegisterClass
doesn't reference target-specific data structures. TargetRegisterClass,
however, freqeuently refers to MCRegisterClass through a pointer, which
prevents moving the large TargetRegisterClass instances to .rodata.
Therefore, merge the fields of TargetRegisterClass into MCRegisterClass
and adjust the remaining fields to use the existing storage mechanism
for pointer-free storage. To avoid invasive code changes, keep
TargetRegisterClass as alias for MCRegisterClass.
This reduces the size of .data.rel.ro by ~122 kiB in an all-target
build while growing .rodata by just 92 kiB. Further size improvements
are possible in future by reordering struct fields and deduplicating
masks/register lists/register class lists.
---
Patch is 55.32 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/207168.diff
48 Files Affected:
- (modified) llvm/include/llvm/CodeGen/FastISel.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/Utils.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/LiveStacks.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/MIRParser/MIParser.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/MachineBasicBlock.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/MachineFunction.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/MachineInstr.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/MachineSSAUpdater.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/RegAllocCommon.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/RegisterBank.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/RegisterBankInfo.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/RegisterScavenging.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/ScheduleDAG.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/TargetLowering.h (+2-1)
- (modified) llvm/include/llvm/CodeGen/TargetRegisterInfo.h (+4-157)
- (modified) llvm/include/llvm/CodeGen/TargetSubtargetInfo.h (+2-1)
- (modified) llvm/include/llvm/MC/MCRegisterInfo.h (+111-1)
- (modified) llvm/lib/CodeGen/AggressiveAntiDepBreaker.h (+2-1)
- (modified) llvm/lib/CodeGen/CriticalAntiDepBreaker.h (+2-1)
- (modified) llvm/lib/CodeGen/RegisterCoalescer.h (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp (+5-4)
- (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h (+2-1)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+4-8)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.h (-5)
- (modified) llvm/lib/Target/Hexagon/BitTracker.h (+2-1)
- (modified) llvm/lib/Target/Hexagon/HexagonBitTracker.cpp (+4-4)
- (modified) llvm/lib/Target/Hexagon/HexagonFrameLowering.h (+2-1)
- (modified) llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h (+2-1)
- (modified) llvm/lib/Target/Mips/MipsISelLowering.h (+2-1)
- (modified) llvm/lib/Target/Mips/MipsInstrInfo.h (+2-1)
- (modified) llvm/lib/Target/Mips/MipsRegisterInfo.h (+2-1)
- (modified) llvm/lib/Target/Mips/MipsSEISelLowering.h (+2-1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h (+2-1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h (+2-1)
- (modified) llvm/lib/Target/Xtensa/XtensaRegisterInfo.h (+2-1)
- (modified) llvm/test/TableGen/RegisterClassCopyCost.td (+2-4)
- (modified) llvm/test/TableGen/RegisterInfoEmitter-inherit-properties.td (+5-14)
- (modified) llvm/test/TableGen/RegisterInfoEmitter-tsflags.td (+4-4)
- (modified) llvm/unittests/CodeGen/MachineInstrTest.cpp (+3-3)
- (modified) llvm/utils/TableGen/RegisterInfoEmitter.cpp (+146-126)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/FastISel.h b/llvm/include/llvm/CodeGen/FastISel.h
index 454ed4126213f..02d2059d54785 100644
--- a/llvm/include/llvm/CodeGen/FastISel.h
+++ b/llvm/include/llvm/CodeGen/FastISel.h
@@ -54,7 +54,8 @@ class MCSymbol;
class TargetInstrInfo;
class TargetLibraryInfo;
class TargetMachine;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
class Type;
class User;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h
index 39c7ad2cf34ca..f54cbafc0dc37 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h
@@ -165,7 +165,8 @@ class LLVM_ABI GISelCSEInfo : public GISelChangeObserver {
void changedInstr(MachineInstr &MI) override;
};
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class RegisterBank;
// Simple builder class to easily profile properties about MIs.
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 511bc17161e03..ee533d2a8d8b8 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -34,7 +34,8 @@ class ConstantInt;
class DataLayout;
class GISelCSEInfo;
class GlobalValue;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class MachineFunction;
class MachineInstr;
class TargetInstrInfo;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index bd97f7f4812f8..93fc33a61eb06 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -49,7 +49,8 @@ class TargetInstrInfo;
class TargetLowering;
class TargetPassConfig;
class TargetRegisterInfo;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class ConstantFP;
class APFloat;
diff --git a/llvm/include/llvm/CodeGen/LiveStacks.h b/llvm/include/llvm/CodeGen/LiveStacks.h
index f2ecdca257bb1..2e5455bc671a8 100644
--- a/llvm/include/llvm/CodeGen/LiveStacks.h
+++ b/llvm/include/llvm/CodeGen/LiveStacks.h
@@ -30,7 +30,8 @@ class AnalysisUsage;
class MachineFunction;
class Module;
class raw_ostream;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
class LiveStacks {
diff --git a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
index d0604bbf59c5c..622862279cfdd 100644
--- a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
+++ b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
@@ -34,7 +34,8 @@ struct SlotMapping;
class SMDiagnostic;
class SourceMgr;
class StringRef;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetSubtargetInfo;
struct VRegInfo {
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index 0aa2bc1bf6cbb..47430a100b3cc 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -47,7 +47,8 @@ class StringRef;
class raw_ostream;
class LiveIntervals;
class LiveVariables;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
// This structure uniquely identifies a basic block section.
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index b3c814e1c3590..70b82bcd96b11 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -70,7 +70,8 @@ class PseudoSourceValueManager;
class raw_ostream;
class SlotIndexes;
class StringRef;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetSubtargetInfo;
struct WinEHFuncInfo;
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index f1f70f019a1b6..2efd3d4d6f095 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -58,7 +58,8 @@ template <typename T> class SmallVectorImpl;
class SmallBitVector;
class StringRef;
class TargetInstrInfo;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/include/llvm/CodeGen/MachineSSAUpdater.h b/llvm/include/llvm/CodeGen/MachineSSAUpdater.h
index ee576cb872ee3..64980b8022829 100644
--- a/llvm/include/llvm/CodeGen/MachineSSAUpdater.h
+++ b/llvm/include/llvm/CodeGen/MachineSSAUpdater.h
@@ -24,7 +24,8 @@ class MachineInstr;
class MachineOperand;
class MachineRegisterInfo;
class TargetInstrInfo;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
template<typename T> class SmallVectorImpl;
template<typename T> class SSAUpdaterTraits;
diff --git a/llvm/include/llvm/CodeGen/RegAllocCommon.h b/llvm/include/llvm/CodeGen/RegAllocCommon.h
index 6c5cb295f5290..7ecf8bebd3fb2 100644
--- a/llvm/include/llvm/CodeGen/RegAllocCommon.h
+++ b/llvm/include/llvm/CodeGen/RegAllocCommon.h
@@ -14,7 +14,8 @@
namespace llvm {
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
class MachineRegisterInfo;
diff --git a/llvm/include/llvm/CodeGen/RegisterBank.h b/llvm/include/llvm/CodeGen/RegisterBank.h
index 97f9c35a388f2..52b229c697acd 100644
--- a/llvm/include/llvm/CodeGen/RegisterBank.h
+++ b/llvm/include/llvm/CodeGen/RegisterBank.h
@@ -20,7 +20,8 @@ namespace llvm {
// Forward declarations.
class RegisterBankInfo;
class raw_ostream;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
/// This class implements the register bank concept.
diff --git a/llvm/include/llvm/CodeGen/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/RegisterBankInfo.h
index 75153a4f840d2..825e06f429079 100644
--- a/llvm/include/llvm/CodeGen/RegisterBankInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterBankInfo.h
@@ -33,7 +33,8 @@ class MachineIRBuilder;
class MachineRegisterInfo;
class raw_ostream;
class TargetInstrInfo;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
/// Holds all the information related to register banks.
diff --git a/llvm/include/llvm/CodeGen/RegisterScavenging.h b/llvm/include/llvm/CodeGen/RegisterScavenging.h
index 9b2c92adb0a6f..3d8e9f5bdc122 100644
--- a/llvm/include/llvm/CodeGen/RegisterScavenging.h
+++ b/llvm/include/llvm/CodeGen/RegisterScavenging.h
@@ -28,7 +28,8 @@ namespace llvm {
class MachineInstr;
class TargetInstrInfo;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
class RegScavenger {
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index 902d6b83faadf..4638632815971 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -43,7 +43,8 @@ class SDNode;
class SUnit;
class ScheduleDAG;
class TargetInstrInfo;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
/// Scheduling dependency. This represents one direction of an edge in the
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 03f3bf26d0608..8f381c5efe2e2 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -63,7 +63,8 @@ class SelectionDAG;
class SMSchedule;
class SwingSchedulerDAG;
class RegScavenger;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
class TargetSchedModel;
class TargetSubtargetInfo;
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 09f522742da4e..75b1ca2d2745f 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -93,7 +93,8 @@ class Module;
class ProfileSummaryInfo;
class TargetLibraryInfo;
class TargetMachine;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
class TargetTransformInfo;
class Value;
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 183848b36e800..736aa8a5cf35a 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -43,162 +43,9 @@ class RegScavenger;
class VirtRegMap;
class LiveIntervals;
class LiveInterval;
-class TargetRegisterClass {
-public:
- using iterator = const MCPhysReg *;
- using const_iterator = const MCPhysReg *;
-
- // Instance variables filled by tablegen, do not use!
- const MCRegisterClass *MC;
- const uint32_t *SubClassMask;
- const uint16_t *SuperRegIndices;
- const LaneBitmask LaneMask;
- /// Classes with a higher priority value are assigned first by register
- /// allocators using a greedy heuristic. The value is in the range [0,31].
- const uint8_t AllocationPriority;
-
- // Change allocation priority heuristic used by greedy.
- const bool GlobalPriority;
-
- /// Configurable target specific flags.
- const uint8_t TSFlags;
- const uint8_t SpillStackID;
- /// Whether the class supports two (or more) disjunct subregister indices.
- const bool HasDisjunctSubRegs;
- /// Whether a combination of subregisters can cover every register in the
- /// class. See also the CoveredBySubRegs description in Target.td.
- const bool CoveredBySubRegs;
- const unsigned *SuperClasses;
- const uint16_t SuperClassesSize;
-
- /// Return the register class ID number.
- unsigned getID() const { return MC->getID(); }
-
- /// begin/end - Return all of the registers in this class.
- ///
- iterator begin() const { return MC->begin(); }
- iterator end() const { return MC->end(); }
-
- /// Return the number of registers in this class.
- unsigned getNumRegs() const { return MC->getNumRegs(); }
-
- ArrayRef<MCPhysReg> getRegisters() const {
- return ArrayRef(begin(), getNumRegs());
- }
-
- /// Return the specified register in the class.
- MCRegister getRegister(unsigned i) const {
- return MC->getRegister(i);
- }
-
- /// Return true if the specified register is included in this register class.
- /// This does not include virtual registers.
- bool contains(Register Reg) const {
- /// FIXME: Historically this function has returned false when given vregs
- /// but it should probably only receive physical registers
- if (!Reg.isPhysical())
- return false;
- return MC->contains(Reg.asMCReg());
- }
-
- /// Return true if both registers are in this class.
- bool contains(Register Reg1, Register Reg2) const {
- /// FIXME: Historically this function has returned false when given a vregs
- /// but it should probably only receive physical registers
- if (!Reg1.isPhysical() || !Reg2.isPhysical())
- return false;
- return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
- }
-
- /// Return the cost of copying a value between two registers in this class. If
- /// this is the maximum value, the register may be impossible to copy.
- uint8_t getCopyCost() const { return MC->getCopyCost(); }
-
- /// \return true if register class is very expensive to copy e.g. status flag
- /// register classes.
- bool expensiveOrImpossibleToCopy() const {
- return MC->getCopyCost() == std::numeric_limits<uint8_t>::max();
- }
-
- /// Return true if this register class may be used to create virtual
- /// registers.
- bool isAllocatable() const { return MC->isAllocatable(); }
-
- /// Return true if this register class has a defined BaseClassOrder.
- bool isBaseClass() const { return MC->isBaseClass(); }
-
- /// Return true if the specified TargetRegisterClass
- /// is a proper sub-class of this TargetRegisterClass.
- bool hasSubClass(const TargetRegisterClass *RC) const {
- return RC != this && hasSubClassEq(RC);
- }
- /// Returns true if RC is a sub-class of or equal to this class.
- bool hasSubClassEq(const TargetRegisterClass *RC) const {
- unsigned ID = RC->getID();
- return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
- }
-
- /// Return true if the specified TargetRegisterClass is a
- /// proper super-class of this TargetRegisterClass.
- bool hasSuperClass(const TargetRegisterClass *RC) const {
- return RC->hasSubClass(this);
- }
-
- /// Returns true if RC is a super-class of or equal to this class.
- bool hasSuperClassEq(const TargetRegisterClass *RC) const {
- return RC->hasSubClassEq(this);
- }
-
- /// Returns a bit vector of subclasses, including this one.
- /// The vector is indexed by class IDs.
- ///
- /// To use it, consider the returned array as a chunk of memory that
- /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
- /// contains a bitset of the ID of the subclasses in big-endian style.
-
- /// I.e., the representation of the memory from left to right at the
- /// bit level looks like:
- /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
- /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
- /// Where the number represents the class ID and XXX bits that
- /// should be ignored.
- ///
- /// See the implementation of hasSubClassEq for an example of how it
- /// can be used.
- const uint32_t *getSubClassMask() const {
- return SubClassMask;
- }
-
- /// Returns a 0-terminated list of sub-register indices that project some
- /// super-register class into this register class. The list has an entry for
- /// each Idx such that:
- ///
- /// There exists SuperRC where:
- /// For all Reg in SuperRC:
- /// this->contains(Reg:Idx)
- const uint16_t *getSuperRegIndices() const {
- return SuperRegIndices;
- }
-
- /// Returns a list of super-classes. The
- /// classes are ordered by ID which is also a topological ordering from large
- /// to small classes. The list does NOT include the current class.
- ArrayRef<unsigned> superclasses() const {
- return ArrayRef(SuperClasses, SuperClassesSize);
- }
-
- /// Return true if this TargetRegisterClass is a subset
- /// class of at least one other TargetRegisterClass.
- bool isASubClass() const { return SuperClasses != nullptr; }
-
- /// Returns the combination of all lane masks of register in this class.
- /// The lane masks of the registers are the combination of all lane masks
- /// of their subregisters. Returns 1 if there are no subregisters.
- LaneBitmask getLaneMask() const {
- return LaneMask;
- }
-};
+// TODO: Remove.
+using TargetRegisterClass = MCRegisterClass;
/// Extra information, not in MCRegisterDesc, about registers.
/// These are used by codegen, not by MC.
@@ -651,7 +498,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
/// index \p SubIdx is \p Reg.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
const TargetRegisterClass *RC) const {
- return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
+ return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC);
}
/// Return a subclass of the register class \p A so that each register in it
@@ -886,7 +733,7 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
/// Returns the name of the register class.
const char *getRegClassName(const TargetRegisterClass *Class) const {
- return MCRegisterInfo::getRegClassName(Class->MC);
+ return MCRegisterInfo::getRegClassName(Class);
}
/// Find the largest common subclass of A and B.
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index fb0589e2c446e..8b8f64f49b595 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -52,7 +52,8 @@ class SUnit;
class TargetFrameLowering;
class TargetInstrInfo;
class TargetLowering;
-class TargetRegisterClass;
+class MCRegisterClass;
+using TargetRegisterClass = MCRegisterClass;
class TargetRegisterInfo;
class TargetSchedModel;
class Triple;
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 499dd6d6afda9..dac8f84119dc3 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -39,6 +39,9 @@ class MCRegisterClass {
using iterator = const MCPhysReg*;
using const_iterator = const MCPhysReg*;
+ MCRegisterClass(const MCRegisterClass &) = delete;
+
+ // TODO: reorder fields to reduce memory usage.
const uint32_t RegsOff; ///< Relative offset to MCPhysReg array.
const uint32_t RegSetOff; ///< Relative offset to uint8_t array.
const uint32_t NameIdx;
@@ -50,6 +53,27 @@ class MCRegisterClass {
const bool Allocatable;
const bool BaseClass;
+ const uint32_t SubClassMaskOff; ///< Relative offset to uin32t_t array.
+ const uint32_t SuperRegIndicesOff; ///< Relative offset to MCPhysReg array.
+ const LaneBitmask LaneMask;
+ /// Classes with a higher priority value are assigned first by register
+ /// allocators using a greedy heuristic. The value is in the range [0,31].
+ const uint8_t AllocationPriority;
+
+ // Change allocation priority heuristic used by greedy.
+ const bool GlobalPriority;
+
+ /// Configurable target specific flags.
+ const uint8_t TSFlags;
+ const uint8_t SpillStackID;
+ /// Whether the class supports two (or more) disjunct subregister indices.
+ const bool HasDisjunctSubRegs;
+ /// Whether a combination of subregisters can cover every register in the
+ /// class. See also the CoveredBySubRegs description in Target.td.
+ const bool CoveredBySubRegs;
+ const uint32_t SuperClassesOff; ///< Relative offset to unsigned array.
+ const uint16_t SuperClassesSize;
+
/// getID() - Return the register class ID number.
///
unsigned getID() const { return ID; }
@@ -73,6 +97,10 @@ class MCRegisterClass {
return begin()[i];
}
+ ArrayRef<MCPhysReg> getRegisters() const {
+ return ArrayRef(begin(), RegsSize);
+ }
+
/// contains - Return true if the specified register is included in this
/// register class. This does not include virtual registers.
bool contains(MCRegister Reg) const {
@@ -101,19 +129,101 @@ class MCRegisterClass {
/// to copy e.g. status flag register classes.
uint8_t getCopyCost() const { return CopyCost; }
+ /// \return true if register class is very expensive to copy e.g. status flag
+ /// register classes.
+ bool expensiveOrImpossibleToCopy() const {
+ return CopyCost == std::numeric_limits<uint8_t>::max();
+ }
+
/// isAllocatable - Return true if this register class may be used to create
/// virtual registers.
bool isAllocatable() const { return Allocatable; }
/// Return true if this register class has a defined BaseClassOrder.
bool isBaseClass() const { return BaseClass; }
+
+ /// Return true if the specified TargetRegisterClass
+ /// is a proper sub-class of this TargetRegisterClass.
+ bool hasSubClass(const MCRegisterClass *RC) const {
+ return RC != this && hasSubClassEq(RC);
+ }
+
+ /// Returns true if RC is a sub-class of or equal to this class.
+ bool hasSubClassEq(const MCRegisterClass *RC) const {
+ unsigned ID = RC->getID();
+ return (getSubClassMask()[ID / 32] >> (ID % 32)) & 1;
+ }
+
+ /// Return true if the specified MCRegisterClass is a
+ /// proper super-class of this MCRegisterClass.
+ bool hasSuperClass(const MCRegisterClass *RC) const {
+ return RC->hasSubClass(this);
+ }
+
+ /// Returns true if RC is a super-class of or equal to this class.
+ bool hasSuperClassEq(const MCRegisterClass *RC) const {
+ return RC->hasSubClassEq(this);
+ }
+
+ /// Returns a bit vector of subclasses, including this one.
+ /// The vector is ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/207168
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