[llvm] [LoongArch] Remove inaccurate LASX conversion pattern and use [X]VFFINT.S.L instead (PR #207107)

[via llvm-commits]

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@@ -8151,15 +8158,91 @@ static SDValue ExtendSrcToDst(SDNode *N, SelectionDAG &DAG, unsigned ExtendOp) {
   return DAG.getNode(N->getOpcode(), DL, VT, Extend);
 }
 
+// Merge two 64 to 32 convert instructions into one,
+// e.g.
+//   vffint.s.l $vr0, $vr1, $vr2
+// will convert 4 si64 into 4 float at once.
+// or
+//   vftintrz.w.d $vr0, $vr1, $vr2
+// which will convert 4 double into 4 si32 at once.
+// also deal with their 256-bits LASX version.
+static SDValue MergeBlocksConvert(SDNode *N, SelectionDAG &DAG, unsigned Opcode,
+                                  unsigned BlockBits) {
+  SDLoc DL(N);
+  MVT DstVT = N->getSimpleValueType(0);
+  SDValue Src = N->getOperand(0);
+  MVT SrcVT = Src.getSimpleValueType();
+  unsigned SrcBits = SrcVT.getSizeInBits();
+
+  SmallVector<SDValue, 8> Blocks;
+  unsigned BlockNumElts = BlockBits / SrcVT.getScalarSizeInBits();
+  MVT BlockVT = MVT::getVectorVT(SrcVT.getScalarType(), BlockNumElts);
+  if (Src.getOpcode() == ISD::CONCAT_VECTORS &&
+      Src.getOperand(0).getValueType() == BlockVT) {
+    for (unsigned i = 0; i < Src.getNumOperands(); i++)
+      Blocks.push_back(Src.getOperand(i));
+  } else if (SrcBits > BlockBits) {
+    // Wider than one register: extract each BlockBits-wide sub-vector.
+    for (unsigned i = 0; i < SrcBits / BlockBits; i++)
+      Blocks.push_back(
+          DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, BlockVT, Src,
+                      DAG.getVectorIdxConstant(i * BlockNumElts, DL)));
+  } else {
+    BlockBits = SrcBits;
+    Blocks.push_back(Src);
+  }
+
+  MVT NativeVT = MVT::getVectorVT(DstVT.getScalarType(),
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wangleiat wrote:

Maybe rename this to `NativeVecVT` for clarity.

https://github.com/llvm/llvm-project/pull/207107