[llvm] [RISCV][XCV] Add LLVM intrinsics for non-representable XCVsimd ops (PR #204880)

[Craig Topper via llvm-commits]

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@@ -94,4 +142,83 @@ let TargetPrefix = "riscv" in {
   def int_riscv_cv_elw_elw
     : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
                 [IntrReadMem, IntrArgMemOnly, IntrHasSideEffects]>;
+
+  // ==== XCVsimd — ADD/SUB ====
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topperc wrote:

Can we drop these empty sections?

https://github.com/llvm/llvm-project/pull/204880