[llvm] [RISCV] Use VECREDUCE_OR instead of VP_REDUCE_OR in combineVectorSizedSetCCEquality. NFCish (PR #207122)

[Luke Lau via llvm-commits]

lukel97 wrote:

Does a fixed vector vecreduce get widened to a vp_reduce during type legalisation? Similar to what we do for loads. Or does it just get the input vector padded with identity ops?

https://github.com/llvm/llvm-project/pull/207122