[llvm] 672dfe9 - [RISCV] Add HasStdExtH to hfence.gvma and hfence.vvma aliases (#207061)

[via llvm-commits]

Author: Craig Topper
Date: 2026-07-01T22:22:49-07:00
New Revision: 672dfe90adb57d5b173d17b9f6a8b9f4c36cbb93

URL: https://github.com/llvm/llvm-project/commit/672dfe90adb57d5b173d17b9f6a8b9f4c36cbb93
DIFF: https://github.com/llvm/llvm-project/commit/672dfe90adb57d5b173d17b9f6a8b9f4c36cbb93.diff

LOG: [RISCV] Add HasStdExtH to hfence.gvma and hfence.vvma aliases (#207061)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/test/MC/RISCV/priv-invalid.s
    llvm/test/MC/RISCV/rv32h-invalid.s
    llvm/test/MC/RISCV/rv64h-invalid.s

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 7b72dfbbad91e..c136560532142 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1159,11 +1159,13 @@ def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0), 2>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
+let Predicates = [HasStdExtH] in {
 def : InstAlias<"hfence.gvma",     (HFENCE_GVMA      X0, X0), 2>;
 def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>;
 
 def : InstAlias<"hfence.vvma",     (HFENCE_VVMA      X0, X0), 2>;
 def : InstAlias<"hfence.vvma $rs", (HFENCE_VVMA GPR:$rs, X0)>;
+}
 
 // ntl.* hints are always available in the assembler and disassembler, even
 // without enabling Zihintntl, per psABI decision

diff  --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s
index 9c07d3e58b14f..273f90ea9a6f6 100644
--- a/llvm/test/MC/RISCV/priv-invalid.s
+++ b/llvm/test/MC/RISCV/priv-invalid.s
@@ -14,13 +14,19 @@ sfence.w.inval 0x10 # CHECK: :[[@LINE]]:1: error: invalid instruction
 
 sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:1: error: invalid instruction
 
-hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
+hfence.vvma zero, a1, a2
+# CHECK: :[[#@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[#@LINE-2]]:13: note: invalid operand for instruction
+# CHECK: :[[#@LINE-3]]:19: note: invalid operand for instruction
 
-hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 
-hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
+hfence.gvma zero, a1, a2
+# CHECK: :[[#@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[#@LINE-2]]:13: note: invalid operand for instruction
+# CHECK: :[[#@LINE-3]]:19: note: invalid operand for instruction
 
-hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 
 hinval.vvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
 

diff  --git a/llvm/test/MC/RISCV/rv32h-invalid.s b/llvm/test/MC/RISCV/rv32h-invalid.s
index 1128b22195bb8..5ce966bfe2b33 100644
--- a/llvm/test/MC/RISCV/rv32h-invalid.s
+++ b/llvm/test/MC/RISCV/rv32h-invalid.s
@@ -3,10 +3,17 @@
 # RUN: not llvm-mc -triple riscv32 < %s 2>&1 \
 # RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-OFFSET
 
-hfence.vvma zero, zero
-# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:19: note: invalid operand for instruction
-# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'H' (Hypervisor)
+hfence.gvma zero, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.gvma zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.gvma # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.vvma zero, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.vvma zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.vvma # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
 
 hlv.h   a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
 

diff  --git a/llvm/test/MC/RISCV/rv64h-invalid.s b/llvm/test/MC/RISCV/rv64h-invalid.s
index 080996b561cb3..94a642b980357 100644
--- a/llvm/test/MC/RISCV/rv64h-invalid.s
+++ b/llvm/test/MC/RISCV/rv64h-invalid.s
@@ -3,10 +3,17 @@
 # RUN: not llvm-mc -triple riscv64 < %s 2>&1 \
 # RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-OFFSET
 
-hfence.vvma zero, zero
-# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:19: note: invalid operand for instruction
-# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'H' (Hypervisor)
+hfence.gvma zero, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.gvma zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.gvma # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.vvma zero, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.vvma zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
+
+hfence.vvma # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
 
 hlv.h   a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)