[llvm] [X86] matchUnaryShuffle - only prefer VZEXT_MOVL to VPMOVZX if it will fold away (PR #207031)
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Wed Jul 1 09:47:26 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Clean up the logic matching VZEXT_MOVL in preference over VPMOVZX - we should only use this if the source vector is GPR->FPU or a single element load (or any type including target loads), which fold away to an implicit zero extension.
Pre-SSE41 targets will attempt to match VZEXT_MOVL again more generally later on.
---
Patch is 69.10 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/207031.diff
8 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+13-17)
- (modified) llvm/test/CodeGen/X86/buildvec-extract.ll (+2-4)
- (modified) llvm/test/CodeGen/X86/clmul-vector-256.ll (+164-166)
- (modified) llvm/test/CodeGen/X86/clmul-vector-512.ll (+148-150)
- (modified) llvm/test/CodeGen/X86/clmul-vector.ll (+99-106)
- (modified) llvm/test/CodeGen/X86/combine-or-shuffle.ll (+15-16)
- (modified) llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll (+12-18)
- (modified) llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll (+5-7)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 50de468045bbe..07a2b692ba94a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -40200,19 +40200,16 @@ static bool matchUnaryShuffle(MVT MaskVT, ArrayRef<int> Mask,
unsigned NumMaskElts = Mask.size();
unsigned MaskEltSize = MaskVT.getScalarSizeInBits();
- // Match against a VZEXT_MOVL vXi32 and vXi16 zero-extending instruction.
- if (Mask[0] == 0 &&
- (MaskEltSize == 32 || (MaskEltSize == 16 && Subtarget.hasFP16()))) {
- if ((isUndefOrZero(Mask[1]) && isUndefInRange(Mask, 2, NumMaskElts - 2)) ||
- (V1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
- isUndefOrZeroInRange(Mask, 1, NumMaskElts - 1))) {
- Shuffle = X86ISD::VZEXT_MOVL;
- if (MaskEltSize == 16)
- SrcVT = DstVT = MaskVT.changeVectorElementType(MVT::f16);
- else
- SrcVT = DstVT = !Subtarget.hasSSE2() ? MVT::v4f32 : MaskVT;
- return true;
- }
+ // Match against a foldable vXi32/vXi16 VZEXT_MOVL zero-extending instruction.
+ if (Mask[0] == 0 && isUndefOrZeroInRange(Mask, 1, NumMaskElts - 1) &&
+ (MaskEltSize == 32 || (MaskEltSize == 16 && Subtarget.hasFP16())) &&
+ (V1.getOpcode() == ISD::SCALAR_TO_VECTOR || isa<MemSDNode>(V1))) {
+ Shuffle = X86ISD::VZEXT_MOVL;
+ if (MaskEltSize == 16)
+ SrcVT = DstVT = MaskVT.changeVectorElementType(MVT::f16);
+ else
+ SrcVT = DstVT = !Subtarget.hasSSE2() ? MVT::v4f32 : MaskVT;
+ return true;
}
// Match against a ANY/SIGN/ZERO_EXTEND_VECTOR_INREG instruction.
@@ -40265,10 +40262,9 @@ static bool matchUnaryShuffle(MVT MaskVT, ArrayRef<int> Mask,
}
// Match against a VZEXT_MOVL instruction, SSE1 only supports 32-bits (MOVSS).
- if (((MaskEltSize == 32) || (MaskEltSize == 64 && Subtarget.hasSSE2()) ||
- (MaskEltSize == 16 && Subtarget.hasFP16())) &&
- isUndefOrEqual(Mask[0], 0) &&
- isUndefOrZeroInRange(Mask, 1, NumMaskElts - 1)) {
+ if (Mask[0] == 0 && isUndefOrZeroInRange(Mask, 1, NumMaskElts - 1) &&
+ ((MaskEltSize == 32) || (MaskEltSize == 64 && Subtarget.hasSSE2()) ||
+ (MaskEltSize == 16 && Subtarget.hasFP16()))) {
Shuffle = X86ISD::VZEXT_MOVL;
if (MaskEltSize == 16)
SrcVT = DstVT = MaskVT.changeVectorElementType(MVT::f16);
diff --git a/llvm/test/CodeGen/X86/buildvec-extract.ll b/llvm/test/CodeGen/X86/buildvec-extract.ll
index 9d856ed7647ca..979247ae906af 100644
--- a/llvm/test/CodeGen/X86/buildvec-extract.ll
+++ b/llvm/test/CodeGen/X86/buildvec-extract.ll
@@ -208,15 +208,13 @@ define <2 x i64> @extract0_i32_zext_insert1_i64_zero(<4 x i32> %x) {
;
; SSE41-LABEL: extract0_i32_zext_insert1_i64_zero:
; SSE41: # %bb.0:
-; SSE41-NEXT: pxor %xmm1, %xmm1
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
+; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; SSE41-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE41-NEXT: retq
;
; AVX-LABEL: extract0_i32_zext_insert1_i64_zero:
; AVX: # %bb.0:
-; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
+; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; AVX-NEXT: retq
%e = extractelement <4 x i32> %x, i32 0
diff --git a/llvm/test/CodeGen/X86/clmul-vector-256.ll b/llvm/test/CodeGen/X86/clmul-vector-256.ll
index 3c0929f70560a..0820dafd55bdd 100644
--- a/llvm/test/CodeGen/X86/clmul-vector-256.ll
+++ b/llvm/test/CodeGen/X86/clmul-vector-256.ll
@@ -1260,19 +1260,19 @@ define <16 x i16> @clmulr_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
define <8 x i32> @clmulr_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1-LABEL: clmulr_v8i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm1[0,1],xmm4[2,3,4,5,6,7]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm0[0,1],xmm4[2,3,4,5,6,7]
+; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm2
+; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm3
; AVX1-NEXT: vpclmulqdq $0, %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vmovq %xmm2, %rax
; AVX1-NEXT: shrq $32, %rax
-; AVX1-NEXT: vmovd %eax, %xmm2
-; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
-; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm5
-; AVX1-NEXT: vpclmulqdq $0, %xmm3, %xmm5, %xmm3
-; AVX1-NEXT: vmovq %xmm3, %rax
-; AVX1-NEXT: shrq $32, %rax
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero
+; AVX1-NEXT: vpclmulqdq $0, %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vmovq %xmm2, %rcx
+; AVX1-NEXT: shrq $32, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm2
; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
+; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm0[2],xmm4[2],xmm0[3],xmm4[3]
; AVX1-NEXT: vpclmulqdq $0, %xmm3, %xmm5, %xmm3
@@ -1287,18 +1287,18 @@ define <8 x i32> @clmulr_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1-NEXT: vpinsrd $3, %eax, %xmm2, %xmm2
; AVX1-NEXT: vpaddd %xmm2, %xmm2, %xmm5
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; AVX1-NEXT: vpblendw {{.*#+}} xmm6 = xmm2[0,1],xmm4[2,3,4,5,6,7]
+; AVX1-NEXT: vpsrlq $32, %xmm2, %xmm6
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
-; AVX1-NEXT: vpblendw {{.*#+}} xmm7 = xmm3[0,1],xmm4[2,3,4,5,6,7]
+; AVX1-NEXT: vpsrlq $32, %xmm3, %xmm7
; AVX1-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
; AVX1-NEXT: vmovq %xmm6, %rax
; AVX1-NEXT: shrq $32, %rax
-; AVX1-NEXT: vmovd %eax, %xmm6
-; AVX1-NEXT: vpsrlq $32, %xmm2, %xmm7
-; AVX1-NEXT: vpsrlq $32, %xmm3, %xmm8
-; AVX1-NEXT: vpclmulqdq $0, %xmm7, %xmm8, %xmm7
-; AVX1-NEXT: vmovq %xmm7, %rax
-; AVX1-NEXT: shrq $32, %rax
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm2[0],zero,xmm2[1],zero
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm7 = xmm3[0],zero,xmm3[1],zero
+; AVX1-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
+; AVX1-NEXT: vmovq %xmm6, %rcx
+; AVX1-NEXT: shrq $32, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm6
; AVX1-NEXT: vpinsrd $1, %eax, %xmm6, %xmm6
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm2[2],xmm4[2],xmm2[3],xmm4[3]
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm3[2],xmm4[2],xmm3[3],xmm4[3]
@@ -1349,20 +1349,20 @@ define <8 x i32> @clmulr_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX2-LABEL: clmulr_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX2-NEXT: vpblendd {{.*#+}} xmm5 = xmm2[0],xmm4[1,2,3]
+; AVX2-NEXT: vpsrlq $32, %xmm2, %xmm4
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
-; AVX2-NEXT: vpblendd {{.*#+}} xmm6 = xmm3[0],xmm4[1,2,3]
-; AVX2-NEXT: vpclmulqdq $0, %xmm5, %xmm6, %xmm5
-; AVX2-NEXT: vmovq %xmm5, %rax
-; AVX2-NEXT: shrq $32, %rax
-; AVX2-NEXT: vmovd %eax, %xmm5
-; AVX2-NEXT: vpsrlq $32, %xmm2, %xmm6
-; AVX2-NEXT: vpsrlq $32, %xmm3, %xmm7
-; AVX2-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
-; AVX2-NEXT: vmovq %xmm6, %rax
+; AVX2-NEXT: vpsrlq $32, %xmm3, %xmm5
+; AVX2-NEXT: vpclmulqdq $0, %xmm4, %xmm5, %xmm4
+; AVX2-NEXT: vmovq %xmm4, %rax
; AVX2-NEXT: shrq $32, %rax
-; AVX2-NEXT: vpinsrd $1, %eax, %xmm5, %xmm5
+; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm2[0],zero,xmm2[1],zero
+; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm3[0],zero,xmm3[1],zero
+; AVX2-NEXT: vpclmulqdq $0, %xmm4, %xmm5, %xmm4
+; AVX2-NEXT: vmovq %xmm4, %rcx
+; AVX2-NEXT: shrq $32, %rcx
+; AVX2-NEXT: vmovd %ecx, %xmm4
+; AVX2-NEXT: vpinsrd $1, %eax, %xmm4, %xmm5
+; AVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX2-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm2[2],xmm4[2],xmm2[3],xmm4[3]
; AVX2-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm3[2],xmm4[2],xmm3[3],xmm4[3]
; AVX2-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
@@ -1375,17 +1375,17 @@ define <8 x i32> @clmulr_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX2-NEXT: vmovq %xmm6, %rax
; AVX2-NEXT: shrq $32, %rax
; AVX2-NEXT: vpinsrd $3, %eax, %xmm5, %xmm5
-; AVX2-NEXT: vpblendd {{.*#+}} xmm6 = xmm1[0],xmm4[1,2,3]
-; AVX2-NEXT: vpblendd {{.*#+}} xmm7 = xmm0[0],xmm4[1,2,3]
+; AVX2-NEXT: vpsrlq $32, %xmm1, %xmm6
+; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm7
; AVX2-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
; AVX2-NEXT: vmovq %xmm6, %rax
; AVX2-NEXT: shrq $32, %rax
-; AVX2-NEXT: vmovd %eax, %xmm6
-; AVX2-NEXT: vpsrlq $32, %xmm1, %xmm7
-; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm8
-; AVX2-NEXT: vpclmulqdq $0, %xmm7, %xmm8, %xmm7
-; AVX2-NEXT: vmovq %xmm7, %rax
-; AVX2-NEXT: shrq $32, %rax
+; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm1[0],zero,xmm1[1],zero
+; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm7 = xmm0[0],zero,xmm0[1],zero
+; AVX2-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
+; AVX2-NEXT: vmovq %xmm6, %rcx
+; AVX2-NEXT: shrq $32, %rcx
+; AVX2-NEXT: vmovd %ecx, %xmm6
; AVX2-NEXT: vpinsrd $1, %eax, %xmm6, %xmm6
; AVX2-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]
; AVX2-NEXT: vpunpckhdq {{.*#+}} xmm4 = xmm0[2],xmm4[2],xmm0[3],xmm4[3]
@@ -1435,58 +1435,57 @@ define <8 x i32> @clmulr_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX512-LABEL: clmulr_v8i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX512-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX512-NEXT: vpblendd {{.*#+}} xmm5 = xmm2[0],xmm4[1,2,3]
+; AVX512-NEXT: vpsrlq $32, %xmm2, %xmm4
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm3
-; AVX512-NEXT: vpblendd {{.*#+}} xmm6 = xmm3[0],xmm4[1,2,3]
-; AVX512-NEXT: vpclmulqdq $0, %xmm5, %xmm6, %xmm5
-; AVX512-NEXT: vmovq %xmm5, %rax
+; AVX512-NEXT: vpsrlq $32, %xmm3, %xmm5
+; AVX512-NEXT: vpclmulqdq $0, %xmm4, %xmm5, %xmm4
+; AVX512-NEXT: vmovq %xmm4, %rax
; AVX512-NEXT: shrq $32, %rax
-; AVX512-NEXT: vmovd %eax, %xmm5
-; AVX512-NEXT: vpsrlq $32, %xmm2, %xmm6
-; AVX512-NEXT: vpsrlq $32, %xmm3, %xmm7
+; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm2[0],zero,xmm2[1],zero
+; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm3[0],zero,xmm3[1],zero
+; AVX512-NEXT: vpclmulqdq $0, %xmm4, %xmm5, %xmm4
+; AVX512-NEXT: vmovq %xmm4, %rcx
+; AVX512-NEXT: shrq $32, %rcx
+; AVX512-NEXT: vmovd %ecx, %xmm4
+; AVX512-NEXT: vpinsrd $1, %eax, %xmm4, %xmm4
+; AVX512-NEXT: vpxor %xmm5, %xmm5, %xmm5
+; AVX512-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm2[2],xmm5[2],xmm2[3],xmm5[3]
+; AVX512-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm3[2],xmm5[2],xmm3[3],xmm5[3]
; AVX512-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
; AVX512-NEXT: vmovq %xmm6, %rax
; AVX512-NEXT: shrq $32, %rax
-; AVX512-NEXT: vpinsrd $1, %eax, %xmm5, %xmm5
-; AVX512-NEXT: vpxor %xmm6, %xmm6, %xmm6
-; AVX512-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm2[2],xmm6[2],xmm2[3],xmm6[3]
-; AVX512-NEXT: vpunpckhdq {{.*#+}} xmm8 = xmm3[2],xmm6[2],xmm3[3],xmm6[3]
-; AVX512-NEXT: vpclmulqdq $0, %xmm7, %xmm8, %xmm7
-; AVX512-NEXT: vmovq %xmm7, %rax
-; AVX512-NEXT: shrq $32, %rax
-; AVX512-NEXT: vpinsrd $2, %eax, %xmm5, %xmm5
-; AVX512-NEXT: vpsrldq {{.*#+}} xmm7 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX512-NEXT: vpsrldq {{.*#+}} xmm8 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX512-NEXT: vpclmulqdq $0, %xmm7, %xmm8, %xmm7
-; AVX512-NEXT: vmovq %xmm7, %rax
-; AVX512-NEXT: shrq $32, %rax
-; AVX512-NEXT: vpinsrd $3, %eax, %xmm5, %xmm5
-; AVX512-NEXT: vpblendd {{.*#+}} xmm7 = xmm1[0],xmm4[1,2,3]
-; AVX512-NEXT: vpblendd {{.*#+}} xmm4 = xmm0[0],xmm4[1,2,3]
-; AVX512-NEXT: vpclmulqdq $0, %xmm7, %xmm4, %xmm4
-; AVX512-NEXT: vmovq %xmm4, %rax
-; AVX512-NEXT: shrq $32, %rax
-; AVX512-NEXT: vmovd %eax, %xmm4
-; AVX512-NEXT: vpsrlq $32, %xmm1, %xmm7
-; AVX512-NEXT: vpsrlq $32, %xmm0, %xmm8
-; AVX512-NEXT: vpclmulqdq $0, %xmm7, %xmm8, %xmm7
-; AVX512-NEXT: vmovq %xmm7, %rax
+; AVX512-NEXT: vpinsrd $2, %eax, %xmm4, %xmm4
+; AVX512-NEXT: vpsrldq {{.*#+}} xmm6 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX512-NEXT: vpsrldq {{.*#+}} xmm7 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX512-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
+; AVX512-NEXT: vmovq %xmm6, %rax
; AVX512-NEXT: shrq $32, %rax
-; AVX512-NEXT: vpinsrd $1, %eax, %xmm4, %xmm4
-; AVX512-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm1[2],xmm6[2],xmm1[3],xmm6[3]
-; AVX512-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm0[2],xmm6[2],xmm0[3],xmm6[3]
-; AVX512-NEXT: vpclmulqdq $0, %xmm7, %xmm6, %xmm6
+; AVX512-NEXT: vpinsrd $3, %eax, %xmm4, %xmm4
+; AVX512-NEXT: vpsrlq $32, %xmm1, %xmm6
+; AVX512-NEXT: vpsrlq $32, %xmm0, %xmm7
+; AVX512-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
; AVX512-NEXT: vmovq %xmm6, %rax
; AVX512-NEXT: shrq $32, %rax
-; AVX512-NEXT: vpinsrd $2, %eax, %xmm4, %xmm4
+; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm1[0],zero,xmm1[1],zero
+; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm7 = xmm0[0],zero,xmm0[1],zero
+; AVX512-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
+; AVX512-NEXT: vmovq %xmm6, %rcx
+; AVX512-NEXT: shrq $32, %rcx
+; AVX512-NEXT: vmovd %ecx, %xmm6
+; AVX512-NEXT: vpinsrd $1, %eax, %xmm6, %xmm6
+; AVX512-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm1[2],xmm5[2],xmm1[3],xmm5[3]
+; AVX512-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm0[2],xmm5[2],xmm0[3],xmm5[3]
+; AVX512-NEXT: vpclmulqdq $0, %xmm7, %xmm5, %xmm5
+; AVX512-NEXT: vmovq %xmm5, %rax
+; AVX512-NEXT: shrq $32, %rax
+; AVX512-NEXT: vpinsrd $2, %eax, %xmm6, %xmm5
; AVX512-NEXT: vpsrldq {{.*#+}} xmm6 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512-NEXT: vpsrldq {{.*#+}} xmm7 = xmm0[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
; AVX512-NEXT: vmovq %xmm6, %rax
; AVX512-NEXT: shrq $32, %rax
-; AVX512-NEXT: vpinsrd $3, %eax, %xmm4, %xmm4
-; AVX512-NEXT: vinserti128 $1, %xmm5, %ymm4, %ymm4
+; AVX512-NEXT: vpinsrd $3, %eax, %xmm5, %xmm5
+; AVX512-NEXT: vinserti128 $1, %xmm4, %ymm5, %ymm4
; AVX512-NEXT: vpaddd %ymm4, %ymm4, %ymm4
; AVX512-NEXT: vpclmulqdq $0, %xmm2, %xmm3, %xmm5
; AVX512-NEXT: vpshufd {{.*#+}} xmm6 = xmm2[1,1,1,1]
@@ -2253,43 +2252,43 @@ define <8 x i32> @clmulh_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX1-LABEL: clmulh_v8i32:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
-; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm3[0,1],xmm2[2,3,4,5,6,7]
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
-; AVX1-NEXT: vpblendw {{.*#+}} xmm6 = xmm5[0,1],xmm2[2,3,4,5,6,7]
-; AVX1-NEXT: vpclmulqdq $0, %xmm4, %xmm6, %xmm4
-; AVX1-NEXT: vmovq %xmm4, %rax
-; AVX1-NEXT: shrq $32, %rax
-; AVX1-NEXT: vmovd %eax, %xmm4
-; AVX1-NEXT: vpsrlq $32, %xmm3, %xmm6
-; AVX1-NEXT: vpsrlq $32, %xmm5, %xmm7
-; AVX1-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
-; AVX1-NEXT: vmovq %xmm6, %rax
+; AVX1-NEXT: vpsrlq $32, %xmm3, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT: vpsrlq $32, %xmm4, %xmm5
+; AVX1-NEXT: vpclmulqdq $0, %xmm2, %xmm5, %xmm2
+; AVX1-NEXT: vmovq %xmm2, %rax
; AVX1-NEXT: shrq $32, %rax
-; AVX1-NEXT: vpinsrd $1, %eax, %xmm4, %xmm4
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm3[0],zero,xmm3[1],zero
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm4[0],zero,xmm4[1],zero
+; AVX1-NEXT: vpclmulqdq $0, %xmm2, %xmm5, %xmm2
+; AVX1-NEXT: vmovq %xmm2, %rcx
+; AVX1-NEXT: shrq $32, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm2
+; AVX1-NEXT: vpinsrd $1, %eax, %xmm2, %xmm5
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm3[2],xmm2[2],xmm3[3],xmm2[3]
-; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm5[2],xmm2[2],xmm5[3],xmm2[3]
+; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm4[2],xmm2[2],xmm4[3],xmm2[3]
; AVX1-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
; AVX1-NEXT: vmovq %xmm6, %rax
; AVX1-NEXT: shrq $32, %rax
-; AVX1-NEXT: vpinsrd $2, %eax, %xmm4, %xmm4
+; AVX1-NEXT: vpinsrd $2, %eax, %xmm5, %xmm5
; AVX1-NEXT: vpsrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX1-NEXT: vpsrldq {{.*#+}} xmm5 = xmm5[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX1-NEXT: vpclmulqdq $0, %xmm3, %xmm5, %xmm3
+; AVX1-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX1-NEXT: vpclmulqdq $0, %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vmovq %xmm3, %rax
; AVX1-NEXT: shrq $32, %rax
-; AVX1-NEXT: vpinsrd $3, %eax, %xmm4, %xmm3
-; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm1[0,1],xmm2[2,3,4,5,6,7]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm5 = xmm0[0,1],xmm2[2,3,4,5,6,7]
+; AVX1-NEXT: vpinsrd $3, %eax, %xmm5, %xmm3
+; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm4
+; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm5
; AVX1-NEXT: vpclmulqdq $0, %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vmovq %xmm4, %rax
; AVX1-NEXT: shrq $32, %rax
-; AVX1-NEXT: vmovd %eax, %xmm4
-; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm5
-; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm6
-; AVX1-NEXT: vpclmulqdq $0, %xmm5, %xmm6, %xmm5
-; AVX1-NEXT: vmovq %xmm5, %rax
-; AVX1-NEXT: shrq $32, %rax
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm1[0],zero,xmm1[1],zero
+; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm0[0],zero,xmm0[1],zero
+; AVX1-NEXT: vpclmulqdq $0, %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vmovq %xmm4, %rcx
+; AVX1-NEXT: shrq $32, %rcx
+; AVX1-NEXT: vmovd %ecx, %xmm4
; AVX1-NEXT: vpinsrd $1, %eax, %xmm4, %xmm4
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm0[2],xmm2[2],xmm0[3],xmm2[3]
@@ -2309,43 +2308,43 @@ define <8 x i32> @clmulh_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; AVX2-LABEL: clmulh_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm3
-; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX2-NEXT: vpblendd {{.*#+}} xmm4 = xmm3[0],xmm2[1,2,3]
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm5
-; AVX2-NEXT: vpblendd {{.*#+}} xmm6 = xmm5[0],xmm2[1,2,3]
-; AVX2-NEXT: vpclmulqdq $0, %xmm4, %xmm6, %xmm4
-; AVX2-NEXT: vmovq %xmm4, %rax
-; AVX2-NEXT: shrq $32, %rax
-; AVX2-NEXT: vmovd %eax, %xmm4
-; AVX2-NEXT: vpsrlq $32, %xmm3, %xmm6
-; AVX2-NEXT: vpsrlq $32, %xmm5, %xmm7
-; AVX2-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
-; AVX2-NEXT: vmovq %xmm6, %rax
+; AVX2-NEXT: vpsrlq $32, %xmm3, %xmm2
+; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm4
+; AVX2-NEXT: vpsrlq $32, %xmm4, %xmm5
+; AVX2-NEXT: vpclmulqdq $0, %xmm2, %xmm5, %xmm2
+; AVX2-NEXT: vmovq %xmm2, %rax
; AVX2-NEXT: shrq $32, %rax
-; AVX2-NEXT: vpinsrd $1, %eax, %xmm4, %xmm4
+; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm3[0],zero,xmm3[1],zero
+; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm4[0],zero,xmm4[1],zero
+; AVX2-NEXT: vpclmulqdq $0, %xmm2, %xmm5, %xmm2
+; AVX2-NEXT: vmovq %xmm2, %rcx
+; AVX2-NEXT: shrq $32, %rcx
+; AVX2-NEXT: vmovd %ecx, %xmm2
+; AVX2-NEXT: vpinsrd $1, %eax, %xmm2, %xmm5
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm3[2],xmm2[2],xmm3[3],xmm2[3]
-; AVX2-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm5[2],xmm2[2],xmm5[3],xmm2[3]
+; AVX2-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm4[2],xmm2[2],xmm4[3],xmm2[3]
; AVX2-NEXT: vpclmulqdq $0, %xmm6, %xmm7, %xmm6
; AVX2-NEXT: vmovq %xmm6, %rax
; AVX2-NEXT: shrq $32, %rax
-; AVX2-NEXT: vpinsrd $2, %eax, %xmm4, %xmm4
+; AVX2-NEXT: vpinsrd $2, %eax, %xmm5, %xmm5
; AVX2-NEXT: vpsrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX2-NEXT: vpsrldq {{.*#+}} xmm5 = xmm5[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX2-NEXT: vpclmulqdq $0, %xmm3, %xmm5, %xmm3
+; AVX2-NEXT: vpsrldq {{.*#+}} xmm4 = xmm4[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; AVX2-NEXT: vpclmulqdq $0, %xmm...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/207031
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