[llvm] [AMDGPU] Avoid slow 64-bit max/min/multiply instructions on GFX1250 (PR #207006)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 1 08:13:03 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
On GFX1250 64-bit integer VALU max/min instructions are slower than
expanding to compare and select, and 64-bit integer VALU multiply is
slower than expanding to a sequence of 32-bit multiplies and adds. Avoid
them by pretending that these cases are not legal during instruction
selection.
---
Patch is 125.73 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/207006.diff
26 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+8-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+3-3)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (+3-3)
- (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.h (+12)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll (+56-36)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll (+6-1)
- (modified) llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll (+208-160)
- (modified) llvm/test/CodeGen/AMDGPU/clmul.ll (+67-69)
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll (+64-32)
- (modified) llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll (+194-64)
- (modified) llvm/test/CodeGen/AMDGPU/mad_64_32.ll (+26-37)
- (modified) llvm/test/CodeGen/AMDGPU/max.ll (+24-4)
- (modified) llvm/test/CodeGen/AMDGPU/min.ll (+24-4)
- (modified) llvm/test/CodeGen/AMDGPU/mul.ll (+52-51)
- (modified) llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll (+25-6)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 9da123c517b81..1a68de155bf88 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1217,6 +1217,11 @@ defm FlatSignedOffset : AMDGPUSubtargetFeature<"flat-signed-offset",
"Immediate offset of FLAT instructions are always signed"
>;
+defm SlowMaxMinMulI64Insts : AMDGPUSubtargetFeature<"slow-max-min-mul-i64-insts",
+ "64-bit integer max/min/mul VALU instructions are slower than expanding to an equivalent code sequence",
+ GenPredicate=false
+>;
+
//===------------------------------------------------------------===//
// Subtarget Features (options and debugging)
//===------------------------------------------------------------===//
@@ -2253,7 +2258,9 @@ def FeatureISAVersion12_50 : FeatureSet<
FeatureSWMMACGfx1200Insts,
FeatureSWMMACGfx1250Insts,
FeatureTransCoexecutionHazard,
- FeatureWMMACoexecutionHazards])>;
+ FeatureWMMACoexecutionHazards,
+ FeatureSlowMaxMinMulI64Insts,
+])>;
def FeatureISAVersion12_51 : FeatureSet<
!listconcat(FeatureISAVersion12_50_Common.Features,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 40dfa3aca26b6..8e77dec772097 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1468,7 +1468,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.widenScalarToNextPow2(0)
.scalarize(0)
.lower();
- if (ST.hasMinMaxI64Insts()) {
+ if (ST.useMinMaxI64Insts()) {
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
.legalFor({S32, S16, S64, V2S16})
.clampMaxNumElements(0, S16, 2)
@@ -4695,7 +4695,7 @@ bool AMDGPULegalizerInfo::legalizeMul(LegalizerHelper &Helper,
assert(Ty.isScalar());
unsigned Size = Ty.getSizeInBits();
- if (ST.hasVMulU64Inst() && Size == 64)
+ if (ST.useVMulU64Inst() && Size == 64)
return true;
unsigned NumParts = Size / 32;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 7f7225ad6d311..ff94bd9450696 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -613,7 +613,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
- bool HasVecMulU64 = ST->hasVMulU64Inst();
+ bool UseVecMulU64 = ST->useVMulU64Inst();
addRulesForGOpcs({G_MUL}, Standard)
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
@@ -622,8 +622,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}})
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
.Uni(S16, {{Sgpr32Trunc}, {Sgpr32AExt, Sgpr32AExt}})
- .Div(S64, {{VgprB64}, {VgprB64, VgprB64}}, HasVecMulU64)
- .Div(S64, {{VgprB64}, {VgprB64, VgprB64}, SplitTo32Mul}, !HasVecMulU64);
+ .Div(S64, {{VgprB64}, {VgprB64, VgprB64}}, UseVecMulU64)
+ .Div(S64, {{VgprB64}, {VgprB64, VgprB64}, SplitTo32Mul}, !UseVecMulU64);
bool hasMulHi = ST->hasScalarMulHiInsts();
addRulesForGOpcs({G_UMULH, G_SMULH}, Standard)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 200234c23c886..95280ebd2a907 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2529,7 +2529,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
// Special case for s_mul_u64. There is not a vector equivalent of
// s_mul_u64. Hence, we have to break down s_mul_u64 into 32-bit vector
// multiplications.
- if (!Subtarget.hasVMulU64Inst() && Opc == AMDGPU::G_MUL &&
+ if (!Subtarget.useVMulU64Inst() && Opc == AMDGPU::G_MUL &&
DstTy.getSizeInBits() == 64) {
applyMappingSMULU64(B, OpdMapper);
return;
@@ -4027,7 +4027,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[0] = getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size);
OpdsMapping[1] = OpdsMapping[2] = OpdsMapping[0];
} else {
- if (MI.getOpcode() == AMDGPU::G_MUL && Subtarget.hasVMulU64Inst())
+ if (MI.getOpcode() == AMDGPU::G_MUL && Subtarget.useVMulU64Inst())
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
else
OpdsMapping[0] =
@@ -4079,7 +4079,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
if (isSALUMapping(MI)) {
// There are no scalar 64-bit min and max, use vector instruction instead.
if (MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 64 &&
- Subtarget.hasMinMaxI64Insts())
+ Subtarget.useMinMaxI64Insts())
return getDefaultMappingVOP(MI);
return getDefaultMappingSOP(MI);
}
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 7e4d9bd20cb2f..01a838e7f0de5 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1042,6 +1042,18 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool requiresWaitOnWorkgroupReleaseFence() const {
return getGeneration() >= GFX10 || isTgSplitEnabled();
}
+
+ // \returns true if ISel should select the native i64 min/max instructions
+ // (V_MIN/MAX_{I|U}64).
+ bool useMinMaxI64Insts() const {
+ return hasMinMaxI64Insts() && !hasSlowMaxMinMulI64Insts();
+ }
+
+ // \returns true if ISel should select the native i64 mul instruction
+ // V_MUL_U64.
+ bool useVMulU64Inst() const {
+ return hasVMulU64Inst() && !hasSlowMaxMinMulI64Insts();
+ }
};
class GCNUserSGPRUsageInfo {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index b2f91e97fd426..bc5aa7efee1a5 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -950,7 +950,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom);
- if (Subtarget->hasVMulU64Inst())
+ if (Subtarget->useVMulU64Inst())
setOperationAction(ISD::MUL, MVT::i64, Legal);
else if (Subtarget->hasScalarSMulU64())
setOperationAction(ISD::MUL, MVT::i64, Custom);
@@ -985,7 +985,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
Custom);
}
- if (Subtarget->hasMinMaxI64Insts())
+ if (Subtarget->useMinMaxI64Insts())
setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i64,
Legal);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 48a85fdc01ea6..923d54cb13401 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7995,7 +7995,7 @@ void SIInstrInfo::moveToVALUImpl(
}
case AMDGPU::S_MUL_U64:
- if (ST.hasVMulU64Inst()) {
+ if (ST.useVMulU64Inst()) {
NewOpcode = AMDGPU::V_MUL_U64_e64;
break;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
index d9e3a8fc5e065..f68f50e6bc703 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
---
name: smax_s64_sv
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
index bf9d07008edc8..40af38df56f48 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
---
name: smin_s64_sv
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
index ed062db6a3060..ec42c3513a531 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
---
name: umax_s64_sv
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
index 5da10087ff74f..59291c663f0ab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1251 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
---
name: umin_s64_sv
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
index b5ec2ac393be7..48807bb502cf0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
@@ -87,8 +87,9 @@ body: |
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX1250-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX1250-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[COPY1]]
- ; GFX1250-NEXT: $vgpr0_vgpr1 = COPY [[SMAX]](s64)
+ ; GFX1250-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
+ ; GFX1250-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GFX1250-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_SMAX %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
index 3eaecf6b19883..0f9fb929ff9aa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
@@ -87,8 +87,9 @@ body: |
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX1250-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX1250-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[COPY1]]
- ; GFX1250-NEXT: $vgpr0_vgpr1 = COPY [[SMIN]](s64)
+ ; GFX1250-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; GFX1250-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GFX1250-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_SMIN %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
index f89425f5e91cb..19f86b4443375 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
@@ -87,8 +87,9 @@ body: |
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX1250-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX1250-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[COPY]], [[COPY1]]
- ; GFX1250-NEXT: $vgpr0_vgpr1 = COPY [[UMAX]](s64)
+ ; GFX1250-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
+ ; GFX1250-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GFX1250-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_UMAX %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
index e3dd7d4137806..e003dfb58377a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
@@ -87,8 +87,9 @@ body: |
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX1250-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX1250-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[COPY]], [[COPY1]]
- ; GFX1250-NEXT: $vgpr0_vgpr1 = COPY [[UMIN]](s64)
+ ; GFX1250-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+ ; GFX1250-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
+ ; GFX1250-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_UMIN %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
index 6a7725d19086a..a0cc2ae1d0ba8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
@@ -17,7 +17,8 @@ define i64 @test_umin_i64(i64 %a, i64 %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_min_u64 v[0:1], v[0:1], v[2:3]
+; CHECK-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; CHECK-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.umin.i64(i64 %a, i64 %b)
ret i64 %r
@@ -28,7 +29,8 @@ define i64 @test_umax_i64(i64 %a, i64 %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_max_u64 v[0:1], v[0:1], v[2:3]
+; CHECK-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
+; CHECK-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.umax.i64(i64 %a, i64 %b)
ret i64 %r
@@ -39,7 +41,8 @@ define i64 @test_smin_i64(i64 %a, i64 %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_min_i64 v[0:1], v[0:1], v[2:3]
+; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; CHECK-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.smin.i64(i64 %a, i64 %b)
ret i64 %r
@@ -50,7 +53,8 @@ define i64 @test_smax_i64(i64 %a, i64 %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_max_i64 v[0:1], v[0:1], v[2:3]
+; CHECK-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
+; CHECK-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.smax.i64(i64 %a, i64 %b)
ret i64 %r
@@ -61,10 +65,15 @@ define <4 x i64> @test_umin_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_min_u64 v[0:1], v[0:1], v[8:9]
-; CHECK-NEXT: v_min_u64 v[2:3], v[2:3], v[10:11]
-; CHECK-NEXT: v_min_u64 v[4:5], v[4:5], v[12:13]
-; CHECK-NEXT: v_min_u64 v[6:7], v[6:7], v[14:15]
+; CHECK-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; CHECK-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
+; CHECK-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[12:13]
+; CHECK-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; CHECK-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_dual_cndmask_b32 v2, v10, v2, s0 :: v_dual_cndmask_b32 v3, v11, v3, s0
+; CHECK-NEXT: v_dual_cndmask_b32 v4, v12, v4, s1 :: v_dual_cndmask_b32 v5, v13, v5, s1
+; CHECK-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %r
@@ -75,10 +84,15 @@ define <4 x i64> @test_umax_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_max_u64 v[0:1], v[0:1], v[8:9]
-; CHECK-NEXT: v_max_u64 v[2:3], v[2:3], v[10:11]
-; CHECK-NEXT: v_max_u64 v[4:5], v[4:5], v[12:13]
-; CHECK-NEXT: v_max_u64 v[6:7], v[6:7], v[14:15]
+; CHECK-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
+; CHECK-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
+; CHECK-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[12:13]
+; CHECK-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; CHECK-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_dual_cndmask_b32 v2, v10, v2, s0 :: v_dual_cndmask_b32 v3, v11, v3, s0
+; CHECK-NEXT: v_dual_cndmask_b32 v4, v12, v4, s1 :: v_dual_cndmask_b32 v5, v13, v5, s1
+; CHECK-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %r
@@ -89,10 +103,15 @@ define <4 x i64> @test_smin_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_min_i64 v[0:1], v[0:1], v[8:9]
-; CHECK-NEXT: v_min_i64 v[2:3], v[2:3], v[10:11]
-; CHECK-NEXT: v_min_i64 v[4:5], v[4:5], v[12:13]
-; CHECK-NEXT: v_min_i64 v[6:7], v[6:7], v[14:15]
+; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
+; CHECK-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
+; CHECK-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[12:13]
+; CHECK-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_dual_cndmask_b32 v2, v10, v2, s0 :: v_dual_cndmask_b32 v3, v11, v3, s0
+; CHECK-NEXT: v_dual_cndmask_b32 v4, v12, v4, s1 :: v_dual_cndmask_b32 v5, v13, v5, s1
+; CHECK-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %r
@@ -103,10 +122,15 @@ define <4 x i64> @test_smax_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_max_i64 v[0:1], v[0:1], v[8:9]
-; CHECK-NEXT: v_max_i64 v[2:3], v[2:3], v[10:11]
-; CHECK-NEXT: v_max_i64 v[4:5], v[4:5], v[12:13]
-; CHECK-NEXT: v_max_i64 v[6:7], v[6:7], v[14:15]
+; CHECK-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
+; CHECK-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
+; CHECK-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[12:13]
+; CHECK-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
+; CHECK-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; CHECK-NEXT: v_dual_cndmask_b32 v2, v10, v2, s0 :: v_dual_cndmask_b32 v3, v11, v3, s0
+; CHECK-NEXT: v_dual_cndmask_b32 v4, v12, v4, s1 :: v_dual_cndmask_b32 v5, v13, v5, s1
+; CHECK-NEXT: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/207006
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