[llvm] [AMDGPU][GlobalISel] Support lowering preloaded kernel arguments (PR #205049)

[Keshav Vinayak Jha via llvm-commits]

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@@ -0,0 +1,142 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stop-after=irtranslator -o - < %s | FileCheck -check-prefix=GFX90A %s
+
+define amdgpu_kernel void @preload_i32_inreg(i32 inreg %x, ptr addrspace(1) %out) #0 {
+  ; GFX90A-LABEL: name: preload_i32_inreg
+  ; GFX90A: bb.1 (%ir-block.0):
+  ; GFX90A-NEXT:   liveins: $sgpr6, $sgpr4_sgpr5
+  ; GFX90A-NEXT: {{  $}}
+  ; GFX90A-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
+  ; GFX90A-NEXT:   [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+  ; GFX90A-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
+  ; GFX90A-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+  ; GFX90A-NEXT:   [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+  ; GFX90A-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+  ; GFX90A-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+  ; GFX90A-NEXT:   [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+  ; GFX90A-NEXT:   G_STORE [[COPY3]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
+  ; GFX90A-NEXT:   S_ENDPGM 0
+  store i32 %x, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @preload_i64_inreg(i64 inreg %x, ptr addrspace(1) %out) #0 {
+  ; GFX90A-LABEL: name: preload_i64_inreg
+  ; GFX90A: bb.1 (%ir-block.0):
+  ; GFX90A-NEXT:   liveins: $sgpr4_sgpr5, $sgpr6_sgpr7
+  ; GFX90A-NEXT: {{  $}}
+  ; GFX90A-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
+  ; GFX90A-NEXT:   [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+  ; GFX90A-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]]
+  ; GFX90A-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
+  ; GFX90A-NEXT:   [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+  ; GFX90A-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+  ; GFX90A-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+  ; GFX90A-NEXT:   [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+  ; GFX90A-NEXT:   G_STORE [[COPY3]](s64), [[LOAD]](p1) :: (store (s64) into %ir.out.load, addrspace 1)
+  ; GFX90A-NEXT:   S_ENDPGM 0
+  store i64 %x, ptr addrspace(1) %out, align 8
+  ret void
+}
+
+define amdgpu_kernel void @preload_ptr_inreg(ptr addrspace(1) inreg %p, ptr addrspace(1) %out) #0 {
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keshavvinayak01 wrote:

Added.

https://github.com/llvm/llvm-project/pull/205049