[llvm] [BOLT][AArch64] Add support for LDR relaxtion on LDRSl/LDRDl/LDRQl (PR #196983)

[Shanzhi Chen via llvm-commits]

================
@@ -1852,7 +1857,8 @@ class MCPlusBuilder {
   ///     adrp x0, PageBase(label)
   ///     ldr  x0, [x0, PageOffset(label)]
   virtual InstructionListType createAdrpLdr(const MCInst &LDRInst,
-                                            MCContext *Ctx) const {
+                                            MCContext *Ctx,
+                                            MCPhysReg Reg = 0) const {
----------------
chenshanzhi wrote:

Thanks. Updated as suggested in latest commit a1c62963b85e06a7ede72661efbc35357a1a9169: 
1. The 3rd parameter is declared as `const MCPhysReg Reg = MCRegister::NoRegister`
2. Add an example for the FPR case in the comment above this declaration:
```
  /// For
  ///
  ///     ldr  q0, [label]
  ///
  /// the following sequence will be generated:
  ///
  ///     adrp Reg, PageBase(label)
  ///     ldr  q0, [Reg, PageOffset(label)]
  ///
  /// where Reg is provided by the 3rd argument.
```

https://github.com/llvm/llvm-project/pull/196983