[llvm] [RISCV] coalesce between VSETVLI and SF_VSETTNT (PR #203438)

[Piyou Chen via llvm-commits]

================
@@ -933,6 +936,109 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
   }
 }
 
+// When twiden != 0, LMUL, tail policy, and mask policy from the user are
+// ignored. The tail policy and mask policy are always treated as agnostic. The
+// normal RVV instruction will ignore the twiden parameter. This observation
+// could allow the RVV instruction and xsfmm instruction to share the same
+// configuration instruction.
+//
+// We need to make sure the AVL, SEW, and AltFmt is same between VSETVL and
+// VSETVLTN.
+//
+// For example:
+//
+// %avl = SETTM or SETTK
+// ...
+// VSETVL %avl, type1
+// VSETVLTNT %avl, type2
+//
+// ->
+//
+// %avl = SETTM or SETTK
+// ...
+// VSETVLTNT %avl, type2
+//
+bool RISCVInsertVSETVLI::canMutatePriorConfigWithTWiden(
+    const MachineInstr &PrevMI, const MachineInstr &MI) const {
+
+  if (PrevMI.getOpcode() != RISCV::PseudoVSETVLI)
+    return false;
+
+  if (MI.getOpcode() != RISCV::PseudoSF_VSETTNT)
+    return false;
+
+  auto PrevInfo = VIA.getInfoForVSETVLI(PrevMI);
+  auto CurrInfo = VIA.getInfoForVSETVLI(MI);
+
+  auto AVLReg = CurrInfo.getAVLReg();
----------------
BeMg wrote:

PseudoSF_VSETTNT only accepts an AVLReg. I've added an assertion for this situation.

cc @topperc @4vtomat 

https://github.com/llvm/llvm-project/pull/203438