[llvm] [RISCV] Add getJumpConditionMergingParams to support branch condition merging (PR #206897)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 1 00:10:18 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
<details>
<summary>Changes</summary>
Override `getJumpConditionMergingParams` so that `shouldKeepJumpConditionsTogether`
can decide whether to keep `br (and/or cond1, cond2)` merged into a single
branch or split it into two branches, based on a configurable cost threshold.
Previously RISCV used the base class default {-1, -1, -1}, which always split
the conditions. Now it returns a base cost of 2 (with likely/unlikely biases),
controllable via `riscv-br-merging-base-cost / -likely-bias / -unlikely-bias`.
This is another approach to #<!-- -->191158 when `TuneJumpIsExpensive` is not set.
---
Patch is 50.14 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206897.diff
10 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+44)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+4)
- (modified) llvm/test/CodeGen/RISCV/double-previous-failure.ll (+19-21)
- (modified) llvm/test/CodeGen/RISCV/jump-is-expensive.ll (+7-7)
- (modified) llvm/test/CodeGen/RISCV/or-is-add.ll (+29-25)
- (modified) llvm/test/CodeGen/RISCV/rvv/pr93587.ll (+3-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll (+8-7)
- (modified) llvm/test/CodeGen/RISCV/select-and.ll (+18-21)
- (modified) llvm/test/CodeGen/RISCV/select-or.ll (+21-24)
- (modified) llvm/test/CodeGen/RISCV/setcc-logic.ll (+348-244)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f12d1dc1e1714..f7034c8d1fd70 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -88,6 +88,41 @@ static cl::opt<bool>
"be combined with a shift"),
cl::init(true));
+static cl::opt<int> BrMergingBaseCostThresh(
+ "riscv-br-merging-base-cost", cl::init(2),
+ cl::desc(
+ "Sets the cost threshold for when multiple conditionals will be merged "
+ "into one branch versus be split in multiple branches. Merging "
+ "conditionals saves branches at the cost of additional instructions. "
+ "This value sets the instruction cost limit, below which conditionals "
+ "will be merged, and above which conditionals will be split. Set to -1 "
+ "to never merge branches."),
+ cl::Hidden);
+
+static cl::opt<int> BrMergingLikelyBias(
+ "riscv-br-merging-likely-bias", cl::init(0),
+ cl::desc(
+ "Increases 'riscv-br-merging-base-cost' in cases that it is "
+ "likely that all conditionals will be executed. For example for "
+ "merging the conditionals (a == b && c > d), if its known that "
+ "a == b is likely, then it is likely that if the conditionals are "
+ "split both sides will be executed, so it may be desirable to "
+ "increase the instruction cost threshold. Set to -1 to never merge "
+ "likely branches."),
+ cl::Hidden);
+
+static cl::opt<int> BrMergingUnlikelyBias(
+ "riscv-br-merging-unlikely-bias", cl::init(-1),
+ cl::desc(
+ "Decreases 'riscv-br-merging-base-cost' in cases that it is unlikely "
+ "that all conditionals will be executed. For example for merging "
+ "the conditionals (a == b && c > d), if its known that a == b is "
+ "unlikely, then it is unlikely that if the conditionals are split "
+ "both sides will be executed, so it may be desirable to decrease "
+ "the instruction cost threshold. Set to -1 to never merge unlikely "
+ "branches."),
+ cl::Hidden);
+
// TODO: Support more ops
static const unsigned ZvfbfaOps[] = {
ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FADD,
@@ -2034,6 +2069,15 @@ EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL,
return VT.changeVectorElementTypeToInteger();
}
+TargetLoweringBase::CondMergingParams
+RISCVTargetLowering::getJumpConditionMergingParams(Instruction::BinaryOps Opc,
+ const Value *Lhs,
+ const Value *Rhs) const {
+ int BaseCost = BrMergingBaseCostThresh.getValue();
+ return {BaseCost, BrMergingLikelyBias.getValue(),
+ BrMergingUnlikelyBias.getValue()};
+}
+
MVT RISCVTargetLowering::getVPExplicitVectorLengthTy() const {
return Subtarget.getXLenVT();
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 4e7912ed815dd..ac1ba4235498c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -202,6 +202,10 @@ class RISCVTargetLowering : public TargetLowering {
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
EVT VT) const override;
+ CondMergingParams
+ getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
+ const Value *Rhs) const override;
+
bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const override {
if (VT == MVT::i8 || VT == MVT::i16)
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
index c0993faa9584a..652ad13025458 100644
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -31,17 +31,16 @@ define i32 @main() nounwind {
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld fa5, 0(sp)
; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_0)(a0)
-; RV32IFD-NEXT: flt.d a0, fa5, fa4
-; RV32IFD-NEXT: bnez a0, .LBB1_3
-; RV32IFD-NEXT: # %bb.1: # %entry
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_1)(a0)
-; RV32IFD-NEXT: flt.d a0, fa4, fa5
-; RV32IFD-NEXT: bnez a0, .LBB1_3
-; RV32IFD-NEXT: # %bb.2: # %if.end
-; RV32IFD-NEXT: call exit
-; RV32IFD-NEXT: .LBB1_3: # %if.then
+; RV32IFD-NEXT: fld fa3, %lo(.LCPI1_1)(a0)
+; RV32IFD-NEXT: flt.d a0, fa5, fa4
+; RV32IFD-NEXT: flt.d a1, fa3, fa5
+; RV32IFD-NEXT: or a0, a0, a1
+; RV32IFD-NEXT: beqz a0, .LBB1_2
+; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: call abort
+; RV32IFD-NEXT: .LBB1_2: # %if.end
+; RV32IFD-NEXT: call exit
;
; RV32IZFINXZDINX-LABEL: main:
; RV32IZFINXZDINX: # %bb.0: # %entry
@@ -53,20 +52,19 @@ define i32 @main() nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
+; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
-; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a4
-; RV32IZFINXZDINX-NEXT: bnez a2, .LBB1_3
-; RV32IZFINXZDINX-NEXT: # %bb.1: # %entry
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a2)
-; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_1)
-; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
-; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0
-; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3
-; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end
-; RV32IZFINXZDINX-NEXT: call exit
-; RV32IZFINXZDINX-NEXT: .LBB1_3: # %if.then
+; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a3)
+; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_1)
+; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
+; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a4
+; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
+; RV32IZFINXZDINX-NEXT: or a0, a4, a0
+; RV32IZFINXZDINX-NEXT: beqz a0, .LBB1_2
+; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.then
; RV32IZFINXZDINX-NEXT: call abort
+; RV32IZFINXZDINX-NEXT: .LBB1_2: # %if.end
+; RV32IZFINXZDINX-NEXT: call exit
entry:
%call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01
diff --git a/llvm/test/CodeGen/RISCV/jump-is-expensive.ll b/llvm/test/CodeGen/RISCV/jump-is-expensive.ll
index 6778223181e2c..13e86057983b2 100644
--- a/llvm/test/CodeGen/RISCV/jump-is-expensive.ll
+++ b/llvm/test/CodeGen/RISCV/jump-is-expensive.ll
@@ -6,16 +6,16 @@
define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHEAP-LABEL: foo:
; CHEAP: # %bb.0: # %entry
-; CHEAP-NEXT: li a2, 5
; CHEAP-NEXT: sext.w a1, a1
-; CHEAP-NEXT: blt a1, a2, .LBB0_3
-; CHEAP-NEXT: # %bb.1: # %entry
; CHEAP-NEXT: sext.w a0, a0
-; CHEAP-NEXT: beqz a0, .LBB0_3
-; CHEAP-NEXT: # %bb.2: # %UnifiedReturnBlock
-; CHEAP-NEXT: ret
-; CHEAP-NEXT: .LBB0_3: # %cond_true
+; CHEAP-NEXT: seqz a0, a0
+; CHEAP-NEXT: slti a1, a1, 5
+; CHEAP-NEXT: or a0, a0, a1
+; CHEAP-NEXT: beqz a0, .LBB0_2
+; CHEAP-NEXT: # %bb.1: # %cond_true
; CHEAP-NEXT: tail bar
+; CHEAP-NEXT: .LBB0_2: # %UnifiedReturnBlock
+; CHEAP-NEXT: ret
;
; EXPENSIVE-LABEL: foo:
; EXPENSIVE: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/RISCV/or-is-add.ll b/llvm/test/CodeGen/RISCV/or-is-add.ll
index cf3260fbee37a..32ae5b4eacbab 100644
--- a/llvm/test/CodeGen/RISCV/or-is-add.ll
+++ b/llvm/test/CodeGen/RISCV/or-is-add.ll
@@ -128,20 +128,22 @@ define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {
; RV32: # %bb.0:
; RV32-NEXT: slli a3, a1, 3
; RV32-NEXT: add a3, a0, a3
-; RV32-NEXT: lw a2, 4(a3)
-; RV32-NEXT: bgez a2, .LBB7_6
-; RV32-NEXT: # %bb.1:
+; RV32-NEXT: lw a4, 4(a3)
; RV32-NEXT: slli a2, a1, 1
; RV32-NEXT: addi a2, a2, 1
-; RV32-NEXT: beq a2, a1, .LBB7_6
-; RV32-NEXT: # %bb.2: # %.preheader
+; RV32-NEXT: xor a5, a2, a1
+; RV32-NEXT: srli a4, a4, 31
+; RV32-NEXT: snez a5, a5
+; RV32-NEXT: and a4, a5, a4
+; RV32-NEXT: beqz a4, .LBB7_5
+; RV32-NEXT: # %bb.1: # %.preheader
; RV32-NEXT: addi a3, a3, 4
-; RV32-NEXT: j .LBB7_4
-; RV32-NEXT: .LBB7_3: # in Loop: Header=BB7_4 Depth=1
+; RV32-NEXT: j .LBB7_3
+; RV32-NEXT: .LBB7_2: # in Loop: Header=BB7_3 Depth=1
; RV32-NEXT: mv a2, a1
; RV32-NEXT: addi a3, a3, 4
-; RV32-NEXT: beq a1, a1, .LBB7_6
-; RV32-NEXT: .LBB7_4: # =>This Inner Loop Header: Depth=1
+; RV32-NEXT: beq a1, a1, .LBB7_5
+; RV32-NEXT: .LBB7_3: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: slli a4, a4, 2
@@ -151,13 +153,13 @@ define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {
; RV32-NEXT: sw a2, 0(a3)
; RV32-NEXT: add a3, a0, a4
; RV32-NEXT: lw a2, 4(a3)
-; RV32-NEXT: bgez a2, .LBB7_3
-; RV32-NEXT: # %bb.5: # in Loop: Header=BB7_4 Depth=1
+; RV32-NEXT: bgez a2, .LBB7_2
+; RV32-NEXT: # %bb.4: # in Loop: Header=BB7_3 Depth=1
; RV32-NEXT: slli a2, a1, 1
; RV32-NEXT: addi a2, a2, 1
; RV32-NEXT: addi a3, a3, 4
-; RV32-NEXT: bne a2, a1, .LBB7_4
-; RV32-NEXT: .LBB7_6:
+; RV32-NEXT: bne a2, a1, .LBB7_3
+; RV32-NEXT: .LBB7_5:
; RV32-NEXT: ret
;
; RV64-LABEL: pr128468:
@@ -166,18 +168,20 @@ define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {
; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: lw a4, 4(a3)
-; RV64-NEXT: bgez a4, .LBB7_6
-; RV64-NEXT: # %bb.1:
; RV64-NEXT: addiw a2, a2, 1
-; RV64-NEXT: beq a2, a1, .LBB7_6
-; RV64-NEXT: # %bb.2: # %.preheader
+; RV64-NEXT: xor a5, a2, a1
+; RV64-NEXT: srli a4, a4, 63
+; RV64-NEXT: snez a5, a5
+; RV64-NEXT: and a4, a5, a4
+; RV64-NEXT: beqz a4, .LBB7_5
+; RV64-NEXT: # %bb.1: # %.preheader
; RV64-NEXT: addi a3, a3, 4
-; RV64-NEXT: j .LBB7_4
-; RV64-NEXT: .LBB7_3: # in Loop: Header=BB7_4 Depth=1
+; RV64-NEXT: j .LBB7_3
+; RV64-NEXT: .LBB7_2: # in Loop: Header=BB7_3 Depth=1
; RV64-NEXT: mv a2, a1
; RV64-NEXT: addi a3, a3, 4
-; RV64-NEXT: beq a1, a1, .LBB7_6
-; RV64-NEXT: .LBB7_4: # =>This Inner Loop Header: Depth=1
+; RV64-NEXT: beq a1, a1, .LBB7_5
+; RV64-NEXT: .LBB7_3: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: mv a4, a1
; RV64-NEXT: mv a1, a2
; RV64-NEXT: slli a4, a4, 2
@@ -188,12 +192,12 @@ define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {
; RV64-NEXT: sw a4, 0(a3)
; RV64-NEXT: add a3, a0, a5
; RV64-NEXT: lw a4, 4(a3)
-; RV64-NEXT: bgez a4, .LBB7_3
-; RV64-NEXT: # %bb.5: # in Loop: Header=BB7_4 Depth=1
+; RV64-NEXT: bgez a4, .LBB7_2
+; RV64-NEXT: # %bb.4: # in Loop: Header=BB7_3 Depth=1
; RV64-NEXT: addiw a2, a2, 1
; RV64-NEXT: addi a3, a3, 4
-; RV64-NEXT: bne a2, a1, .LBB7_4
-; RV64-NEXT: .LBB7_6:
+; RV64-NEXT: bne a2, a1, .LBB7_3
+; RV64-NEXT: .LBB7_5:
; RV64-NEXT: ret
%4 = shl nsw i32 %1, 1
%5 = or disjoint i32 %4, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr93587.ll b/llvm/test/CodeGen/RISCV/rvv/pr93587.ll
index c2998bf20fa0a..38b79ee2fec14 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr93587.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr93587.ll
@@ -14,12 +14,10 @@ define i16 @f() {
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: j .LBB0_1
-; CHECK-NEXT: # %bb.2: # %BB1
-; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: li a0, 1
; CHECK-NEXT: bnez a0, .LBB0_1
-; CHECK-NEXT: j .LBB0_3
-; CHECK-NEXT: .LBB0_3: # %BB2
+; CHECK-NEXT: j .LBB0_2
+; CHECK-NEXT: .LBB0_2: # %BB2
; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
index ff5c4e52bb586..b4b5ce9f4e960 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
@@ -76,14 +76,15 @@ define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr noc
; RV64: # %bb.0: # %entry
; RV64-NEXT: blez a3, .LBB0_6
; RV64-NEXT: # %bb.1: # %for.body.preheader
-; RV64-NEXT: li a5, 8
+; RV64-NEXT: sub a4, a0, a1
+; RV64-NEXT: sltiu a5, a3, 8
+; RV64-NEXT: sltiu a4, a4, 32
+; RV64-NEXT: or a4, a5, a4
+; RV64-NEXT: beqz a4, .LBB0_3
+; RV64-NEXT: # %bb.2:
; RV64-NEXT: li a4, 0
-; RV64-NEXT: bltu a3, a5, .LBB0_7
-; RV64-NEXT: # %bb.2: # %for.body.preheader
-; RV64-NEXT: sub a5, a0, a1
-; RV64-NEXT: li a6, 31
-; RV64-NEXT: bgeu a6, a5, .LBB0_7
-; RV64-NEXT: # %bb.3: # %vector.ph
+; RV64-NEXT: j .LBB0_7
+; RV64-NEXT: .LBB0_3: # %vector.ph
; RV64-NEXT: lui a4, 524288
; RV64-NEXT: addiw a4, a4, -8
; RV64-NEXT: and a4, a3, a4
diff --git a/llvm/test/CodeGen/RISCV/select-and.ll b/llvm/test/CodeGen/RISCV/select-and.ll
index 2c9d0a8b56425..7a5f5d62cabba 100644
--- a/llvm/test/CodeGen/RISCV/select-and.ll
+++ b/llvm/test/CodeGen/RISCV/select-and.ll
@@ -48,15 +48,14 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: beqz a0, .LBB1_3
-; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beqz a1, .LBB1_3
-; RV32I-NEXT: # %bb.2: # %if.then
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: call both
-; RV32I-NEXT: j .LBB1_4
-; RV32I-NEXT: .LBB1_3: # %if.else
+; RV32I-NEXT: j .LBB1_3
+; RV32I-NEXT: .LBB1_2: # %if.else
; RV32I-NEXT: call neither
-; RV32I-NEXT: .LBB1_4: # %if.end
+; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -65,15 +64,14 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: beqz a0, .LBB1_3
-; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beqz a1, .LBB1_3
-; RV64I-NEXT: # %bb.2: # %if.then
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB1_2
+; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call both
-; RV64I-NEXT: j .LBB1_4
-; RV64I-NEXT: .LBB1_3: # %if.else
+; RV64I-NEXT: j .LBB1_3
+; RV64I-NEXT: .LBB1_2: # %if.else
; RV64I-NEXT: call neither
-; RV64I-NEXT: .LBB1_4: # %if.end
+; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -82,15 +80,14 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I-CCMOV: # %bb.0:
; RV64I-CCMOV-NEXT: addi sp, sp, -16
; RV64I-CCMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-CCMOV-NEXT: beqz a0, .LBB1_3
-; RV64I-CCMOV-NEXT: # %bb.1:
-; RV64I-CCMOV-NEXT: beqz a1, .LBB1_3
-; RV64I-CCMOV-NEXT: # %bb.2: # %if.then
+; RV64I-CCMOV-NEXT: and a0, a0, a1
+; RV64I-CCMOV-NEXT: beqz a0, .LBB1_2
+; RV64I-CCMOV-NEXT: # %bb.1: # %if.then
; RV64I-CCMOV-NEXT: call both
-; RV64I-CCMOV-NEXT: j .LBB1_4
-; RV64I-CCMOV-NEXT: .LBB1_3: # %if.else
+; RV64I-CCMOV-NEXT: j .LBB1_3
+; RV64I-CCMOV-NEXT: .LBB1_2: # %if.else
; RV64I-CCMOV-NEXT: call neither
-; RV64I-CCMOV-NEXT: .LBB1_4: # %if.end
+; RV64I-CCMOV-NEXT: .LBB1_3: # %if.end
; RV64I-CCMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-CCMOV-NEXT: addi sp, sp, 16
; RV64I-CCMOV-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/select-or.ll b/llvm/test/CodeGen/RISCV/select-or.ll
index 091c8b1a11e71..6dbe291f8ed99 100644
--- a/llvm/test/CodeGen/RISCV/select-or.ll
+++ b/llvm/test/CodeGen/RISCV/select-or.ll
@@ -48,15 +48,14 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: bnez a0, .LBB1_3
-; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bnez a1, .LBB1_3
-; RV32I-NEXT: # %bb.2: # %if.else
-; RV32I-NEXT: call neither
-; RV32I-NEXT: j .LBB1_4
-; RV32I-NEXT: .LBB1_3: # %if.then
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: call either
-; RV32I-NEXT: .LBB1_4: # %if.end
+; RV32I-NEXT: j .LBB1_3
+; RV32I-NEXT: .LBB1_2: # %if.else
+; RV32I-NEXT: call neither
+; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -65,15 +64,14 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: bnez a0, .LBB1_3
-; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bnez a1, .LBB1_3
-; RV64I-NEXT: # %bb.2: # %if.else
-; RV64I-NEXT: call neither
-; RV64I-NEXT: j .LBB1_4
-; RV64I-NEXT: .LBB1_3: # %if.then
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB1_2
+; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call either
-; RV64I-NEXT: .LBB1_4: # %if.end
+; RV64I-NEXT: j .LBB1_3
+; RV64I-NEXT: .LBB1_2: # %if.else
+; RV64I-NEXT: call neither
+; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -82,15 +80,14 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I-CCMOV: # %bb.0:
; RV64I-CCMOV-NEXT: addi sp, sp, -16
; RV64I-CCMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-CCMOV-NEXT: bnez a0, .LBB1_3
-; RV64I-CCMOV-NEXT: # %bb.1:
-; RV64I-CCMOV-NEXT: bnez a1, .LBB1_3
-; RV64I-CCMOV-NEXT: # %bb.2: # %if.else
-; RV64I-CCMOV-NEXT: call neither
-; RV64I-CCMOV-NEXT: j .LBB1_4
-; RV64I-CCMOV-NEXT: .LBB1_3: # %if.then
+; RV64I-CCMOV-NEXT: or a0, a0, a1
+; RV64I-CCMOV-NEXT: beqz a0, .LBB1_2
+; RV64I-CCMOV-NEXT: # %bb.1: # %if.then
; RV64I-CCMOV-NEXT: call either
-; RV64I-CCMOV-NEXT: .LBB1_4: # %if.end
+; RV64I-CCMOV-NEXT: j .LBB1_3
+; RV64I-CCMOV-NEXT: .LBB1_2: # %if.else
+; RV64I-CCMOV-NEXT: call neither
+; RV64I-CCMOV-NEXT: .LBB1_3: # %if.end
; RV64I-CCMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-CCMOV-NEXT: addi sp, sp, 16
; RV64I-CCMOV-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll
index 4e14893290ca8..68415bade0d97 100644
--- a/llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -297,22 +297,26 @@ declare void @bar(...)
define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_sge_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: blt a0, a1, .LBB13_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB13_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB13_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB13_3:
+; RV32I-NEXT: .LBB13_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_sge_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: blt a0, a1, .LBB13_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB13_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB13_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB13_3:
+; RV64I-NEXT: .LBB13_2:
; RV64I-NEXT: tail bar
%5 = icmp sge i32 %0, %1
%6 = icmp eq i32 %2, %3
@@ -330,22 +334,26 @@ define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_sle_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: blt a1, a0, .LBB14_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB14_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: b...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206897
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