[llvm] [VPlan] Compute blend masks from minimum set of edge masks (PR #201783)

[Luke Lau via llvm-commits]

================
@@ -1145,14 +1146,16 @@ define float @reduction_conditional(ptr %A, ptr %B, ptr %C, float %S) {
 ; CHECK-INTERLEAVED-NEXT:    [[TMP16:%.*]] = select <4 x i1> [[TMP6]], <4 x i1> [[TMP8]], <4 x i1> zeroinitializer
 ; CHECK-INTERLEAVED-NEXT:    [[TMP17:%.*]] = fadd fast <4 x float> [[VEC_PHI]], [[WIDE_LOAD]]
 ; CHECK-INTERLEAVED-NEXT:    [[TMP18:%.*]] = fadd fast <4 x float> [[VEC_PHI1]], [[WIDE_LOAD2]]
+; CHECK-INTERLEAVED-NEXT:    [[TMP27:%.*]] = xor <4 x i1> [[TMP5]], splat (i1 true)
+; CHECK-INTERLEAVED-NEXT:    [[TMP28:%.*]] = xor <4 x i1> [[TMP6]], splat (i1 true)
 ; CHECK-INTERLEAVED-NEXT:    [[TMP20:%.*]] = select <4 x i1> [[TMP19]], <4 x i1> [[TMP11]], <4 x i1> zeroinitializer
 ; CHECK-INTERLEAVED-NEXT:    [[TMP22:%.*]] = select <4 x i1> [[TMP21]], <4 x i1> [[TMP12]], <4 x i1> zeroinitializer
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI:%.*]] = select <4 x i1> [[TMP20]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP13]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI5:%.*]] = select <4 x i1> [[TMP15]], <4 x float> [[TMP17]], <4 x float> [[PREDPHI]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI6]] = select <4 x i1> [[TMP5]], <4 x float> [[PREDPHI5]], <4 x float> [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI7:%.*]] = select <4 x i1> [[TMP22]], <4 x float> [[VEC_PHI1]], <4 x float> [[TMP14]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI8:%.*]] = select <4 x i1> [[TMP16]], <4 x float> [[TMP18]], <4 x float> [[PREDPHI7]]
-; CHECK-INTERLEAVED-NEXT:    [[PREDPHI9]] = select <4 x i1> [[TMP6]], <4 x float> [[PREDPHI8]], <4 x float> [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT:    [[TMP25:%.*]] = or <4 x i1> [[TMP20]], [[TMP27]]
+; CHECK-INTERLEAVED-NEXT:    [[TMP26:%.*]] = or <4 x i1> [[TMP22]], [[TMP28]]
+; CHECK-INTERLEAVED-NEXT:    [[PREDPHI:%.*]] = select <4 x i1> [[TMP25]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP13]]
----------------
lukel97 wrote:

This is merging two identical incoming values so they share a single mask + select, in the previous version we had two selects each for VEC_PHI and VEC_PHI1 but these are now just one select. 

So the codegen ends up being a bit better, since mask instructions are cheaper than selects on the full VF, and the logical-nots in the mask typically get folded into the selects anyway. Here's the diff for this IR on aarch64:

```diff
diff -u /var/folders/yl/qbdtspsx7t97vqcl6dm6q9540000gn/T/buffer-content-lTlICd /var/folders/yl/qbdtspsx7t97vqcl6dm6q9540000gn/T/buffer-content-uqXJJx
--- /var/folders/yl/qbdtspsx7t97vqcl6dm6q9540000gn/T/buffer-content-lTlICd	2026-07-01 14:01:40
+++ /var/folders/yl/qbdtspsx7t97vqcl6dm6q9540000gn/T/buffer-content-uqXJJx	2026-07-01 14:01:40
@@ -17,35 +17,31 @@
 	fmov	v0.4s, #1.00000000
 .LBB0_1:                                // %vector.body
                                         // =>This Inner Loop Header: Depth=1
-	ldp	q4, q5, [x9, #-16]
+	ldp	q4, q7, [x8, #-16]
 	subs	x10, x10, #8
-	ldp	q16, q17, [x8, #-16]
+	ldp	q5, q6, [x9, #-16]
 	add	x8, x8, #32
 	add	x9, x9, #32
-	fcmgt	v6.4s, v4.4s, v3.4s
-	fcmgt	v7.4s, v5.4s, v3.4s
-	fcmgt	v18.4s, v16.4s, v0.4s
-	fcmgt	v19.4s, v17.4s, v0.4s
-	fcmgt	v20.4s, v4.4s, v16.4s
-	fcmgt	v21.4s, v5.4s, v17.4s
-	fadd	v16.4s, v1.4s, v16.4s
-	fadd	v17.4s, v2.4s, v17.4s
+	fcmgt	v16.4s, v4.4s, v0.4s
+	fcmgt	v17.4s, v7.4s, v0.4s
+	fcmgt	v18.4s, v5.4s, v3.4s
+	fcmgt	v19.4s, v6.4s, v3.4s
+	fcmgt	v20.4s, v5.4s, v4.4s
+	fcmgt	v21.4s, v6.4s, v7.4s
 	fadd	v4.4s, v1.4s, v4.4s
-	fadd	v5.4s, v2.4s, v5.4s
-	mvn	v6.16b, v6.16b
-	mvn	v7.16b, v7.16b
-	bic	v6.16b, v6.16b, v18.16b
-	bic	v7.16b, v7.16b, v19.16b
-	and	v6.16b, v6.16b, v20.16b
-	and	v7.16b, v7.16b, v21.16b
-	bsl	v6.16b, v1.16b, v16.16b
-	bsl	v7.16b, v2.16b, v17.16b
-	and	v16.16b, v20.16b, v18.16b
-	and	v17.16b, v21.16b, v19.16b
-	bif	v4.16b, v6.16b, v16.16b
-	bif	v5.16b, v7.16b, v17.16b
-	bit	v1.16b, v4.16b, v20.16b
-	bit	v2.16b, v5.16b, v21.16b
+	fadd	v7.4s, v2.4s, v7.4s
+	fadd	v5.4s, v1.4s, v5.4s
+	fadd	v6.4s, v2.4s, v6.4s
+	orr	v18.16b, v16.16b, v18.16b
+	orr	v19.16b, v17.16b, v19.16b
+	and	v18.16b, v18.16b, v20.16b
+	and	v19.16b, v19.16b, v21.16b
+	bit	v1.16b, v4.16b, v18.16b
+	bit	v2.16b, v7.16b, v19.16b
+	and	v4.16b, v20.16b, v16.16b
+	and	v7.16b, v21.16b, v17.16b
+	bit	v1.16b, v5.16b, v4.16b
+	bit	v2.16b, v6.16b, v7.16b
 	b.ne	.LBB0_1
 // %bb.2:                               // %for.end
 	fadd	v0.4s, v2.4s, v1.4s
```

https://github.com/llvm/llvm-project/pull/201783