[llvm] [RegisterCoalescer] Narrow full COPYs with dead destination lanes (PR #199631)
Yuyang Zhang via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 30 19:25:27 PDT 2026
https://github.com/yuyzhang512 updated https://github.com/llvm/llvm-project/pull/199631
>From f2a988066f9e2e09acb53a2892d0c0e23996ffc5 Mon Sep 17 00:00:00 2001
From: yuyzhang512 <yuyzhang at amd.com>
Date: Tue, 30 Jun 2026 08:27:01 +0000
Subject: [PATCH] [RegisterCoalescer] Narrow full COPYs with dead destination
lanes
A full `%dst = COPY %src` can define lanes that are dead at the copy:
overwritten by a later subreg def before any use. The full-width COPY def
still interferes on those lanes, which blocks coalescing the overwriting
defs and leaves redundant copies behind.
Narrow such a COPY to the surviving lanes so the overwriting defs can
coalesce on a later attempt:
%dst = COPY %src
%dst.sub0 = ... ; overwrites sub0 before use
-->
%dst.sub1 = COPY %src.sub1
The pattern is common with SelectionDAG vector lowering. insertelement on a
shared base vector expands to a full COPY of the base followed by a subreg
def that overwrites the inserted lane, so the copied base lane is dead. On a
gfx1250 tensor-load kernel this removes 5 s_mov (29 -> 24).
GlobalISel does not hit this: it builds each vector from scalar operands, so
the dead-lane copies never form.
The regenerated in-tree tests (AMDGPU, PowerPC, RISCV, Thumb2) show the
narrowing is neutral or removes instructions on every affected case; the
RISCV expandload test drops 256 instructions.
---
llvm/lib/CodeGen/RegisterCoalescer.cpp | 46 +
.../AMDGPU/coalesce-narrow-dead-lane-copy.mir | 27 +
.../AMDGPU/couldnt-join-subrange-3.mir | 3 +-
llvm/test/CodeGen/AMDGPU/itofp.i128.ll | 66 +-
.../regcoalesce-cannot-join-failures.mir | 2 +-
...keep-valid-lanes-implicit-def-bug39602.mir | 4 +-
.../AMDGPU/splitkit-getsubrangeformask.ll | 100 +-
.../CodeGen/PowerPC/ppc64-acc-regalloc.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/expandload.ll | 1536 ++++++-----------
.../rvv/fixed-vectors-shuffle-exact-vlen.ll | 4 +-
.../RISCV/rvv/vector-interleave-store.ll | 2 +-
llvm/test/CodeGen/Thumb2/mve-vst2.ll | 31 +-
llvm/test/CodeGen/Thumb2/mve-vst3.ll | 38 +-
13 files changed, 709 insertions(+), 1162 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/coalesce-narrow-dead-lane-copy.mir
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 4b4ba2144f964..1e1479bab1054 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -2220,6 +2220,52 @@ bool RegisterCoalescer::joinCopy(
if (removePartialRedundancy(CP, *CopyMI))
return true;
+ // Narrow a full `%dst = COPY %src` whose destination has lanes that are
+ // dead at the copy (overwritten before use): the dead-lane def causes false
+ // interference, so narrow to the surviving lanes and let the overwriting
+ // defs coalesce.
+ if (!CP.isPartial() && !CP.isPhys()) {
+ Register CopySrcReg = CopyMI->getOperand(1).getReg();
+ Register CopyDstReg = CopyMI->getOperand(0).getReg();
+ LiveInterval &SrcLI = LIS->getInterval(CopySrcReg);
+ LiveInterval &DstLI = LIS->getInterval(CopyDstReg);
+ if (SrcLI.hasSubRanges() && DstLI.hasSubRanges()) {
+ SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
+ // Lanes the source provides a value for.
+ LaneBitmask SrcLanes = LaneBitmask::getNone();
+ for (auto &SR : SrcLI.subranges())
+ SrcLanes |= SR.LaneMask;
+ // Drop those whose destination def is dead (overwritten before use).
+ LaneBitmask SurvivingLanes = SrcLanes;
+ for (auto &SR : DstLI.subranges())
+ if (SR.Query(CopyIdx).isDeadDef())
+ SurvivingLanes &= ~SR.LaneMask;
+
+ if (SurvivingLanes.any() && SurvivingLanes != SrcLanes) {
+ const TargetRegisterClass *SrcRC = MRI->getRegClass(CopySrcReg);
+ const TargetRegisterClass *DstRC = MRI->getRegClass(CopyDstReg);
+ SmallVector<unsigned, 4> SubRegIdxs;
+ if (TRI->getCoveringSubRegIndexes(SrcRC, SurvivingLanes,
+ SubRegIdxs) &&
+ SubRegIdxs.size() == 1 &&
+ TRI->getSubClassWithSubReg(DstRC, SubRegIdxs[0])) {
+ unsigned SubIdx = SubRegIdxs[0];
+ LLVM_DEBUG(dbgs() << "\tNarrowing COPY to "
+ << TRI->getSubRegIndexName(SubIdx) << '\n');
+ CopyMI->getOperand(0).setSubReg(SubIdx);
+ CopyMI->getOperand(0).setIsUndef(true);
+ CopyMI->getOperand(1).setSubReg(SubIdx);
+ LIS->removeInterval(CopyDstReg);
+ LIS->createAndComputeVirtRegInterval(CopyDstReg);
+ LIS->removeInterval(CopySrcReg);
+ LIS->createAndComputeVirtRegInterval(CopySrcReg);
+ Again = true;
+ return false;
+ }
+ }
+ }
+ }
+
// Otherwise, we are unable to join the intervals.
LLVM_DEBUG(dbgs() << "\tInterference!\n");
Again = true; // May be possible to coalesce later.
diff --git a/llvm/test/CodeGen/AMDGPU/coalesce-narrow-dead-lane-copy.mir b/llvm/test/CodeGen/AMDGPU/coalesce-narrow-dead-lane-copy.mir
new file mode 100644
index 0000000000000..87d7f9d2bbc6b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/coalesce-narrow-dead-lane-copy.mir
@@ -0,0 +1,27 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=register-coalescer -o - %s | FileCheck %s
+
+# %4 = COPY %3 copies both lanes, but %4.sub0 = COPY %2 overwrites sub0 before
+# any use, so the COPY's sub0 def is dead. The full-width COPY blocks coalescing
+# %2 into %4.sub0. Check the COPY is narrowed to its surviving lane (sub1), which
+# lets %4.sub0 = COPY %2 coalesce away: the four input COPYs become one.
+---
+name: narrow_copy_dead_dst_lane
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: narrow_copy_dead_dst_lane
+ ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 2
+ ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 3
+ ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub1
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]]
+ %0:sreg_32 = S_MOV_B32 1
+ %1:sreg_32 = S_MOV_B32 2
+ %2:sreg_32 = S_MOV_B32 3
+ undef %3.sub0:sgpr_128 = COPY %0
+ %3.sub1:sgpr_128 = COPY %1
+ %4:sgpr_128 = COPY %3
+ %4.sub0:sgpr_128 = COPY %2
+ S_ENDPGM 0, implicit %3, implicit %4
+...
diff --git a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
index 004abb4bb0ccd..5186c546419d4 100644
--- a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
+++ b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
@@ -29,7 +29,8 @@ body: |
; GCN-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY [[V_MUL_LO_I32_e64_]]
- ; GCN-NEXT: [[V_MUL_LO_I32_e64_:%[0-9]+]].sub3:vreg_128 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, [[COPY]].sub3, implicit $exec
+ ; GCN-NEXT: undef [[V_MUL_LO_I32_e64_:%[0-9]+]].sub3:vreg_128 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, [[COPY]].sub3, implicit $exec
+ ; GCN-NEXT: [[V_MUL_LO_I32_e64_:%[0-9]+]].sub0_sub1_sub2:vreg_128 = COPY [[COPY]].sub0_sub1_sub2
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_I32 [[S_MOV_B32_]], 1, implicit-def dead $scc
; GCN-NEXT: S_CMP_LT_U32 [[S_MOV_B32_]], 3, implicit-def $scc
; GCN-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
index 4bc09f2c9abe5..841744d7d1f88 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
@@ -592,39 +592,38 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_or_b32_e32 v10, v0, v10
; SDAG-NEXT: v_lshrrev_b64 v[0:1], v13, v[6:7]
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v12
-; SDAG-NEXT: v_add_u32_e32 v16, 55, v9
; SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v12
; SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; SDAG-NEXT: v_lshrrev_b64 v[10:11], v12, v[6:7]
-; SDAG-NEXT: v_lshrrev_b64 v[12:13], v13, v[4:5]
-; SDAG-NEXT: v_lshlrev_b64 v[14:15], v16, v[6:7]
-; SDAG-NEXT: v_add_u32_e32 v9, -9, v9
-; SDAG-NEXT: v_or_b32_e32 v15, v15, v13
-; SDAG-NEXT: v_or_b32_e32 v14, v14, v12
-; SDAG-NEXT: v_lshlrev_b64 v[12:13], v9, v[4:5]
+; SDAG-NEXT: v_add_u32_e32 v15, 55, v9
; SDAG-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v12
+; SDAG-NEXT: v_lshrrev_b64 v[11:12], v13, v[4:5]
+; SDAG-NEXT: v_lshlrev_b64 v[13:14], v15, v[6:7]
+; SDAG-NEXT: v_add_u32_e32 v9, -9, v9
+; SDAG-NEXT: v_cndmask_b32_e32 v16, 0, v10, vcc
+; SDAG-NEXT: v_lshlrev_b64 v[9:10], v9, v[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v9, v13, v15, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; SDAG-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
-; SDAG-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v9, v12, v14, vcc
+; SDAG-NEXT: v_or_b32_e32 v12, v14, v12
+; SDAG-NEXT: v_or_b32_e32 v11, v13, v11
+; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
+; SDAG-NEXT: v_lshlrev_b64 v[4:5], v15, v[4:5]
+; SDAG-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
+; SDAG-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; SDAG-NEXT: v_cndmask_b32_e64 v7, v10, v7, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v6, v9, v6, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
; SDAG-NEXT: v_or_b32_e32 v5, v5, v7
; SDAG-NEXT: v_or_b32_e32 v4, v4, v6
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
-; SDAG-NEXT: v_mov_b32_e32 v6, v10
+; SDAG-NEXT: v_mov_b32_e32 v6, v16
; SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; SDAG-NEXT: v_mov_b32_e32 v5, v1
; SDAG-NEXT: v_mov_b32_e32 v4, v0
-; SDAG-NEXT: v_mov_b32_e32 v7, v11
; SDAG-NEXT: .LBB2_6: ; %Flow1
; SDAG-NEXT: s_or_b64 exec, exec, s[12:13]
; SDAG-NEXT: .LBB2_7: ; %Flow2
@@ -889,39 +888,38 @@ define double @uitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_or_b32_e32 v9, v4, v9
; SDAG-NEXT: v_lshrrev_b64 v[4:5], v12, v[2:3]
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v11
-; SDAG-NEXT: v_add_u32_e32 v15, 55, v8
; SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
; SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; SDAG-NEXT: v_lshrrev_b64 v[9:10], v11, v[2:3]
-; SDAG-NEXT: v_lshrrev_b64 v[11:12], v12, v[0:1]
-; SDAG-NEXT: v_lshlrev_b64 v[13:14], v15, v[2:3]
-; SDAG-NEXT: v_add_u32_e32 v8, -9, v8
-; SDAG-NEXT: v_or_b32_e32 v14, v14, v12
-; SDAG-NEXT: v_or_b32_e32 v13, v13, v11
-; SDAG-NEXT: v_lshlrev_b64 v[11:12], v8, v[0:1]
+; SDAG-NEXT: v_add_u32_e32 v14, 55, v8
; SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
-; SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
+; SDAG-NEXT: v_lshrrev_b64 v[10:11], v12, v[0:1]
+; SDAG-NEXT: v_lshlrev_b64 v[12:13], v14, v[2:3]
+; SDAG-NEXT: v_add_u32_e32 v8, -9, v8
+; SDAG-NEXT: v_cndmask_b32_e32 v15, 0, v9, vcc
+; SDAG-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]
; SDAG-NEXT: v_cndmask_b32_e64 v5, v5, v1, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v4, v4, v0, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v8, v12, v14, vcc
-; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
-; SDAG-NEXT: v_lshlrev_b64 v[0:1], v15, v[0:1]
-; SDAG-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
-; SDAG-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc
+; SDAG-NEXT: v_or_b32_e32 v11, v13, v11
+; SDAG-NEXT: v_or_b32_e32 v10, v12, v10
+; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
+; SDAG-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1]
+; SDAG-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
+; SDAG-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; SDAG-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[4:5]
; SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; SDAG-NEXT: v_or_b32_e32 v1, v1, v3
; SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
-; SDAG-NEXT: v_mov_b32_e32 v2, v9
+; SDAG-NEXT: v_mov_b32_e32 v2, v15
; SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SDAG-NEXT: v_or_b32_e32 v4, v4, v0
; SDAG-NEXT: v_mov_b32_e32 v0, v4
; SDAG-NEXT: v_mov_b32_e32 v1, v5
-; SDAG-NEXT: v_mov_b32_e32 v3, v10
; SDAG-NEXT: .LBB3_6: ; %Flow1
; SDAG-NEXT: s_or_b64 exec, exec, s[12:13]
; SDAG-NEXT: .LBB3_7: ; %Flow2
diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
index f36720beca4a7..58377c10fd769 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
@@ -63,7 +63,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64 = S_MOV_B32 0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub1:sreg_64 = COPY [[S_MOV_B32_]].sub1
; CHECK-NEXT: dead [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64 = COPY [[S_MOV_B32_]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]].sub1
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir b/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
index 4be94f7599948..fdbc2946f77f2 100644
--- a/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
+++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: [[DEF:%[0-9]+]].sub0:sreg_64 = S_MOV_B32 0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY [[DEF]]
+ ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub1:sreg_64 = COPY [[DEF]].sub1
; CHECK-NEXT: dead [[DEF:%[0-9]+]].sub1:sreg_64 = COPY [[DEF]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]].sub1
bb.0:
@@ -45,7 +45,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64 = S_MOV_B32 0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY [[S_MOV_B32_]]
+ ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub1:sreg_64 = COPY [[S_MOV_B32_]].sub1
; CHECK-NEXT: dead [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64 = COPY [[S_MOV_B32_]].sub0
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]].sub1
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
index c0c1763d54cc0..e3c4e953cd6dd 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
@@ -69,11 +69,13 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
; CHECK-NEXT: [[S_ADD_U32_3:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_ASHR_I32_3:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 undef %174:sreg_32, 31, implicit-def dead $scc
; CHECK-NEXT: undef [[S_ADD_U32_4:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY6]], undef %174:sreg_32, implicit-def $scc
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM3:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_3]], 64, 0 :: (invariant load (s128) from %ir.101, addrspace 4)
; CHECK-NEXT: [[S_ADD_U32_4:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef [[S_ADD_U32_5:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY7]].sub0, [[S_LSHL_B32_]], implicit-def $scc
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM3:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_3]], 64, 0 :: (invariant load (s128) from %ir.101, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM4:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_4]], 64, 0 :: (invariant load (s128) from %ir.109, addrspace 4)
; CHECK-NEXT: [[S_ADD_U32_5:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef [[S_ADD_U32_6:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY7]].sub0, [[S_LSHL_B32_1]], implicit-def $scc
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM5:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_5]], 0, 0 :: (invariant load (s128) from %ir.114, addrspace 4)
; CHECK-NEXT: [[S_ADD_U32_6:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: undef [[S_ADD_U32_7:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY7]].sub0, undef %174:sreg_32, implicit-def $scc
; CHECK-NEXT: [[S_ADD_U32_7:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc
@@ -93,15 +95,17 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM2:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_MOV_B32_]], 16, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %362:sgpr_128, undef %363:sreg_32, 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM3:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %373:sgpr_128, 16, 0 :: (dereferenceable invariant load (s32))
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM4:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_4]], 64, 0 :: (invariant load (s128) from %ir.109, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM5:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_5]], 0, 0 :: (invariant load (s128) from %ir.114, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM6:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_6]], 0, 0 :: (invariant load (s128) from %ir.119, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM7:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_7]], 0, 0 :: (invariant load (s128) from %ir.126, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM6:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_5]], 224, 0 :: (invariant load (s128) from %ir.131, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM7:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_6]], 0, 0 :: (invariant load (s128) from %ir.119, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM8:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_6]], 224, 0 :: (invariant load (s128) from %ir.136, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM1]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM9:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_7]], 0, 0 :: (invariant load (s128) from %ir.126, addrspace 4)
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %357:sgpr_128, [[S_ADD_I32_]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %368:sgpr_128, [[S_ADD_I32_1]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM2]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN4:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM3]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN5:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM4]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN6:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM5]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[S_ADD_I32_2:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM]], -98, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_3:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM1]], -114, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_4:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM2]], -130, implicit-def dead $scc
@@ -116,16 +120,15 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
; CHECK-NEXT: [[S_ADD_U32_15:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %39:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LSHL4_ADD_U32_:%[0-9]+]]:sreg_32 = S_LSHL4_ADD_U32 [[COPY12]], 16, implicit-def dead $scc
; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM undef %388:sgpr_128, [[S_LSHL4_ADD_U32_]], 0, 0 :: (dereferenceable invariant load (s32))
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN5:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM4]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM8:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_5]], 224, 0 :: (invariant load (s128) from %ir.131, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM9:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY7]], 224, 0 :: (invariant load (s128) from %ir.147, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM10:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_5]], 576, 0 :: (invariant load (s128) from %ir.152, addrspace 4)
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN6:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM5]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM11:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_6]], 224, 0 :: (invariant load (s128) from %ir.136, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM12:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_7]], 576, 0 :: (invariant load (s128) from %ir.164, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM13:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_8]], 224, 0 :: (invariant load (s128) from %ir.142, addrspace 4)
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN7:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM6]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN8:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM7]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN7:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM7]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM10:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_8]], 224, 0 :: (invariant load (s128) from %ir.142, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM11:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY7]], 224, 0 :: (invariant load (s128) from %ir.147, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM12:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_5]], 576, 0 :: (invariant load (s128) from %ir.152, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM13:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_7]], 576, 0 :: (invariant load (s128) from %ir.164, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM14:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_8]], 576, 0 :: (invariant load (s128) from %ir.159, addrspace 4)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN8:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM6]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN9:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM8]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN10:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM9]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[S_ADD_I32_6:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM4]], -217, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_7:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM3]], -233, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_8:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM5]], -249, implicit-def dead $scc
@@ -137,82 +140,71 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
; CHECK-NEXT: undef [[S_ADD_U32_16:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY2]], [[S_LSHL_B32_2]], implicit-def $scc
; CHECK-NEXT: [[S_ADD_U32_16:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %36:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LSHL_B32_3:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY13]], 4, implicit-def dead $scc
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN9:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM8]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN11:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM10]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[S_ASHR_I32_4:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_3]], 31, implicit-def dead $scc
; CHECK-NEXT: undef [[S_ADD_U32_17:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY2]], [[S_LSHL_B32_3]], implicit-def $scc
; CHECK-NEXT: [[S_ADD_U32_17:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %36:sreg_32, [[S_ASHR_I32_4]], implicit-def dead $scc, implicit $scc
; CHECK-NEXT: [[S_LSHL_B32_4:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY5]], 3, implicit-def dead $scc
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN10:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM11]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN12:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM11]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[S_ASHR_I32_5:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_4]], 31, implicit-def dead $scc
; CHECK-NEXT: undef [[S_ADD_U32_18:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY]].sub0, [[S_LSHL_B32_4]], implicit-def $scc
; CHECK-NEXT: [[S_ADD_U32_18:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %57:sreg_32, [[S_ASHR_I32_5]], implicit-def dead $scc, implicit $scc
- ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[S_ADD_U32_18]], 168, 0 :: (invariant load (s32) from %ir.276, align 8, addrspace 4)
- ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM14:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_8]], 576, 0 :: (invariant load (s128) from %ir.159, addrspace 4)
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN11:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM13]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN12:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM9]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN13:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM10]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 553734060
- ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 -1
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]]
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_LOAD_DWORD_IMM [[S_ADD_U32_18]], 168, 0 :: (invariant load (s32) from %ir.276, align 8, addrspace 4)
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN13:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM12]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM15:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_9]], 0, 0 :: (invariant load (s128) from %ir.172, addrspace 4)
- ; CHECK-NEXT: [[COPY15:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub1
- ; CHECK-NEXT: [[COPY15:%[0-9]+]].sub0:sgpr_128 = COPY [[S_LOAD_DWORD_IMM]]
- ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY15]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN14:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM14]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN15:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM12]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 553734060
+ ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 -1
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM16:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_10]], 0, 0 :: (invariant load (s128) from %ir.180, addrspace 4)
+ ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2_sub3:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]].sub2_sub3
+ ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN15:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM13]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM4:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM17:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_11]], 0, 0 :: (invariant load (s128) from %ir.185, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN16:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM15]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[S_LSHL_B32_5:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], 3, implicit-def dead $scc
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %73.sub0_sub1_sub2_sub3, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[S_LSHL_B32_5:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY4]], 3, implicit-def dead $scc
+ ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM16]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[S_ASHR_I32_6:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_5]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_14:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM4]], -467, implicit-def dead $scc
; CHECK-NEXT: undef [[S_ADD_U32_19:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY]].sub0, [[S_LSHL_B32_5]], implicit-def $scc
; CHECK-NEXT: [[S_ADD_U32_19:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %57:sreg_32, [[S_ASHR_I32_6]], implicit-def dead $scc, implicit $scc
- ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[S_ADD_U32_19]], 168, 0 :: (invariant load (s64) from %ir.285, addrspace 4)
- ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET2:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM16]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFSET3:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[S_LOAD_DWORDX4_IMM17]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: undef [[S_LOAD_DWORDX2_IMM1:%[0-9]+]].sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[S_ADD_U32_19]], 168, 0 :: (invariant load (s64) from %ir.285, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM18:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_12]], 0, 0 :: (invariant load (s128) from %ir.207, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM19:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_13]], 0, 0 :: (invariant load (s128) from %ir.213, addrspace 4)
- ; CHECK-NEXT: [[COPY16:%[0-9]+]]:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]]
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM20:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_14]], 0, 0 :: (invariant load (s128) from %ir.218, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM21:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_15]], 0, 0 :: (invariant load (s128) from %ir.223, addrspace 4)
- ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORDX2_IMM1]].sub1, 65535, implicit-def dead $scc
- ; CHECK-NEXT: [[COPY16:%[0-9]+]].sub0:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM1]].sub0
- ; CHECK-NEXT: [[COPY16:%[0-9]+]].sub1:sgpr_128 = COPY [[S_AND_B32_]]
- ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY16]], 0, 0 :: (dereferenceable invariant load (s32))
+ ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]].sub2_sub3:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]].sub2_sub3
+ ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]].sub1:sgpr_128 = S_AND_B32 [[S_LOAD_DWORDX2_IMM1]].sub1, 65535, implicit-def dead $scc
+ ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM5:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORDX2_IMM1]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN17:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM18]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN18:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM19]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN19:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM20]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
- ; CHECK-NEXT: [[S_LSHL_B32_6:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], 3, implicit-def dead $scc
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN20:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM21]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
+ ; CHECK-NEXT: [[S_LSHL_B32_6:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY3]], 3, implicit-def dead $scc
; CHECK-NEXT: [[S_ASHR_I32_7:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_6]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_15:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM5]], -468, implicit-def dead $scc
; CHECK-NEXT: undef [[S_ADD_U32_20:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY]].sub0, [[S_LSHL_B32_6]], implicit-def $scc
; CHECK-NEXT: [[S_ADD_U32_20:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %57:sreg_32, [[S_ASHR_I32_7]], implicit-def dead $scc, implicit $scc
- ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM2:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[S_ADD_U32_20]], 168, 0 :: (invariant load (s64) from %ir.296, addrspace 4)
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]]
- ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_LOAD_DWORDX2_IMM2]].sub1, 65535, implicit-def dead $scc
- ; CHECK-NEXT: [[COPY17:%[0-9]+]].sub0:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM2]].sub0
- ; CHECK-NEXT: [[COPY17:%[0-9]+]].sub1:sgpr_128 = COPY [[S_AND_B32_1]]
- ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY17]], 0, 0 :: (dereferenceable invariant load (s32))
+ ; CHECK-NEXT: undef [[S_LOAD_DWORDX2_IMM2:%[0-9]+]].sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[S_ADD_U32_20]], 168, 0 :: (invariant load (s64) from %ir.296, addrspace 4)
+ ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM2:%[0-9]+]].sub2_sub3:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]].sub2_sub3
+ ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM2:%[0-9]+]].sub1:sgpr_128 = S_AND_B32 [[S_LOAD_DWORDX2_IMM2]].sub1, 65535, implicit-def dead $scc
+ ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM6:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORDX2_IMM2]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM22:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_16]], 160, 0 :: (invariant load (s128) from %ir.259, addrspace 4)
- ; CHECK-NEXT: [[S_LSHL_B32_7:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY14]], 3, implicit-def dead $scc
; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM23:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[S_ADD_U32_17]], 160, 0 :: (invariant load (s128) from %ir.268, addrspace 4)
+ ; CHECK-NEXT: [[S_LSHL_B32_7:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY14]], 3, implicit-def dead $scc
; CHECK-NEXT: [[S_ASHR_I32_8:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[S_LSHL_B32_7]], 31, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_16:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM6]], -469, implicit-def dead $scc
; CHECK-NEXT: undef [[S_ADD_U32_21:%[0-9]+]].sub0:sreg_64 = S_ADD_U32 [[COPY]].sub0, [[S_LSHL_B32_7]], implicit-def $scc
; CHECK-NEXT: [[S_ADD_U32_21:%[0-9]+]].sub1:sreg_64 = S_ADDC_U32 undef %57:sreg_32, [[S_ASHR_I32_8]], implicit-def dead $scc, implicit $scc
- ; CHECK-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[S_ADD_U32_21]], 168, 0 :: (invariant load (s32) from %ir.308, align 8, addrspace 4)
+ ; CHECK-NEXT: undef [[S_LOAD_DWORD_IMM:%[0-9]+]].sub0:sgpr_128 = S_LOAD_DWORD_IMM [[S_ADD_U32_21]], 168, 0 :: (invariant load (s32) from %ir.308, align 8, addrspace 4)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN21:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM22]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_IDXEN22:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM23]], 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), align 1, addrspace 8)
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM23]]
; CHECK-NEXT: KILL [[S_LOAD_DWORDX4_IMM22]]
- ; CHECK-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32 = S_AND_B32 %73.sub0, 65535, implicit-def dead $scc
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]].sub1:sgpr_128 = COPY [[S_AND_B32_2]]
- ; CHECK-NEXT: [[COPY18:%[0-9]+]].sub0:sgpr_128 = COPY [[S_LOAD_DWORD_IMM1]]
- ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM7:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[COPY18]], 0, 0 :: (dereferenceable invariant load (s32))
+ ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2_sub3:sgpr_128 = COPY [[S_LOAD_DWORDX2_IMM]].sub2_sub3
+ ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub1:sgpr_128 = S_AND_B32 %73.sub0, 65535, implicit-def dead $scc
+ ; CHECK-NEXT: [[S_BUFFER_LOAD_DWORD_IMM7:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[S_LOAD_DWORD_IMM]], 0, 0 :: (dereferenceable invariant load (s32))
; CHECK-NEXT: [[S_ADD_I32_17:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_IMM]], -474, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_18:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM3]], -475, implicit-def dead $scc
; CHECK-NEXT: [[S_ADD_I32_19:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BUFFER_LOAD_DWORD_SGPR_IMM3]], -491, implicit-def dead $scc
@@ -262,11 +254,11 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
; CHECK-NEXT: [[V_OR_B32_e64_12:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_11]], [[V_SUBREV_U32_e64_6]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_8:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 39, [[BUFFER_LOAD_FORMAT_X_IDXEN]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_13:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_12]], [[V_SUBREV_U32_e64_7]], implicit $exec
- ; CHECK-NEXT: [[V_SUBREV_U32_e64_9:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 50, [[BUFFER_LOAD_FORMAT_X_IDXEN8]], 0, implicit $exec
+ ; CHECK-NEXT: [[V_SUBREV_U32_e64_9:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 50, [[BUFFER_LOAD_FORMAT_X_IDXEN10]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_14:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_13]], [[V_SUBREV_U32_e64_8]], implicit $exec
- ; CHECK-NEXT: [[V_SUBREV_U32_e64_10:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 51, [[BUFFER_LOAD_FORMAT_X_IDXEN9]], 0, implicit $exec
+ ; CHECK-NEXT: [[V_SUBREV_U32_e64_10:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 51, [[BUFFER_LOAD_FORMAT_X_IDXEN8]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_15:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_14]], [[V_SUBREV_U32_e64_9]], implicit $exec
- ; CHECK-NEXT: [[V_SUBREV_U32_e64_11:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 52, [[BUFFER_LOAD_FORMAT_X_IDXEN10]], 0, implicit $exec
+ ; CHECK-NEXT: [[V_SUBREV_U32_e64_11:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 52, [[BUFFER_LOAD_FORMAT_X_IDXEN9]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_16:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_15]], [[V_SUBREV_U32_e64_10]], implicit $exec
; CHECK-NEXT: [[V_SUBREV_U32_e64_12:%[0-9]+]]:vgpr_32 = V_SUBREV_U32_e64 53, [[BUFFER_LOAD_FORMAT_X_IDXEN11]], 0, implicit $exec
; CHECK-NEXT: [[V_OR_B32_e64_17:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_16]], [[V_SUBREV_U32_e64_11]], implicit $exec
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
index 596b03f1d4411..c122ee9c73714 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
@@ -37,7 +37,6 @@ define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2) local_unnamed_addr {
; CHECK-NEXT: xxlxor vs12, vs12, vs12
; CHECK-NEXT: lxv vs4, -16(r5)
; CHECK-NEXT: xxlor vs10, v4, v4
-; CHECK-NEXT: xxlor vs8, v4, v4
; CHECK-NEXT: xxlor vs8, v2, v2
; CHECK-NEXT: mulld r6, r6, r3
; CHECK-NEXT: xvmaddadp vs7, vs0, v1
@@ -58,13 +57,14 @@ define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2) local_unnamed_addr {
; CHECK-NEXT: xvmuldp vs5, v7, v2
; CHECK-NEXT: xxlor vs4, v2, v2
; CHECK-NEXT: xxlor vs1, v3, v3
+; CHECK-NEXT: vmr v3, v5
; CHECK-NEXT: xxlor vs11, v5, v5
-; CHECK-NEXT: xxlor vs9, v5, v5
; CHECK-NEXT: xxlor vs15, vs13, vs13
; CHECK-NEXT: xxmtacc acc1
+; CHECK-NEXT: xxlor vs9, v3, v3
; CHECK-NEXT: xxmtacc acc0
-; CHECK-NEXT: xxmtacc acc2
; CHECK-NEXT: xxmtacc acc3
+; CHECK-NEXT: xxmtacc acc2
; CHECK-NEXT: xvf64gerpp acc0, vsp34, vs0
; CHECK-NEXT: xvf64gerpp acc1, vsp34, vs0
; CHECK-NEXT: xvf64gerpp acc2, vsp34, vs0
@@ -130,7 +130,6 @@ define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2) local_unnamed_addr {
; TRACKLIVE-NEXT: xxlxor vs12, vs12, vs12
; TRACKLIVE-NEXT: lxv vs4, -16(r5)
; TRACKLIVE-NEXT: xxlor vs10, v4, v4
-; TRACKLIVE-NEXT: xxlor vs8, v4, v4
; TRACKLIVE-NEXT: xxlor vs8, v2, v2
; TRACKLIVE-NEXT: mulld r6, r6, r3
; TRACKLIVE-NEXT: xvmaddadp vs7, vs0, v1
@@ -151,13 +150,14 @@ define void @acc_regalloc(ptr %arg, ptr %arg1, ptr %arg2) local_unnamed_addr {
; TRACKLIVE-NEXT: xvmuldp vs5, v7, v2
; TRACKLIVE-NEXT: xxlor vs4, v2, v2
; TRACKLIVE-NEXT: xxlor vs1, v3, v3
+; TRACKLIVE-NEXT: vmr v3, v5
; TRACKLIVE-NEXT: xxlor vs11, v5, v5
-; TRACKLIVE-NEXT: xxlor vs9, v5, v5
; TRACKLIVE-NEXT: xxlor vs15, vs13, vs13
; TRACKLIVE-NEXT: xxmtacc acc1
+; TRACKLIVE-NEXT: xxlor vs9, v3, v3
; TRACKLIVE-NEXT: xxmtacc acc0
-; TRACKLIVE-NEXT: xxmtacc acc2
; TRACKLIVE-NEXT: xxmtacc acc3
+; TRACKLIVE-NEXT: xxmtacc acc2
; TRACKLIVE-NEXT: xvf64gerpp acc0, vsp34, vs0
; TRACKLIVE-NEXT: xvf64gerpp acc1, vsp34, vs0
; TRACKLIVE-NEXT: xvf64gerpp acc2, vsp34, vs0
diff --git a/llvm/test/CodeGen/RISCV/rvv/expandload.ll b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
index be50ef3e17a71..890b815cc30d3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/expandload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
@@ -2200,11 +2200,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 158
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 157
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_168: # %else626
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -2213,13 +2211,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: bgez a2, .LBB61_170
; CHECK-RV32-NEXT: # %bb.169: # %cond.load629
; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 159
; CHECK-RV32-NEXT: li a4, 158
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a4
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_170: # %else630
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -2349,11 +2345,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 190
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 189
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_202: # %else754
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -2362,13 +2356,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: bgez a3, .LBB61_204
; CHECK-RV32-NEXT: # %bb.203: # %cond.load757
; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
; CHECK-RV32-NEXT: li a3, 191
; CHECK-RV32-NEXT: li a4, 190
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a4
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_204: # %else758
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -2498,11 +2490,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 222
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 221
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_236: # %else882
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -2511,13 +2501,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: bgez a2, .LBB61_238
; CHECK-RV32-NEXT: # %bb.237: # %cond.load885
; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 223
; CHECK-RV32-NEXT: li a4, 222
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a4
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_238: # %else886
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -2647,11 +2635,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 254
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 253
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_270: # %else1010
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -2660,13 +2646,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: bgez a2, .LBB61_272
; CHECK-RV32-NEXT: # %bb.271: # %cond.load1013
; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 255
; CHECK-RV32-NEXT: li a3, 254
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: .LBB61_272: # %else1014
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -5319,11 +5303,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 129
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 128
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 2
; CHECK-RV32-NEXT: bnez a2, .LBB61_664
@@ -5332,11 +5314,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 130
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 129
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 4
; CHECK-RV32-NEXT: bnez a2, .LBB61_665
@@ -5345,11 +5325,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 131
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 130
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 8
; CHECK-RV32-NEXT: bnez a2, .LBB61_666
@@ -5358,11 +5336,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 132
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 131
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 16
; CHECK-RV32-NEXT: bnez a2, .LBB61_667
@@ -5371,11 +5347,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 133
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 132
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 32
; CHECK-RV32-NEXT: bnez a2, .LBB61_668
@@ -5384,11 +5358,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 134
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 133
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 64
; CHECK-RV32-NEXT: bnez a2, .LBB61_669
@@ -5397,11 +5369,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 135
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 134
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 128
; CHECK-RV32-NEXT: bnez a2, .LBB61_670
@@ -5410,11 +5380,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 136
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 135
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 256
; CHECK-RV32-NEXT: bnez a2, .LBB61_671
@@ -5423,11 +5391,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 137
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 136
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 512
; CHECK-RV32-NEXT: bnez a2, .LBB61_672
@@ -5436,11 +5402,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 138
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 137
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 1024
; CHECK-RV32-NEXT: bnez a2, .LBB61_673
@@ -5449,11 +5413,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 139
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 138
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 20
; CHECK-RV32-NEXT: bltz a2, .LBB61_674
@@ -5462,11 +5424,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 140
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 139
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 19
; CHECK-RV32-NEXT: bltz a2, .LBB61_675
@@ -5475,11 +5435,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 141
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 140
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 18
; CHECK-RV32-NEXT: bltz a2, .LBB61_676
@@ -5488,11 +5446,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 142
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 141
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 17
; CHECK-RV32-NEXT: bltz a2, .LBB61_677
@@ -5501,11 +5457,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 143
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 142
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 16
; CHECK-RV32-NEXT: bltz a2, .LBB61_678
@@ -5514,11 +5468,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 144
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 143
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 15
; CHECK-RV32-NEXT: bltz a2, .LBB61_679
@@ -5527,11 +5479,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 145
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 144
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 14
; CHECK-RV32-NEXT: bltz a2, .LBB61_680
@@ -5540,11 +5490,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 146
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 145
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 13
; CHECK-RV32-NEXT: bltz a2, .LBB61_681
@@ -5553,11 +5501,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 147
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 146
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 12
; CHECK-RV32-NEXT: bltz a2, .LBB61_682
@@ -5566,11 +5512,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 148
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 147
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 11
; CHECK-RV32-NEXT: bltz a2, .LBB61_683
@@ -5579,11 +5523,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 149
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 148
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 10
; CHECK-RV32-NEXT: bltz a2, .LBB61_684
@@ -5592,11 +5534,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 150
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 149
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 9
; CHECK-RV32-NEXT: bltz a2, .LBB61_685
@@ -5605,11 +5545,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 151
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 150
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 8
; CHECK-RV32-NEXT: bltz a2, .LBB61_686
@@ -5618,11 +5556,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 152
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 151
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 7
; CHECK-RV32-NEXT: bltz a2, .LBB61_687
@@ -5631,11 +5567,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 153
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 152
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 6
; CHECK-RV32-NEXT: bltz a2, .LBB61_688
@@ -5644,11 +5578,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 154
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 153
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 5
; CHECK-RV32-NEXT: bltz a2, .LBB61_689
@@ -5657,11 +5589,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 155
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 154
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 4
; CHECK-RV32-NEXT: bltz a2, .LBB61_690
@@ -5670,11 +5600,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 156
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 155
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 3
; CHECK-RV32-NEXT: bltz a2, .LBB61_691
@@ -5683,11 +5611,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 157
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 156
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 2
; CHECK-RV32-NEXT: bgez a2, .LBB61_1029
@@ -5696,13 +5622,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: j .LBB61_168
; CHECK-RV32-NEXT: .LBB61_692: # %cond.load633
; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 160
; CHECK-RV32-NEXT: li a4, 159
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a4
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 1
; CHECK-RV32-NEXT: bnez a3, .LBB61_693
@@ -5711,11 +5635,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 161
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 160
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 2
; CHECK-RV32-NEXT: bnez a3, .LBB61_694
@@ -5724,11 +5646,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 162
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 161
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 4
; CHECK-RV32-NEXT: bnez a3, .LBB61_695
@@ -5737,11 +5657,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 163
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 162
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 8
; CHECK-RV32-NEXT: bnez a3, .LBB61_696
@@ -5750,11 +5668,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 164
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 163
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 16
; CHECK-RV32-NEXT: bnez a3, .LBB61_697
@@ -5763,11 +5679,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 165
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 164
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 32
; CHECK-RV32-NEXT: bnez a3, .LBB61_698
@@ -5776,11 +5690,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 166
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 165
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 64
; CHECK-RV32-NEXT: bnez a3, .LBB61_699
@@ -5789,11 +5701,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 167
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 166
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 128
; CHECK-RV32-NEXT: bnez a3, .LBB61_700
@@ -5802,11 +5712,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 168
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 167
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 256
; CHECK-RV32-NEXT: bnez a3, .LBB61_701
@@ -5815,11 +5723,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 169
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 168
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 512
; CHECK-RV32-NEXT: bnez a3, .LBB61_702
@@ -5828,11 +5734,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 170
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 169
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 1024
; CHECK-RV32-NEXT: bnez a3, .LBB61_703
@@ -5841,11 +5745,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 171
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 170
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 20
; CHECK-RV32-NEXT: bltz a3, .LBB61_704
@@ -5854,11 +5756,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 172
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 171
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 19
; CHECK-RV32-NEXT: bltz a3, .LBB61_705
@@ -5867,11 +5767,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 173
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 172
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 18
; CHECK-RV32-NEXT: bltz a3, .LBB61_706
@@ -5880,11 +5778,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 174
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 173
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 17
; CHECK-RV32-NEXT: bltz a3, .LBB61_707
@@ -5893,11 +5789,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 175
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 174
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 16
; CHECK-RV32-NEXT: bltz a3, .LBB61_708
@@ -5906,11 +5800,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 176
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 175
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 15
; CHECK-RV32-NEXT: bltz a3, .LBB61_709
@@ -5919,11 +5811,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 177
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 176
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 14
; CHECK-RV32-NEXT: bltz a3, .LBB61_710
@@ -5932,11 +5822,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 178
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 177
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 13
; CHECK-RV32-NEXT: bltz a3, .LBB61_711
@@ -5945,11 +5833,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 179
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 178
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 12
; CHECK-RV32-NEXT: bltz a3, .LBB61_712
@@ -5958,11 +5844,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 180
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 179
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 11
; CHECK-RV32-NEXT: bltz a3, .LBB61_713
@@ -5971,11 +5855,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 181
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 180
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 10
; CHECK-RV32-NEXT: bltz a3, .LBB61_714
@@ -5984,11 +5866,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 182
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 181
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 9
; CHECK-RV32-NEXT: bltz a3, .LBB61_715
@@ -5997,11 +5877,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 183
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 182
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 8
; CHECK-RV32-NEXT: bltz a3, .LBB61_716
@@ -6010,11 +5888,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 184
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 183
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 7
; CHECK-RV32-NEXT: bltz a3, .LBB61_717
@@ -6023,11 +5899,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 185
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 184
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 6
; CHECK-RV32-NEXT: bltz a3, .LBB61_718
@@ -6036,11 +5910,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 186
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 185
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 5
; CHECK-RV32-NEXT: bltz a3, .LBB61_719
@@ -6049,11 +5921,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 187
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 186
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 4
; CHECK-RV32-NEXT: bltz a3, .LBB61_720
@@ -6062,11 +5932,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 188
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 187
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 3
; CHECK-RV32-NEXT: bltz a3, .LBB61_721
@@ -6075,11 +5943,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a3, 0(a0)
; CHECK-RV32-NEXT: li a4, 189
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a3
+; CHECK-RV32-NEXT: vmv.s.x v16, a3
; CHECK-RV32-NEXT: li a3, 188
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a3, a2, 2
; CHECK-RV32-NEXT: bgez a3, .LBB61_1030
@@ -6088,13 +5954,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: j .LBB61_202
; CHECK-RV32-NEXT: .LBB61_722: # %cond.load761
; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 192
; CHECK-RV32-NEXT: li a4, 191
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a4
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 1
; CHECK-RV32-NEXT: bnez a2, .LBB61_723
@@ -6103,11 +5967,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 193
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 192
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 2
; CHECK-RV32-NEXT: bnez a2, .LBB61_724
@@ -6116,11 +5978,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 194
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 193
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 4
; CHECK-RV32-NEXT: bnez a2, .LBB61_725
@@ -6129,11 +5989,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 195
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 194
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 8
; CHECK-RV32-NEXT: bnez a2, .LBB61_726
@@ -6142,11 +6000,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 196
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 195
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 16
; CHECK-RV32-NEXT: bnez a2, .LBB61_727
@@ -6155,11 +6011,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 197
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 196
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 32
; CHECK-RV32-NEXT: bnez a2, .LBB61_728
@@ -6168,11 +6022,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 198
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 197
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 64
; CHECK-RV32-NEXT: bnez a2, .LBB61_729
@@ -6181,11 +6033,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 199
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 198
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 128
; CHECK-RV32-NEXT: bnez a2, .LBB61_730
@@ -6194,11 +6044,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 200
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 199
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 256
; CHECK-RV32-NEXT: bnez a2, .LBB61_731
@@ -6207,11 +6055,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 201
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 200
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 512
; CHECK-RV32-NEXT: bnez a2, .LBB61_732
@@ -6220,11 +6066,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 202
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 201
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a3, 1024
; CHECK-RV32-NEXT: bnez a2, .LBB61_733
@@ -6233,11 +6077,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 203
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 202
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 20
; CHECK-RV32-NEXT: bltz a2, .LBB61_734
@@ -6246,11 +6088,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 204
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 203
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 19
; CHECK-RV32-NEXT: bltz a2, .LBB61_735
@@ -6259,11 +6099,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 205
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 204
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 18
; CHECK-RV32-NEXT: bltz a2, .LBB61_736
@@ -6272,11 +6110,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 206
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 205
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 17
; CHECK-RV32-NEXT: bltz a2, .LBB61_737
@@ -6285,11 +6121,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 207
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 206
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 16
; CHECK-RV32-NEXT: bltz a2, .LBB61_738
@@ -6298,11 +6132,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 208
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 207
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 15
; CHECK-RV32-NEXT: bltz a2, .LBB61_739
@@ -6311,11 +6143,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 209
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 208
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 14
; CHECK-RV32-NEXT: bltz a2, .LBB61_740
@@ -6324,11 +6154,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 210
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 209
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 13
; CHECK-RV32-NEXT: bltz a2, .LBB61_741
@@ -6337,11 +6165,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 211
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 210
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 12
; CHECK-RV32-NEXT: bltz a2, .LBB61_742
@@ -6350,11 +6176,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 212
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 211
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 11
; CHECK-RV32-NEXT: bltz a2, .LBB61_743
@@ -6363,11 +6187,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 213
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 212
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 10
; CHECK-RV32-NEXT: bltz a2, .LBB61_744
@@ -6376,11 +6198,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 214
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 213
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 9
; CHECK-RV32-NEXT: bltz a2, .LBB61_745
@@ -6389,11 +6209,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 215
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 214
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 8
; CHECK-RV32-NEXT: bltz a2, .LBB61_746
@@ -6402,11 +6220,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 216
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 215
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 7
; CHECK-RV32-NEXT: bltz a2, .LBB61_747
@@ -6415,11 +6231,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 217
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 216
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 6
; CHECK-RV32-NEXT: bltz a2, .LBB61_748
@@ -6428,11 +6242,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 218
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 217
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 5
; CHECK-RV32-NEXT: bltz a2, .LBB61_749
@@ -6441,11 +6253,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 219
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 218
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 4
; CHECK-RV32-NEXT: bltz a2, .LBB61_750
@@ -6454,11 +6264,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 220
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 219
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 3
; CHECK-RV32-NEXT: bltz a2, .LBB61_751
@@ -6467,11 +6275,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a4, 221
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a2
+; CHECK-RV32-NEXT: vmv.s.x v20, a2
; CHECK-RV32-NEXT: li a2, 220
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a3, 2
; CHECK-RV32-NEXT: bgez a2, .LBB61_1031
@@ -6480,13 +6286,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: j .LBB61_236
; CHECK-RV32-NEXT: .LBB61_752: # %cond.load889
; CHECK-RV32-NEXT: lbu a2, 0(a0)
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 224
; CHECK-RV32-NEXT: li a3, 223
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 1
; CHECK-RV32-NEXT: bnez a2, .LBB61_753
@@ -6495,11 +6299,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 225
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 224
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 2
; CHECK-RV32-NEXT: bnez a2, .LBB61_754
@@ -6508,11 +6310,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 226
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 225
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 4
; CHECK-RV32-NEXT: bnez a2, .LBB61_755
@@ -6521,11 +6321,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 227
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 226
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 8
; CHECK-RV32-NEXT: bnez a2, .LBB61_756
@@ -6534,11 +6332,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 228
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 227
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 16
; CHECK-RV32-NEXT: bnez a2, .LBB61_757
@@ -6547,11 +6343,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 229
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 228
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 32
; CHECK-RV32-NEXT: bnez a2, .LBB61_758
@@ -6560,11 +6354,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 230
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 229
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 64
; CHECK-RV32-NEXT: bnez a2, .LBB61_759
@@ -6573,11 +6365,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 231
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 230
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 128
; CHECK-RV32-NEXT: bnez a2, .LBB61_760
@@ -6586,11 +6376,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 232
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 231
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 256
; CHECK-RV32-NEXT: bnez a2, .LBB61_761
@@ -6599,11 +6387,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 233
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 232
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 512
; CHECK-RV32-NEXT: bnez a2, .LBB61_762
@@ -6612,11 +6398,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 234
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 233
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a2, a4, 1024
; CHECK-RV32-NEXT: bnez a2, .LBB61_763
@@ -6625,11 +6409,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 235
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 234
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 20
; CHECK-RV32-NEXT: bltz a2, .LBB61_764
@@ -6638,11 +6420,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 236
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 235
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 19
; CHECK-RV32-NEXT: bltz a2, .LBB61_765
@@ -6651,11 +6431,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 237
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 236
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 18
; CHECK-RV32-NEXT: bltz a2, .LBB61_766
@@ -6664,11 +6442,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 238
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 237
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 17
; CHECK-RV32-NEXT: bltz a2, .LBB61_767
@@ -6677,11 +6453,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 239
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 238
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 16
; CHECK-RV32-NEXT: bltz a2, .LBB61_768
@@ -6690,11 +6464,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 240
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 239
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 15
; CHECK-RV32-NEXT: bltz a2, .LBB61_769
@@ -6703,11 +6475,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 241
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 240
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 14
; CHECK-RV32-NEXT: bltz a2, .LBB61_770
@@ -6716,11 +6486,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 242
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 241
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 13
; CHECK-RV32-NEXT: bltz a2, .LBB61_771
@@ -6729,11 +6497,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 243
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 242
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 12
; CHECK-RV32-NEXT: bltz a2, .LBB61_772
@@ -6742,11 +6508,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 244
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 243
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 11
; CHECK-RV32-NEXT: bltz a2, .LBB61_773
@@ -6755,11 +6519,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 245
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 244
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 10
; CHECK-RV32-NEXT: bltz a2, .LBB61_774
@@ -6768,11 +6530,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 246
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 245
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 9
; CHECK-RV32-NEXT: bltz a2, .LBB61_775
@@ -6781,11 +6541,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 247
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 246
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 8
; CHECK-RV32-NEXT: bltz a2, .LBB61_776
@@ -6794,11 +6552,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 248
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 247
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 7
; CHECK-RV32-NEXT: bltz a2, .LBB61_777
@@ -6807,11 +6563,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 249
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 248
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 6
; CHECK-RV32-NEXT: bltz a2, .LBB61_778
@@ -6820,11 +6574,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 250
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 249
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 5
; CHECK-RV32-NEXT: bltz a2, .LBB61_779
@@ -6833,11 +6585,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 251
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 250
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 4
; CHECK-RV32-NEXT: bltz a2, .LBB61_780
@@ -6846,11 +6596,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 252
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 251
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 3
; CHECK-RV32-NEXT: bltz a2, .LBB61_781
@@ -6859,11 +6607,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: lbu a2, 0(a0)
; CHECK-RV32-NEXT: li a3, 253
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vmv4r.v v16, v8
-; CHECK-RV32-NEXT: vmv.s.x v20, a2
+; CHECK-RV32-NEXT: vmv.s.x v16, a2
; CHECK-RV32-NEXT: li a2, 252
-; CHECK-RV32-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV32-NEXT: vmv4r.v v8, v16
+; CHECK-RV32-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: slli a2, a4, 2
; CHECK-RV32-NEXT: bgez a2, .LBB61_1032
@@ -6872,13 +6618,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: j .LBB61_270
; CHECK-RV32-NEXT: .LBB61_782: # %cond.load1017
; CHECK-RV32-NEXT: lbu a3, 0(a0)
-; CHECK-RV32-NEXT: vmv4r.v v20, v8
-; CHECK-RV32-NEXT: vmv.s.x v24, a3
+; CHECK-RV32-NEXT: vmv.s.x v20, a3
; CHECK-RV32-NEXT: li a3, 256
; CHECK-RV32-NEXT: li a4, 255
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV32-NEXT: vslideup.vx v20, v24, a4
-; CHECK-RV32-NEXT: vmv4r.v v8, v20
+; CHECK-RV32-NEXT: vslideup.vx v8, v20, a4
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: andi a3, a2, 1
; CHECK-RV32-NEXT: bnez a3, .LBB61_783
@@ -10364,11 +10108,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 190
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 189
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_195: # %else754
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -10377,13 +10119,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: bgez a2, .LBB61_197
; CHECK-RV64-NEXT: # %bb.196: # %cond.load757
; CHECK-RV64-NEXT: lbu a2, 0(a0)
-; CHECK-RV64-NEXT: vmv4r.v v20, v8
-; CHECK-RV64-NEXT: vmv.s.x v24, a2
+; CHECK-RV64-NEXT: vmv.s.x v20, a2
; CHECK-RV64-NEXT: li a2, 191
; CHECK-RV64-NEXT: li a3, 190
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vslideup.vx v20, v24, a3
-; CHECK-RV64-NEXT: vmv4r.v v8, v20
+; CHECK-RV64-NEXT: vslideup.vx v8, v20, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_197: # %else758
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -10641,11 +10381,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 254
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 253
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_261: # %else1010
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -10654,13 +10392,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: bgez a1, .LBB61_263
; CHECK-RV64-NEXT: # %bb.262: # %cond.load1013
; CHECK-RV64-NEXT: lbu a1, 0(a0)
-; CHECK-RV64-NEXT: vmv4r.v v20, v8
-; CHECK-RV64-NEXT: vmv.s.x v24, a1
+; CHECK-RV64-NEXT: vmv.s.x v20, a1
; CHECK-RV64-NEXT: li a1, 255
; CHECK-RV64-NEXT: li a3, 254
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vslideup.vx v20, v24, a3
-; CHECK-RV64-NEXT: vmv4r.v v8, v20
+; CHECK-RV64-NEXT: vslideup.vx v8, v20, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: .LBB61_263: # %else1014
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -13300,11 +13036,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 129
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 128
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 2
; CHECK-RV64-NEXT: bnez a2, .LBB61_652
@@ -13313,11 +13047,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 130
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 129
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 4
; CHECK-RV64-NEXT: bnez a2, .LBB61_653
@@ -13326,11 +13058,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 131
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 130
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 8
; CHECK-RV64-NEXT: bnez a2, .LBB61_654
@@ -13339,11 +13069,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 132
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 131
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 16
; CHECK-RV64-NEXT: bnez a2, .LBB61_655
@@ -13352,11 +13080,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 133
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 132
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 32
; CHECK-RV64-NEXT: bnez a2, .LBB61_656
@@ -13365,11 +13091,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 134
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 133
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 64
; CHECK-RV64-NEXT: bnez a2, .LBB61_657
@@ -13378,11 +13102,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 135
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 134
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 128
; CHECK-RV64-NEXT: bnez a2, .LBB61_658
@@ -13391,11 +13113,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 136
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 135
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 256
; CHECK-RV64-NEXT: bnez a2, .LBB61_659
@@ -13404,11 +13124,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 137
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 136
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 512
; CHECK-RV64-NEXT: bnez a2, .LBB61_660
@@ -13417,11 +13135,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 138
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 137
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 1024
; CHECK-RV64-NEXT: bnez a2, .LBB61_661
@@ -13430,11 +13146,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 139
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 138
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 52
; CHECK-RV64-NEXT: bltz a2, .LBB61_662
@@ -13443,11 +13157,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 140
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 139
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 51
; CHECK-RV64-NEXT: bltz a2, .LBB61_663
@@ -13456,11 +13168,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 141
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 140
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 50
; CHECK-RV64-NEXT: bltz a2, .LBB61_664
@@ -13469,11 +13179,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 142
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 141
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 49
; CHECK-RV64-NEXT: bltz a2, .LBB61_665
@@ -13482,11 +13190,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 143
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 142
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 48
; CHECK-RV64-NEXT: bltz a2, .LBB61_666
@@ -13495,11 +13201,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 144
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 143
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 47
; CHECK-RV64-NEXT: bltz a2, .LBB61_667
@@ -13508,11 +13212,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 145
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 144
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 46
; CHECK-RV64-NEXT: bltz a2, .LBB61_668
@@ -13521,11 +13223,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 146
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 145
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 45
; CHECK-RV64-NEXT: bltz a2, .LBB61_669
@@ -13534,11 +13234,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 147
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 146
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 44
; CHECK-RV64-NEXT: bltz a2, .LBB61_670
@@ -13547,11 +13245,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 148
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 147
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 43
; CHECK-RV64-NEXT: bltz a2, .LBB61_671
@@ -13560,11 +13256,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 149
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 148
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 42
; CHECK-RV64-NEXT: bltz a2, .LBB61_672
@@ -13573,11 +13267,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 150
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 149
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 41
; CHECK-RV64-NEXT: bltz a2, .LBB61_673
@@ -13586,11 +13278,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 151
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 150
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 40
; CHECK-RV64-NEXT: bltz a2, .LBB61_674
@@ -13599,11 +13289,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 152
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 151
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 39
; CHECK-RV64-NEXT: bltz a2, .LBB61_675
@@ -13612,11 +13300,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 153
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 152
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 38
; CHECK-RV64-NEXT: bltz a2, .LBB61_676
@@ -13625,11 +13311,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 154
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 153
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 37
; CHECK-RV64-NEXT: bltz a2, .LBB61_677
@@ -13638,11 +13322,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 155
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 154
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 36
; CHECK-RV64-NEXT: bltz a2, .LBB61_678
@@ -13651,11 +13333,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 156
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 155
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 35
; CHECK-RV64-NEXT: bltz a2, .LBB61_679
@@ -13664,11 +13344,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 157
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 156
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 34
; CHECK-RV64-NEXT: bltz a2, .LBB61_680
@@ -13677,11 +13355,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 158
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 157
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 33
; CHECK-RV64-NEXT: bltz a2, .LBB61_681
@@ -13690,11 +13366,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 159
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 158
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 32
; CHECK-RV64-NEXT: bltz a2, .LBB61_682
@@ -13703,11 +13377,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 160
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 159
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 31
; CHECK-RV64-NEXT: bltz a2, .LBB61_683
@@ -13716,11 +13388,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 161
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 160
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 30
; CHECK-RV64-NEXT: bltz a2, .LBB61_684
@@ -13729,11 +13399,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 162
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 161
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 29
; CHECK-RV64-NEXT: bltz a2, .LBB61_685
@@ -13742,11 +13410,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 163
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 162
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 28
; CHECK-RV64-NEXT: bltz a2, .LBB61_686
@@ -13755,11 +13421,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 164
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 163
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 27
; CHECK-RV64-NEXT: bltz a2, .LBB61_687
@@ -13768,11 +13432,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 165
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 164
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 26
; CHECK-RV64-NEXT: bltz a2, .LBB61_688
@@ -13781,11 +13443,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 166
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 165
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 25
; CHECK-RV64-NEXT: bltz a2, .LBB61_689
@@ -13794,11 +13454,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 167
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 166
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 24
; CHECK-RV64-NEXT: bltz a2, .LBB61_690
@@ -13807,11 +13465,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 168
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 167
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 23
; CHECK-RV64-NEXT: bltz a2, .LBB61_691
@@ -13820,11 +13476,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 169
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 168
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 22
; CHECK-RV64-NEXT: bltz a2, .LBB61_692
@@ -13833,11 +13487,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 170
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 169
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 21
; CHECK-RV64-NEXT: bltz a2, .LBB61_693
@@ -13846,11 +13498,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 171
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 170
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 20
; CHECK-RV64-NEXT: bltz a2, .LBB61_694
@@ -13859,11 +13509,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 172
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 171
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 19
; CHECK-RV64-NEXT: bltz a2, .LBB61_695
@@ -13872,11 +13520,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 173
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 172
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 18
; CHECK-RV64-NEXT: bltz a2, .LBB61_696
@@ -13885,11 +13531,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 174
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 173
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 17
; CHECK-RV64-NEXT: bltz a2, .LBB61_697
@@ -13898,11 +13542,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 175
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 174
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 16
; CHECK-RV64-NEXT: bltz a2, .LBB61_698
@@ -13911,11 +13553,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 176
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 175
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 15
; CHECK-RV64-NEXT: bltz a2, .LBB61_699
@@ -13924,11 +13564,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 177
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 176
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 14
; CHECK-RV64-NEXT: bltz a2, .LBB61_700
@@ -13937,11 +13575,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 178
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 177
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 13
; CHECK-RV64-NEXT: bltz a2, .LBB61_701
@@ -13950,11 +13586,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 179
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 178
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 12
; CHECK-RV64-NEXT: bltz a2, .LBB61_702
@@ -13963,11 +13597,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 180
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 179
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 11
; CHECK-RV64-NEXT: bltz a2, .LBB61_703
@@ -13976,11 +13608,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 181
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 180
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 10
; CHECK-RV64-NEXT: bltz a2, .LBB61_704
@@ -13989,11 +13619,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 182
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 181
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 9
; CHECK-RV64-NEXT: bltz a2, .LBB61_705
@@ -14002,11 +13630,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 183
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 182
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 8
; CHECK-RV64-NEXT: bltz a2, .LBB61_706
@@ -14015,11 +13641,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 184
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 183
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 7
; CHECK-RV64-NEXT: bltz a2, .LBB61_707
@@ -14028,11 +13652,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 185
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 184
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 6
; CHECK-RV64-NEXT: bltz a2, .LBB61_708
@@ -14041,11 +13663,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 186
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 185
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 5
; CHECK-RV64-NEXT: bltz a2, .LBB61_709
@@ -14054,11 +13674,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 187
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 186
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 4
; CHECK-RV64-NEXT: bltz a2, .LBB61_710
@@ -14067,11 +13685,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 188
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 187
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 3
; CHECK-RV64-NEXT: bltz a2, .LBB61_711
@@ -14080,11 +13696,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a2, 0(a0)
; CHECK-RV64-NEXT: li a3, 189
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 188
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a2
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a2
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a2, a1, 2
; CHECK-RV64-NEXT: bgez a2, .LBB61_1027
@@ -14093,13 +13707,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: j .LBB61_195
; CHECK-RV64-NEXT: .LBB61_712: # %cond.load761
; CHECK-RV64-NEXT: lbu a1, 0(a0)
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 192
; CHECK-RV64-NEXT: li a3, 191
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 1
; CHECK-RV64-NEXT: bnez a1, .LBB61_713
@@ -14108,11 +13720,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 193
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 192
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 2
; CHECK-RV64-NEXT: bnez a1, .LBB61_714
@@ -14121,11 +13731,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 194
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 193
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 4
; CHECK-RV64-NEXT: bnez a1, .LBB61_715
@@ -14134,11 +13742,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 195
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 194
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 8
; CHECK-RV64-NEXT: bnez a1, .LBB61_716
@@ -14147,11 +13753,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 196
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 195
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 16
; CHECK-RV64-NEXT: bnez a1, .LBB61_717
@@ -14160,11 +13764,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 197
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 196
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 32
; CHECK-RV64-NEXT: bnez a1, .LBB61_718
@@ -14173,11 +13775,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 198
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 197
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 64
; CHECK-RV64-NEXT: bnez a1, .LBB61_719
@@ -14186,11 +13786,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 199
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 198
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 128
; CHECK-RV64-NEXT: bnez a1, .LBB61_720
@@ -14199,11 +13797,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 200
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 199
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 256
; CHECK-RV64-NEXT: bnez a1, .LBB61_721
@@ -14212,11 +13808,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 201
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 200
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 512
; CHECK-RV64-NEXT: bnez a1, .LBB61_722
@@ -14225,11 +13819,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 202
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 201
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a1, a2, 1024
; CHECK-RV64-NEXT: bnez a1, .LBB61_723
@@ -14238,11 +13830,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 203
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 202
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 52
; CHECK-RV64-NEXT: bltz a1, .LBB61_724
@@ -14251,11 +13841,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 204
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 203
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 51
; CHECK-RV64-NEXT: bltz a1, .LBB61_725
@@ -14264,11 +13852,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 205
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 204
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 50
; CHECK-RV64-NEXT: bltz a1, .LBB61_726
@@ -14277,11 +13863,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 206
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 205
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 49
; CHECK-RV64-NEXT: bltz a1, .LBB61_727
@@ -14290,11 +13874,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 207
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 206
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 48
; CHECK-RV64-NEXT: bltz a1, .LBB61_728
@@ -14303,11 +13885,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 208
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 207
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 47
; CHECK-RV64-NEXT: bltz a1, .LBB61_729
@@ -14316,11 +13896,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 209
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 208
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 46
; CHECK-RV64-NEXT: bltz a1, .LBB61_730
@@ -14329,11 +13907,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 210
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 209
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 45
; CHECK-RV64-NEXT: bltz a1, .LBB61_731
@@ -14342,11 +13918,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 211
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 210
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 44
; CHECK-RV64-NEXT: bltz a1, .LBB61_732
@@ -14355,11 +13929,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 212
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 211
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 43
; CHECK-RV64-NEXT: bltz a1, .LBB61_733
@@ -14368,11 +13940,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 213
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 212
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 42
; CHECK-RV64-NEXT: bltz a1, .LBB61_734
@@ -14381,11 +13951,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 214
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 213
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 41
; CHECK-RV64-NEXT: bltz a1, .LBB61_735
@@ -14394,11 +13962,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 215
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 214
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 40
; CHECK-RV64-NEXT: bltz a1, .LBB61_736
@@ -14407,11 +13973,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 216
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 215
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 39
; CHECK-RV64-NEXT: bltz a1, .LBB61_737
@@ -14420,11 +13984,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 217
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 216
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 38
; CHECK-RV64-NEXT: bltz a1, .LBB61_738
@@ -14433,11 +13995,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 218
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 217
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 37
; CHECK-RV64-NEXT: bltz a1, .LBB61_739
@@ -14446,11 +14006,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 219
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 218
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 36
; CHECK-RV64-NEXT: bltz a1, .LBB61_740
@@ -14459,11 +14017,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 220
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 219
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 35
; CHECK-RV64-NEXT: bltz a1, .LBB61_741
@@ -14472,11 +14028,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 221
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 220
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 34
; CHECK-RV64-NEXT: bltz a1, .LBB61_742
@@ -14485,11 +14039,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 222
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 221
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 33
; CHECK-RV64-NEXT: bltz a1, .LBB61_743
@@ -14498,11 +14050,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 223
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 222
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 32
; CHECK-RV64-NEXT: bltz a1, .LBB61_744
@@ -14511,11 +14061,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 224
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 223
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 31
; CHECK-RV64-NEXT: bltz a1, .LBB61_745
@@ -14524,11 +14072,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 225
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 224
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 30
; CHECK-RV64-NEXT: bltz a1, .LBB61_746
@@ -14537,11 +14083,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 226
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 225
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 29
; CHECK-RV64-NEXT: bltz a1, .LBB61_747
@@ -14550,11 +14094,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 227
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 226
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 28
; CHECK-RV64-NEXT: bltz a1, .LBB61_748
@@ -14563,11 +14105,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 228
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 227
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 27
; CHECK-RV64-NEXT: bltz a1, .LBB61_749
@@ -14576,11 +14116,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 229
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 228
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 26
; CHECK-RV64-NEXT: bltz a1, .LBB61_750
@@ -14589,11 +14127,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 230
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 229
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 25
; CHECK-RV64-NEXT: bltz a1, .LBB61_751
@@ -14602,11 +14138,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 231
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 230
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 24
; CHECK-RV64-NEXT: bltz a1, .LBB61_752
@@ -14615,11 +14149,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 232
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 231
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 23
; CHECK-RV64-NEXT: bltz a1, .LBB61_753
@@ -14628,11 +14160,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 233
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 232
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 22
; CHECK-RV64-NEXT: bltz a1, .LBB61_754
@@ -14641,11 +14171,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 234
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 233
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 21
; CHECK-RV64-NEXT: bltz a1, .LBB61_755
@@ -14654,11 +14182,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 235
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 234
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 20
; CHECK-RV64-NEXT: bltz a1, .LBB61_756
@@ -14667,11 +14193,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 236
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 235
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 19
; CHECK-RV64-NEXT: bltz a1, .LBB61_757
@@ -14680,11 +14204,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 237
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 236
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 18
; CHECK-RV64-NEXT: bltz a1, .LBB61_758
@@ -14693,11 +14215,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 238
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 237
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 17
; CHECK-RV64-NEXT: bltz a1, .LBB61_759
@@ -14706,11 +14226,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 239
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 238
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 16
; CHECK-RV64-NEXT: bltz a1, .LBB61_760
@@ -14719,11 +14237,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 240
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 239
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 15
; CHECK-RV64-NEXT: bltz a1, .LBB61_761
@@ -14732,11 +14248,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 241
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 240
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 14
; CHECK-RV64-NEXT: bltz a1, .LBB61_762
@@ -14745,11 +14259,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 242
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 241
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 13
; CHECK-RV64-NEXT: bltz a1, .LBB61_763
@@ -14758,11 +14270,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 243
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 242
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 12
; CHECK-RV64-NEXT: bltz a1, .LBB61_764
@@ -14771,11 +14281,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 244
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 243
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 11
; CHECK-RV64-NEXT: bltz a1, .LBB61_765
@@ -14784,11 +14292,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 245
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 244
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 10
; CHECK-RV64-NEXT: bltz a1, .LBB61_766
@@ -14797,11 +14303,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 246
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 245
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 9
; CHECK-RV64-NEXT: bltz a1, .LBB61_767
@@ -14810,11 +14314,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 247
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 246
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 8
; CHECK-RV64-NEXT: bltz a1, .LBB61_768
@@ -14823,11 +14325,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 248
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 247
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 7
; CHECK-RV64-NEXT: bltz a1, .LBB61_769
@@ -14836,11 +14336,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 249
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 248
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 6
; CHECK-RV64-NEXT: bltz a1, .LBB61_770
@@ -14849,11 +14347,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 250
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 249
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 5
; CHECK-RV64-NEXT: bltz a1, .LBB61_771
@@ -14862,11 +14358,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 251
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 250
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 4
; CHECK-RV64-NEXT: bltz a1, .LBB61_772
@@ -14875,11 +14369,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 252
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 251
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 3
; CHECK-RV64-NEXT: bltz a1, .LBB61_773
@@ -14888,11 +14380,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: li a3, 253
; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a1
+; CHECK-RV64-NEXT: vmv.s.x v16, a1
; CHECK-RV64-NEXT: li a1, 252
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: slli a1, a2, 2
; CHECK-RV64-NEXT: bgez a1, .LBB61_1028
@@ -14901,13 +14391,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: j .LBB61_261
; CHECK-RV64-NEXT: .LBB61_774: # %cond.load1017
; CHECK-RV64-NEXT: lbu a2, 0(a0)
-; CHECK-RV64-NEXT: vmv4r.v v16, v8
-; CHECK-RV64-NEXT: vmv.s.x v20, a2
+; CHECK-RV64-NEXT: vmv.s.x v16, a2
; CHECK-RV64-NEXT: li a2, 256
; CHECK-RV64-NEXT: li a3, 255
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m4, tu, ma
-; CHECK-RV64-NEXT: vslideup.vx v16, v20, a3
-; CHECK-RV64-NEXT: vmv4r.v v8, v16
+; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: andi a2, a1, 1
; CHECK-RV64-NEXT: bnez a2, .LBB61_775
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
index 534eb5ca75fc4..7c4349160db18 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
@@ -396,7 +396,7 @@ define void @shuffle_i128_ldst(ptr %p) vscale_range(2,2) {
; CHECK-NEXT: vl4re64.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: vmv2r.v v12, v8
; CHECK-NEXT: vmv1r.v v14, v11
; CHECK-NEXT: vmv1r.v v15, v10
; CHECK-NEXT: vs4r.v v12, (a0)
@@ -414,7 +414,7 @@ define void @shuffle_i256_ldst(ptr %p) vscale_range(2,2) {
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v8
; CHECK-NEXT: vmv1r.v v11, v9
-; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: vmv4r.v v16, v8
; CHECK-NEXT: vmv1r.v v20, v14
; CHECK-NEXT: vmv1r.v v21, v15
; CHECK-NEXT: vmv1r.v v22, v12
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
index 615f2b2774d72..33453710ccbcb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
@@ -99,7 +99,7 @@ define void @vector_interleave_store_nxv16i64_nxv8i64(<vscale x 8 x i64> %a, <vs
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vid.v v6
; CHECK-NEXT: vand.vi v4, v6, 1
-; CHECK-NEXT: vmv8r.v v24, v8
+; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: vmv4r.v v28, v16
; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vmsne.vi v0, v4, 0
diff --git a/llvm/test/CodeGen/Thumb2/mve-vst2.ll b/llvm/test/CodeGen/Thumb2/mve-vst2.ll
index fa7b0e4d6bcc8..6d2e5487d0d7b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vst2.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vst2.ll
@@ -200,26 +200,25 @@ define void @vst2_v8i16_align1(ptr %src, ptr %dst) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vmovx.f16 s13, s8
+; CHECK-NEXT: vins.f16 s8, s4
+; CHECK-NEXT: vmovx.f16 s4, s4
; CHECK-NEXT: vmovx.f16 s1, s10
; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vins.f16 s10, s6
; CHECK-NEXT: vmovx.f16 s3, s11
-; CHECK-NEXT: vmovx.f16 s6, s7
; CHECK-NEXT: vins.f16 s11, s7
-; CHECK-NEXT: vins.f16 s3, s6
-; CHECK-NEXT: vmovx.f16 s6, s8
-; CHECK-NEXT: vins.f16 s8, s4
-; CHECK-NEXT: vmovx.f16 s4, s4
-; CHECK-NEXT: vmov q3, q2
-; CHECK-NEXT: vins.f16 s6, s4
+; CHECK-NEXT: vmovx.f16 s6, s7
+; CHECK-NEXT: vins.f16 s13, s4
; CHECK-NEXT: vmovx.f16 s15, s9
; CHECK-NEXT: vins.f16 s9, s5
; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vins.f16 s1, s0
; CHECK-NEXT: vmov.f32 s0, s10
-; CHECK-NEXT: vins.f16 s15, s4
+; CHECK-NEXT: vins.f16 s3, s6
; CHECK-NEXT: vmov.f32 s2, s11
-; CHECK-NEXT: vmov.f32 s13, s6
+; CHECK-NEXT: vins.f16 s15, s4
+; CHECK-NEXT: vmov.f32 s12, s8
; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s14, s9
; CHECK-NEXT: vstrb.8 q3, [r1]
@@ -583,24 +582,22 @@ define void @vst2_v8f16_align1(ptr %src, ptr %dst) {
; CHECK-NEXT: vins.f16 s1, s0
; CHECK-NEXT: vmovx.f16 s3, s7
; CHECK-NEXT: vmovx.f16 s0, s11
-; CHECK-NEXT: vins.f16 s6, s10
+; CHECK-NEXT: vmovx.f16 s13, s4
; CHECK-NEXT: vins.f16 s3, s0
-; CHECK-NEXT: vmovx.f16 s10, s4
; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vins.f16 s7, s11
; CHECK-NEXT: vins.f16 s4, s8
-; CHECK-NEXT: vins.f16 s10, s0
-; CHECK-NEXT: vmovx.f16 s8, s5
+; CHECK-NEXT: vins.f16 s13, s0
+; CHECK-NEXT: vmovx.f16 s15, s5
; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vmovx.f16 s0, s9
-; CHECK-NEXT: vmov q3, q1
-; CHECK-NEXT: vins.f16 s8, s0
+; CHECK-NEXT: vins.f16 s6, s10
+; CHECK-NEXT: vins.f16 s15, s0
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s2, s7
-; CHECK-NEXT: vmov.f32 s13, s10
+; CHECK-NEXT: vmov.f32 s12, s4
; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s14, s5
-; CHECK-NEXT: vmov.f32 s15, s8
; CHECK-NEXT: vstrb.8 q3, [r1]
; CHECK-NEXT: bx lr
entry:
diff --git a/llvm/test/CodeGen/Thumb2/mve-vst3.ll b/llvm/test/CodeGen/Thumb2/mve-vst3.ll
index 8e140187c20a2..845b3dee6ecf9 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vst3.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vst3.ll
@@ -1215,30 +1215,28 @@ define void @vst3_v4f16(ptr %src, ptr %dst) {
; CHECK-NEXT: ldrd r3, r2, [r0, #8]
; CHECK-NEXT: ldrd r4, r0, [r0, #16]
; CHECK-NEXT: vmov q0[2], q0[0], lr, r3
-; CHECK-NEXT: vmov.32 q2[0], r4
; CHECK-NEXT: vmov q0[3], q0[1], r12, r2
-; CHECK-NEXT: vmov q1, q2
-; CHECK-NEXT: vmovx.f16 s9, s3
-; CHECK-NEXT: vmov.32 q1[1], r0
-; CHECK-NEXT: vmovx.f16 s4, s0
-; CHECK-NEXT: vmov.f32 s6, s8
+; CHECK-NEXT: vmov.32 q1[0], r4
+; CHECK-NEXT: vmov q2, q1
+; CHECK-NEXT: vmovx.f16 s6, s0
+; CHECK-NEXT: vmov.f32 s5, s4
+; CHECK-NEXT: vmov.32 q2[1], r0
+; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vins.f16 s0, s2
+; CHECK-NEXT: vmovx.f16 s6, s2
+; CHECK-NEXT: vmovx.f16 s4, s4
+; CHECK-NEXT: vmovx.f16 s2, s1
; CHECK-NEXT: vins.f16 s6, s4
-; CHECK-NEXT: vmovx.f16 s4, s8
-; CHECK-NEXT: vmovx.f16 s2, s2
-; CHECK-NEXT: vins.f16 s2, s4
-; CHECK-NEXT: vmovx.f16 s4, s1
-; CHECK-NEXT: vmovx.f16 s8, s5
-; CHECK-NEXT: vins.f16 s5, s4
-; CHECK-NEXT: vins.f16 s9, s8
-; CHECK-NEXT: vmov.f32 s8, s5
+; CHECK-NEXT: vmovx.f16 s4, s9
+; CHECK-NEXT: vins.f16 s9, s2
+; CHECK-NEXT: vmov.f32 s12, s9
+; CHECK-NEXT: vmovx.f16 s13, s3
+; CHECK-NEXT: vins.f16 s13, s4
; CHECK-NEXT: vins.f16 s1, s3
-; CHECK-NEXT: vmov r0, r2, d4
-; CHECK-NEXT: vmov q2, q0
-; CHECK-NEXT: vmov.f32 s9, s6
-; CHECK-NEXT: vmov.f32 s10, s2
-; CHECK-NEXT: vmov.f32 s11, s1
-; CHECK-NEXT: vstrw.32 q2, [r1]
+; CHECK-NEXT: vmov.f32 s4, s0
+; CHECK-NEXT: vmov.f32 s7, s1
+; CHECK-NEXT: vstrw.32 q1, [r1]
+; CHECK-NEXT: vmov r0, r2, d6
; CHECK-NEXT: strd r0, r2, [r1, #16]
; CHECK-NEXT: pop {r4, pc}
entry:
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