[llvm] 276f45f - [AMDGPU][NFC] Pre-commit test for constant-offset named barrier signal_var (#205217)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 30 09:54:59 PDT 2026
Author: Chinmay Deshpande
Date: 2026-06-30T09:54:53-07:00
New Revision: 276f45fcf2e9d3f59bc7dc3bb924888b0d6cbb56
URL: https://github.com/llvm/llvm-project/commit/276f45fcf2e9d3f59bc7dc3bb924888b0d6cbb56
DIFF: https://github.com/llvm/llvm-project/commit/276f45fcf2e9d3f59bc7dc3bb924888b0d6cbb56.diff
LOG: [AMDGPU][NFC] Pre-commit test for constant-offset named barrier signal_var (#205217)
Added:
llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll b/llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
new file mode 100644
index 0000000000000..b4e7d3cb16128
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
@@ -0,0 +1,258 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=GISEL %s
+; RUN: llc -global-isel=0 -amdgpu-enable-object-linking -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=OBJ-SDAG %s
+; RUN: llc -global-isel=1 -amdgpu-enable-object-linking -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=OBJ-GISEL %s
+
+ at bars = internal addrspace(3) global [2 x target("amdgcn.named.barrier", 0)] poison
+
+; A constant-offset GEP into an array of named barriers (&bars[1]) is a
+; compile-time-constant barrier address and should select the immediate
+; s_barrier_signal form, like the bare &bars[0]. With object linking the
+; barrier is externalized and the offset folds into the relocation addend
+; (... at abs32@lo+16) instead of a runtime add.
+
+define amdgpu_kernel void @signal_var_bar0() {
+; SDAG-LABEL: signal_var_bar0:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-NEXT: s_mov_b32 m0, 0x100001
+; SDAG-NEXT: s_barrier_init m0
+; SDAG-NEXT: s_barrier_signal 1
+; SDAG-NEXT: s_barrier_wait 0
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: signal_var_bar0:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: s_mov_b32 m0, 0x100001
+; GISEL-NEXT: s_barrier_init m0
+; GISEL-NEXT: s_barrier_signal 1
+; GISEL-NEXT: s_barrier_wait 0
+; GISEL-NEXT: s_endpgm
+;
+; OBJ-SDAG-LABEL: signal_var_bar0:
+; OBJ-SDAG: ; %bb.0:
+; OBJ-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-SDAG-NEXT: s_lshr_b32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, 4
+; OBJ-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-SDAG-NEXT: s_and_b32 s0, s0, 63
+; OBJ-SDAG-NEXT: s_or_b32 m0, 0x100000, s0
+; OBJ-SDAG-NEXT: s_barrier_init m0
+; OBJ-SDAG-NEXT: s_mov_b32 m0, s0
+; OBJ-SDAG-NEXT: s_barrier_signal m0
+; OBJ-SDAG-NEXT: s_barrier_wait 0
+; OBJ-SDAG-NEXT: s_endpgm
+;
+; OBJ-GISEL-LABEL: signal_var_bar0:
+; OBJ-GISEL: ; %bb.0:
+; OBJ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-GISEL-NEXT: s_lshr_b32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, 4
+; OBJ-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-GISEL-NEXT: s_and_b32 s0, s0, 63
+; OBJ-GISEL-NEXT: s_or_b32 m0, s0, 0x100000
+; OBJ-GISEL-NEXT: s_barrier_init m0
+; OBJ-GISEL-NEXT: s_mov_b32 m0, s0
+; OBJ-GISEL-NEXT: s_barrier_signal m0
+; OBJ-GISEL-NEXT: s_barrier_wait 0
+; OBJ-GISEL-NEXT: s_endpgm
+ call void @llvm.amdgcn.s.barrier.init(ptr addrspace(3) @bars, i32 16)
+ call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bars, i32 0)
+ call void @llvm.amdgcn.s.barrier.wait(i16 0)
+ ret void
+}
+
+define amdgpu_kernel void @signal_var_bar1() {
+; SDAG-LABEL: signal_var_bar1:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-NEXT: s_mov_b32 m0, 0x100002
+; SDAG-NEXT: s_barrier_init m0
+; SDAG-NEXT: s_mov_b32 m0, 2
+; SDAG-NEXT: s_barrier_signal m0
+; SDAG-NEXT: s_barrier_wait 1
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: signal_var_bar1:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: s_mov_b32 m0, 0x100002
+; GISEL-NEXT: s_barrier_init m0
+; GISEL-NEXT: s_barrier_signal 2
+; GISEL-NEXT: s_barrier_wait 1
+; GISEL-NEXT: s_endpgm
+;
+; OBJ-SDAG-LABEL: signal_var_bar1:
+; OBJ-SDAG: ; %bb.0:
+; OBJ-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-SDAG-NEXT: s_add_co_i32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, 16
+; OBJ-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-SDAG-NEXT: s_lshr_b32 s0, s0, 4
+; OBJ-SDAG-NEXT: s_and_b32 s0, s0, 63
+; OBJ-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; OBJ-SDAG-NEXT: s_or_b32 m0, 0x100000, s0
+; OBJ-SDAG-NEXT: s_barrier_init m0
+; OBJ-SDAG-NEXT: s_mov_b32 m0, s0
+; OBJ-SDAG-NEXT: s_barrier_signal m0
+; OBJ-SDAG-NEXT: s_barrier_wait 1
+; OBJ-SDAG-NEXT: s_endpgm
+;
+; OBJ-GISEL-LABEL: signal_var_bar1:
+; OBJ-GISEL: ; %bb.0:
+; OBJ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-GISEL-NEXT: s_add_co_u32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, 16
+; OBJ-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-GISEL-NEXT: s_lshr_b32 s0, s0, 4
+; OBJ-GISEL-NEXT: s_and_b32 s0, s0, 63
+; OBJ-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; OBJ-GISEL-NEXT: s_or_b32 m0, s0, 0x100000
+; OBJ-GISEL-NEXT: s_barrier_init m0
+; OBJ-GISEL-NEXT: s_mov_b32 m0, s0
+; OBJ-GISEL-NEXT: s_barrier_signal m0
+; OBJ-GISEL-NEXT: s_barrier_wait 1
+; OBJ-GISEL-NEXT: s_endpgm
+ %p1 = getelementptr inbounds [2 x target("amdgcn.named.barrier", 0)], ptr addrspace(3) @bars, i32 0, i32 1
+ call void @llvm.amdgcn.s.barrier.init(ptr addrspace(3) %p1, i32 16)
+ call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) %p1, i32 0)
+ call void @llvm.amdgcn.s.barrier.wait(i16 1)
+ ret void
+}
+
+; A byte offset that does not land on a named-barrier boundary is valid IR and
+; must not crash the compiler. The offset folds into the address; a sub-object
+; offset stays within barrier 0 and selects the same barrier as &bars[0].
+
+define amdgpu_kernel void @signal_var_misaligned() {
+; SDAG-LABEL: signal_var_misaligned:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-NEXT: s_mov_b32 m0, 0x100001
+; SDAG-NEXT: s_barrier_init m0
+; SDAG-NEXT: s_mov_b32 m0, 1
+; SDAG-NEXT: s_barrier_signal m0
+; SDAG-NEXT: s_barrier_wait 1
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: signal_var_misaligned:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: s_mov_b32 m0, 0x100001
+; GISEL-NEXT: s_barrier_init m0
+; GISEL-NEXT: s_barrier_signal 1
+; GISEL-NEXT: s_barrier_wait 1
+; GISEL-NEXT: s_endpgm
+;
+; OBJ-SDAG-LABEL: signal_var_misaligned:
+; OBJ-SDAG: ; %bb.0:
+; OBJ-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-SDAG-NEXT: s_lshr_b32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, 4
+; OBJ-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-SDAG-NEXT: s_and_b32 s0, s0, 63
+; OBJ-SDAG-NEXT: s_or_b32 m0, 0x100000, s0
+; OBJ-SDAG-NEXT: s_barrier_init m0
+; OBJ-SDAG-NEXT: s_mov_b32 m0, s0
+; OBJ-SDAG-NEXT: s_barrier_signal m0
+; OBJ-SDAG-NEXT: s_barrier_wait 1
+; OBJ-SDAG-NEXT: s_endpgm
+;
+; OBJ-GISEL-LABEL: signal_var_misaligned:
+; OBJ-GISEL: ; %bb.0:
+; OBJ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-GISEL-NEXT: s_add_co_u32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, 1
+; OBJ-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-GISEL-NEXT: s_lshr_b32 s0, s0, 4
+; OBJ-GISEL-NEXT: s_and_b32 s0, s0, 63
+; OBJ-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; OBJ-GISEL-NEXT: s_or_b32 m0, s0, 0x100000
+; OBJ-GISEL-NEXT: s_barrier_init m0
+; OBJ-GISEL-NEXT: s_mov_b32 m0, s0
+; OBJ-GISEL-NEXT: s_barrier_signal m0
+; OBJ-GISEL-NEXT: s_barrier_wait 1
+; OBJ-GISEL-NEXT: s_endpgm
+ %p1 = getelementptr i8, ptr addrspace(3) @bars, i32 1
+ call void @llvm.amdgcn.s.barrier.init(ptr addrspace(3) %p1, i32 16)
+ call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) %p1, i32 0)
+ call void @llvm.amdgcn.s.barrier.wait(i16 1)
+ ret void
+}
+
+; A runtime (non-constant) index into the array of named barriers cannot fold
+; into an immediate or relocation addend. The barrier address must be computed
+; at runtime and the m0 register form of s_barrier_signal must be selected.
+
+define amdgpu_kernel void @signal_var_dynamic(i32 %idx) {
+; SDAG-LABEL: signal_var_dynamic:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-NEXT: s_load_b32 s0, s[4:5], 0x0 nv
+; SDAG-NEXT: s_wait_kmcnt 0x0
+; SDAG-NEXT: s_lshl4_add_u32 s0, s0, 0x802010
+; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; SDAG-NEXT: s_lshr_b32 s0, s0, 4
+; SDAG-NEXT: s_and_b32 s0, s0, 63
+; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-NEXT: s_or_b32 m0, 0x100000, s0
+; SDAG-NEXT: s_barrier_init m0
+; SDAG-NEXT: s_mov_b32 m0, s0
+; SDAG-NEXT: s_barrier_signal m0
+; SDAG-NEXT: s_barrier_wait 1
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: signal_var_dynamic:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: s_load_b32 s0, s[4:5], 0x0 nv
+; GISEL-NEXT: s_wait_kmcnt 0x0
+; GISEL-NEXT: s_lshl_b32 s0, s0, 4
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GISEL-NEXT: s_add_co_u32 s0, 0x802010, s0
+; GISEL-NEXT: s_lshr_b32 s0, s0, 4
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GISEL-NEXT: s_and_b32 s0, s0, 63
+; GISEL-NEXT: s_or_b32 m0, s0, 0x100000
+; GISEL-NEXT: s_barrier_init m0
+; GISEL-NEXT: s_mov_b32 m0, s0
+; GISEL-NEXT: s_barrier_signal m0
+; GISEL-NEXT: s_barrier_wait 1
+; GISEL-NEXT: s_endpgm
+;
+; OBJ-SDAG-LABEL: signal_var_dynamic:
+; OBJ-SDAG: ; %bb.0:
+; OBJ-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x0 nv
+; OBJ-SDAG-NEXT: s_wait_kmcnt 0x0
+; OBJ-SDAG-NEXT: s_lshl4_add_u32 s0, s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo
+; OBJ-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-SDAG-NEXT: s_lshr_b32 s0, s0, 4
+; OBJ-SDAG-NEXT: s_and_b32 s0, s0, 63
+; OBJ-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; OBJ-SDAG-NEXT: s_or_b32 m0, 0x100000, s0
+; OBJ-SDAG-NEXT: s_barrier_init m0
+; OBJ-SDAG-NEXT: s_mov_b32 m0, s0
+; OBJ-SDAG-NEXT: s_barrier_signal m0
+; OBJ-SDAG-NEXT: s_barrier_wait 1
+; OBJ-SDAG-NEXT: s_endpgm
+;
+; OBJ-GISEL-LABEL: signal_var_dynamic:
+; OBJ-GISEL: ; %bb.0:
+; OBJ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x0 nv
+; OBJ-GISEL-NEXT: s_wait_kmcnt 0x0
+; OBJ-GISEL-NEXT: s_lshl_b32 s0, s0, 4
+; OBJ-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-GISEL-NEXT: s_add_co_u32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, s0
+; OBJ-GISEL-NEXT: s_lshr_b32 s0, s0, 4
+; OBJ-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-GISEL-NEXT: s_and_b32 s0, s0, 63
+; OBJ-GISEL-NEXT: s_or_b32 m0, s0, 0x100000
+; OBJ-GISEL-NEXT: s_barrier_init m0
+; OBJ-GISEL-NEXT: s_mov_b32 m0, s0
+; OBJ-GISEL-NEXT: s_barrier_signal m0
+; OBJ-GISEL-NEXT: s_barrier_wait 1
+; OBJ-GISEL-NEXT: s_endpgm
+ %p1 = getelementptr [2 x target("amdgcn.named.barrier", 0)], ptr addrspace(3) @bars, i32 0, i32 %idx
+ call void @llvm.amdgcn.s.barrier.init(ptr addrspace(3) %p1, i32 16)
+ call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) %p1, i32 0)
+ call void @llvm.amdgcn.s.barrier.wait(i16 1)
+ ret void
+}
More information about the llvm-commits
mailing list