[llvm] [MC][TableGen] Make MCRegisterClasses relocation-free (PR #206753)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 30 08:51:59 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-hexagon
Author: Alexis Engelke (aengelke)
<details>
<summary>Changes</summary>
MCRegisterClasses currently store pointers to the register list and the
bit set. Store these three types together in one data structure and use
relative offsets to avoid these relocations and move the large
MCRegisterClasses array from .data.rel.ro into .data. This reduces the
amount of data that needs to be relocated by 86 KB.
This has two side effects: first, MCRegisterClass is not copyable and
the few uses that did copy were changed. Second, the MCRegisterClasses
array is no longer easily accessible as a global (well, it *technically*
is, but that requires the type of the entire storage struct, which I
don't want to expose). Therefore, these accesses need to go through a
function; which shouldn't be too costly and be inlined in an LTO build.
---
Patch is 130.20 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206753.diff
31 Files Affected:
- (modified) bolt/lib/Core/MCPlusBuilder.cpp (+1-1)
- (modified) llvm/include/llvm/MC/MCRegisterInfo.h (+16-5)
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+52-49)
- (modified) llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (+13-13)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp (+8-8)
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (+3-3)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+2-1)
- (modified) llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (+98-97)
- (modified) llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (+2-2)
- (modified) llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (+4-4)
- (modified) llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp (+1-1)
- (modified) llvm/lib/Target/BPF/BPFMIChecking.cpp (+1-1)
- (modified) llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (+1-1)
- (modified) llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (+2-1)
- (modified) llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp (+5-5)
- (modified) llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+30-30)
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+3-3)
- (modified) llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp (+51-50)
- (modified) llvm/lib/Target/X86/AsmParser/X86Operand.h (+24-22)
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (+2-2)
- (modified) llvm/lib/Target/X86/X86ExpandPseudo.cpp (+2-2)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+1-1)
- (modified) llvm/test/TableGen/AsmPredicateCombiningRISCV.td (+10-10)
- (modified) llvm/test/TableGen/CompressInstEmitter/suboperands.td (+18-18)
- (modified) llvm/test/TableGen/RegClassByHwModeCompressPat.td (+26-26)
- (modified) llvm/test/TableGen/RegisterClassCopyCost.td (+5-4)
- (modified) llvm/utils/TableGen/CompressInstEmitter.cpp (+3-2)
- (modified) llvm/utils/TableGen/RegisterInfoEmitter.cpp (+95-58)
``````````diff
diff --git a/bolt/lib/Core/MCPlusBuilder.cpp b/bolt/lib/Core/MCPlusBuilder.cpp
index 0cb4ba1ebfbd7..1bcae94214909 100644
--- a/bolt/lib/Core/MCPlusBuilder.cpp
+++ b/bolt/lib/Core/MCPlusBuilder.cpp
@@ -603,7 +603,7 @@ void MCPlusBuilder::initAliases() {
void MCPlusBuilder::initSizeMap() {
SizeMap.resize(RegInfo->getNumRegs());
// Build size map
- for (auto RC : RegInfo->regclasses())
+ for (const auto &RC : RegInfo->regclasses())
for (MCPhysReg Reg : RC)
SizeMap[Reg] = RC.getSizeInBits() / 8;
}
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 6e879ae108f0f..499dd6d6afda9 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -39,8 +39,8 @@ class MCRegisterClass {
using iterator = const MCPhysReg*;
using const_iterator = const MCPhysReg*;
- const iterator RegsBegin;
- const uint8_t *const RegSet;
+ const uint32_t RegsOff; ///< Relative offset to MCPhysReg array.
+ const uint32_t RegSetOff; ///< Relative offset to uint8_t array.
const uint32_t NameIdx;
const uint32_t RegSizeInBits;
const uint16_t RegsSize;
@@ -56,8 +56,11 @@ class MCRegisterClass {
/// begin/end - Return all of the registers in this class.
///
- iterator begin() const { return RegsBegin; }
- iterator end() const { return RegsBegin + RegsSize; }
+ iterator begin() const {
+ return reinterpret_cast<iterator>(reinterpret_cast<const char *>(this) +
+ RegsOff);
+ }
+ iterator end() const { return begin() + RegsSize; }
/// getNumRegs - Return the number of registers in this class.
///
@@ -67,7 +70,7 @@ class MCRegisterClass {
///
MCRegister getRegister(unsigned i) const {
assert(i < getNumRegs() && "Register number out of range!");
- return RegsBegin[i];
+ return begin()[i];
}
/// contains - Return true if the specified register is included in this
@@ -78,6 +81,7 @@ class MCRegisterClass {
unsigned Byte = RegNo / 8;
if (Byte >= RegSetSize)
return false;
+ const uint8_t *RegSet = reinterpret_cast<const uint8_t *>(this) + RegSetOff;
return (RegSet[Byte] & (1 << InByte)) != 0;
}
@@ -105,6 +109,13 @@ class MCRegisterClass {
bool isBaseClass() const { return BaseClass; }
};
+template <unsigned RegClassCount, unsigned RegCount, unsigned BitSetSize>
+struct MCRegisterClassStorage {
+ MCRegisterClass Classes[RegClassCount];
+ MCPhysReg Regs[RegCount];
+ uint8_t BitSets[BitSetSize];
+};
+
/// MCRegisterDesc - This record contains information about a particular
/// register. The SubRegs field is a zero terminated array of registers that
/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index b3fda2fe849fa..bd1f9b08e97e8 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1286,16 +1286,16 @@ class AArch64Operand : public MCParsedAsmOperand {
bool isNeonVectorRegLo() const {
return Kind == k_Register && Reg.Kind == RegKind::NeonVector &&
- (AArch64MCRegisterClasses[AArch64::FPR128_loRegClassID].contains(
- Reg.Reg) ||
- AArch64MCRegisterClasses[AArch64::FPR64_loRegClassID].contains(
- Reg.Reg));
+ (getAArch64MCRegisterClass(AArch64::FPR128_loRegClassID)
+ .contains(Reg.Reg) ||
+ getAArch64MCRegisterClass(AArch64::FPR64_loRegClassID)
+ .contains(Reg.Reg));
}
bool isNeonVectorReg0to7() const {
return Kind == k_Register && Reg.Kind == RegKind::NeonVector &&
- (AArch64MCRegisterClasses[AArch64::FPR128_0to7RegClassID].contains(
- Reg.Reg));
+ (getAArch64MCRegisterClass(AArch64::FPR128_0to7RegClassID)
+ .contains(Reg.Reg));
}
bool isMatrix() const { return Kind == k_MatrixRegister; }
@@ -1317,7 +1317,7 @@ class AArch64Operand : public MCParsedAsmOperand {
}
return (Kind == k_Register && Reg.Kind == RK) &&
- AArch64MCRegisterClasses[Class].contains(getReg());
+ getAArch64MCRegisterClass(Class).contains(getReg());
}
template <unsigned Class> bool isSVEVectorReg() const {
@@ -1344,12 +1344,12 @@ class AArch64Operand : public MCParsedAsmOperand {
}
return (Kind == k_Register && Reg.Kind == RK) &&
- AArch64MCRegisterClasses[Class].contains(getReg());
+ getAArch64MCRegisterClass(Class).contains(getReg());
}
template <unsigned Class> bool isFPRasZPR() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[Class].contains(getReg());
+ getAArch64MCRegisterClass(Class).contains(getReg());
}
template <int ElementWidth, unsigned Class>
@@ -1424,30 +1424,32 @@ class AArch64Operand : public MCParsedAsmOperand {
bool isGPR32as64() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.Reg);
+ getAArch64MCRegisterClass(AArch64::GPR64RegClassID)
+ .contains(Reg.Reg);
}
bool isGPR64as32() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.Reg);
+ getAArch64MCRegisterClass(AArch64::GPR32RegClassID)
+ .contains(Reg.Reg);
}
bool isGPR64x8() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].contains(
- Reg.Reg);
+ getAArch64MCRegisterClass(AArch64::GPR64x8ClassRegClassID)
+ .contains(Reg.Reg);
}
bool isWSeqPair() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
- Reg.Reg);
+ getAArch64MCRegisterClass(AArch64::WSeqPairsClassRegClassID)
+ .contains(Reg.Reg);
}
bool isXSeqPair() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains(
- Reg.Reg);
+ getAArch64MCRegisterClass(AArch64::XSeqPairsClassRegClassID)
+ .contains(Reg.Reg);
}
bool isSyspXzrPair() const {
@@ -1471,7 +1473,7 @@ class AArch64Operand : public MCParsedAsmOperand {
template <unsigned RegClassID> bool isGPR64() const {
return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
- AArch64MCRegisterClasses[RegClassID].contains(getReg());
+ getAArch64MCRegisterClass(RegClassID).contains(getReg());
}
template <unsigned RegClassID, int ExtWidth>
@@ -1518,7 +1520,7 @@ class AArch64Operand : public MCParsedAsmOperand {
isTypedVectorList<VectorKind, NumRegs, NumElements, ElementWidth>();
if (!Res)
return DiagnosticPredicate::NoMatch;
- if (!AArch64MCRegisterClasses[RegClass].contains(VectorList.Reg))
+ if (!getAArch64MCRegisterClass(RegClass).contains(VectorList.Reg))
return DiagnosticPredicate::NearMatch;
return DiagnosticPredicate::Match;
}
@@ -1784,7 +1786,7 @@ class AArch64Operand : public MCParsedAsmOperand {
if (!isMatrix())
return DiagnosticPredicate::NoMatch;
if (getMatrixKind() != Kind ||
- !AArch64MCRegisterClasses[RegClass].contains(getMatrixReg()) ||
+ !getAArch64MCRegisterClass(RegClass).contains(getMatrixReg()) ||
EltSize != getMatrixElementWidth())
return DiagnosticPredicate::NearMatch;
return DiagnosticPredicate::Match;
@@ -1828,7 +1830,7 @@ class AArch64Operand : public MCParsedAsmOperand {
void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
assert(
- AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(getReg()));
+ getAArch64MCRegisterClass(AArch64::GPR64RegClassID).contains(getReg()));
const MCRegisterInfo *RI = Ctx.getRegisterInfo();
MCRegister Reg = RI->getRegClass(AArch64::GPR32RegClassID)
@@ -1840,7 +1842,7 @@ class AArch64Operand : public MCParsedAsmOperand {
void addGPR64as32Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
assert(
- AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg()));
+ getAArch64MCRegisterClass(AArch64::GPR32RegClassID).contains(getReg()));
const MCRegisterInfo *RI = Ctx.getRegisterInfo();
MCRegister Reg = RI->getRegClass(AArch64::GPR64RegClassID)
@@ -1881,15 +1883,15 @@ class AArch64Operand : public MCParsedAsmOperand {
void addVectorReg64Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- assert(
- AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
+ assert(getAArch64MCRegisterClass(AArch64::FPR128RegClassID)
+ .contains(getReg()));
Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0));
}
void addVectorReg128Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- assert(
- AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
+ assert(getAArch64MCRegisterClass(AArch64::FPR128RegClassID)
+ .contains(getReg()));
Inst.addOperand(MCOperand::createReg(getReg()));
}
@@ -5340,9 +5342,8 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
!static_cast<AArch64Operand &>(*Operands[1]).isScalarReg())
return Error(Loc, "Only valid when first operand is register");
- bool IsXReg =
- AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
- Operands[1]->getReg());
+ bool IsXReg = getAArch64MCRegisterClass(AArch64::GPR64allRegClassID)
+ .contains(Operands[1]->getReg());
MCContext& Ctx = getContext();
E = SMLoc::getFromPointer(Loc.getPointer() - 1);
@@ -5680,7 +5681,7 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
" source");
}
- auto PPRRegClass = AArch64MCRegisterClasses[AArch64::PPRRegClassID];
+ const auto &PPRRegClass = getAArch64MCRegisterClass(AArch64::PPRRegClassID);
if (Prefix.isPredicated()) {
int PgIdx = -1;
@@ -6679,8 +6680,8 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
uint64_t Op3Val = Op3CE->getValue();
uint64_t NewOp3Val = 0;
uint64_t NewOp4Val = 0;
- if (AArch64MCRegisterClasses[AArch64::GPR32allRegClassID].contains(
- Op2.getReg())) {
+ if (getAArch64MCRegisterClass(AArch64::GPR32allRegClassID)
+ .contains(Op2.getReg())) {
NewOp3Val = (32 - Op3Val) & 0x1f;
NewOp4Val = 31 - Op3Val;
} else {
@@ -6714,8 +6715,8 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
uint64_t Width = WidthCE->getValue();
uint64_t RegWidth = 0;
- if (AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
- Op1.getReg()))
+ if (getAArch64MCRegisterClass(AArch64::GPR64allRegClassID)
+ .contains(Op1.getReg()))
RegWidth = 64;
else
RegWidth = 32;
@@ -6770,8 +6771,8 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
uint64_t Op4Val = Op4CE->getValue();
uint64_t RegWidth = 0;
- if (AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
- Op1.getReg()))
+ if (getAArch64MCRegisterClass(AArch64::GPR64allRegClassID)
+ .contains(Op1.getReg()))
RegWidth = 64;
else
RegWidth = 32;
@@ -6834,8 +6835,8 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
uint64_t Op4Val = Op4CE->getValue();
uint64_t RegWidth = 0;
- if (AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
- Op1.getReg()))
+ if (getAArch64MCRegisterClass(AArch64::GPR64allRegClassID)
+ .contains(Op1.getReg()))
RegWidth = 64;
else
RegWidth = 32;
@@ -6915,8 +6916,8 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "sxth")) {
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
if (Op.isScalarReg() &&
- AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
- Op.getReg())) {
+ getAArch64MCRegisterClass(AArch64::GPR64allRegClassID)
+ .contains(Op.getReg())) {
// The source register can be Wn here, but the matcher expects a
// GPR64. Twiddle it here if necessary.
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
@@ -6932,8 +6933,8 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
else if (NumOperands == 3 && (Tok == "uxtb" || Tok == "uxth")) {
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
if (Op.isScalarReg() &&
- AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
- Op.getReg())) {
+ getAArch64MCRegisterClass(AArch64::GPR64allRegClassID)
+ .contains(Op.getReg())) {
// The source register can be Wn here, but the matcher expects a
// GPR32. Twiddle it here if necessary.
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
@@ -8718,9 +8719,9 @@ ParseStatus AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
"even/odd register pair");
const MCRegisterClass &WRegClass =
- AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
+ getAArch64MCRegisterClass(AArch64::GPR32RegClassID);
const MCRegisterClass &XRegClass =
- AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
+ getAArch64MCRegisterClass(AArch64::GPR64RegClassID);
bool isXReg = XRegClass.contains(FirstReg),
isWReg = WRegClass.contains(FirstReg);
@@ -8755,11 +8756,13 @@ ParseStatus AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
MCRegister Pair;
if (isXReg) {
- Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64,
- &AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID]);
+ Pair = RI->getMatchingSuperReg(
+ FirstReg, AArch64::sube64,
+ &getAArch64MCRegisterClass(AArch64::XSeqPairsClassRegClassID));
} else {
- Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube32,
- &AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID]);
+ Pair = RI->getMatchingSuperReg(
+ FirstReg, AArch64::sube32,
+ &getAArch64MCRegisterClass(AArch64::WSeqPairsClassRegClassID));
}
Operands.push_back(AArch64Operand::CreateReg(Pair, RegKind::Scalar, S,
@@ -8895,7 +8898,7 @@ ParseStatus AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) {
const MCRegisterInfo *RI = ctx.getRegisterInfo();
MCRegister X8Reg = RI->getMatchingSuperReg(
XReg, AArch64::x8sub_0,
- &AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID]);
+ &getAArch64MCRegisterClass(AArch64::GPR64x8ClassRegClassID));
if (!X8Reg)
return Error(SS,
"expected an even-numbered x-register in the range [x0,x22]");
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 8fa1913ce24e5..15f40e2fa9f1b 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -54,7 +54,7 @@ static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
MCRegister Register =
- AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);
+ getAArch64MCRegisterClass(RegClassID).getRegister(RegNo + FirstReg);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -68,8 +68,8 @@ DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
return Fail;
MCRegister Register =
- AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
- RegNo >> 1);
+ getAArch64MCRegisterClass(AArch64::GPR64x8ClassRegClassID)
+ .getRegister(RegNo >> 1);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -82,7 +82,7 @@ static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
if (Reg < Min || Reg > Max || (Reg & 1))
return Fail;
MCRegister Register =
- AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
+ getAArch64MCRegisterClass(AArch64::ZPRRegClassID).getRegister(Reg);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -96,7 +96,7 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
MCRegister Register =
- AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(Reg);
+ getAArch64MCRegisterClass(AArch64::ZPR2RegClassID).getRegister(Reg);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -107,7 +107,7 @@ static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
return Fail;
MCRegister Register =
- AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
+ getAArch64MCRegisterClass(AArch64::ZPR_KRegClassID).getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -118,7 +118,7 @@ static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo * 4 > 28)
return Fail;
MCRegister Register =
- AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
+ getAArch64MCRegisterClass(AArch64::ZPR4RegClassID).getRegister(RegNo * 4);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -155,7 +155,7 @@ static DecodeStatus DecodeMPR16RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
MCRegister Reg =
- AArch64MCRegisterClasses[AArch64::MPR16RegClassID].getRegister(RegNo);
+ getAArch64MCRegisterClass(AArch64::MPR16RegClassID).getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return Success;
}
@@ -164,7 +164,7 @@ static DecodeStatus DecodeMPR32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
MCRegister Reg =
- AArch64MCRegisterClasses[AArch64::MPR32RegClassID].getRegister(RegNo);
+ getAArch64MCRegisterClass(AArch64::MPR32RegClassID).getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return Success;
}
@@ -173,7 +173,7 @@ static DecodeStatus DecodeMPR64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
MCRegister Reg =
- AArch64MCRegisterClasses[AArch64::MPR64RegClassID].getRegister(RegNo);
+ getAArch64MCRegisterClass(AArch64::MPR64RegClassID).getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return Success;
}
@@ -182,7 +182,7 @@ static DecodeStatus DecodeMPR128RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
MCRegister Reg =
- AArch64MCRegisterClasses[AArch64::MPR128RegClassID].getRegister(RegNo);
+ getAArch64MCRegisterClass(AArch64::MPR128RegClassID).getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Reg));
return Success;
}
@@ -193,7 +193,7 @@ static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206753
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