[llvm] [AMDGPU][NFC] Pre-commit test for constant-offset named barrier signal_var (PR #205217)

[Krzysztof Drewniak via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=GISEL %s
+; RUN: llc -global-isel=0 -amdgpu-enable-object-linking -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=OBJ-SDAG %s
+; RUN: llc -global-isel=1 -amdgpu-enable-object-linking -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefix=OBJ-GISEL %s
+
+ at bars = internal addrspace(3) global [2 x target("amdgcn.named.barrier", 0)] poison
+
+; A constant-offset GEP into an array of named barriers (&bars[1]) is a
+; compile-time-constant barrier address and should select the immediate
+; s_barrier_signal form, like the bare &bars[0]. With object linking the
+; barrier is externalized and the offset folds into the relocation addend
+; (... at abs32@lo+16) instead of a runtime add.
+
+define amdgpu_kernel void @signal_var_bar0() {
+; SDAG-LABEL: signal_var_bar0:
+; SDAG:       ; %bb.0:
+; SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-NEXT:    s_mov_b32 m0, 0x400001
+; SDAG-NEXT:    s_barrier_init m0
+; SDAG-NEXT:    s_barrier_signal 1
+; SDAG-NEXT:    s_barrier_wait 0
+; SDAG-NEXT:    s_endpgm
+;
+; GISEL-LABEL: signal_var_bar0:
+; GISEL:       ; %bb.0:
+; GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT:    s_mov_b32 m0, 1
+; GISEL-NEXT:    s_barrier_init m0
+; GISEL-NEXT:    s_barrier_signal 1
+; GISEL-NEXT:    s_barrier_wait 0
+; GISEL-NEXT:    s_endpgm
+;
+; OBJ-SDAG-LABEL: signal_var_bar0:
+; OBJ-SDAG:       ; %bb.0:
+; OBJ-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-SDAG-NEXT:    s_lshr_b32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, 4
+; OBJ-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-SDAG-NEXT:    s_and_b32 s0, s0, 63
+; OBJ-SDAG-NEXT:    s_or_b32 m0, 0x400000, s0
+; OBJ-SDAG-NEXT:    s_barrier_init m0
+; OBJ-SDAG-NEXT:    s_mov_b32 m0, s0
+; OBJ-SDAG-NEXT:    s_barrier_signal m0
+; OBJ-SDAG-NEXT:    s_barrier_wait 0
+; OBJ-SDAG-NEXT:    s_endpgm
+;
+; OBJ-GISEL-LABEL: signal_var_bar0:
+; OBJ-GISEL:       ; %bb.0:
+; OBJ-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; OBJ-GISEL-NEXT:    s_lshr_b32 s0, __amdgpu_named_barrier.bars.5a19a560517f8a3a4347b4502da34a70 at abs32@lo, 4
+; OBJ-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; OBJ-GISEL-NEXT:    s_and_b32 s0, s0, 63
+; OBJ-GISEL-NEXT:    s_mov_b32 m0, s0
+; OBJ-GISEL-NEXT:    s_barrier_init m0
+; OBJ-GISEL-NEXT:    s_mov_b32 m0, s0
+; OBJ-GISEL-NEXT:    s_barrier_signal m0
+; OBJ-GISEL-NEXT:    s_barrier_wait 0
+; OBJ-GISEL-NEXT:    s_endpgm
+  call void @llvm.amdgcn.s.barrier.init(ptr addrspace(3) @bars, i32 64)
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krzysz00 wrote:

Hyper-nit: we might want to use realistic values here - I don't think you can have 64 subgroups participating in a barrier these days.

https://github.com/llvm/llvm-project/pull/205217