[lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[via llvm-commits]

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@@ -8731,22 +8698,33 @@ ParseStatus AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
   MCRegister SecondReg;
   Res = tryParseScalarRegister(SecondReg);
   if (!Res.isSuccess())
-    return Error(E, "expected second odd register of a consecutive same-size "
-                    "even/odd register pair");
+    return Error(E, IsXZRPair ? "expected second xzr in xzr/xzr register pair"
+                              : SecondRegExpected);
+
+  // For SYSP, Rt == 31 denotes the optional-pair default. If the explicit
+  // pair starts with xzr, the derived second register must be xzr too.
+  if (IsXZRPair) {
+    if (!XRegClass.contains(SecondReg) || SecondReg != AArch64::XZR)
+      return Error(E, "expected second xzr in xzr/xzr register pair");
+    Operands.push_back(AArch64Operand::CreateReg(AArch64::XZR, RegKind::Scalar,
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Lukacma wrote:

Why did you need to create an artificial one ? Couldn't you have just added (xzr, xzr) to XSeqPairs ?

https://github.com/llvm/llvm-project/pull/182410