[llvm] [AMDGPU] Select the high-half 16-bit packing idiom to v_lshl_or_b32 (PR #206058)

[Joe Nash via llvm-commits]

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@@ -4024,6 +4024,28 @@ def : GCNPat <
   (v2i16 (V_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
 >;
 
+// Fold the (hi << 16) | z high-half packing idiom into v_lshl_or_b32.
+// DAGCombine canonicalizes a 16-bit value shifted into the high half to
+// bitcast(build_vector (i16 0), hi), leaving no shl for the
+// (or (shl x, y), z) selection to match, so match the build_vector directly.
+let True16Predicate = NotUseRealTrue16Insts in
+def : GCNPat <
+  (i32 (DivergentBinFrag<or>
+    (i32 (bitconvert (v2i16 (build_vector (i16 0), (i16 VGPR_32:$src_hi))))),
+    i32:$src2)),
+  (V_LSHL_OR_B32_e64 VGPR_32:$src_hi, (i32 16), VSrc_b32:$src2)
+>;
+
+let True16Predicate = UseRealTrue16Insts in
+def : GCNPat <
+  (i32 (DivergentBinFrag<or>
+    (i32 (bitconvert (v2i16 (build_vector (i16 0), (i16 VGPR_16:$src_hi))))),
+    i32:$src2)),
+  (V_LSHL_OR_B32_e64
+    (i32 (REG_SEQUENCE VGPR_32, VGPR_16:$src_hi, lo16, (i16 (IMPLICIT_DEF)), hi16)),
+    (i32 16), VSrc_b32:$src2)
----------------
Sisyph wrote:

I like @jayfoad 's suggested pattern better. The two instruction sequence with v_or_b16 is the best one that doesn't restrict RA freedom. I don't know from a perf perspective whether it is better to restrict RA freedom, or use the two instruction sequence instead of one instruction sequence. But the two instruction sequence can be combined into an lshl_or in a postRA peephole, whereas if we had the peephole in place we would want to remove these lshl_or isel patterns. 

https://github.com/llvm/llvm-project/pull/206058