[llvm] [X86] Lower vector 8-bit `rotl(x, 1)` to `(x + x) - (x < 0)` pattern (PR #206221)

[Simon Pilgrim via llvm-commits]

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@@ -32405,6 +32405,16 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
     return DAG.getNode(ISD::AVGCEILU, DL, VT, R, Neg);
   }
 
+  // rotl(x,1) -> psubb(x+x, x<0)
+  if (EltSizeInBits == 8 && IsCstSplat &&
----------------
RKSimon wrote:

Move the cheap tests first:
```suggestion
  if (IsROTL && EltSizeInBits == 8 && IsCstSplat &&
```

https://github.com/llvm/llvm-project/pull/206221