[llvm] [X86][SSE] Improve ISD::FP_TO_*INT_SAT vector lowering (PR #199416)

via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 30 01:30:30 PDT 2026


================
@@ -22899,7 +22909,122 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
                               dl, VecI16VT, Src);
     return DAG.getNode(ISD::TRUNCATE, dl, DstVT, Res);
   }
+  if ((DstVT == MVT::v4i32 && Subtarget.hasSSE2()) ||
+      (DstVT == MVT::v8i32 && Subtarget.hasAVX()) ||
+      (DstVT == MVT::v16i32 && Subtarget.hasAVX512())) {
+    unsigned SatWidth = SatVT.getScalarSizeInBits();
+    assert(SatWidth <= 32 &&
+           "Expected saturation width no wider than result element");
+
+    if (SatWidth == 32 && (SrcVT.getScalarType() == MVT::f32 ||
+                           SrcVT.getScalarType() == MVT::f64)) {
+      if (IsSigned) {
+        // Use X86ISD::CVTTP2SI (CVTTPS2DQ/CVTTPD2DQ) which has defined
+        // out-of-range behavior: maps overflow and NaN to 0x80000000 (INT_MIN).
+        SDValue Cvt = DAG.getNode(X86ISD::CVTTP2SI, dl, DstVT, Src);
+        APFloat PosOvfBoundFlt(SrcVT.getScalarType().getFltSemantics());
+        PosOvfBoundFlt.convertFromAPInt(APInt::getSignedMinValue(32),
+                                        /*IsSigned=*/true,
+                                        APFloat::rmTowardZero);
+        PosOvfBoundFlt.changeSign();
+        SDValue PosOvfBound = DAG.getConstantFP(PosOvfBoundFlt, dl, SrcVT);
----------------
Panadulek wrote:

@RKSimon Friendly reminder 

https://github.com/llvm/llvm-project/pull/199416


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