[llvm] [Mips][GISel][NFC] Regenerate CHECK lines in zextLoad_and_sextLoad.mir (PR #206631)
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Mon Jun 29 19:08:35 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-mips
Author: Ilpo Ruotsalainen (lonemeow)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/206631.diff
1 Files Affected:
- (modified) llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir (+55-45)
``````````diff
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
index 2e1c82c879f51..b2d6acbc7267f 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
@@ -24,10 +24,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$v0 = COPY %2(s32)
@@ -44,10 +45,11 @@ body: |
; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$v0 = COPY %2(s32)
@@ -64,10 +66,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
%3:_(s32) = G_ANYEXT %2(s16)
@@ -85,10 +88,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$v0 = COPY %3(s32)
@@ -105,12 +109,13 @@ body: |
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
- ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: $v1 = COPY [[C]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
+ ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
@@ -129,10 +134,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$v0 = COPY %2(s32)
@@ -149,10 +155,11 @@ body: |
; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$v0 = COPY %2(s32)
@@ -169,10 +176,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
%3:_(s32) = G_ANYEXT %2(s16)
@@ -190,10 +198,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$v0 = COPY %3(s32)
@@ -210,13 +219,14 @@ body: |
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
- ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: $v1 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
+ ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
+ ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: $v1 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32) from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
``````````
</details>
https://github.com/llvm/llvm-project/pull/206631
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