[llvm] [X86] Narrow vXi32/vXi64 usubsat to vpsubusb/vpsubusw when LHS is known to fit in fewer bits (PR #206592)

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Mon Jun 29 14:50:09 PDT 2026


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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/X86/X86ISelLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0eddc7254..6c342c066 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2074,7 +2074,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
       setOperationAction(ISD::ROTR,             VT, Legal);
       setOperationAction(ISD::ABS,              VT, Legal);
       setOperationAction(ISD::CTPOP,            VT, Custom);
-      setOperationAction(ISD::USUBSAT,          VT, Custom);
+      setOperationAction(ISD::USUBSAT, VT, Custom);
     }
 
     for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
@@ -29923,12 +29923,14 @@ static SDValue LowerADDSAT_SUBSAT(SDValue Op, SelectionDAG &DAG,
 
   unsigned BitWidth = VT.getScalarSizeInBits();
   if (Opcode == ISD::USUBSAT) {
-    // Narrow a vXiN USUBSAT to vXi8 or vXi16 when LHS is known to fit in fewer bits (higher bits are zero)
-    // x86 has native vpsubusb/vpsubusw but no vpsubusd/vpsubusq.
-    // If CountMaxActiveBits(N0) <= NarrowBits we know every element of N0 fits in NarrowBits.
-    // The upper bits (ScalarBits - NarrowBits) bits of N0 are zero.
-    // We fill the same upper bits of N1 with 0xFF...F so that the byte/word saturating subtract on those positions
-    // always saturates to zero, leaving only narrow low bits doing the real work.
+    // Narrow a vXiN USUBSAT to vXi8 or vXi16 when LHS is known to fit in fewer
+    // bits (higher bits are zero) x86 has native vpsubusb/vpsubusw but no
+    // vpsubusd/vpsubusq. If CountMaxActiveBits(N0) <= NarrowBits we know every
+    // element of N0 fits in NarrowBits. The upper bits (ScalarBits -
+    // NarrowBits) bits of N0 are zero. We fill the same upper bits of N1 with
+    // 0xFF...F so that the byte/word saturating subtract on those positions
+    // always saturates to zero, leaving only narrow low bits doing the real
+    // work.
     unsigned ScalarBits = VT.getScalarSizeInBits();
     if (ScalarBits == 32 || ScalarBits == 64) {
       KnownBits Known = DAG.computeKnownBits(X);
@@ -29949,7 +29951,8 @@ static SDValue LowerADDSAT_SUBSAT(SDValue Op, SelectionDAG &DAG,
           SDValue YWithUpperOnes = DAG.getNode(ISD::OR, DL, VT, Y, Mask);
           SDValue NarrowX = DAG.getBitcast(NarrowVT, X);
           SDValue NarrowY = DAG.getBitcast(NarrowVT, YWithUpperOnes);
-          SDValue NarrowSub = DAG.getNode(ISD::USUBSAT, DL, NarrowVT, NarrowX, NarrowY);
+          SDValue NarrowSub =
+              DAG.getNode(ISD::USUBSAT, DL, NarrowVT, NarrowX, NarrowY);
           return DAG.getBitcast(VT, NarrowSub);
         }
       }

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https://github.com/llvm/llvm-project/pull/206592


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