[llvm] 1e1d455 - [LV] Add test with missing fold of buildvector (NFC). (#206540)

[via llvm-commits]

Author: Florian Hahn
Date: 2026-06-29T17:56:39Z
New Revision: 1e1d455e977d8028decd3af5e5af6f93cd64a7fc

URL: https://github.com/llvm/llvm-project/commit/1e1d455e977d8028decd3af5e5af6f93cd64a7fc
DIFF: https://github.com/llvm/llvm-project/commit/1e1d455e977d8028decd3af5e5af6f93cd64a7fc.diff

LOG: [LV] Add test with missing fold of buildvector (NFC). (#206540)

Add test where we create a build vector with only the first lane used.

Added: 
    llvm/test/Transforms/LoopVectorize/VPlan/buildvector-first-lane-only.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopVectorize/VPlan/buildvector-first-lane-only.ll b/llvm/test/Transforms/LoopVectorize/VPlan/buildvector-first-lane-only.ll
new file mode 100644
index 0000000000000..54614ad7c2035
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/buildvector-first-lane-only.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -p loop-vectorize -force-vector-width=4 -tail-folding-policy=must-fold-tail -force-tail-folding-style=data -vplan-print-after=printFinalVPlan -disable-output 2>&1 | FileCheck %s
+
+define i32 @last_active_lane_live_out(i32 %x) {
+; CHECK-LABEL: VPlan for loop in 'last_active_lane_live_out'
+; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK-NEXT:  Live-in ir<2> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<entry>:
+; CHECK-NEXT:  Successor(s): vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT:  vector.ph:
+; CHECK-NEXT:    EMIT vp<[[VP2:%[0-9]+]]> = step-vector i32
+; CHECK-NEXT:    EMIT vp<[[VP3:%[0-9]+]]> = broadcast ir<%x>
+; CHECK-NEXT:    EMIT vp<[[VP4:%[0-9]+]]> = mul vp<[[VP2]]>, vp<[[VP3]]>
+; CHECK-NEXT:  Successor(s): vector.body
+; CHECK-EMPTY:
+; CHECK-NEXT:  vector.body:
+; CHECK-NEXT:  Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT:  middle.block:
+; CHECK-NEXT:    vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS ir<0>, ir<1>, ir<4>, ir<1>
+; CHECK-NEXT:    vp<[[VP6:%[0-9]+]]> = SCALAR-STEPS ir<0>, ir<1>, ir<4>, ir<2>
+; CHECK-NEXT:    vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS ir<0>, ir<1>, ir<4>, ir<3>
+; CHECK-NEXT:    EMIT vp<[[VP8:%[0-9]+]]> = buildvector ir<0>, vp<[[VP5]]>, vp<[[VP6]]>, vp<[[VP7]]>
+; CHECK-NEXT:    EMIT vp<%active.lane.mask> = active lane mask vp<[[VP8]]>, ir<2>, ir<1>
+; CHECK-NEXT:    EMIT vp<[[VP9:%[0-9]+]]> = not vp<%active.lane.mask>
+; CHECK-NEXT:    EMIT vp<%first.inactive.lane> = first-active-lane vp<[[VP9]]>
+; CHECK-NEXT:    EMIT vp<%last.active.lane> = sub vp<%first.inactive.lane>, ir<1>
+; CHECK-NEXT:    EMIT vp<[[VP10:%[0-9]+]]> = extractelement vp<[[VP4]]>, vp<%last.active.lane>
+; CHECK-NEXT:  Successor(s): ir-bb<exit>
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<exit>:
+; CHECK-NEXT:    IR   %red.lcssa = phi i32 [ %red, %loop ] (extra operand: vp<[[VP10]]> from middle.block)
+; CHECK-NEXT:  No successors
+; CHECK-NEXT:  }
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %red = phi i32 [ 0, %entry ], [ %add, %loop ]
+  %add = add i32 %red, %x
+  %iv.next = add i64 %iv, 1
+  %ec = icmp eq i64 %iv, 1
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret i32 %red
+}