[llvm] [AMDGPU] Remove explicit PartialThreshold setting in loop unrolling (PR #198901)

[Ravil Dorozhinskii via llvm-commits]

ravil-mobile wrote:

> > The change resulted in an aggressive transformation (i.e., loop unrolling in a software pipelined loop) that led to increased register pressure beyond the physical register file capacity.
> 
> That doesn't sound like an issue with this change. It seems more like a case of suboptimal instruction scheduling, or perhaps an interaction between instruction scheduling and register allocation. For example, the RA may not be able to stay within the budget assumed by the scheduler.

Agree. I guess this PR just unlocked a latent bug in the backend

https://github.com/llvm/llvm-project/pull/198901