[llvm] [AArch64] Fix correctness of FORM_TRANSPOSED_REG_TUPLE expansions (PR #205528)

[Benjamin Maxwell via llvm-commits]

================
@@ -1282,26 +1282,114 @@ bool AArch64ExpandPseudoImpl::expandMultiVecPseudo(
   return true;
 }
 
+struct Copy {
+  Register Dst;
+  Register Src;
+  int SrcTupleIdx = -1;
+};
+
 bool AArch64ExpandPseudoImpl::expandFormTuplePseudo(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI, unsigned Size) {
   assert((Size == 2 || Size == 4) && "Invalid Tuple Size");
-  MachineInstr &MI = *MBBI;
-  Register ReturnTuple = MI.getOperand(0).getReg();
 
   const TargetRegisterInfo *TRI =
       MBB.getParent()->getSubtarget().getRegisterInfo();
+
+  MachineInstr &MI = *MBBI;
+  DebugLoc DL = MI.getDebugLoc();
+  Register Tuple = MI.getOperand(0).getReg();
+
+  // Collect the copies required to form the tuple. Count if any tuple members
+  // appear as operands to the FORM_TRANSPOSED_REG_TUPLE. If a destination
+  // also appears as a source operand, we can't write to that register until
+  // we've handled the other copies that use it.
+
+  Copy Copies[4] = {};
+  unsigned Users[4] = {};
+
+  for (unsigned I = 0; I < Size; ++I) {
+    Register Dst = TRI->getSubReg(Tuple, AArch64::zsub0 + I);
+    Register Src = MI.getOperand(I + 1).getReg();
+
+    Copies[I] = {Dst, Src};
+
+    if (Dst != Src && TRI->isSubRegister(Tuple, Src)) {
+      int SrcTupleIdx = TRI->getSubRegIndex(Tuple, Src) - AArch64::zsub0;
+      Copies[I].SrcTupleIdx = SrcTupleIdx;
+      ++Users[SrcTupleIdx];
----------------
MacDue wrote:

Yes, `z19, z20, z21, z22 = pseudo z17, z19, z20, z21`.  

This can be scheduled as:
```
    z22 = copy z21
    z21 = copy z20
    z20 = copy z19
    z19 = copy z17
```

Any example, where _all_ source operands are within the tuple is going to be a permutation or identity. Any example with at least one free register may be possible to schedule (though not in all cases, it could still contain a permutation). 

https://github.com/llvm/llvm-project/pull/205528