[llvm] 195ca1f - [SystemZ] Limit latency scheduling to SUs with latency of at least 5. (#206459)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 29 05:52:33 PDT 2026
Author: Jonas Paulsson
Date: 2026-06-29T14:52:28+02:00
New Revision: 195ca1f266d88b5f49fbb5a4612214a20b48886b
URL: https://github.com/llvm/llvm-project/commit/195ca1f266d88b5f49fbb5a4612214a20b48886b
DIFF: https://github.com/llvm/llvm-project/commit/195ca1f266d88b5f49fbb5a4612214a20b48886b.diff
LOG: [SystemZ] Limit latency scheduling to SUs with latency of at least 5. (#206459)
The latency reduction heuristic is highly effective, but it seems preferred
to not "move everything around", but rather focus on instructions that have
somewhat longer latencies. The basic idea behind this is that the input
order is fairly good to begin with and not just "any random order", so it
should not be disturbed unnecessarily.
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
llvm/test/CodeGen/SystemZ/args-22.ll
llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
llvm/test/CodeGen/SystemZ/bswap-09.ll
llvm/test/CodeGen/SystemZ/bswap-10.ll
llvm/test/CodeGen/SystemZ/call-zos-vec.ll
llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll
llvm/test/CodeGen/SystemZ/dag-combine-05.ll
llvm/test/CodeGen/SystemZ/dag-combine-07.ll
llvm/test/CodeGen/SystemZ/fold-masked-merge.ll
llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll
llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll
llvm/test/CodeGen/SystemZ/fp-half.ll
llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-explicit-regs-zEC12.ll
llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-zEC12.ll
llvm/test/CodeGen/SystemZ/int-cmp-65.ll
llvm/test/CodeGen/SystemZ/int-conv-14.ll
llvm/test/CodeGen/SystemZ/int-conv-15.ll
llvm/test/CodeGen/SystemZ/int-mul-13.ll
llvm/test/CodeGen/SystemZ/int-uadd-14.ll
llvm/test/CodeGen/SystemZ/int-usub-13.ll
llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll
llvm/test/CodeGen/SystemZ/misched-prera-cmp-elim.mir
llvm/test/CodeGen/SystemZ/misched-prera-latencies.mir
llvm/test/CodeGen/SystemZ/misched-prera-loads.mir
llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
llvm/test/CodeGen/SystemZ/risbg-04.ll
llvm/test/CodeGen/SystemZ/rot-03.ll
llvm/test/CodeGen/SystemZ/shift-12.ll
llvm/test/CodeGen/SystemZ/shift-13.ll
llvm/test/CodeGen/SystemZ/shift-14.ll
llvm/test/CodeGen/SystemZ/shift-15.ll
llvm/test/CodeGen/SystemZ/shift-16.ll
llvm/test/CodeGen/SystemZ/shift-17.ll
llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll
llvm/test/CodeGen/SystemZ/soft-float-args.ll
llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
llvm/test/CodeGen/SystemZ/vec-args-04.ll
llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
llvm/test/CodeGen/SystemZ/vec-cmpsel-01.ll
llvm/test/CodeGen/SystemZ/vec-eval.ll
llvm/test/CodeGen/SystemZ/vec-perm-12.ll
llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll
llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
index fe22ceac5fce7..606273a5e0df8 100644
--- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
@@ -80,15 +80,21 @@ bool SystemZPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
return TryCand.Reason != NoCand;
}
- if (!RegionPolicy.DisableLatencyHeuristic)
+ // Do latency scheduling by trying to not increase the scheduled latency
+ // (going bottom-up). This is important for performance, but it is best to
+ // only do it when likely beneficial and not "move everything around": Only
+ // apply this to SUs that have somewhat longer latencies, and don't push an
+ // SU upwards if it's on the critical path.
+ if (!RegionPolicy.DisableLatencyHeuristic &&
+ std::max(TryCand.SU->Latency, Cand.SU->Latency) >= 5)
if (const SUnit *HigherSU =
TryCand.SU->getHeight() > Cand.SU->getHeight() ? TryCand.SU
: TryCand.SU->getHeight() < Cand.SU->getHeight() ? Cand.SU
: nullptr)
if (HigherSU->getHeight() > Zone->getScheduledLatency() &&
HigherSU->getDepth() < computeRemLatency(*Zone)) {
- // The higher SU increases the scheduled latency but is not on the
- // Critical Path by Depth, so put it above the other one.
+ // HigherSU would increase the scheduled latency and there is room
+ // above for it next to the critical path, so wait with it.
tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(), TryCand, Cand,
GenericSchedulerBase::BotHeightReduce);
return TryCand.Reason != NoCand;
diff --git a/llvm/test/CodeGen/SystemZ/args-22.ll b/llvm/test/CodeGen/SystemZ/args-22.ll
index 0d20cd1ebc7c1..388a0e3784c00 100644
--- a/llvm/test/CodeGen/SystemZ/args-22.ll
+++ b/llvm/test/CodeGen/SystemZ/args-22.ll
@@ -124,8 +124,8 @@ define void @arg1(%Ty1 %A) {
; VECTOR-NEXT: lgrl %r1, Dst at GOT
; VECTOR-NEXT: vrepib %v1, 8
; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
-; VECTOR-NEXT: vsrlb %v1, %v0, %v1
-; VECTOR-NEXT: vsteg %v1, 0(%r1), 1
+; VECTOR-NEXT: vsrlb %v0, %v0, %v1
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty1 %A, ptr @Dst
ret void
@@ -351,14 +351,14 @@ define void @arg3(%Ty3 %A) {
;
; VECTOR-LABEL: arg3:
; VECTOR: # %bb.0:
-; VECTOR-NEXT: vl %v0, 0(%r2), 3
-; VECTOR-NEXT: vl %v1, 0(%r3), 3
+; VECTOR-NEXT: vl %v0, 0(%r3), 3
; VECTOR-NEXT: lgrl %r1, Dst at GOT
-; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
-; VECTOR-NEXT: vrepib %v2, 8
-; VECTOR-NEXT: vsrlb %v2, %v0, %v2
-; VECTOR-NEXT: vst %v1, 16(%r1), 3
-; VECTOR-NEXT: vsteg %v2, 0(%r1), 1
+; VECTOR-NEXT: vl %v1, 0(%r2), 3
+; VECTOR-NEXT: vsteb %v1, 8(%r1), 15
+; VECTOR-NEXT: vst %v0, 16(%r1), 3
+; VECTOR-NEXT: vrepib %v0, 8
+; VECTOR-NEXT: vsrlb %v0, %v1, %v0
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty3 %A, ptr @Dst
ret void
@@ -402,11 +402,11 @@ define void @call3() {
; VECTOR-NEXT: vlrepg %v1, 0(%r1)
; VECTOR-NEXT: vrepib %v2, 8
; VECTOR-NEXT: vslb %v1, %v1, %v2
-; VECTOR-NEXT: vl %v2, 16(%r1), 3
; VECTOR-NEXT: vo %v0, %v0, %v1
+; VECTOR-NEXT: vl %v1, 16(%r1), 3
; VECTOR-NEXT: la %r2, 176(%r15)
; VECTOR-NEXT: la %r3, 160(%r15)
-; VECTOR-NEXT: vst %v2, 160(%r15), 3
+; VECTOR-NEXT: vst %v1, 160(%r15), 3
; VECTOR-NEXT: vst %v0, 176(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr at PLT
; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
@@ -810,10 +810,10 @@ define void @arg6(%Ty6 %A) {
; VECTOR-NEXT: vsteb %v1, 24(%r1), 15
; VECTOR-NEXT: vrepib %v2, 8
; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
-; VECTOR-NEXT: vsrlb %v3, %v1, %v2
-; VECTOR-NEXT: vsrlb %v2, %v0, %v2
-; VECTOR-NEXT: vsteg %v3, 16(%r1), 1
-; VECTOR-NEXT: vsteg %v2, 0(%r1), 1
+; VECTOR-NEXT: vsrlb %v1, %v1, %v2
+; VECTOR-NEXT: vsrlb %v0, %v0, %v2
+; VECTOR-NEXT: vsteg %v1, 16(%r1), 1
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty6 %A, ptr @Dst
ret void
@@ -854,17 +854,17 @@ define void @call6() {
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgrl %r1, Src at GOT
-; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vgbm %v1, 0
; VECTOR-NEXT: vleb %v1, 8(%r1), 15
; VECTOR-NEXT: vlrepg %v2, 0(%r1)
-; VECTOR-NEXT: vleb %v0, 24(%r1), 15
-; VECTOR-NEXT: vlrepg %v3, 16(%r1)
-; VECTOR-NEXT: vrepib %v4, 8
-; VECTOR-NEXT: vslb %v2, %v2, %v4
-; VECTOR-NEXT: vslb %v3, %v3, %v4
+; VECTOR-NEXT: vrepib %v3, 8
+; VECTOR-NEXT: vslb %v2, %v2, %v3
+; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vo %v1, %v1, %v2
-; VECTOR-NEXT: vo %v0, %v0, %v3
+; VECTOR-NEXT: vleb %v0, 24(%r1), 15
+; VECTOR-NEXT: vlrepg %v2, 16(%r1)
+; VECTOR-NEXT: vslb %v2, %v2, %v3
+; VECTOR-NEXT: vo %v0, %v0, %v2
; VECTOR-NEXT: la %r2, 176(%r15)
; VECTOR-NEXT: la %r3, 160(%r15)
; VECTOR-NEXT: vst %v0, 160(%r15), 3
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
index b7d76f4e12098..09edd6eb227af 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
@@ -111,11 +111,11 @@ define i128 @atomicrmw_nand(ptr %src, i128 %b) {
; CHECK-NEXT: vlvgp %v1, %r0, %r1
; CHECK-NEXT: .LBB4_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vnn %v2, %v1, %v0
; CHECK-NEXT: vlgvg %r1, %v1, 1
; CHECK-NEXT: vlgvg %r0, %v1, 0
-; CHECK-NEXT: vlgvg %r5, %v2, 1
-; CHECK-NEXT: vlgvg %r4, %v2, 0
+; CHECK-NEXT: vnn %v1, %v1, %v0
+; CHECK-NEXT: vlgvg %r5, %v1, 1
+; CHECK-NEXT: vlgvg %r4, %v1, 0
; CHECK-NEXT: cdsg %r0, %r4, 0(%r3)
; CHECK-NEXT: vlvgp %v1, %r0, %r1
; CHECK-NEXT: jl .LBB4_1
@@ -335,10 +335,10 @@ define i128 @atomicrmw_uinc_wrap(ptr %src, i128 %b) {
; CHECK-LABEL: atomicrmw_uinc_wrap:
; CHECK: # %bb.0:
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: larl %r4, .LCPI11_0
-; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: lpq %r0, 0(%r3)
; CHECK-NEXT: vlvgp %v2, %r0, %r1
+; CHECK-NEXT: larl %r1, .LCPI11_0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
; CHECK-NEXT: j .LBB11_2
; CHECK-NEXT: .LBB11_1: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB11_2 Depth=1
@@ -376,11 +376,11 @@ define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) {
; CHECK-LABEL: atomicrmw_udec_wrap:
; CHECK: # %bb.0:
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: larl %r4, .LCPI12_0
-; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vgbm %v2, 65535
; CHECK-NEXT: lpq %r0, 0(%r3)
; CHECK-NEXT: vlvgp %v3, %r0, %r1
-; CHECK-NEXT: vgbm %v2, 65535
+; CHECK-NEXT: larl %r1, .LCPI12_0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
; CHECK-NEXT: j .LBB12_2
; CHECK-NEXT: .LBB12_1: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
diff --git a/llvm/test/CodeGen/SystemZ/bswap-09.ll b/llvm/test/CodeGen/SystemZ/bswap-09.ll
index e8468acaee431..a2d8273c89695 100644
--- a/llvm/test/CodeGen/SystemZ/bswap-09.ll
+++ b/llvm/test/CodeGen/SystemZ/bswap-09.ll
@@ -9,14 +9,14 @@ declare i128 @llvm.bswap.i128(i128 %a)
define i128 @f1(i128 %a, i128 %b, i128 %c) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r3), 3
; CHECK-NEXT: larl %r1, .LCPI0_0
+; CHECK-NEXT: vaq %v1, %v2, %v1
; CHECK-NEXT: vl %v2, 0(%r1), 3
-; CHECK-NEXT: vl %v3, 0(%r5), 3
+; CHECK-NEXT: vl %v0, 0(%r5), 3
+; CHECK-NEXT: vperm %v1, %v1, %v1, %v2
; CHECK-NEXT: vaq %v0, %v1, %v0
-; CHECK-NEXT: vperm %v0, %v0, %v0, %v2
-; CHECK-NEXT: vaq %v0, %v0, %v3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%in = add i128 %a, %b
@@ -32,9 +32,9 @@ define i128 @f2(i128 %a, i128 %b) {
; CHECK-NEXT: vl %v0, 0(%r4), 3
; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: larl %r1, .LCPI1_0
-; CHECK-NEXT: vl %v2, 0(%r1), 3
; CHECK-NEXT: vaq %v0, %v1, %v0
-; CHECK-NEXT: vperm %v0, %v0, %v0, %v2
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vperm %v0, %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%in = add i128 %a, %b
@@ -47,11 +47,11 @@ define i128 @f3(i128 %a, i128 %b) {
; CHECK-LABEL: f3:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI2_0
-; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vl %v1, 0(%r1), 3
-; CHECK-NEXT: vl %v2, 0(%r4), 3
-; CHECK-NEXT: vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT: vaq %v0, %v0, %v2
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v2, 0(%r1), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vperm %v1, %v1, %v1, %v2
+; CHECK-NEXT: vaq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%swapped = call i128 @llvm.bswap.i128(i128 %a)
diff --git a/llvm/test/CodeGen/SystemZ/bswap-10.ll b/llvm/test/CodeGen/SystemZ/bswap-10.ll
index 465c666808958..6de2970b80e2e 100644
--- a/llvm/test/CodeGen/SystemZ/bswap-10.ll
+++ b/llvm/test/CodeGen/SystemZ/bswap-10.ll
@@ -9,14 +9,14 @@ declare i128 @llvm.bswap.i128(i128 %a)
define i128 @f1(i128 %a, i128 %b, i128 %c) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r3), 3
; CHECK-NEXT: larl %r1, .LCPI0_0
+; CHECK-NEXT: vaq %v1, %v2, %v1
; CHECK-NEXT: vl %v2, 0(%r1), 3
-; CHECK-NEXT: vl %v3, 0(%r5), 3
+; CHECK-NEXT: vl %v0, 0(%r5), 3
+; CHECK-NEXT: vperm %v1, %v1, %v1, %v2
; CHECK-NEXT: vaq %v0, %v1, %v0
-; CHECK-NEXT: vperm %v0, %v0, %v0, %v2
-; CHECK-NEXT: vaq %v0, %v0, %v3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%in = add i128 %a, %b
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vec.ll b/llvm/test/CodeGen/SystemZ/call-zos-vec.ll
index 32d29cb8ebc08..20bf2687c957e 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-vec.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-vec.ll
@@ -9,15 +9,15 @@ entry:
}
; CHECK-LABEL: sum_vecs1
-; CHECK: vaf 0,24,25
-; CHECK: vaf 0,0,26
-; CHECK: vaf 0,0,27
-; CHECK: vaf 0,0,28
-; CHECK: vaf 0,0,29
-; CHECK: vl 1,2304(4),4
-; CHECK: vaf 0,0,30
-; CHECK: vaf 0,0,31
-; CHECK: vaf 24,0,1
+; CHECK: vaf 1,24,25
+; CHECK: vaf 1,1,26
+; CHECK: vaf 1,1,27
+; CHECK: vaf 1,1,28
+; CHECK: vaf 1,1,29
+; CHECK: vl 0,2304(4),4
+; CHECK: vaf 1,1,30
+; CHECK: vaf 1,1,31
+; CHECK: vaf 24,1,0
define <4 x i32> @sum_vecs1(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8, <4 x i32> %v9) {
entry:
%add0 = add <4 x i32> %v1, %v2
diff --git a/llvm/test/CodeGen/SystemZ/canonicalize-vars.ll b/llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
index e7e9bbc207af2..e6659d385ae5f 100644
--- a/llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
+++ b/llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
@@ -129,13 +129,13 @@ define <8 x half> @canonicalize_v8f16(<8 x half> %a) nounwind {
; Z16-NEXT: vgmf %v1, 2, 8
; Z16-NEXT: meebr %f0, %f1
; Z16-NEXT: brasl %r14, __truncsfhf2 at PLT
-; Z16-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vl %v2, 192(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
; Z16-NEXT: # kill: def $f0h killed $f0h def $v0
-; Z16-NEXT: vreph %v1, %v1, 5
-; Z16-NEXT: vmrhh %v0, %v0, %v2
+; Z16-NEXT: vmrhh %v0, %v0, %v1
; Z16-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
-; Z16-NEXT: ldr %f0, %f1
+; Z16-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vreph %v0, %v0, 5
+; Z16-NEXT: # kill: def $f0h killed $f0h killed $v0
; Z16-NEXT: brasl %r14, __extendhfsf2 at PLT
; Z16-NEXT: vgmf %v1, 2, 8
; Z16-NEXT: meebr %f0, %f1
@@ -150,13 +150,13 @@ define <8 x half> @canonicalize_v8f16(<8 x half> %a) nounwind {
; Z16-NEXT: meebr %f0, %f1
; Z16-NEXT: brasl %r14, __truncsfhf2 at PLT
; Z16-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vl %v2, 192(%r15), 3 # 16-byte Reload
; Z16-NEXT: # kill: def $f0h killed $f0h def $v0
-; Z16-NEXT: vmrhh %v1, %v0, %v1
+; Z16-NEXT: vmrhh %v0, %v0, %v1
+; Z16-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vmrhf %v0, %v0, %v1
+; Z16-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
; Z16-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vmrhf %v1, %v1, %v2
; Z16-NEXT: vreph %v0, %v0, 3
-; Z16-NEXT: vst %v1, 192(%r15), 3 # 16-byte Spill
; Z16-NEXT: # kill: def $f0h killed $f0h killed $v0
; Z16-NEXT: brasl %r14, __extendhfsf2 at PLT
; Z16-NEXT: vgmf %v1, 2, 8
@@ -262,13 +262,13 @@ define void @canonicalize_ptr_v8f16(ptr %out) nounwind {
; Z16-NEXT: vgmf %v1, 2, 8
; Z16-NEXT: meebr %f0, %f1
; Z16-NEXT: brasl %r14, __truncsfhf2 at PLT
-; Z16-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vl %v2, 192(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
; Z16-NEXT: # kill: def $f0h killed $f0h def $v0
-; Z16-NEXT: vreph %v1, %v1, 5
-; Z16-NEXT: vmrhh %v0, %v0, %v2
+; Z16-NEXT: vmrhh %v0, %v0, %v1
; Z16-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
-; Z16-NEXT: ldr %f0, %f1
+; Z16-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vreph %v0, %v0, 5
+; Z16-NEXT: # kill: def $f0h killed $f0h killed $v0
; Z16-NEXT: brasl %r14, __extendhfsf2 at PLT
; Z16-NEXT: vgmf %v1, 2, 8
; Z16-NEXT: meebr %f0, %f1
@@ -283,13 +283,13 @@ define void @canonicalize_ptr_v8f16(ptr %out) nounwind {
; Z16-NEXT: meebr %f0, %f1
; Z16-NEXT: brasl %r14, __truncsfhf2 at PLT
; Z16-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vl %v2, 192(%r15), 3 # 16-byte Reload
; Z16-NEXT: # kill: def $f0h killed $f0h def $v0
-; Z16-NEXT: vmrhh %v1, %v0, %v1
+; Z16-NEXT: vmrhh %v0, %v0, %v1
+; Z16-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vmrhf %v0, %v0, %v1
+; Z16-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
; Z16-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vmrhf %v1, %v1, %v2
; Z16-NEXT: vreph %v0, %v0, 3
-; Z16-NEXT: vst %v1, 192(%r15), 3 # 16-byte Spill
; Z16-NEXT: # kill: def $f0h killed $f0h killed $v0
; Z16-NEXT: brasl %r14, __extendhfsf2 at PLT
; Z16-NEXT: vgmf %v1, 2, 8
diff --git a/llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll b/llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll
index 40c138b84cd40..5f4b1dbf1bc10 100644
--- a/llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll
+++ b/llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll
@@ -7,8 +7,8 @@
define void @fun(i32 %Arg) {
; CHECK-LABEL: fun:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhi %r0, 0
; CHECK-NEXT: ahi %r2, 1
+; CHECK-NEXT: lhi %r0, 0
; CHECK-NEXT: cijlh %r0, 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: tmll %r2, 16
diff --git a/llvm/test/CodeGen/SystemZ/dag-combine-05.ll b/llvm/test/CodeGen/SystemZ/dag-combine-05.ll
index 692d74250c1a0..60528ad67d039 100644
--- a/llvm/test/CodeGen/SystemZ/dag-combine-05.ll
+++ b/llvm/test/CodeGen/SystemZ/dag-combine-05.ll
@@ -9,18 +9,18 @@
define void @fun(i16 %arg0, ptr %src, ptr %dst) {
; CHECK-LABEL: fun:
; CHECK: # %bb.0: # %bb
-; CHECK-NEXT: llh %r0, 0(%r3)
-; CHECK-NEXT: llhr %r1, %r2
-; CHECK-NEXT: chi %r1, 9616
+; CHECK-NEXT: llhr %r0, %r2
+; CHECK-NEXT: llh %r2, 0(%r3)
+; CHECK-NEXT: chi %r0, 9616
; CHECK-NEXT: lhi %r1, 0
; CHECK-NEXT: lochil %r1, 1
-; CHECK-NEXT: afi %r0, 65535
-; CHECK-NEXT: llhr %r2, %r0
-; CHECK-NEXT: lhi %r3, 0
-; CHECK-NEXT: cr %r2, %r0
-; CHECK-NEXT: lochilh %r3, 1
-; CHECK-NEXT: ar %r1, %r3
-; CHECK-NEXT: st %r1, 0(%r4)
+; CHECK-NEXT: afi %r2, 65535
+; CHECK-NEXT: llhr %r3, %r2
+; CHECK-NEXT: lhi %r0, 0
+; CHECK-NEXT: cr %r3, %r2
+; CHECK-NEXT: lochilh %r0, 1
+; CHECK-NEXT: ar %r0, %r1
+; CHECK-NEXT: st %r0, 0(%r4)
; CHECK-NEXT: br %r14
bb:
%tmp = icmp ult i16 %arg0, 9616
diff --git a/llvm/test/CodeGen/SystemZ/dag-combine-07.ll b/llvm/test/CodeGen/SystemZ/dag-combine-07.ll
index 4c65a5371583a..7dd76b61846ef 100644
--- a/llvm/test/CodeGen/SystemZ/dag-combine-07.ll
+++ b/llvm/test/CodeGen/SystemZ/dag-combine-07.ll
@@ -11,11 +11,11 @@ define void @func_5(ptr %Dst) {
; CHECK-LABEL: func_5:
; CHECK: # %bb.0:
; CHECK-NEXT: lgrl %r1, G2 at GOT
-; CHECK-NEXT: lgrl %r3, G1 at GOT
; CHECK-NEXT: llihl %r0, 50
; CHECK-NEXT: oill %r0, 2
; CHECK-NEXT: stg %r0, 0(%r1)
-; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: lgrl %r1, G1 at GOT
+; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: mvhi 0(%r2), 2
; CHECK-NEXT: br %r14
store i64 214748364802, ptr @G2, align 8
diff --git a/llvm/test/CodeGen/SystemZ/fold-masked-merge.ll b/llvm/test/CodeGen/SystemZ/fold-masked-merge.ll
index 86edaeda71e94..c014345507f69 100644
--- a/llvm/test/CodeGen/SystemZ/fold-masked-merge.ll
+++ b/llvm/test/CodeGen/SystemZ/fold-masked-merge.ll
@@ -96,17 +96,17 @@ define i32 @not_a_masked_merge0(i32 %a0, i32 %a1, i32 %a2) {
; NO-MISC3-LABEL: not_a_masked_merge0:
; NO-MISC3: # %bb.0:
; NO-MISC3-NEXT: lcr %r0, %r2
-; NO-MISC3-NEXT: nr %r2, %r3
+; NO-MISC3-NEXT: nr %r3, %r2
; NO-MISC3-NEXT: nr %r0, %r4
-; NO-MISC3-NEXT: or %r2, %r0
+; NO-MISC3-NEXT: ork %r2, %r3, %r0
; NO-MISC3-NEXT: br %r14
;
; MISC3-LABEL: not_a_masked_merge0:
; MISC3: # %bb.0:
; MISC3-NEXT: lcr %r0, %r2
-; MISC3-NEXT: nr %r2, %r3
+; MISC3-NEXT: nr %r3, %r2
; MISC3-NEXT: nr %r0, %r4
-; MISC3-NEXT: or %r2, %r0
+; MISC3-NEXT: ork %r2, %r3, %r0
; MISC3-NEXT: br %r14
%and0 = and i32 %a0, %a1
%not_a_not = sub i32 0, %a0
@@ -162,10 +162,10 @@ define i32 @not_a_masked_merge2(i32 %a0, i32 %a1, i32 %a2) {
define i32 @not_a_masked_merge3(i32 %a0, i32 %a1, i32 %a2) {
; NO-MISC3-LABEL: not_a_masked_merge3:
; NO-MISC3: # %bb.0:
-; NO-MISC3-NEXT: xr %r4, %r2
-; NO-MISC3-NEXT: nr %r2, %r3
-; NO-MISC3-NEXT: xilf %r4, 4294967295
-; NO-MISC3-NEXT: or %r2, %r4
+; NO-MISC3-NEXT: nr %r3, %r2
+; NO-MISC3-NEXT: xr %r2, %r4
+; NO-MISC3-NEXT: xilf %r2, 4294967295
+; NO-MISC3-NEXT: or %r2, %r3
; NO-MISC3-NEXT: br %r14
;
; MISC3-LABEL: not_a_masked_merge3:
@@ -238,8 +238,8 @@ define i32 @masked_merge_no_transform1(i32 %a0, i32 %a1, i32 %a2, ptr %p1) {
; MISC3: # %bb.0:
; MISC3-NEXT: nrk %r0, %r2, %r3
; MISC3-NEXT: ncrk %r1, %r4, %r2
-; MISC3-NEXT: or %r0, %r1
; MISC3-NEXT: xilf %r2, 4294967295
+; MISC3-NEXT: or %r0, %r1
; MISC3-NEXT: st %r2, 0(%r5)
; MISC3-NEXT: lr %r2, %r0
; MISC3-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll b/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
index d1997e98fbe68..c2c5889a689e4 100644
--- a/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
@@ -209,16 +209,16 @@ define fp128 @f13(fp128 %a, float %b) {
;
; Z16-LABEL: f13:
; Z16: # %bb.0:
+; Z16-NEXT: vl %v1, 0(%r3), 3
; Z16-NEXT: vlgvf %r0, %v0, 0
-; Z16-NEXT: vl %v0, 0(%r3), 3
; Z16-NEXT: tmlh %r0, 32768
; Z16-NEXT: je .LBB13_2
; Z16-NEXT: # %bb.1:
-; Z16-NEXT: wflnxb %v0, %v0
+; Z16-NEXT: wflnxb %v0, %v1
; Z16-NEXT: vst %v0, 0(%r2), 3
; Z16-NEXT: br %r14
; Z16-NEXT: .LBB13_2:
-; Z16-NEXT: wflpxb %v0, %v0
+; Z16-NEXT: wflpxb %v0, %v1
; Z16-NEXT: vst %v0, 0(%r2), 3
; Z16-NEXT: br %r14
%b128 = fpext float %b to fp128
@@ -239,16 +239,16 @@ define fp128 @f14(fp128 %a, double %b) {
;
; Z16-LABEL: f14:
; Z16: # %bb.0:
+; Z16-NEXT: vl %v1, 0(%r3), 3
; Z16-NEXT: lgdr %r0, %f0
-; Z16-NEXT: vl %v0, 0(%r3), 3
; Z16-NEXT: tmhh %r0, 32768
; Z16-NEXT: je .LBB14_2
; Z16-NEXT: # %bb.1:
-; Z16-NEXT: wflnxb %v0, %v0
+; Z16-NEXT: wflnxb %v0, %v1
; Z16-NEXT: vst %v0, 0(%r2), 3
; Z16-NEXT: br %r14
; Z16-NEXT: .LBB14_2:
-; Z16-NEXT: wflpxb %v0, %v0
+; Z16-NEXT: wflpxb %v0, %v1
; Z16-NEXT: vst %v0, 0(%r2), 3
; Z16-NEXT: br %r14
%b128 = fpext double %b to fp128
diff --git a/llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll b/llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll
index f141ee0599222..825472299d028 100644
--- a/llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll
@@ -198,10 +198,10 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: std %f8, 240(%r15) # 8-byte Spill
; VECTOR-NEXT: .cfi_offset %f8, -168
; VECTOR-NEXT: vl %v0, 16(%r2), 3
+; VECTOR-NEXT: mvc 160(16,%r15), 0(%r2) # 16-byte Folded Spill
; VECTOR-NEXT: lgr %r13, %r3
; VECTOR-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: vreph %v0, %v0, 7
-; VECTOR-NEXT: mvc 160(16,%r15), 0(%r2) # 16-byte Folded Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -224,13 +224,13 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: aebr %f0, %f8
; VECTOR-NEXT: brasl %r14, __truncsfhf2 at PLT
-; VECTOR-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
-; VECTOR-NEXT: vl %v2, 208(%r15), 3 # 16-byte Reload
+; VECTOR-NEXT: vl %v1, 208(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: # kill: def $f0h killed $f0h def $v0
-; VECTOR-NEXT: vreph %v1, %v1, 5
-; VECTOR-NEXT: vmrhh %v0, %v0, %v2
+; VECTOR-NEXT: vmrhh %v0, %v0, %v1
; VECTOR-NEXT: vst %v0, 208(%r15), 3 # 16-byte Spill
-; VECTOR-NEXT: ldr %f0, %f1
+; VECTOR-NEXT: vl %v0, 176(%r15), 3 # 16-byte Reload
+; VECTOR-NEXT: vreph %v0, %v0, 5
+; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
; VECTOR-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
@@ -253,13 +253,13 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: aebr %f0, %f8
; VECTOR-NEXT: brasl %r14, __truncsfhf2 at PLT
; VECTOR-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
-; VECTOR-NEXT: vl %v2, 208(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: # kill: def $f0h killed $f0h def $v0
-; VECTOR-NEXT: vmrhh %v1, %v0, %v1
+; VECTOR-NEXT: vmrhh %v0, %v0, %v1
+; VECTOR-NEXT: vl %v1, 208(%r15), 3 # 16-byte Reload
+; VECTOR-NEXT: vmrhf %v0, %v0, %v1
+; VECTOR-NEXT: vst %v0, 208(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: vl %v0, 176(%r15), 3 # 16-byte Reload
-; VECTOR-NEXT: vmrhf %v1, %v1, %v2
; VECTOR-NEXT: vreph %v0, %v0, 3
-; VECTOR-NEXT: vst %v1, 208(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
diff --git a/llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll b/llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll
index 8c23a06df8cf2..66b5d76fd9871 100644
--- a/llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll
@@ -242,10 +242,10 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: std %f8, 208(%r15) # 8-byte Spill
; VECTOR-NEXT: .cfi_offset %f8, -168
; VECTOR-NEXT: vl %v0, 16(%r2), 3
+; VECTOR-NEXT: mvc 176(16,%r15), 0(%r2) # 16-byte Folded Spill
; VECTOR-NEXT: lgr %r13, %r3
; VECTOR-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: vreph %v0, %v0, 7
-; VECTOR-NEXT: mvc 176(16,%r15), 0(%r2) # 16-byte Folded Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -256,9 +256,9 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: cebr %f0, %f8
; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lhi %r11, 0
-; VECTOR-NEXT: vreph %v0, %v0, 3
; VECTOR-NEXT: lhi %r12, 0
; VECTOR-NEXT: lochie %r11, -1
+; VECTOR-NEXT: vreph %v0, %v0, 3
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -279,13 +279,13 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: cebr %f0, %f8
-; VECTOR-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
+; VECTOR-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lhi %r0, 0
-; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lochie %r0, -1
-; VECTOR-NEXT: vlvgh %v1, %r0, 0
+; VECTOR-NEXT: vlvgh %v0, %r0, 0
+; VECTOR-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
+; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: vreph %v0, %v0, 1
-; VECTOR-NEXT: vst %v1, 160(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -294,13 +294,13 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: cebr %f0, %f8
-; VECTOR-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
+; VECTOR-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lhi %r0, 0
-; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lochie %r0, -1
-; VECTOR-NEXT: vlvgh %v1, %r0, 1
+; VECTOR-NEXT: vlvgh %v0, %r0, 1
+; VECTOR-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
+; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: vreph %v0, %v0, 2
-; VECTOR-NEXT: vst %v1, 160(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -309,13 +309,13 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: cebr %f0, %f8
-; VECTOR-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
+; VECTOR-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lhi %r0, 0
-; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lochie %r0, -1
-; VECTOR-NEXT: vlvgh %v1, %r0, 2
+; VECTOR-NEXT: vlvgh %v0, %r0, 2
+; VECTOR-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
+; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: vreph %v0, %v0, 4
-; VECTOR-NEXT: vst %v1, 160(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -324,13 +324,13 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: cebr %f0, %f8
-; VECTOR-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
+; VECTOR-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lhi %r0, 0
-; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lochie %r0, -1
-; VECTOR-NEXT: vlvgh %v1, %r0, 4
+; VECTOR-NEXT: vlvgh %v0, %r0, 4
+; VECTOR-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
+; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: vreph %v0, %v0, 5
-; VECTOR-NEXT: vst %v1, 160(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -339,13 +339,13 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: cebr %f0, %f8
-; VECTOR-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
+; VECTOR-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lhi %r0, 0
-; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: lochie %r0, -1
-; VECTOR-NEXT: vlvgh %v1, %r0, 5
+; VECTOR-NEXT: vlvgh %v0, %r0, 5
+; VECTOR-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
+; VECTOR-NEXT: vl %v0, 192(%r15), 3 # 16-byte Reload
; VECTOR-NEXT: vreph %v0, %v0, 6
-; VECTOR-NEXT: vst %v1, 160(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -391,20 +391,20 @@ define void @fun1(ptr %Src, ptr %Dst) {
; CHECK-NEXT: .cfi_offset %f9, -176
; CHECK-NEXT: .cfi_offset %f10, -184
; CHECK-NEXT: .cfi_offset %f11, -192
-; CHECK-NEXT: lgh %r0, 4(%r2)
; CHECK-NEXT: lgh %r1, 2(%r2)
; CHECK-NEXT: lgr %r13, %r3
; CHECK-NEXT: lgh %r3, 0(%r2)
+; CHECK-NEXT: lgh %r0, 4(%r2)
; CHECK-NEXT: lgh %r2, 6(%r2)
-; CHECK-NEXT: sllg %r0, %r0, 48
; CHECK-NEXT: sllg %r1, %r1, 48
; CHECK-NEXT: ldgr %f8, %r1
; CHECK-NEXT: sllg %r1, %r3, 48
+; CHECK-NEXT: ldgr %f11, %r1
+; CHECK-NEXT: sllg %r1, %r2, 48
+; CHECK-NEXT: sllg %r0, %r0, 48
+; CHECK-NEXT: ldgr %f10, %r1
; CHECK-NEXT: ldgr %f0, %r0
; CHECK-NEXT: # kill: def $f0h killed $f0h killed $f0d
-; CHECK-NEXT: sllg %r0, %r2, 48
-; CHECK-NEXT: ldgr %f11, %r1
-; CHECK-NEXT: ldgr %f10, %r0
; CHECK-NEXT: brasl %r14, __extendhfsf2 at PLT
; CHECK-NEXT: ler %f9, %f0
; CHECK-NEXT: ler %f0, %f11
@@ -429,15 +429,15 @@ define void @fun1(ptr %Src, ptr %Dst) {
; CHECK-NEXT: brasl %r14, __truncsfhf2 at PLT
; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d
; CHECK-NEXT: lgdr %r0, %f0
-; CHECK-NEXT: lgdr %r1, %f9
+; CHECK-NEXT: srlg %r0, %r0, 48
+; CHECK-NEXT: sth %r0, 2(%r13)
+; CHECK-NEXT: lgdr %r0, %f9
; CHECK-NEXT: ld %f8, 184(%r15) # 8-byte Reload
; CHECK-NEXT: ld %f9, 176(%r15) # 8-byte Reload
; CHECK-NEXT: ld %f10, 168(%r15) # 8-byte Reload
; CHECK-NEXT: ld %f11, 160(%r15) # 8-byte Reload
; CHECK-NEXT: srlg %r0, %r0, 48
-; CHECK-NEXT: srlg %r1, %r1, 48
-; CHECK-NEXT: sth %r0, 2(%r13)
-; CHECK-NEXT: sth %r1, 0(%r13)
+; CHECK-NEXT: sth %r0, 0(%r13)
; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
; CHECK-NEXT: br %r14
;
@@ -460,31 +460,31 @@ define void @fun1(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: vlreph %v0, 4(%r2)
; VECTOR-NEXT: vlreph %v8, 2(%r2)
; VECTOR-NEXT: vlreph %v11, 0(%r2)
-; VECTOR-NEXT: vlreph %v10, 6(%r2)
+; VECTOR-NEXT: vlreph %v9, 6(%r2)
; VECTOR-NEXT: lgr %r13, %r3
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
-; VECTOR-NEXT: ldr %f9, %f0
+; VECTOR-NEXT: ldr %f10, %f0
; VECTOR-NEXT: ldr %f0, %f11
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
-; VECTOR-NEXT: cebr %f0, %f9
+; VECTOR-NEXT: cebr %f0, %f10
; VECTOR-NEXT: je .LBB1_2
; VECTOR-NEXT: # %bb.1:
-; VECTOR-NEXT: ldr %f0, %f9
+; VECTOR-NEXT: ldr %f0, %f10
; VECTOR-NEXT: .LBB1_2:
; VECTOR-NEXT: brasl %r14, __truncsfhf2 at PLT
-; VECTOR-NEXT: ldr %f9, %f0
-; VECTOR-NEXT: ldr %f0, %f10
-; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f10, %f0
+; VECTOR-NEXT: ldr %f0, %f9
+; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
+; VECTOR-NEXT: ldr %f9, %f0
; VECTOR-NEXT: ldr %f0, %f8
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
-; VECTOR-NEXT: cebr %f0, %f10
+; VECTOR-NEXT: cebr %f0, %f9
; VECTOR-NEXT: je .LBB1_4
; VECTOR-NEXT: # %bb.3:
-; VECTOR-NEXT: ldr %f0, %f10
+; VECTOR-NEXT: ldr %f0, %f9
; VECTOR-NEXT: .LBB1_4:
; VECTOR-NEXT: brasl %r14, __truncsfhf2 at PLT
-; VECTOR-NEXT: vsteh %v9, 0(%r13), 0
+; VECTOR-NEXT: vsteh %v10, 0(%r13), 0
; VECTOR-NEXT: ld %f8, 184(%r15) # 8-byte Reload
; VECTOR-NEXT: ld %f9, 176(%r15) # 8-byte Reload
; VECTOR-NEXT: ld %f10, 168(%r15) # 8-byte Reload
diff --git a/llvm/test/CodeGen/SystemZ/fp-half.ll b/llvm/test/CodeGen/SystemZ/fp-half.ll
index 2de7fd3c79461..7706e86392c9c 100644
--- a/llvm/test/CodeGen/SystemZ/fp-half.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-half.ll
@@ -566,12 +566,12 @@ define void @fun11() {
; NOVEC-NEXT: lghrl %r0, .LCPI11_0
; NOVEC-NEXT: lghrl %r1, .LCPI11_1
; NOVEC-NEXT: lzer %f2
-; NOVEC-NEXT: lcdfr %f0, %f2
; NOVEC-NEXT: sllg %r0, %r0, 48
-; NOVEC-NEXT: sllg %r1, %r1, 48
+; NOVEC-NEXT: lcdfr %f0, %f2
; NOVEC-NEXT: ldgr %f4, %r0
; NOVEC-NEXT: # kill: def $f4h killed $f4h killed $f4d
-; NOVEC-NEXT: ldgr %f6, %r1
+; NOVEC-NEXT: sllg %r0, %r1, 48
+; NOVEC-NEXT: ldgr %f6, %r0
; NOVEC-NEXT: # kill: def $f6h killed $f6h killed $f6d
; NOVEC-NEXT: brasl %r14, foo2 at PLT
; NOVEC-NEXT: lmg %r14, %r15, 272(%r15)
diff --git a/llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-explicit-regs-zEC12.ll b/llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-explicit-regs-zEC12.ll
index cb6e9ca81bcfa..6228ffaa35fa2 100644
--- a/llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-explicit-regs-zEC12.ll
+++ b/llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-explicit-regs-zEC12.ll
@@ -212,13 +212,13 @@ define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) {
; CHECK-NEXT: aghi %r15, -176
; CHECK-NEXT: .cfi_def_cfa_offset 336
; CHECK-NEXT: # kill: def $r4l killed $r4l def $r4d
-; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: sllg %r0, %r4, 32
; CHECK-NEXT: lr %r0, %r5
-; CHECK-NEXT: sllg %r1, %r2, 32
-; CHECK-NEXT: lr %r1, %r3
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: stg %r0, 168(%r15)
-; CHECK-NEXT: stg %r1, 160(%r15)
+; CHECK-NEXT: sllg %r0, %r2, 32
+; CHECK-NEXT: lr %r0, %r3
+; CHECK-NEXT: stg %r0, 160(%r15)
; CHECK-NEXT: ld %f0, 160(%r15)
; CHECK-NEXT: ld %f2, 168(%r15)
; CHECK-NEXT: #APP
diff --git a/llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-zEC12.ll b/llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-zEC12.ll
index 7f06f66e6411e..19969ccf4e297 100644
--- a/llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-zEC12.ll
+++ b/llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-zEC12.ll
@@ -205,13 +205,13 @@ define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) {
; CHECK-NEXT: aghi %r15, -176
; CHECK-NEXT: .cfi_def_cfa_offset 336
; CHECK-NEXT: # kill: def $r4l killed $r4l def $r4d
-; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: sllg %r0, %r4, 32
; CHECK-NEXT: lr %r0, %r5
-; CHECK-NEXT: sllg %r1, %r2, 32
-; CHECK-NEXT: lr %r1, %r3
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
; CHECK-NEXT: stg %r0, 168(%r15)
-; CHECK-NEXT: stg %r1, 160(%r15)
+; CHECK-NEXT: sllg %r0, %r2, 32
+; CHECK-NEXT: lr %r0, %r3
+; CHECK-NEXT: stg %r0, 160(%r15)
; CHECK-NEXT: ld %f0, 160(%r15)
; CHECK-NEXT: ld %f2, 168(%r15)
; CHECK-NEXT: #APP
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-65.ll b/llvm/test/CodeGen/SystemZ/int-cmp-65.ll
index d9aff41f597b4..f1d850200fe41 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-65.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-65.ll
@@ -247,10 +247,10 @@ define i128 @i128_addc_xor_inv(i128 %a, i128 %b) {
;
; Z13-LABEL: i128_addc_xor_inv:
; Z13: # %bb.0:
-; Z13-NEXT: vl %v0, 0(%r4), 3
-; Z13-NEXT: vl %v1, 0(%r3), 3
-; Z13-NEXT: vno %v0, %v0, %v0
-; Z13-NEXT: vscbiq %v0, %v0, %v1
+; Z13-NEXT: vl %v1, 0(%r4), 3
+; Z13-NEXT: vl %v0, 0(%r3), 3
+; Z13-NEXT: vno %v1, %v1, %v1
+; Z13-NEXT: vscbiq %v0, %v1, %v0
; Z13-NEXT: vst %v0, 0(%r2), 3
; Z13-NEXT: br %r14
%b.not = xor i128 %b, -1
diff --git a/llvm/test/CodeGen/SystemZ/int-conv-14.ll b/llvm/test/CodeGen/SystemZ/int-conv-14.ll
index b8e40379b07fc..6df086058cd3c 100644
--- a/llvm/test/CodeGen/SystemZ/int-conv-14.ll
+++ b/llvm/test/CodeGen/SystemZ/int-conv-14.ll
@@ -332,9 +332,9 @@ define i128 @f25(i1 %a) {
; CHECK-LABEL: f25:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI24_0
-; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vlvgp %v1, %r3, %r3
-; CHECK-NEXT: vn %v0, %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vlvgp %v0, %r3, %r3
+; CHECK-NEXT: vn %v0, %v0, %v1
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vsq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -350,10 +350,10 @@ define i128 @f26(ptr %ptr) {
; CHECK-NEXT: vgbm %v0, 0
; CHECK-NEXT: vleb %v0, 0(%r3), 15
; CHECK-NEXT: larl %r1, .LCPI25_0
-; CHECK-NEXT: vl %v1, 0(%r1), 3
-; CHECK-NEXT: vgbm %v2, 0
-; CHECK-NEXT: vn %v0, %v0, %v1
-; CHECK-NEXT: vsq %v0, %v2, %v0
+; CHECK-NEXT: vl %v2, 0(%r1), 3
+; CHECK-NEXT: vgbm %v1, 0
+; CHECK-NEXT: vn %v0, %v0, %v2
+; CHECK-NEXT: vsq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%a = load i1, ptr %ptr
@@ -366,9 +366,9 @@ define i128 @f27(i1 %a) {
; CHECK-LABEL: f27:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI26_0
-; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vlvgp %v1, %r3, %r3
-; CHECK-NEXT: vn %v0, %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vlvgp %v0, %r3, %r3
+; CHECK-NEXT: vn %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%res = zext i1 %a to i128
diff --git a/llvm/test/CodeGen/SystemZ/int-conv-15.ll b/llvm/test/CodeGen/SystemZ/int-conv-15.ll
index da9a2be186a73..f2c9ee5fa1f57 100644
--- a/llvm/test/CodeGen/SystemZ/int-conv-15.ll
+++ b/llvm/test/CodeGen/SystemZ/int-conv-15.ll
@@ -332,9 +332,9 @@ define i128 @f25(i1 %a) {
; CHECK-LABEL: f25:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI24_0
-; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vlvgp %v1, %r3, %r3
-; CHECK-NEXT: vn %v0, %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vlvgp %v0, %r3, %r3
+; CHECK-NEXT: vn %v0, %v0, %v1
; CHECK-NEXT: vlcq %v0, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -364,9 +364,9 @@ define i128 @f27(i1 %a) {
; CHECK-LABEL: f27:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI26_0
-; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vlvgp %v1, %r3, %r3
-; CHECK-NEXT: vn %v0, %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vlvgp %v0, %r3, %r3
+; CHECK-NEXT: vn %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%res = zext i1 %a to i128
diff --git a/llvm/test/CodeGen/SystemZ/int-mul-13.ll b/llvm/test/CodeGen/SystemZ/int-mul-13.ll
index db159187f7ec8..82937cf66c629 100644
--- a/llvm/test/CodeGen/SystemZ/int-mul-13.ll
+++ b/llvm/test/CodeGen/SystemZ/int-mul-13.ll
@@ -24,12 +24,12 @@ define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
-; CHECK-NEXT: srag %r0, %r4, 63
+; CHECK-NEXT: srag %r1, %r4, 63
; CHECK-NEXT: # kill: def $r3d killed $r3d def $r2q
-; CHECK-NEXT: srag %r1, %r3, 63
-; CHECK-NEXT: ngr %r0, %r3
+; CHECK-NEXT: srag %r0, %r3, 63
+; CHECK-NEXT: ngr %r1, %r3
; CHECK-NEXT: mlgr %r2, %r4
-; CHECK-NEXT: ngr %r1, %r4
+; CHECK-NEXT: ngr %r0, %r4
; CHECK-NEXT: agr %r0, %r1
; CHECK-NEXT: sgr %r2, %r0
; CHECK-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-14.ll b/llvm/test/CodeGen/SystemZ/int-uadd-14.ll
index a3603111aa2dc..c8873a4dfadef 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-14.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-14.ll
@@ -6,17 +6,17 @@
define zeroext i1 @f1(i256 %a, i256 %b, ptr %res) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 16(%r3), 3
-; CHECK-NEXT: vl %v1, 16(%r2), 3
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vl %v3, 0(%r2), 3
-; CHECK-NEXT: vaccq %v4, %v1, %v0
-; CHECK-NEXT: vaq %v0, %v1, %v0
-; CHECK-NEXT: vacccq %v5, %v3, %v2, %v4
+; CHECK-NEXT: vl %v2, 16(%r3), 3
+; CHECK-NEXT: vl %v3, 16(%r2), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-NEXT: vaccq %v4, %v3, %v2
+; CHECK-NEXT: vacccq %v5, %v1, %v0, %v4
; CHECK-NEXT: vlgvg %r2, %v5, 1
-; CHECK-NEXT: vacq %v2, %v3, %v2, %v4
-; CHECK-NEXT: vst %v0, 16(%r4), 3
-; CHECK-NEXT: vst %v2, 0(%r4), 3
+; CHECK-NEXT: vacq %v0, %v1, %v0, %v4
+; CHECK-NEXT: vaq %v1, %v3, %v2
+; CHECK-NEXT: vst %v1, 16(%r4), 3
+; CHECK-NEXT: vst %v0, 0(%r4), 3
; CHECK-NEXT: br %r14
%t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)
%val = extractvalue {i256, i1} %t, 0
@@ -28,12 +28,12 @@ define zeroext i1 @f1(i256 %a, i256 %b, ptr %res) {
define zeroext i1 @f2(i256 %a, i256 %b) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 16(%r3), 3
-; CHECK-NEXT: vl %v1, 16(%r2), 3
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vl %v3, 0(%r2), 3
-; CHECK-NEXT: vaccq %v0, %v1, %v0
-; CHECK-NEXT: vacccq %v0, %v3, %v2, %v0
+; CHECK-NEXT: vl %v2, 16(%r3), 3
+; CHECK-NEXT: vl %v3, 16(%r2), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-NEXT: vaccq %v2, %v3, %v2
+; CHECK-NEXT: vacccq %v0, %v1, %v0, %v2
; CHECK-NEXT: vlgvg %r2, %v0, 1
; CHECK-NEXT: br %r14
%t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)
@@ -44,15 +44,15 @@ define zeroext i1 @f2(i256 %a, i256 %b) {
define i256 @f3(i256 %a, i256 %b) {
; CHECK-LABEL: f3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 16(%r4), 3
-; CHECK-NEXT: vl %v1, 16(%r3), 3
-; CHECK-NEXT: vl %v2, 0(%r4), 3
-; CHECK-NEXT: vl %v3, 0(%r3), 3
-; CHECK-NEXT: vaccq %v4, %v1, %v0
-; CHECK-NEXT: vaq %v0, %v1, %v0
-; CHECK-NEXT: vacq %v2, %v3, %v2, %v4
-; CHECK-NEXT: vst %v0, 16(%r2), 3
-; CHECK-NEXT: vst %v2, 0(%r2), 3
+; CHECK-NEXT: vl %v2, 16(%r4), 3
+; CHECK-NEXT: vl %v3, 16(%r3), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vaccq %v4, %v3, %v2
+; CHECK-NEXT: vacq %v0, %v1, %v0, %v4
+; CHECK-NEXT: vaq %v1, %v3, %v2
+; CHECK-NEXT: vst %v1, 16(%r2), 3
+; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)
%val = extractvalue {i256, i1} %t, 0
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-13.ll b/llvm/test/CodeGen/SystemZ/int-usub-13.ll
index ebdda5c69ecbd..794af3b73fbe2 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-13.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-13.ll
@@ -6,18 +6,18 @@
define zeroext i1 @f1(i256 %a, i256 %b, ptr %res) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 16(%r3), 3
-; CHECK-NEXT: vl %v1, 16(%r2), 3
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vl %v3, 0(%r2), 3
-; CHECK-NEXT: vscbiq %v4, %v1, %v0
-; CHECK-NEXT: vsq %v0, %v1, %v0
-; CHECK-NEXT: vsbcbiq %v5, %v3, %v2, %v4
+; CHECK-NEXT: vl %v2, 16(%r3), 3
+; CHECK-NEXT: vl %v3, 16(%r2), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-NEXT: vscbiq %v4, %v3, %v2
+; CHECK-NEXT: vsbcbiq %v5, %v1, %v0, %v4
; CHECK-NEXT: vlgvg %r2, %v5, 1
-; CHECK-NEXT: vsbiq %v2, %v3, %v2, %v4
+; CHECK-NEXT: vsbiq %v0, %v1, %v0, %v4
+; CHECK-NEXT: vsq %v1, %v3, %v2
; CHECK-NEXT: xilf %r2, 1
-; CHECK-NEXT: vst %v0, 16(%r4), 3
-; CHECK-NEXT: vst %v2, 0(%r4), 3
+; CHECK-NEXT: vst %v1, 16(%r4), 3
+; CHECK-NEXT: vst %v0, 0(%r4), 3
; CHECK-NEXT: br %r14
%t = call {i256, i1} @llvm.usub.with.overflow.i256(i256 %a, i256 %b)
%val = extractvalue {i256, i1} %t, 0
@@ -29,12 +29,12 @@ define zeroext i1 @f1(i256 %a, i256 %b, ptr %res) {
define zeroext i1 @f2(i256 %a, i256 %b) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 16(%r3), 3
-; CHECK-NEXT: vl %v1, 16(%r2), 3
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vl %v3, 0(%r2), 3
-; CHECK-NEXT: vscbiq %v0, %v1, %v0
-; CHECK-NEXT: vsbcbiq %v0, %v3, %v2, %v0
+; CHECK-NEXT: vl %v2, 16(%r3), 3
+; CHECK-NEXT: vl %v3, 16(%r2), 3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-NEXT: vscbiq %v2, %v3, %v2
+; CHECK-NEXT: vsbcbiq %v0, %v1, %v0, %v2
; CHECK-NEXT: vlgvg %r2, %v0, 1
; CHECK-NEXT: xilf %r2, 1
; CHECK-NEXT: br %r14
@@ -46,15 +46,15 @@ define zeroext i1 @f2(i256 %a, i256 %b) {
define i256 @f3(i256 %a, i256 %b) {
; CHECK-LABEL: f3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 16(%r4), 3
-; CHECK-NEXT: vl %v1, 16(%r3), 3
-; CHECK-NEXT: vl %v2, 0(%r4), 3
-; CHECK-NEXT: vl %v3, 0(%r3), 3
-; CHECK-NEXT: vscbiq %v4, %v1, %v0
-; CHECK-NEXT: vsq %v0, %v1, %v0
-; CHECK-NEXT: vsbiq %v2, %v3, %v2, %v4
-; CHECK-NEXT: vst %v0, 16(%r2), 3
-; CHECK-NEXT: vst %v2, 0(%r2), 3
+; CHECK-NEXT: vl %v2, 16(%r4), 3
+; CHECK-NEXT: vl %v3, 16(%r3), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vscbiq %v4, %v3, %v2
+; CHECK-NEXT: vsbiq %v0, %v1, %v0, %v4
+; CHECK-NEXT: vsq %v1, %v3, %v2
+; CHECK-NEXT: vst %v1, 16(%r2), 3
+; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%t = call {i256, i1} @llvm.usub.with.overflow.i256(i256 %a, i256 %b)
%val = extractvalue {i256, i1} %t, 0
diff --git a/llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll b/llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll
index d67d085b2402a..0f98f40b8e62a 100644
--- a/llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll
+++ b/llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; Test that DAGCombiner gets helped by computeKnownBitsForTargetNode() with
; vector intrinsics.
;
@@ -10,9 +11,9 @@ declare {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64>, <2 x i64>)
; PACKS_CC (operand elements are 0): i64 -> i32
define <4 x i32> @f0() {
; CHECK-LABEL: f0:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> <i64 0, i64 0>, <2 x i64> <i64 0, i64 0>)
%extr = extractvalue {<4 x i32>, i32} %call, 0
%and = and <4 x i32> %extr, <i32 1, i32 1, i32 1, i32 1>
@@ -24,10 +25,10 @@ define <4 x i32> @f0() {
; of vrepif. Similarly for more test cases below.
define <4 x i32> @f1() {
; CHECK-LABEL: f1:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepig %v0, 1
-; CHECK-NEXT: vpksgs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepig %v0, 1
+; CHECK-NEXT: vpksgs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> <i64 1, i64 1>, <2 x i64> <i64 1, i64 1>)
%extr = extractvalue {<4 x i32>, i32} %call, 0
%and = and <4 x i32> %extr, <i32 1, i32 1, i32 1, i32 1>
@@ -37,9 +38,9 @@ define <4 x i32> @f1() {
; PACKS_CC (operand elements are 0): i32 -> i16
define <8 x i16> @f2() {
; CHECK-LABEL: f2:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> <i32 0, i32 0, i32 0, i32 0>,
<4 x i32> <i32 0, i32 0, i32 0, i32 0>)
%extr = extractvalue {<8 x i16>, i32} %call, 0
@@ -50,10 +51,10 @@ define <8 x i16> @f2() {
; PACKS_CC (operand elements are 1): i32 -> i16
define <8 x i16> @f3() {
; CHECK-LABEL: f3:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepif %v0, 1
-; CHECK-NEXT: vpksfs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepif %v0, 1
+; CHECK-NEXT: vpksfs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> <i32 1, i32 1, i32 1, i32 1>,
<4 x i32> <i32 1, i32 1, i32 1, i32 1>)
%extr = extractvalue {<8 x i16>, i32} %call, 0
@@ -64,9 +65,9 @@ define <8 x i16> @f3() {
; PACKS_CC (operand elements are 0): i16 -> i8
define <16 x i8> @f4() {
; CHECK-LABEL: f4:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpkshs(
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>,
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
@@ -79,10 +80,10 @@ define <16 x i8> @f4() {
; PACKS_CC (operand elements are 1): i16 -> i8
define <16 x i8> @f5() {
; CHECK-LABEL: f5:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepih %v0, 1
-; CHECK-NEXT: vpkshs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepih %v0, 1
+; CHECK-NEXT: vpkshs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpkshs(
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>,
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
@@ -99,9 +100,9 @@ declare {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64>, <2 x i64>)
; PACKLS_CC (operand elements are 0): i64 -> i32
define <4 x i32> @f6() {
; CHECK-LABEL: f6:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> <i64 0, i64 0>, <2 x i64> <i64 0, i64 0>)
%extr = extractvalue {<4 x i32>, i32} %call, 0
%and = and <4 x i32> %extr, <i32 1, i32 1, i32 1, i32 1>
@@ -111,10 +112,10 @@ define <4 x i32> @f6() {
; PACKLS_CC (operand elements are 1): i64 -> i32
define <4 x i32> @f7() {
; CHECK-LABEL: f7:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepig %v0, 1
-; CHECK-NEXT: vpklsgs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepig %v0, 1
+; CHECK-NEXT: vpklsgs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> <i64 1, i64 1>, <2 x i64> <i64 1, i64 1>)
%extr = extractvalue {<4 x i32>, i32} %call, 0
%and = and <4 x i32> %extr, <i32 1, i32 1, i32 1, i32 1>
@@ -124,9 +125,9 @@ define <4 x i32> @f7() {
; PACKLS_CC (operand elements are 0): i32 -> i16
define <8 x i16> @f8() {
; CHECK-LABEL: f8:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> <i32 0, i32 0, i32 0, i32 0>,
<4 x i32> <i32 0, i32 0, i32 0, i32 0>)
%extr = extractvalue {<8 x i16>, i32} %call, 0
@@ -137,10 +138,10 @@ define <8 x i16> @f8() {
; PACKLS_CC (operand elements are 1): i32 -> i16
define <8 x i16> @f9() {
; CHECK-LABEL: f9:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepif %v0, 1
-; CHECK-NEXT: vpklsfs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepif %v0, 1
+; CHECK-NEXT: vpklsfs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> <i32 1, i32 1, i32 1, i32 1>,
<4 x i32> <i32 1, i32 1, i32 1, i32 1>)
%extr = extractvalue {<8 x i16>, i32} %call, 0
@@ -151,9 +152,9 @@ define <8 x i16> @f9() {
; PACKLS_CC (operand elements are 0): i16 -> i8
define <16 x i8> @f10() {
; CHECK-LABEL: f10:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpklshs(
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>,
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
@@ -166,10 +167,10 @@ define <16 x i8> @f10() {
; PACKLS_CC (operand elements are 1): i16 -> i8
define <16 x i8> @f11() {
; CHECK-LABEL: f11:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepih %v0, 1
-; CHECK-NEXT: vpklshs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepih %v0, 1
+; CHECK-NEXT: vpklshs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpklshs(
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>,
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
@@ -186,9 +187,9 @@ declare <4 x i32> @llvm.s390.vpksg(<2 x i64>, <2 x i64>)
; PACKS (operand elements are 0): i64 -> i32
define <4 x i32> @f12() {
; CHECK-LABEL: f12:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call <4 x i32> @llvm.s390.vpksg(<2 x i64> <i64 0, i64 0>, <2 x i64> <i64 0, i64 0>)
%and = and <4 x i32> %call, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %and
@@ -197,10 +198,10 @@ define <4 x i32> @f12() {
; PACKS (operand elements are 1): i64 -> i32
define <4 x i32> @f13() {
; CHECK-LABEL: f13:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepig %v0, 1
-; CHECK-NEXT: vpksg %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepig %v0, 1
+; CHECK-NEXT: vpksg %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <4 x i32> @llvm.s390.vpksg(<2 x i64> <i64 1, i64 1>, <2 x i64> <i64 1, i64 1>)
%and = and <4 x i32> %call, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %and
@@ -209,9 +210,9 @@ define <4 x i32> @f13() {
; PACKS (operand elements are 0): i32 -> i16
define <8 x i16> @f14() {
; CHECK-LABEL: f14:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call <8 x i16> @llvm.s390.vpksf(<4 x i32> <i32 0, i32 0, i32 0, i32 0>,
<4 x i32> <i32 0, i32 0, i32 0, i32 0>)
%and = and <8 x i16> %call, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -221,10 +222,10 @@ define <8 x i16> @f14() {
; PACKS (operand elements are 1): i32 -> i16
define <8 x i16> @f15() {
; CHECK-LABEL: f15:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepif %v0, 1
-; CHECK-NEXT: vpksf %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepif %v0, 1
+; CHECK-NEXT: vpksf %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <8 x i16> @llvm.s390.vpksf(<4 x i32> <i32 1, i32 1, i32 1, i32 1>,
<4 x i32> <i32 1, i32 1, i32 1, i32 1>)
%and = and <8 x i16> %call, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -234,9 +235,9 @@ define <8 x i16> @f15() {
; PACKS (operand elements are 0): i16 -> i8
define <16 x i8> @f16() {
; CHECK-LABEL: f16:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call <16 x i8> @llvm.s390.vpksh(
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>,
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
@@ -248,10 +249,10 @@ define <16 x i8> @f16() {
; PACKS (operand elements are 1): i16 -> i8
define <16 x i8> @f17() {
; CHECK-LABEL: f17:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepih %v0, 1
-; CHECK-NEXT: vpksh %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepih %v0, 1
+; CHECK-NEXT: vpksh %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <16 x i8> @llvm.s390.vpksh(
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>,
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
@@ -267,9 +268,9 @@ declare <4 x i32> @llvm.s390.vpklsg(<2 x i64>, <2 x i64>)
; PACKLS (operand elements are 0): i64 -> i32
define <4 x i32> @f18() {
; CHECK-LABEL: f18:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call <4 x i32> @llvm.s390.vpklsg(<2 x i64> <i64 0, i64 0>, <2 x i64> <i64 0, i64 0>)
%and = and <4 x i32> %call, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %and
@@ -278,10 +279,10 @@ define <4 x i32> @f18() {
; PACKLS (operand elements are 1): i64 -> i32
define <4 x i32> @f19() {
; CHECK-LABEL: f19:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepig %v0, 1
-; CHECK-NEXT: vpklsg %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepig %v0, 1
+; CHECK-NEXT: vpklsg %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <4 x i32> @llvm.s390.vpklsg(<2 x i64> <i64 1, i64 1>, <2 x i64> <i64 1, i64 1>)
%and = and <4 x i32> %call, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %and
@@ -290,9 +291,9 @@ define <4 x i32> @f19() {
; PACKLS (operand elements are 0): i32 -> i16
define <8 x i16> @f20() {
; CHECK-LABEL: f20:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call <8 x i16> @llvm.s390.vpklsf(<4 x i32> <i32 0, i32 0, i32 0, i32 0>,
<4 x i32> <i32 0, i32 0, i32 0, i32 0>)
%and = and <8 x i16> %call, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -302,10 +303,10 @@ define <8 x i16> @f20() {
; PACKLS (operand elements are 1): i32 -> i16
define <8 x i16> @f21() {
; CHECK-LABEL: f21:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepif %v0, 1
-; CHECK-NEXT: vpklsf %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepif %v0, 1
+; CHECK-NEXT: vpklsf %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <8 x i16> @llvm.s390.vpklsf(<4 x i32> <i32 1, i32 1, i32 1, i32 1>,
<4 x i32> <i32 1, i32 1, i32 1, i32 1>)
%and = and <8 x i16> %call, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -315,9 +316,9 @@ define <8 x i16> @f21() {
; PACKLS (operand elements are 0): i16 -> i8
define <16 x i8> @f22() {
; CHECK-LABEL: f22:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%call = call <16 x i8> @llvm.s390.vpklsh(
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>,
<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
@@ -329,10 +330,10 @@ define <16 x i8> @f22() {
; PACKLS (operand elements are 1): i16 -> i8
define <16 x i8> @f23() {
; CHECK-LABEL: f23:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepih %v0, 1
-; CHECK-NEXT: vpklsh %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepih %v0, 1
+; CHECK-NEXT: vpklsh %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <16 x i8> @llvm.s390.vpklsh(
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>,
<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
@@ -346,9 +347,9 @@ declare <2 x i64> @llvm.s390.vpdi(<2 x i64>, <2 x i64>, i32)
; VPDI (operand elements are 0):
define <2 x i64> @f24() {
; CHECK-LABEL: f24:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%perm = call <2 x i64> @llvm.s390.vpdi(<2 x i64> <i64 0, i64 0>,
<2 x i64> <i64 0, i64 0>, i32 0)
%res = and <2 x i64> %perm, <i64 1, i64 1>
@@ -358,10 +359,10 @@ define <2 x i64> @f24() {
; VPDI (operand elements are 1):
define <2 x i64> @f25() {
; CHECK-LABEL: f25:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepig %v0, 1
-; CHECK-NEXT: vpdi %v24, %v0, %v0, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepig %v0, 1
+; CHECK-NEXT: vpdi %v24, %v0, %v0, 0
+; CHECK-NEXT: br %r14
%perm = call <2 x i64> @llvm.s390.vpdi(<2 x i64> <i64 1, i64 1>,
<2 x i64> <i64 1, i64 1>, i32 0)
%res = and <2 x i64> %perm, <i64 1, i64 1>
@@ -373,9 +374,9 @@ declare <16 x i8> @llvm.s390.vsldb(<16 x i8>, <16 x i8>, i32)
; VSLDB (operand elements are 0):
define <16 x i8> @f26() {
; CHECK-LABEL: f26:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%shfd = call <16 x i8> @llvm.s390.vsldb(<16 x i8>
<i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,
i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>
@@ -391,10 +392,10 @@ define <16 x i8> @f26() {
; VSLDB (operand elements are 1):
define <16 x i8> @f27() {
; CHECK-LABEL: f27:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vrepib %v0, 1
-; CHECK-NEXT: vsldb %v24, %v0, %v0, 1
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepib %v0, 1
+; CHECK-NEXT: vsldb %v24, %v0, %v0, 1
+; CHECK-NEXT: br %r14
%shfd = call <16 x i8> @llvm.s390.vsldb(<16 x i8>
<i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>
@@ -410,9 +411,9 @@ define <16 x i8> @f27() {
; Test that intrinsic CC result is recognized.
define i32 @f28(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: f28:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: lhi %r2, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b)
%cc = extractvalue {<8 x i16>, i32} %call, 1
%res = and i32 %cc, -4
@@ -424,9 +425,9 @@ declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>)
; Test VPERM (operand elements are 0):
define <16 x i8> @f29() {
; CHECK-LABEL: f29:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v24, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v24, 0
+; CHECK-NEXT: br %r14
%perm = call <16 x i8> @llvm.s390.vperm(
<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,
i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>,
@@ -442,11 +443,11 @@ define <16 x i8> @f29() {
; Test VPERM (operand elements are 1):
define <16 x i8> @f30() {
; CHECK-LABEL: f30:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: vgbm %v0, 0
-; CHECK-NEXT: vrepib %v1, 1
-; CHECK-NEXT: vperm %v24, %v1, %v1, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vgbm %v0, 0
+; CHECK-NEXT: vrepib %v1, 1
+; CHECK-NEXT: vperm %v24, %v1, %v1, %v0
+; CHECK-NEXT: br %r14
%perm = call <16 x i8> @llvm.s390.vperm(
<16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>,
@@ -462,16 +463,16 @@ define <16 x i8> @f30() {
; Test VPERM with various constant operands.
define i32 @f31() {
; CHECK-LABEL: f31:
-; CHECK-LABEL: # %bb.0:
-; CHECK-NEXT: larl %r1, .LCPI31_0
-; CHECK-NEXT: larl %r2, .LCPI31_1
-; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vl %v1, 0(%r2), 3
-; CHECK-NEXT: vperm %v0, %v1, %v1, %v0
-; CHECK-NEXT: vlgvb %r2, %v0, 0
-; CHECK-NEXT: nilf %r2, 7
-; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI31_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: larl %r1, .LCPI31_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vperm %v0, %v1, %v1, %v0
+; CHECK-NEXT: vlgvb %r2, %v0, 0
+; CHECK-NEXT: nilf %r2, 7
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%P = tail call <16 x i8> @llvm.s390.vperm(<16 x i8> <i8 0, i8 1, i8 1, i8 2, i8 1, i8 2, i8 2, i8 3, i8 1, i8 2, i8 2, i8 3, i8 2, i8 3, i8 3, i8 4>, <16 x i8> <i8 0, i8 1, i8 1, i8 2, i8 1, i8 2, i8 2, i8 3, i8 1, i8 2, i8 2, i8 3, i8 2, i8 3, i8 3, i8 4>, <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0>)
%E = extractelement <16 x i8> %P, i64 0
%res = zext i8 %E to i32
diff --git a/llvm/test/CodeGen/SystemZ/misched-prera-cmp-elim.mir b/llvm/test/CodeGen/SystemZ/misched-prera-cmp-elim.mir
index 421b2328c3612..e03f55d4090d2 100644
--- a/llvm/test/CodeGen/SystemZ/misched-prera-cmp-elim.mir
+++ b/llvm/test/CodeGen/SystemZ/misched-prera-cmp-elim.mir
@@ -9,8 +9,9 @@
# CHECK-NEXT: fun0:%bb.0
# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: fun0:%bb.1
-# CHECK: Queue BotQ.A: 4 5
-# CHECK-NEXT: Cand SU(4) FIRST
+# CHECK: Queue BotQ.A: 6 4
+# CHECK-NEXT: Cand SU(6) FIRST
+# CHECK-NEXT: Cand SU(4) WEAK
# CHECK-NEXT: Pick Bot WEAK [pre-RA]
# CHECK-NEXT: Scheduling SU(4) %7:gr32bit = NRK %6:gr32bit, %0:gr32bit, implicit-def dead $cc
# CHECK: *** Final schedule for %bb.1 ***
@@ -19,8 +20,8 @@
# CHECK-NEXT: SU(2): %6:gr32bit = LHIMux 0
# CHECK-NEXT: SU(3): %6:gr32bit = LOCHIMux %6:gr32bit(tied-def 0), 1, 14, 8, implicit $cc
# CHECK-NEXT: SU(5): %3:addr32bit = OILMux %3:addr32bit(tied-def 0), 1, implicit-def dead $cc
-# CHECK-NEXT: SU(4): %7:gr32bit = NRK %6:gr32bit, %0:gr32bit, implicit-def dead $cc
# CHECK-NEXT: SU(6): %8:gr32bit = SLLK %1:gr32bit, %3:addr32bit, 0
+# CHECK-NEXT: SU(4): %7:gr32bit = NRK %6:gr32bit, %0:gr32bit, implicit-def dead $cc
# CHECK-NEXT: SU(7): CHIMux %7:gr32bit, 0, implicit-def $cc
# CHECK-NEXT: SU(8): %8:gr32bit = LOCHIMux %8:gr32bit(tied-def 0), 0, 14, 8, implicit $cc
# CHECK-NEXT: SU(9): %4:gr32bit = ORK %8:gr32bit, %4:gr32bit, implicit-def dead $cc
diff --git a/llvm/test/CodeGen/SystemZ/misched-prera-latencies.mir b/llvm/test/CodeGen/SystemZ/misched-prera-latencies.mir
index 974c959323ecf..8cc6aed65b1df 100644
--- a/llvm/test/CodeGen/SystemZ/misched-prera-latencies.mir
+++ b/llvm/test/CodeGen/SystemZ/misched-prera-latencies.mir
@@ -139,8 +139,8 @@ body: |
Return
...
-# The TMLL64 should be scheduled first even though the LA is available and of
-# lesser height, because the TMLL64 Depth equals the remaining latency (on CP).
+# The MSGFI should be scheduled first even though the LA is available and of
+# lesser height, because the MSGFI Depth equals the remaining latency (on CP).
# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: fun4:%bb.0
# CHECK: ********** MI Scheduling **********
@@ -152,20 +152,20 @@ body: |
# CHECK-NEXT: Latency : 1
# CHECK-NEXT: Depth : 0
# CHECK-NEXT: Height : 0
-# CHECK: SU(4): TMLL64 %5:gr64bit, 1, implicit-def $cc
-# CHECK-NEXT: # preds left : 1
+# CHECK: SU(4): dead %5:gr64bit = MSGFI %5:gr64bit(tied-def 0), 1
+# CHECK-NEXT: # preds left : 2
# CHECK-NEXT: # succs left : 1
# CHECK-NEXT: # rdefs left : 0
-# CHECK-NEXT: Latency : 1
+# CHECK-NEXT: Latency : 5
# CHECK-NEXT: Depth : 3
-# CHECK-NEXT: Height : 1
+# CHECK-NEXT: Height : 4
# CHECK: Queue BotQ.A: 0 4
# CHECK: *** Final schedule for %bb.1 ***
+# CHECK-NEXT: SU(0): dead %2:addr64bit = LA %0:addr64bit, 1, $noreg
# CHECK-NEXT: SU(1): %3:gr64bit = COPY %1:gr32bit
# CHECK-NEXT: SU(2): %4:gr64bit = COPY %3:gr64bit
# CHECK-NEXT: SU(3): %5:gr64bit = COPY %4:gr64bit
-# CHECK-NEXT: SU(0): dead %2:addr64bit = LA %0:addr64bit, 1, $noreg
-# CHECK-NEXT: SU(4): TMLL64 %5:gr64bit, 1, implicit-def $cc
+# CHECK-NEXT: SU(4): dead %5:gr64bit = MSGFI %5:gr64bit(tied-def 0), 1
---
name: fun4
tracksRegLiveness: true
@@ -181,8 +181,6 @@ body: |
%3:gr64bit = COPY %1
%4:gr64bit = COPY %3
%5:gr64bit = COPY %4
- TMLL64 %5, 1, implicit-def $cc
- BRC 15, 7, %bb.1, implicit killed $cc
+ %5:gr64bit = MSGFI %5, 1
Return
...
-
diff --git a/llvm/test/CodeGen/SystemZ/misched-prera-loads.mir b/llvm/test/CodeGen/SystemZ/misched-prera-loads.mir
index af38362fd199a..580cf423e2448 100644
--- a/llvm/test/CodeGen/SystemZ/misched-prera-loads.mir
+++ b/llvm/test/CodeGen/SystemZ/misched-prera-loads.mir
@@ -14,16 +14,16 @@
define void @fun6(ptr %Arg) { ret void }
...
-# The LHIMux could be scheduled below the CGHI to avoid the overlap of %0 and
+# The LHIMux could be scheduled below the CGHI to avoid the overlap of %1 and
# %3, but this is not done in small regions like this.
# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: fun0:%bb.0
# CHECK-NOT: Pick Bot REG-EXCESS [pre-RA]
# CHECK: *** Final schedule for %bb.0 ***
# CHECK-NEXT: SU(0): %0:gr64bit = COPY $r2d
+# CHECK-NEXT: SU(1): %1:gr32bit = LHIMux 1
# CHECK-NEXT: SU(2): %2:gr64bit = LCGR %0:gr64bit, implicit-def dead $cc
# CHECK-NEXT: SU(3): %3:gr64bit = RISBGN undef %3:gr64bit(tied-def 0), %2:gr64bit, 29, 188, 0
-# CHECK-NEXT: SU(1): %1:gr32bit = LHIMux 1
# CHECK-NEXT: SU(4): CGHI %3:gr64bit, 0, implicit-def $cc
# CHECK: fun0:%bb.1
---
@@ -171,7 +171,7 @@ body: |
# CHECK: Queue BotQ.A: 36 2
# CHECK-NOT: Cand SU(2) REG-EXCESS
# CHECK-NOT: Scheduling SU(2)
-# CHECK: Pick Bot BOT-HEIGHT [pre-RA]
+# CHECK: Pick Bot FIRST [pre-RA]
# CHECK-NEXT: Scheduling SU(36)
# CHECK: Queue BotQ.A: 2 32
# CHECK: Pick Bot REG-EXCESS [pre-RA]
@@ -242,8 +242,7 @@ body: |
# Check a case (AGR) where a use is tied to the def which means the register
# is live into the instruction and there is no point in scheduling it low
-# (pressure
diff is empty). It still ends up low in the final schedule due to
-# the latency reduction heuristic.
+# (pressure
diff is empty).
# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: fun3:%bb.0
#
@@ -259,14 +258,14 @@ body: |
#
# CHECK: Queue BotQ.A: 37 3
# CHECK: Scheduling SU(37)
-# CHECK: Queue BotQ.A: 3 36
-# CHECK: Pick Bot BOT-HEIGHT [pre-RA]
-# CHECK-NEXT: Scheduling SU(3)
+# CHECK-NOT: Pick Bot BOT-HEIGHT [pre-RA]
+# CHECK-NOT: Pick Bot REG-EXCESS [pre-RA]
#
# CHECK: *** Final schedule for %bb.0 ***
-# CHECK: SU(36): %35:gr64bit = AGFI %34:gr64bit(tied-def 0), 1, implicit-def dead $cc
+# CHECK-NEXT: SU(0): %0:gr64bit = COPY $r2d
+# CHECK-NEXT: SU(1): %1:gr64bit = COPY $r3d
+# CHECK-NEXT: SU(2): %2:gr64bit = COPY %1:gr64bit
# CHECK-NEXT: SU(3): %2:gr64bit = AGR %2:gr64bit(tied-def 0), %1:gr64bit, implicit-def dead $cc
-# CHECK-NEXT: SU(37): %36:gr64bit = AGFI %35:gr64bit(tied-def 0), 1, implicit-def dead $cc
# CHECK: fun3:%bb.1
---
name: fun3
@@ -439,39 +438,29 @@ body: |
# CHECK: ********** MI Scheduling **********
# CHECK-NEXT: fun5:%bb.0
#
-# CHECK: SU(30): %A0:gr64bit = AGRK %Z0:gr64bit, %Z0:gr64bit, implicit-def dead $cc
-# CHECK: Height : 1
-# CHECK: SU(31): %A1:gr64bit = AGRK %Z1:gr64bit, %Z1:gr64bit, implicit-def dead $cc
-# CHECK: Height : 1
-# CHECK: SU(32):
-# CHECK: SU(36): %A6:gr64bit = AGRK %A5:gr64bit, %Z0:gr64bit, implicit-def dead $cc
-# CHECK: Height : 1
-# CHECK: SU(37):
-# CHECK: SU(38): %A9:gr64bit = AGRK %A7:gr64bit, %A7:gr64bit, implicit-def dead $cc
-# CHECK: Height : 1
-# CHECK: SU(39):
-#
# CHECK: Queue BotQ.A: 27 38 36 34 33 32 31 30
-# CHECK: Pick Bot ORDER [pre-RA]
-# CHECK-NEXT: Scheduling SU(38)
+# CHECK: Scheduling SU(38)
# CHECK: Queue BotQ.A: 27 30 36 34 33 32 31 37
-# CHECK: Pick Bot BOT-HEIGHT [pre-RA]
-# CHECK-NEXT: Scheduling SU(36)
-# CHECK: Queue BotQ.A: 27 30 37 34 33 32 31 35
+# CHECK: Scheduling SU(37)
+# CHECK: Queue BotQ.A: 27 30 36 34 33 32 31
+# CHECK: Scheduling SU(36)
+# CHECK: Queue BotQ.A: 27 30 31 34 33 32 35
+# CHECK: Scheduling SU(35)
+# CHECK: Queue BotQ.A: 27 30 31 34 33 32
# CHECK: Pick Bot REG-EXCESS [pre-RA]
# CHECK-NEXT: Scheduling SU(30)
#
# CHECK: *** Final schedule for %bb.0 ***
-# CHECK: SU(28): %Z0:gr64bit = LGHI 1
-# CHECK-NEXT: SU(29): %Z1:gr64bit = LGHI 1
+# CHECK: SU(29): %Z1:gr64bit = LGHI 1
# CHECK-NEXT: SU(31): %A1:gr64bit = AGRK %Z1:gr64bit, %Z1:gr64bit, implicit-def dead $cc
# CHECK-NEXT: SU(32): %A2:gr64bit = AGRK %Z1:gr64bit, %Z1:gr64bit, implicit-def dead $cc
# CHECK-NEXT: SU(33): %A3:gr64bit = AGRK %Z1:gr64bit, %Z1:gr64bit, implicit-def dead $cc
-# CHECK-NEXT: SU(35): %A5:gr64bit = AGRK undef %F0:gr64bit, undef %F0:gr64bit, implicit-def dead $cc
-# CHECK-NEXT: SU(37): %A7:gr64bit = AGRK undef %F1:gr64bit, undef %F1:gr64bit, implicit-def dead $cc
# CHECK-NEXT: SU(34): %A4:gr64bit = AGRK %Z1:gr64bit, %Z1:gr64bit, implicit-def dead $cc
+# CHECK-NEXT: SU(28): %Z0:gr64bit = LGHI 1
# CHECK-NEXT: SU(30): %A0:gr64bit = AGRK %Z0:gr64bit, %Z0:gr64bit, implicit-def dead $cc
+# CHECK-NEXT: SU(35): %A5:gr64bit = AGRK undef %F0:gr64bit, undef %F0:gr64bit, implicit-def dead $cc
# CHECK-NEXT: SU(36): %A6:gr64bit = AGRK %A5:gr64bit, %Z0:gr64bit, implicit-def dead $cc
+# CHECK-NEXT: SU(37): %A7:gr64bit = AGRK undef %F1:gr64bit, undef %F1:gr64bit, implicit-def dead $cc
# CHECK-NEXT: SU(38): %A9:gr64bit = AGRK %A7:gr64bit, %A7:gr64bit, implicit-def dead $cc
# CHECK-NEXT: SU(39): STG %A0:gr64bit, $noreg, 0, $noreg :: (store (s64) into `ptr null`)
# CHECK-NEXT: SU(40): STG %A1:gr64bit, $noreg, 0, $noreg :: (store (s64) into `ptr null`)
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
index 7439b246b65b2..94547c471ed4a 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
@@ -26,8 +26,8 @@ body: |
; CHECK-LABEL: name: main
; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 43
; CHECK-NEXT: undef [[LGHI:%[0-9]+]].subreg_l32:gr64bit = MSR [[LGHI]].subreg_l32, [[LGHI]].subreg_l32
- ; CHECK-NEXT: [[LGHI:%[0-9]+]].subreg_l32:gr64bit = AHIMux [[LGHI]].subreg_l32, 9, implicit-def dead $cc
; CHECK-NEXT: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]].subreg_l32:gr64bit = AHIMux [[LGHI]].subreg_l32, 9, implicit-def dead $cc
; CHECK-NEXT: undef [[LGFI:%[0-9]+]].subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI]].subreg_l32
; CHECK-NEXT: [[LGFI:%[0-9]+]]:gr128bit = DLGR [[LGFI]], [[LGHI1]]
; CHECK-NEXT: Return implicit [[LGFI]]
diff --git a/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll b/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
index f8f1542096b15..ff9b6a34c1d53 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
+++ b/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
@@ -14,10 +14,10 @@
define void @main(i16 %in) {
; CHECK-LABEL: main:
; CHECK: # %bb.0:
-; CHECK-NEXT: lhr %r0, %r2
+; CHECK-NEXT: lhr %r2, %r2
; CHECK-NEXT: larl %r1, g_151
; CHECK-NEXT: lghi %r3, 0
-; CHECK-NEXT: chi %r0, 0
+; CHECK-NEXT: chi %r2, 0
; CHECK-NEXT: lhi %r0, 1
; CHECK-NEXT: locghile %r3, 1
; CHECK-NEXT: o %r0, 0(%r1)
diff --git a/llvm/test/CodeGen/SystemZ/risbg-04.ll b/llvm/test/CodeGen/SystemZ/risbg-04.ll
index c9f03b451d24a..ae7e780db334b 100644
--- a/llvm/test/CodeGen/SystemZ/risbg-04.ll
+++ b/llvm/test/CodeGen/SystemZ/risbg-04.ll
@@ -258,10 +258,9 @@ define i64 @f20(i64 %foo) {
define i32 @f21(i32 %foo, ptr %dest) {
; CHECK-LABEL: f21:
; CHECK: # %bb.0:
-; CHECK-NEXT: risblg %r0, %r2, 28, 158, 36
-; CHECK-NEXT: sra %r2, 28
-; CHECK-NEXT: st %r2, 0(%r3)
-; CHECK-NEXT: lr %r2, %r0
+; CHECK-NEXT: srak %r0, %r2, 28
+; CHECK-NEXT: risblg %r2, %r2, 28, 158, 36
+; CHECK-NEXT: st %r0, 0(%r3)
; CHECK-NEXT: br %r14
%shr = ashr i32 %foo, 28
store i32 %shr, ptr %dest
@@ -273,10 +272,9 @@ define i32 @f21(i32 %foo, ptr %dest) {
define i64 @f22(i64 %foo, ptr %dest) {
; CHECK-LABEL: f22:
; CHECK: # %bb.0:
-; CHECK-NEXT: risbg %r0, %r2, 60, 190, 4
-; CHECK-NEXT: srag %r1, %r2, 60
-; CHECK-NEXT: lgr %r2, %r0
-; CHECK-NEXT: stg %r1, 0(%r3)
+; CHECK-NEXT: srag %r0, %r2, 60
+; CHECK-NEXT: risbg %r2, %r2, 60, 190, 4
+; CHECK-NEXT: stg %r0, 0(%r3)
; CHECK-NEXT: br %r14
%shr = ashr i64 %foo, 60
store i64 %shr, ptr %dest
@@ -487,10 +485,9 @@ define i64 @f38(i64 %foo) {
define i64 @f39(i64 %foo, ptr %dest) {
; CHECK-LABEL: f39:
; CHECK: # %bb.0:
-; CHECK-NEXT: risbg %r0, %r2, 33, 189, 31
-; CHECK-NEXT: srag %r1, %r2, 35
-; CHECK-NEXT: lgr %r2, %r0
-; CHECK-NEXT: stg %r1, 0(%r3)
+; CHECK-NEXT: srag %r0, %r2, 35
+; CHECK-NEXT: risbg %r2, %r2, 33, 189, 31
+; CHECK-NEXT: stg %r0, 0(%r3)
; CHECK-NEXT: br %r14
%ashr = ashr i64 %foo, 35
store i64 %ashr, ptr %dest
diff --git a/llvm/test/CodeGen/SystemZ/rot-03.ll b/llvm/test/CodeGen/SystemZ/rot-03.ll
index 403ea976ebcea..8f42439dabdf8 100644
--- a/llvm/test/CodeGen/SystemZ/rot-03.ll
+++ b/llvm/test/CodeGen/SystemZ/rot-03.ll
@@ -8,10 +8,10 @@ define i128 @f1(i128 %val) {
; CHECK: # %bb.0:
; CHECK-NEXT: vl %v0, 0(%r3), 3
; CHECK-NEXT: vrepib %v1, 100
+; CHECK-NEXT: vsrlb %v2, %v0, %v1
+; CHECK-NEXT: vsrl %v1, %v2, %v1
; CHECK-NEXT: vrepib %v2, 28
-; CHECK-NEXT: vsrlb %v3, %v0, %v1
; CHECK-NEXT: vslb %v0, %v0, %v2
-; CHECK-NEXT: vsrl %v1, %v3, %v1
; CHECK-NEXT: vsl %v0, %v0, %v2
; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -47,19 +47,19 @@ define i128 @f3(i128 %val, i128 %amt) {
; CHECK-LABEL: f3:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vl %v0, 0(%r3), 3
; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vslb %v2, %v0, %v1
+; CHECK-NEXT: vsl %v1, %v2, %v1
+; CHECK-NEXT: vrepib %v2, 1
; CHECK-NEXT: xilf %r0, 4294967295
+; CHECK-NEXT: vsrl %v0, %v0, %v2
; CHECK-NEXT: vlvgp %v2, %r0, %r0
-; CHECK-NEXT: vrepib %v3, 1
-; CHECK-NEXT: vrepb %v1, %v1, 15
-; CHECK-NEXT: vsrl %v3, %v0, %v3
; CHECK-NEXT: vrepb %v2, %v2, 15
-; CHECK-NEXT: vslb %v0, %v0, %v1
-; CHECK-NEXT: vsrlb %v3, %v3, %v2
-; CHECK-NEXT: vsl %v0, %v0, %v1
-; CHECK-NEXT: vsrl %v1, %v3, %v2
-; CHECK-NEXT: vo %v0, %v0, %v1
+; CHECK-NEXT: vsrlb %v0, %v0, %v2
+; CHECK-NEXT: vsrl %v0, %v0, %v2
+; CHECK-NEXT: vo %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/shift-12.ll b/llvm/test/CodeGen/SystemZ/shift-12.ll
index f3858b28cd060..419caeebbbf9d 100644
--- a/llvm/test/CodeGen/SystemZ/shift-12.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-12.ll
@@ -122,11 +122,11 @@ define i32 @f10(i32 %a, i32 %sh) {
define i128 @f11(i128 %a, i32 %sh) {
; CHECK-LABEL: f11:
; CHECK: # %bb.0:
-; CHECK-NEXT: vlvgp %v0, %r4, %r4
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vslb %v1, %v1, %v0
-; CHECK-NEXT: vsl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r4, %r4
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vslb %v0, %v0, %v1
+; CHECK-NEXT: vsl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i32 %sh, 127
@@ -138,11 +138,11 @@ define i128 @f11(i128 %a, i32 %sh) {
define i128 @f12(i128 %a, i32 %sh) {
; CHECK-LABEL: f12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vlvgp %v0, %r4, %r4
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrlb %v1, %v1, %v0
-; CHECK-NEXT: vsrl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r4, %r4
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrlb %v0, %v0, %v1
+; CHECK-NEXT: vsrl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i32 %sh, 127
@@ -154,11 +154,11 @@ define i128 @f12(i128 %a, i32 %sh) {
define i128 @f13(i128 %a, i32 %sh) {
; CHECK-LABEL: f13:
; CHECK: # %bb.0:
-; CHECK-NEXT: vlvgp %v0, %r4, %r4
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrab %v1, %v1, %v0
-; CHECK-NEXT: vsra %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r4, %r4
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrab %v0, %v0, %v1
+; CHECK-NEXT: vsra %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i32 %sh, 127
diff --git a/llvm/test/CodeGen/SystemZ/shift-13.ll b/llvm/test/CodeGen/SystemZ/shift-13.ll
index 0ba08b34c48c8..e214a18861172 100644
--- a/llvm/test/CodeGen/SystemZ/shift-13.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-13.ll
@@ -48,11 +48,11 @@ define i128 @f4(i128 %a, i128 %sh) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vslb %v1, %v1, %v0
-; CHECK-NEXT: vsl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vslb %v0, %v0, %v1
+; CHECK-NEXT: vsl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%res = shl i128 %a, %sh
@@ -64,11 +64,11 @@ define i128 @f5(i128 %a, i128 %sh) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vslb %v1, %v1, %v0
-; CHECK-NEXT: vsl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vslb %v0, %v0, %v1
+; CHECK-NEXT: vsl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 127
@@ -81,11 +81,11 @@ define i128 @f6(i128 %a, i128 %sh) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vslb %v1, %v1, %v0
-; CHECK-NEXT: vsl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vslb %v0, %v0, %v1
+; CHECK-NEXT: vsl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 511
@@ -99,11 +99,11 @@ define i128 @f7(i128 %a, i128 %sh) {
; CHECK: # %bb.0:
; CHECK-NEXT: lhi %r0, 63
; CHECK-NEXT: n %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vslb %v1, %v1, %v0
-; CHECK-NEXT: vsl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vslb %v0, %v0, %v1
+; CHECK-NEXT: vsl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 63
@@ -115,15 +115,15 @@ define i128 @f7(i128 %a, i128 %sh) {
define i128 @f8(i128 %a, i128 %b, i128 %sh) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r5), 3
-; CHECK-NEXT: vn %v0, %v1, %v0
-; CHECK-NEXT: vlgvf %r0, %v0, 3
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vslb %v1, %v1, %v0
-; CHECK-NEXT: vsl %v0, %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r5), 3
+; CHECK-NEXT: vn %v1, %v2, %v1
+; CHECK-NEXT: vlgvf %r0, %v1, 3
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vslb %v0, %v0, %v1
+; CHECK-NEXT: vsl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, %b
@@ -136,16 +136,16 @@ define i128 @f9(i128 %a, i128 %sh) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI8_0
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r1), 3
-; CHECK-NEXT: vn %v0, %v0, %v1
-; CHECK-NEXT: vlgvf %r0, %v0, 3
-; CHECK-NEXT: vlvgp %v1, %r0, %r0
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vrepb %v1, %v1, 15
-; CHECK-NEXT: vslb %v2, %v2, %v1
-; CHECK-NEXT: vsl %v1, %v2, %v1
-; CHECK-NEXT: vaq %v0, %v0, %v1
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r1), 3
+; CHECK-NEXT: vn %v1, %v1, %v2
+; CHECK-NEXT: vlgvf %r0, %v1, 3
+; CHECK-NEXT: vlvgp %v2, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v2, %v2, 15
+; CHECK-NEXT: vslb %v0, %v0, %v2
+; CHECK-NEXT: vsl %v0, %v0, %v2
+; CHECK-NEXT: vaq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 127
diff --git a/llvm/test/CodeGen/SystemZ/shift-14.ll b/llvm/test/CodeGen/SystemZ/shift-14.ll
index 321bbf3e6d478..e45126043f273 100644
--- a/llvm/test/CodeGen/SystemZ/shift-14.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-14.ll
@@ -48,11 +48,11 @@ define i128 @f4(i128 %a, i128 %sh) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrlb %v1, %v1, %v0
-; CHECK-NEXT: vsrl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrlb %v0, %v0, %v1
+; CHECK-NEXT: vsrl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%res = lshr i128 %a, %sh
@@ -64,11 +64,11 @@ define i128 @f5(i128 %a, i128 %sh) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrlb %v1, %v1, %v0
-; CHECK-NEXT: vsrl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrlb %v0, %v0, %v1
+; CHECK-NEXT: vsrl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 127
@@ -81,11 +81,11 @@ define i128 @f6(i128 %a, i128 %sh) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrlb %v1, %v1, %v0
-; CHECK-NEXT: vsrl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrlb %v0, %v0, %v1
+; CHECK-NEXT: vsrl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 511
@@ -99,11 +99,11 @@ define i128 @f7(i128 %a, i128 %sh) {
; CHECK: # %bb.0:
; CHECK-NEXT: lhi %r0, 63
; CHECK-NEXT: n %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrlb %v1, %v1, %v0
-; CHECK-NEXT: vsrl %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrlb %v0, %v0, %v1
+; CHECK-NEXT: vsrl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 63
@@ -115,15 +115,15 @@ define i128 @f7(i128 %a, i128 %sh) {
define i128 @f8(i128 %a, i128 %b, i128 %sh) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r5), 3
-; CHECK-NEXT: vn %v0, %v1, %v0
-; CHECK-NEXT: vlgvf %r0, %v0, 3
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrlb %v1, %v1, %v0
-; CHECK-NEXT: vsrl %v0, %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r5), 3
+; CHECK-NEXT: vn %v1, %v2, %v1
+; CHECK-NEXT: vlgvf %r0, %v1, 3
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrlb %v0, %v0, %v1
+; CHECK-NEXT: vsrl %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, %b
@@ -136,16 +136,16 @@ define i128 @f9(i128 %a, i128 %sh) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI8_0
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r1), 3
-; CHECK-NEXT: vn %v0, %v0, %v1
-; CHECK-NEXT: vlgvf %r0, %v0, 3
-; CHECK-NEXT: vlvgp %v1, %r0, %r0
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vrepb %v1, %v1, 15
-; CHECK-NEXT: vsrlb %v2, %v2, %v1
-; CHECK-NEXT: vsrl %v1, %v2, %v1
-; CHECK-NEXT: vaq %v0, %v0, %v1
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r1), 3
+; CHECK-NEXT: vn %v1, %v1, %v2
+; CHECK-NEXT: vlgvf %r0, %v1, 3
+; CHECK-NEXT: vlvgp %v2, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v2, %v2, 15
+; CHECK-NEXT: vsrlb %v0, %v0, %v2
+; CHECK-NEXT: vsrl %v0, %v0, %v2
+; CHECK-NEXT: vaq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 127
diff --git a/llvm/test/CodeGen/SystemZ/shift-15.ll b/llvm/test/CodeGen/SystemZ/shift-15.ll
index 6c32a39471efc..e21d05c4c91c8 100644
--- a/llvm/test/CodeGen/SystemZ/shift-15.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-15.ll
@@ -48,11 +48,11 @@ define i128 @f4(i128 %a, i128 %sh) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrab %v1, %v1, %v0
-; CHECK-NEXT: vsra %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrab %v0, %v0, %v1
+; CHECK-NEXT: vsra %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%res = ashr i128 %a, %sh
@@ -64,11 +64,11 @@ define i128 @f5(i128 %a, i128 %sh) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrab %v1, %v1, %v0
-; CHECK-NEXT: vsra %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrab %v0, %v0, %v1
+; CHECK-NEXT: vsra %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 127
@@ -81,11 +81,11 @@ define i128 @f6(i128 %a, i128 %sh) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrab %v1, %v1, %v0
-; CHECK-NEXT: vsra %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrab %v0, %v0, %v1
+; CHECK-NEXT: vsra %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 511
@@ -99,11 +99,11 @@ define i128 @f7(i128 %a, i128 %sh) {
; CHECK: # %bb.0:
; CHECK-NEXT: lhi %r0, 63
; CHECK-NEXT: n %r0, 12(%r4)
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrab %v1, %v1, %v0
-; CHECK-NEXT: vsra %v0, %v1, %v0
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrab %v0, %v0, %v1
+; CHECK-NEXT: vsra %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 63
@@ -115,15 +115,15 @@ define i128 @f7(i128 %a, i128 %sh) {
define i128 @f8(i128 %a, i128 %b, i128 %sh) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r5), 3
-; CHECK-NEXT: vn %v0, %v1, %v0
-; CHECK-NEXT: vlgvf %r0, %v0, 3
-; CHECK-NEXT: vlvgp %v0, %r0, %r0
-; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vrepb %v0, %v0, 15
-; CHECK-NEXT: vsrab %v1, %v1, %v0
-; CHECK-NEXT: vsra %v0, %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r5), 3
+; CHECK-NEXT: vn %v1, %v2, %v1
+; CHECK-NEXT: vlgvf %r0, %v1, 3
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v1, %v1, 15
+; CHECK-NEXT: vsrab %v0, %v0, %v1
+; CHECK-NEXT: vsra %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, %b
@@ -136,16 +136,16 @@ define i128 @f9(i128 %a, i128 %sh) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI8_0
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r1), 3
-; CHECK-NEXT: vn %v0, %v0, %v1
-; CHECK-NEXT: vlgvf %r0, %v0, 3
-; CHECK-NEXT: vlvgp %v1, %r0, %r0
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vrepb %v1, %v1, 15
-; CHECK-NEXT: vsrab %v2, %v2, %v1
-; CHECK-NEXT: vsra %v1, %v2, %v1
-; CHECK-NEXT: vaq %v0, %v0, %v1
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r1), 3
+; CHECK-NEXT: vn %v1, %v1, %v2
+; CHECK-NEXT: vlgvf %r0, %v1, 3
+; CHECK-NEXT: vlvgp %v2, %r0, %r0
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vrepb %v2, %v2, 15
+; CHECK-NEXT: vsrab %v0, %v0, %v2
+; CHECK-NEXT: vsra %v0, %v0, %v2
+; CHECK-NEXT: vaq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%and = and i128 %sh, 127
diff --git a/llvm/test/CodeGen/SystemZ/shift-16.ll b/llvm/test/CodeGen/SystemZ/shift-16.ll
index 68cd908c80a42..d81c3546998be 100644
--- a/llvm/test/CodeGen/SystemZ/shift-16.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-16.ll
@@ -7,26 +7,26 @@
define i256 @f1(i256 %a, i256 %sh) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: l %r0, 28(%r4)
; CHECK-NEXT: vl %v1, 16(%r3), 3
; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: l %r0, 28(%r4)
; CHECK-NEXT: clijhe %r0, 128, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lr %r1, %r0
; CHECK-NEXT: xilf %r1, 4294967295
; CHECK-NEXT: vlvgp %v2, %r0, %r0
-; CHECK-NEXT: vlvgp %v3, %r1, %r1
+; CHECK-NEXT: vlvgp %v5, %r1, %r1
; CHECK-NEXT: vrepib %v4, 1
-; CHECK-NEXT: vrepb %v5, %v2, 15
-; CHECK-NEXT: vsrl %v2, %v1, %v4
-; CHECK-NEXT: vrepb %v3, %v3, 15
-; CHECK-NEXT: vslb %v4, %v0, %v5
-; CHECK-NEXT: vsrlb %v2, %v2, %v3
-; CHECK-NEXT: vslb %v1, %v1, %v5
-; CHECK-NEXT: vsl %v4, %v4, %v5
-; CHECK-NEXT: vsrl %v2, %v2, %v3
-; CHECK-NEXT: vo %v2, %v4, %v2
-; CHECK-NEXT: vsl %v1, %v1, %v5
+; CHECK-NEXT: vrepb %v3, %v2, 15
+; CHECK-NEXT: vsrl %v4, %v1, %v4
+; CHECK-NEXT: vrepb %v5, %v5, 15
+; CHECK-NEXT: vslb %v2, %v0, %v3
+; CHECK-NEXT: vsrlb %v4, %v4, %v5
+; CHECK-NEXT: vslb %v1, %v1, %v3
+; CHECK-NEXT: vsl %v2, %v2, %v3
+; CHECK-NEXT: vsrl %v4, %v4, %v5
+; CHECK-NEXT: vo %v2, %v2, %v4
+; CHECK-NEXT: vsl %v1, %v1, %v3
; CHECK-NEXT: cijlh %r0, 0, .LBB0_3
; CHECK-NEXT: j .LBB0_4
; CHECK-NEXT: .LBB0_2:
@@ -51,26 +51,26 @@ define i256 @f1(i256 %a, i256 %sh) {
define i256 @f2(i256 %a, i256 %sh) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
-; CHECK-NEXT: l %r0, 28(%r4)
; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vl %v0, 16(%r3), 3
+; CHECK-NEXT: l %r0, 28(%r4)
; CHECK-NEXT: clijhe %r0, 128, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lr %r1, %r0
; CHECK-NEXT: xilf %r1, 4294967295
; CHECK-NEXT: vlvgp %v2, %r0, %r0
-; CHECK-NEXT: vlvgp %v3, %r1, %r1
+; CHECK-NEXT: vlvgp %v5, %r1, %r1
; CHECK-NEXT: vrepib %v4, 1
-; CHECK-NEXT: vrepb %v5, %v2, 15
-; CHECK-NEXT: vsl %v2, %v1, %v4
-; CHECK-NEXT: vrepb %v3, %v3, 15
-; CHECK-NEXT: vsrlb %v4, %v0, %v5
-; CHECK-NEXT: vslb %v2, %v2, %v3
-; CHECK-NEXT: vsrlb %v1, %v1, %v5
-; CHECK-NEXT: vsrl %v4, %v4, %v5
-; CHECK-NEXT: vsl %v2, %v2, %v3
-; CHECK-NEXT: vo %v2, %v2, %v4
-; CHECK-NEXT: vsrl %v1, %v1, %v5
+; CHECK-NEXT: vrepb %v3, %v2, 15
+; CHECK-NEXT: vsl %v4, %v1, %v4
+; CHECK-NEXT: vrepb %v5, %v5, 15
+; CHECK-NEXT: vsrlb %v2, %v0, %v3
+; CHECK-NEXT: vslb %v4, %v4, %v5
+; CHECK-NEXT: vsrlb %v1, %v1, %v3
+; CHECK-NEXT: vsrl %v2, %v2, %v3
+; CHECK-NEXT: vsl %v4, %v4, %v5
+; CHECK-NEXT: vo %v2, %v4, %v2
+; CHECK-NEXT: vsrl %v1, %v1, %v3
; CHECK-NEXT: cijlh %r0, 0, .LBB1_3
; CHECK-NEXT: j .LBB1_4
; CHECK-NEXT: .LBB1_2:
@@ -95,37 +95,37 @@ define i256 @f2(i256 %a, i256 %sh) {
define i256 @f3(i256 %a, i256 %sh) {
; CHECK-LABEL: f3:
; CHECK: # %bb.0:
-; CHECK-NEXT: l %r0, 28(%r4)
; CHECK-NEXT: vl %v0, 16(%r3), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: l %r0, 28(%r4)
+; CHECK-NEXT: vl %v2, 0(%r3), 3
; CHECK-NEXT: clijhe %r0, 128, .LBB2_2
; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vrepb %v3, %v1, 15
+; CHECK-NEXT: vsrab %v1, %v2, %v3
+; CHECK-NEXT: vsrlb %v4, %v0, %v3
+; CHECK-NEXT: vsra %v1, %v1, %v3
; CHECK-NEXT: lr %r1, %r0
-; CHECK-NEXT: xilf %r1, 4294967295
-; CHECK-NEXT: vlvgp %v2, %r0, %r0
-; CHECK-NEXT: vlvgp %v3, %r1, %r1
+; CHECK-NEXT: vsrl %v3, %v4, %v3
; CHECK-NEXT: vrepib %v4, 1
-; CHECK-NEXT: vrepb %v2, %v2, 15
-; CHECK-NEXT: vsl %v4, %v1, %v4
-; CHECK-NEXT: vrepb %v3, %v3, 15
-; CHECK-NEXT: vsrlb %v5, %v0, %v2
-; CHECK-NEXT: vslb %v4, %v4, %v3
-; CHECK-NEXT: vsrab %v1, %v1, %v2
-; CHECK-NEXT: vsrl %v5, %v5, %v2
-; CHECK-NEXT: vsl %v3, %v4, %v3
-; CHECK-NEXT: vsra %v1, %v1, %v2
-; CHECK-NEXT: vo %v2, %v3, %v5
+; CHECK-NEXT: xilf %r1, 4294967295
+; CHECK-NEXT: vsl %v2, %v2, %v4
+; CHECK-NEXT: vlvgp %v4, %r1, %r1
+; CHECK-NEXT: vrepb %v4, %v4, 15
+; CHECK-NEXT: vslb %v2, %v2, %v4
+; CHECK-NEXT: vsl %v2, %v2, %v4
+; CHECK-NEXT: vo %v2, %v2, %v3
; CHECK-NEXT: cijlh %r0, 0, .LBB2_3
; CHECK-NEXT: j .LBB2_4
; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: vrepib %v1, 127
+; CHECK-NEXT: vsrab %v3, %v2, %v1
; CHECK-NEXT: ahik %r1, %r0, -128
-; CHECK-NEXT: vlvgp %v2, %r1, %r1
-; CHECK-NEXT: vrepib %v3, 127
-; CHECK-NEXT: vrepb %v2, %v2, 15
-; CHECK-NEXT: vsrab %v4, %v1, %v3
-; CHECK-NEXT: vsrab %v5, %v1, %v2
-; CHECK-NEXT: vsra %v1, %v4, %v3
-; CHECK-NEXT: vsra %v2, %v5, %v2
+; CHECK-NEXT: vsra %v1, %v3, %v1
+; CHECK-NEXT: vlvgp %v3, %r1, %r1
+; CHECK-NEXT: vrepb %v3, %v3, 15
+; CHECK-NEXT: vsrab %v2, %v2, %v3
+; CHECK-NEXT: vsra %v2, %v2, %v3
; CHECK-NEXT: cije %r0, 0, .LBB2_4
; CHECK-NEXT: .LBB2_3:
; CHECK-NEXT: vlr %v0, %v2
diff --git a/llvm/test/CodeGen/SystemZ/shift-17.ll b/llvm/test/CodeGen/SystemZ/shift-17.ll
index 474b1a9230c77..8f5f9abd0540b 100644
--- a/llvm/test/CodeGen/SystemZ/shift-17.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-17.ll
@@ -32,14 +32,14 @@ define i128 @f1(i128 %a, i128 %b) {
define i128 @f2(i128 %a, i128 %b) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vrepib %v1, 123
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vsrlb %v0, %v0, %v1
-; CHECK-NEXT: vrepib %v3, 5
-; CHECK-NEXT: vsl %v2, %v2, %v3
-; CHECK-NEXT: vsrl %v0, %v0, %v1
-; CHECK-NEXT: vo %v0, %v2, %v0
+; CHECK-NEXT: vrepib %v2, 5
+; CHECK-NEXT: vsl %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v2, 123
+; CHECK-NEXT: vsrlb %v0, %v0, %v2
+; CHECK-NEXT: vsrl %v0, %v0, %v2
+; CHECK-NEXT: vo %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
;
@@ -58,14 +58,14 @@ define i128 @f2(i128 %a, i128 %b) {
define i128 @f3(i128 %a, i128 %b) {
; CHECK-LABEL: f3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vrepib %v2, 86
-; CHECK-NEXT: vrepib %v3, 42
; CHECK-NEXT: vsrlb %v1, %v1, %v2
-; CHECK-NEXT: vslb %v0, %v0, %v3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
; CHECK-NEXT: vsrl %v1, %v1, %v2
-; CHECK-NEXT: vsl %v0, %v0, %v3
+; CHECK-NEXT: vrepib %v2, 42
+; CHECK-NEXT: vslb %v0, %v0, %v2
+; CHECK-NEXT: vsl %v0, %v0, %v2
; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -88,18 +88,18 @@ define i128 @f4(i128 %a, i128 %b, i128 %sh) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r5)
+; CHECK-NEXT: vlvgp %v2, %r0, %r0
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vrepb %v2, %v2, 15
+; CHECK-NEXT: vslb %v1, %v1, %v2
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vsl %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v2, 1
; CHECK-NEXT: xilf %r0, 4294967295
+; CHECK-NEXT: vsrl %v0, %v0, %v2
; CHECK-NEXT: vlvgp %v2, %r0, %r0
-; CHECK-NEXT: vl %v3, 0(%r3), 3
-; CHECK-NEXT: vrepib %v4, 1
-; CHECK-NEXT: vrepb %v1, %v1, 15
-; CHECK-NEXT: vsrl %v0, %v0, %v4
; CHECK-NEXT: vrepb %v2, %v2, 15
-; CHECK-NEXT: vslb %v3, %v3, %v1
; CHECK-NEXT: vsrlb %v0, %v0, %v2
-; CHECK-NEXT: vsl %v1, %v3, %v1
; CHECK-NEXT: vsrl %v0, %v0, %v2
; CHECK-NEXT: vo %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -108,18 +108,18 @@ define i128 @f4(i128 %a, i128 %b, i128 %sh) {
; Z15-LABEL: f4:
; Z15: # %bb.0:
; Z15-NEXT: l %r0, 12(%r5)
+; Z15-NEXT: vlvgp %v2, %r0, %r0
+; Z15-NEXT: vl %v1, 0(%r3), 3
+; Z15-NEXT: vrepb %v2, %v2, 15
; Z15-NEXT: vl %v0, 0(%r4), 3
-; Z15-NEXT: vlvgp %v1, %r0, %r0
+; Z15-NEXT: vslb %v1, %v1, %v2
+; Z15-NEXT: vsl %v1, %v1, %v2
+; Z15-NEXT: vrepib %v2, 1
; Z15-NEXT: xilf %r0, 4294967295
+; Z15-NEXT: vsrl %v0, %v0, %v2
; Z15-NEXT: vlvgp %v2, %r0, %r0
-; Z15-NEXT: vl %v3, 0(%r3), 3
-; Z15-NEXT: vrepib %v4, 1
-; Z15-NEXT: vrepb %v1, %v1, 15
-; Z15-NEXT: vsrl %v0, %v0, %v4
; Z15-NEXT: vrepb %v2, %v2, 15
-; Z15-NEXT: vslb %v3, %v3, %v1
; Z15-NEXT: vsrlb %v0, %v0, %v2
-; Z15-NEXT: vsl %v1, %v3, %v1
; Z15-NEXT: vsrl %v0, %v0, %v2
; Z15-NEXT: vo %v0, %v1, %v0
; Z15-NEXT: vst %v0, 0(%r2), 3
@@ -153,14 +153,14 @@ define i128 @f5(i128 %a, i128 %b) {
define i128 @f6(i128 %a, i128 %b) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vrepib %v1, 123
-; CHECK-NEXT: vl %v2, 0(%r4), 3
-; CHECK-NEXT: vslb %v0, %v0, %v1
-; CHECK-NEXT: vrepib %v3, 5
-; CHECK-NEXT: vsrl %v2, %v2, %v3
-; CHECK-NEXT: vsl %v0, %v0, %v1
-; CHECK-NEXT: vo %v0, %v0, %v2
+; CHECK-NEXT: vrepib %v2, 5
+; CHECK-NEXT: vsrl %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v2, 123
+; CHECK-NEXT: vslb %v0, %v0, %v2
+; CHECK-NEXT: vsl %v0, %v0, %v2
+; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
;
@@ -179,14 +179,14 @@ define i128 @f6(i128 %a, i128 %b) {
define i128 @f7(i128 %a, i128 %b) {
; CHECK-LABEL: f7:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vrepib %v2, 42
-; CHECK-NEXT: vrepib %v3, 86
; CHECK-NEXT: vsrlb %v1, %v1, %v2
-; CHECK-NEXT: vslb %v0, %v0, %v3
+; CHECK-NEXT: vl %v0, 0(%r3), 3
; CHECK-NEXT: vsrl %v1, %v1, %v2
-; CHECK-NEXT: vsl %v0, %v0, %v3
+; CHECK-NEXT: vrepib %v2, 86
+; CHECK-NEXT: vslb %v0, %v0, %v2
+; CHECK-NEXT: vsl %v0, %v0, %v2
; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
@@ -209,18 +209,18 @@ define i128 @f8(i128 %a, i128 %b, i128 %sh) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0:
; CHECK-NEXT: l %r0, 12(%r5)
+; CHECK-NEXT: vlvgp %v2, %r0, %r0
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vrepb %v2, %v2, 15
+; CHECK-NEXT: vsrlb %v1, %v1, %v2
; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vsrl %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v2, 1
; CHECK-NEXT: xilf %r0, 4294967295
+; CHECK-NEXT: vsl %v0, %v0, %v2
; CHECK-NEXT: vlvgp %v2, %r0, %r0
-; CHECK-NEXT: vl %v3, 0(%r4), 3
-; CHECK-NEXT: vrepib %v4, 1
-; CHECK-NEXT: vrepb %v1, %v1, 15
-; CHECK-NEXT: vsl %v0, %v0, %v4
; CHECK-NEXT: vrepb %v2, %v2, 15
-; CHECK-NEXT: vsrlb %v3, %v3, %v1
; CHECK-NEXT: vslb %v0, %v0, %v2
-; CHECK-NEXT: vsrl %v1, %v3, %v1
; CHECK-NEXT: vsl %v0, %v0, %v2
; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -229,18 +229,18 @@ define i128 @f8(i128 %a, i128 %b, i128 %sh) {
; Z15-LABEL: f8:
; Z15: # %bb.0:
; Z15-NEXT: l %r0, 12(%r5)
+; Z15-NEXT: vlvgp %v2, %r0, %r0
+; Z15-NEXT: vl %v1, 0(%r4), 3
+; Z15-NEXT: vrepb %v2, %v2, 15
; Z15-NEXT: vl %v0, 0(%r3), 3
-; Z15-NEXT: vlvgp %v1, %r0, %r0
+; Z15-NEXT: vsrlb %v1, %v1, %v2
+; Z15-NEXT: vsrl %v1, %v1, %v2
+; Z15-NEXT: vrepib %v2, 1
; Z15-NEXT: xilf %r0, 4294967295
+; Z15-NEXT: vsl %v0, %v0, %v2
; Z15-NEXT: vlvgp %v2, %r0, %r0
-; Z15-NEXT: vl %v3, 0(%r4), 3
-; Z15-NEXT: vrepib %v4, 1
-; Z15-NEXT: vrepb %v1, %v1, 15
-; Z15-NEXT: vsl %v0, %v0, %v4
; Z15-NEXT: vrepb %v2, %v2, 15
-; Z15-NEXT: vsrlb %v3, %v3, %v1
; Z15-NEXT: vslb %v0, %v0, %v2
-; Z15-NEXT: vsrl %v1, %v3, %v1
; Z15-NEXT: vsl %v0, %v0, %v2
; Z15-NEXT: vo %v0, %v0, %v1
; Z15-NEXT: vst %v0, 0(%r2), 3
@@ -253,14 +253,14 @@ define i128 @f8(i128 %a, i128 %b, i128 %sh) {
define i128 @f9(i128 %a, i128 %b) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vrepib %v1, 123
-; CHECK-NEXT: vl %v2, 0(%r4), 3
-; CHECK-NEXT: vslb %v0, %v0, %v1
-; CHECK-NEXT: vrepib %v3, 5
-; CHECK-NEXT: vsrl %v2, %v2, %v3
-; CHECK-NEXT: vsl %v0, %v0, %v1
-; CHECK-NEXT: vo %v0, %v0, %v2
+; CHECK-NEXT: vrepib %v2, 5
+; CHECK-NEXT: vsrl %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v2, 123
+; CHECK-NEXT: vslb %v0, %v0, %v2
+; CHECK-NEXT: vsl %v0, %v0, %v2
+; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
;
@@ -279,14 +279,14 @@ define i128 @f9(i128 %a, i128 %b) {
define i128 @f10(i128 %a, i128 %b) {
; CHECK-LABEL: f10:
; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vrepib %v1, 123
-; CHECK-NEXT: vl %v2, 0(%r3), 3
-; CHECK-NEXT: vsrlb %v0, %v0, %v1
-; CHECK-NEXT: vrepib %v3, 5
-; CHECK-NEXT: vsl %v2, %v2, %v3
-; CHECK-NEXT: vsrl %v0, %v0, %v1
-; CHECK-NEXT: vo %v0, %v2, %v0
+; CHECK-NEXT: vrepib %v2, 5
+; CHECK-NEXT: vsl %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v2, 123
+; CHECK-NEXT: vsrlb %v0, %v0, %v2
+; CHECK-NEXT: vsrl %v0, %v0, %v2
+; CHECK-NEXT: vo %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
;
diff --git a/llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll b/llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll
index 8682df6b99d04..4ad7e33ea2d82 100644
--- a/llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll
+++ b/llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll
@@ -65,9 +65,9 @@ define <4 x i32> @f3() {
; CHECK-LABEL: f3:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI3_0
-; CHECK-NEXT: larl %r2, .LCPI3_1
; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-NEXT: larl %r1, .LCPI3_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
; CHECK-NEXT: vpklsgs %v24, %v1, %v0
; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> <i64 0, i64 1>, <2 x i64> <i64 1, i64 0>)
@@ -119,9 +119,9 @@ define <4 x i32> @f6() {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI6_0
-; CHECK-NEXT: larl %r2, .LCPI6_1
; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-NEXT: larl %r1, .LCPI6_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
; CHECK-NEXT: vpksg %v24, %v1, %v0
; CHECK-NEXT: br %r14
%call = call <4 x i32> @llvm.s390.vpksg(<2 x i64> <i64 0, i64 1>, <2 x i64> <i64 1, i64 0>)
@@ -170,9 +170,9 @@ define <4 x i32> @f9() {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI9_0
-; CHECK-NEXT: larl %r2, .LCPI9_1
; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-NEXT: larl %r1, .LCPI9_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
; CHECK-NEXT: vpklsg %v24, %v1, %v0
; CHECK-NEXT: br %r14
%call = call <4 x i32> @llvm.s390.vpklsg(<2 x i64> <i64 0, i64 1>, <2 x i64> <i64 1, i64 0>)
@@ -219,9 +219,9 @@ define <2 x i64> @f12() {
; CHECK-LABEL: f12:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI12_0
-; CHECK-NEXT: larl %r2, .LCPI12_1
; CHECK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-NEXT: larl %r1, .LCPI12_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
; CHECK-NEXT: vpdi %v24, %v1, %v0, 0
; CHECK-NEXT: br %r14
%perm = call <2 x i64> @llvm.s390.vpdi(<2 x i64> <i64 0, i64 1>,
diff --git a/llvm/test/CodeGen/SystemZ/soft-float-args.ll b/llvm/test/CodeGen/SystemZ/soft-float-args.ll
index 542c61b27ace0..06b362672b1f6 100644
--- a/llvm/test/CodeGen/SystemZ/soft-float-args.ll
+++ b/llvm/test/CodeGen/SystemZ/soft-float-args.ll
@@ -56,9 +56,8 @@ define fp128 @f2_fp128(fp128 %arg) {
define <2 x double> @f3(<2 x double> %arg) {
; CHECK-LABEL: f3:
; CHECK-NOT: %{{[fv]}}
-; CHECK: lg %r0, 0(%r2)
-; CHECK-NEXT: lg %r13, 8(%r2)
-; CHECK-NEXT: lgr %r2, %r0
+; CHECK: lg %r13, 8(%r2)
+; CHECK-NEXT: lg %r2, 0(%r2)
; CHECK-NEXT: llihh %r3, 16368
; CHECK-NEXT: brasl %r14, __adddf3 at PLT
; CHECK-NEXT: lgr %r12, %r2
@@ -157,11 +156,10 @@ define <2 x double> @f9(<2 x double> %A, <2 x double> %B, <2 x double> %C,
; CHECK: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: lg %r1, 344(%r15)
-; CHECK-NEXT: lg %r0, 0(%r2)
-; CHECK-NEXT: lg %r3, 0(%r1)
; CHECK-NEXT: lg %r13, 8(%r2)
+; CHECK-NEXT: lg %r2, 0(%r2)
+; CHECK-NEXT: lg %r3, 0(%r1)
; CHECK-NEXT: lg %r12, 8(%r1)
-; CHECK-NEXT: lgr %r2, %r0
; CHECK-NEXT: brasl %r14, __adddf3 at PLT
; CHECK-NEXT: lgr %r11, %r2
; CHECK-NEXT: lgr %r2, %r13
diff --git a/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll b/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
index 4f2ec35868af7..f7bbad9055afd 100644
--- a/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
+++ b/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
@@ -5,34 +5,34 @@
define void @fun0(<4 x i31> %src, ptr %p)
; CHECK-LABEL: fun0:
; CHECK: # %bb.0:
+; CHECK-NEXT: vlgvf %r0, %v24, 0
+; CHECK-NEXT: vlvgp %v0, %r0, %r0
+; CHECK-NEXT: vrepib %v1, 93
; CHECK-NEXT: vlgvf %r0, %v24, 1
-; CHECK-NEXT: vlgvf %r1, %v24, 0
-; CHECK-NEXT: larl %r3, .LCPI0_0
-; CHECK-NEXT: vlgvf %r4, %v24, 2
-; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vslb %v0, %v0, %v1
+; CHECK-NEXT: larl %r1, .LCPI0_0
+; CHECK-NEXT: vl %v2, 0(%r1), 3
+; CHECK-NEXT: vsl %v0, %v0, %v1
; CHECK-NEXT: vlvgp %v1, %r0, %r0
-; CHECK-NEXT: vlvgp %v2, %r1, %r1
-; CHECK-NEXT: vlvgp %v3, %r4, %r4
-; CHECK-NEXT: vrepib %v4, 93
-; CHECK-NEXT: vn %v1, %v1, %v0
-; CHECK-NEXT: vrepib %v5, 62
-; CHECK-NEXT: vslb %v2, %v2, %v4
-; CHECK-NEXT: vslb %v1, %v1, %v5
-; CHECK-NEXT: vn %v3, %v3, %v0
-; CHECK-NEXT: vrepib %v6, 31
+; CHECK-NEXT: vn %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v3, 62
+; CHECK-NEXT: vslb %v1, %v1, %v3
+; CHECK-NEXT: vlgvf %r0, %v24, 2
+; CHECK-NEXT: vsl %v1, %v1, %v3
+; CHECK-NEXT: vo %v0, %v0, %v1
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
+; CHECK-NEXT: vn %v1, %v1, %v2
+; CHECK-NEXT: vrepib %v3, 31
+; CHECK-NEXT: vslb %v1, %v1, %v3
; CHECK-NEXT: vlgvf %r0, %v24, 3
-; CHECK-NEXT: vslb %v3, %v3, %v6
-; CHECK-NEXT: vsl %v2, %v2, %v4
-; CHECK-NEXT: vsl %v1, %v1, %v5
-; CHECK-NEXT: vlvgp %v4, %r0, %r0
+; CHECK-NEXT: vsl %v1, %v1, %v3
+; CHECK-NEXT: vo %v0, %v0, %v1
+; CHECK-NEXT: vlvgp %v1, %r0, %r0
; CHECK-NEXT: larl %r1, .LCPI0_1
-; CHECK-NEXT: vo %v1, %v2, %v1
-; CHECK-NEXT: vsl %v2, %v3, %v6
-; CHECK-NEXT: vo %v1, %v1, %v2
-; CHECK-NEXT: vl %v2, 0(%r1), 3
-; CHECK-NEXT: vn %v0, %v4, %v0
-; CHECK-NEXT: vo %v0, %v1, %v0
-; CHECK-NEXT: vn %v0, %v0, %v2
+; CHECK-NEXT: vn %v1, %v1, %v2
+; CHECK-NEXT: vo %v0, %v0, %v1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vn %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 4
; CHECK-NEXT: br %r14
{
@@ -49,34 +49,34 @@ define i16 @fun1(<16 x i1> %src)
; CHECK-NEXT: vlgvb %r0, %v24, 0
; CHECK-NEXT: vlgvb %r1, %v24, 1
; CHECK-NEXT: risblg %r0, %r0, 16, 144, 15
-; CHECK-NEXT: vlgvb %r2, %v24, 2
; CHECK-NEXT: rosbg %r0, %r1, 49, 49, 14
+; CHECK-NEXT: vlgvb %r1, %v24, 2
+; CHECK-NEXT: rosbg %r0, %r1, 50, 50, 13
; CHECK-NEXT: vlgvb %r1, %v24, 3
-; CHECK-NEXT: rosbg %r0, %r2, 50, 50, 13
-; CHECK-NEXT: vlgvb %r2, %v24, 4
; CHECK-NEXT: rosbg %r0, %r1, 51, 51, 12
+; CHECK-NEXT: vlgvb %r1, %v24, 4
+; CHECK-NEXT: rosbg %r0, %r1, 52, 52, 11
; CHECK-NEXT: vlgvb %r1, %v24, 5
-; CHECK-NEXT: rosbg %r0, %r2, 52, 52, 11
-; CHECK-NEXT: vlgvb %r2, %v24, 6
; CHECK-NEXT: rosbg %r0, %r1, 53, 53, 10
+; CHECK-NEXT: vlgvb %r1, %v24, 6
+; CHECK-NEXT: rosbg %r0, %r1, 54, 54, 9
; CHECK-NEXT: vlgvb %r1, %v24, 7
-; CHECK-NEXT: rosbg %r0, %r2, 54, 54, 9
-; CHECK-NEXT: vlgvb %r2, %v24, 8
; CHECK-NEXT: rosbg %r0, %r1, 55, 55, 8
+; CHECK-NEXT: vlgvb %r1, %v24, 8
+; CHECK-NEXT: rosbg %r0, %r1, 56, 56, 7
; CHECK-NEXT: vlgvb %r1, %v24, 9
-; CHECK-NEXT: rosbg %r0, %r2, 56, 56, 7
-; CHECK-NEXT: vlgvb %r2, %v24, 10
; CHECK-NEXT: rosbg %r0, %r1, 57, 57, 6
+; CHECK-NEXT: vlgvb %r1, %v24, 10
+; CHECK-NEXT: rosbg %r0, %r1, 58, 58, 5
; CHECK-NEXT: vlgvb %r1, %v24, 11
-; CHECK-NEXT: rosbg %r0, %r2, 58, 58, 5
-; CHECK-NEXT: vlgvb %r2, %v24, 12
; CHECK-NEXT: rosbg %r0, %r1, 59, 59, 4
+; CHECK-NEXT: vlgvb %r1, %v24, 12
+; CHECK-NEXT: rosbg %r0, %r1, 60, 60, 3
; CHECK-NEXT: vlgvb %r1, %v24, 13
-; CHECK-NEXT: rosbg %r0, %r2, 60, 60, 3
-; CHECK-NEXT: vlgvb %r2, %v24, 14
; CHECK-NEXT: rosbg %r0, %r1, 61, 61, 2
+; CHECK-NEXT: vlgvb %r1, %v24, 14
+; CHECK-NEXT: rosbg %r0, %r1, 62, 62, 1
; CHECK-NEXT: vlgvb %r1, %v24, 15
-; CHECK-NEXT: rosbg %r0, %r2, 62, 62, 1
; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 0
; CHECK-NEXT: llhr %r2, %r0
; CHECK-NEXT: aghi %r15, 168
@@ -179,9 +179,9 @@ define void @fun3(ptr %src, ptr %p)
; CHECK-NEXT: vrepib %v2, 32
; CHECK-NEXT: vslb %v0, %v0, %v2
; CHECK-NEXT: vo %v0, %v1, %v0
-; CHECK-NEXT: vsrlb %v1, %v0, %v2
; CHECK-NEXT: vstef %v0, 8(%r3), 3
-; CHECK-NEXT: vsteg %v1, 0(%r3), 1
+; CHECK-NEXT: vsrlb %v0, %v0, %v2
+; CHECK-NEXT: vsteg %v0, 0(%r3), 1
; CHECK-NEXT: br %r14
{
%tmp = load <3 x i31>, ptr %src
diff --git a/llvm/test/CodeGen/SystemZ/vec-args-04.ll b/llvm/test/CodeGen/SystemZ/vec-args-04.ll
index cc9a3d2d0cfff..b1cd278992541 100644
--- a/llvm/test/CodeGen/SystemZ/vec-args-04.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-args-04.ll
@@ -19,9 +19,10 @@ define void @foo() {
; CHECK-VEC-NEXT: aghi %r15, -192
; CHECK-VEC-NEXT: .cfi_def_cfa_offset 352
; CHECK-VEC-NEXT: larl %r1, .LCPI0_0
-; CHECK-VEC-NEXT: larl %r2, .LCPI0_1
; CHECK-VEC-NEXT: vl %v0, 0(%r1), 3
-; CHECK-VEC-NEXT: vl %v1, 0(%r2), 3
+; CHECK-VEC-NEXT: larl %r1, .LCPI0_1
+; CHECK-VEC-NEXT: vst %v0, 176(%r15), 3
+; CHECK-VEC-NEXT: vl %v0, 0(%r1), 3
; CHECK-VEC-NEXT: vrepib %v24, 1
; CHECK-VEC-NEXT: vrepib %v26, 2
; CHECK-VEC-NEXT: vrepib %v28, 3
@@ -30,8 +31,7 @@ define void @foo() {
; CHECK-VEC-NEXT: vrepib %v27, 6
; CHECK-VEC-NEXT: vrepib %v29, 7
; CHECK-VEC-NEXT: vrepib %v31, 8
-; CHECK-VEC-NEXT: vst %v0, 176(%r15), 3
-; CHECK-VEC-NEXT: vst %v1, 160(%r15), 3
+; CHECK-VEC-NEXT: vst %v0, 160(%r15), 3
; CHECK-VEC-NEXT: brasl %r14, bar at PLT
; CHECK-VEC-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-VEC-NEXT: br %r14
@@ -44,9 +44,10 @@ define void @foo() {
; CHECK-STACK-NEXT: aghi %r15, -192
; CHECK-STACK-NEXT: .cfi_def_cfa_offset 352
; CHECK-STACK-NEXT: larl %r1, .LCPI0_0
-; CHECK-STACK-NEXT: larl %r2, .LCPI0_1
; CHECK-STACK-NEXT: vl %v0, 0(%r1), 3
-; CHECK-STACK-NEXT: vl %v1, 0(%r2), 3
+; CHECK-STACK-NEXT: larl %r1, .LCPI0_1
+; CHECK-STACK-NEXT: vst %v0, 176(%r15), 3
+; CHECK-STACK-NEXT: vl %v0, 0(%r1), 3
; CHECK-STACK-NEXT: vrepib %v24, 1
; CHECK-STACK-NEXT: vrepib %v26, 2
; CHECK-STACK-NEXT: vrepib %v28, 3
@@ -55,8 +56,7 @@ define void @foo() {
; CHECK-STACK-NEXT: vrepib %v27, 6
; CHECK-STACK-NEXT: vrepib %v29, 7
; CHECK-STACK-NEXT: vrepib %v31, 8
-; CHECK-STACK-NEXT: vst %v0, 176(%r15), 3
-; CHECK-STACK-NEXT: vst %v1, 160(%r15), 3
+; CHECK-STACK-NEXT: vst %v0, 160(%r15), 3
; CHECK-STACK-NEXT: brasl %r14, bar at PLT
; CHECK-STACK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-STACK-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll b/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
index 5034358b675c7..015425e40f641 100644
--- a/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
@@ -63,7 +63,7 @@ define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16
; CHECK-DAG: vceqh [[REG4:%v[0-9]+]], %v30, %v27
; CHECK-DAG: vl [[REG5:%v[0-9]+]], 176(%r15)
; CHECK-DAG: vl [[REG6:%v[0-9]+]], 160(%r15)
-; CHECK-DAG: vo [[REG7:%v[0-9]+]], %v0, [[REG4]]
+; CHECK-DAG: vo [[REG7:%v[0-9]+]], [[REG1]], [[REG4]]
; CHECK-DAG: vo [[REG8:%v[0-9]+]], [[REG2]], [[REG3]]
; CHECK-DAG: vsel %v24, %v29, [[REG6]], [[REG8]]
; CHECK-DAG: vsel %v26, %v31, [[REG5]], [[REG7]]
@@ -117,10 +117,10 @@ define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8>
define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
; CHECK-LABEL: fun6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vceqb %v0, %v28, %v30
-; CHECK-NEXT: vceqh %v1, %v24, %v26
-; CHECK-NEXT: vuphb %v0, %v0
-; CHECK-NEXT: vo %v0, %v1, %v0
+; CHECK-NEXT: vceqb %v1, %v28, %v30
+; CHECK-NEXT: vceqh %v0, %v24, %v26
+; CHECK-NEXT: vuphb %v1, %v1
+; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
; CHECK-NEXT: br %r14
%cmp0 = icmp eq <2 x i16> %val1, %val2
@@ -133,10 +133,10 @@ define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8
define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i32> %val5, <2 x i32> %val6) {
; CHECK-LABEL: fun7:
; CHECK: # %bb.0:
-; CHECK-NEXT: vceqb %v0, %v28, %v30
-; CHECK-NEXT: vceqh %v1, %v24, %v26
-; CHECK-NEXT: vuphb %v0, %v0
-; CHECK-NEXT: vo %v0, %v1, %v0
+; CHECK-NEXT: vceqb %v1, %v28, %v30
+; CHECK-NEXT: vceqh %v0, %v24, %v26
+; CHECK-NEXT: vuphb %v1, %v1
+; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vuphh %v0, %v0
; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
; CHECK-NEXT: br %r14
@@ -259,10 +259,10 @@ define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <
define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {
; CHECK-LABEL: fun13:
; CHECK: # %bb.0:
-; CHECK-NEXT: vceqg %v0, %v28, %v30
-; CHECK-NEXT: vceqf %v1, %v24, %v26
-; CHECK-NEXT: vpkg %v0, %v0, %v0
-; CHECK-NEXT: vx %v0, %v1, %v0
+; CHECK-NEXT: vceqg %v1, %v28, %v30
+; CHECK-NEXT: vceqf %v0, %v24, %v26
+; CHECK-NEXT: vpkg %v1, %v1, %v1
+; CHECK-NEXT: vx %v0, %v0, %v1
; CHECK-NEXT: vpkf %v0, %v0, %v0
; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
; CHECK-NEXT: br %r14
@@ -276,10 +276,10 @@ define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x
define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
; CHECK-LABEL: fun14:
; CHECK: # %bb.0:
-; CHECK-NEXT: vceqg %v0, %v28, %v30
-; CHECK-NEXT: vceqf %v1, %v24, %v26
-; CHECK-NEXT: vpkg %v0, %v0, %v0
-; CHECK-NEXT: vx %v0, %v1, %v0
+; CHECK-NEXT: vceqg [[REG0:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT: vceqf [[REG1:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vpkg [[REG0]], [[REG0]], [[REG0]]
+; CHECK-NEXT: vx %v0, [[REG1]], [[REG0]]
; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
; CHECK-NEXT: br %r14
%cmp0 = icmp eq <2 x i32> %val1, %val2
@@ -324,10 +324,10 @@ define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i32> %val5, <4 x i32> %val6) {
; CHECK-LABEL: fun17:
; CHECK: # %bb.0:
-; CHECK-NEXT: vceqh %v0, %v28, %v30
-; CHECK-NEXT: vceqf %v1, %v24, %v26
-; CHECK-NEXT: vuphh %v0, %v0
-; CHECK-NEXT: vn %v0, %v1, %v0
+; CHECK-NEXT: vceqh [[REG0:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT: vceqf [[REG1:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vuphh [[REG0]], [[REG0]]
+; CHECK-NEXT: vn %v0, [[REG1]], [[REG0]]
; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
; CHECK-NEXT: br %r14
%cmp0 = icmp eq <4 x i32> %val1, %val2
@@ -340,14 +340,14 @@ define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i64> %val5, <4 x i64> %val6) {
; CHECK-LABEL: fun18:
; CHECK: # %bb.0:
-; CHECK-NEXT: vceqh %v0, %v28, %v30
-; CHECK-NEXT: vceqf %v1, %v24, %v26
-; CHECK-NEXT: vuphh %v0, %v0
-; CHECK-NEXT: vn %v0, %v1, %v0
-; CHECK-DAG: vuphf [[REG0:%v[0-9]+]], %v0
-; CHECK-DAG: vuplf [[REG1:%v[0-9]+]], %v0
-; CHECK-NEXT: vsel %v24, %v25, %v29, [[REG0]]
-; CHECK-NEXT: vsel %v26, %v27, %v31, [[REG1]]
+; CHECK-NEXT: vceqh [[REG0:%v[0-9]+]], %v28, %v30
+; CHECK-NEXT: vceqf [[REG1:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vuphh [[REG0]], [[REG0]]
+; CHECK-NEXT: vn %v0, [[REG1]], [[REG0]]
+; CHECK-DAG: vuphf [[REG2:%v[0-9]+]], %v0
+; CHECK-DAG: vuplf [[REG3:%v[0-9]+]], %v0
+; CHECK-NEXT: vsel %v24, %v25, %v29, [[REG2]]
+; CHECK-NEXT: vsel %v26, %v27, %v31, [[REG3]]
; CHECK-NEXT: br %r14
%cmp0 = icmp eq <4 x i32> %val1, %val2
%cmp1 = icmp eq <4 x i16> %val3, %val4
@@ -483,19 +483,19 @@ define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %va
; CHECK-NEXT: vldeb %v3, %v3
; CHECK-NEXT: vfchdb %v0, %v1, %v0
; CHECK-NEXT: vfchdb %v1, %v3, %v2
-; CHECK-NEXT: vfchdb %v2, %v28, %v30
; CHECK-NEXT: vpkg %v0, %v1, %v0
-; CHECK-NEXT: vpkg %v1, %v2, %v2
+; CHECK-NEXT: vfchdb %v1, %v28, %v30
+; CHECK-NEXT: vpkg %v1, %v1, %v1
; CHECK-NEXT: vo %v0, %v0, %v1
; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun25:
; CHECK-Z14: # %bb.0:
-; CHECK-Z14-NEXT: vfchdb %v0, %v28, %v30
-; CHECK-Z14-NEXT: vfchsb %v1, %v24, %v26
-; CHECK-Z14-NEXT: vpkg %v0, %v0, %v0
-; CHECK-Z14-NEXT: vo %v0, %v1, %v0
+; CHECK-Z14-NEXT: vfchdb %v1, %v28, %v30
+; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
+; CHECK-Z14-NEXT: vpkg %v1, %v1, %v1
+; CHECK-Z14-NEXT: vo %v0, %v0, %v1
; CHECK-Z14-NEXT: vsel %v24, %v25, %v27, %v0
; CHECK-Z14-NEXT: br %r14
%cmp0 = fcmp ogt <2 x float> %val1, %val2
@@ -581,8 +581,8 @@ define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val
; CHECK-DAG: vmrhf [[REG17:%v[0-9]+]], %v30, %v30
; CHECK-DAG: vldeb [[REG19:%v[0-9]+]], [[REG17]]
; CHECK-DAG: vldeb [[REG20:%v[0-9]+]], [[REG8]]
-; CHECK-NEXT: vfchdb %v3, [[REG20]], [[REG19]]
-; CHECK-NEXT: vpkg [[REG21:%v[0-9]+]], %v3, [[REG16]]
+; CHECK-NEXT: vfchdb %v2, [[REG20]], [[REG19]]
+; CHECK-NEXT: vpkg [[REG21:%v[0-9]+]], %v2, [[REG16]]
; CHECK-NEXT: vx %v0, [[REG11]], [[REG21]]
; CHECK-NEXT: vsel %v24, %v25, %v27, %v0
; CHECK-NEXT: br %r14
@@ -621,11 +621,11 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %va
; CHECK-NEXT: vpkg %v0, %v1, %v0
; CHECK-NEXT: vldeb %v4, %v4
; CHECK-NEXT: vldeb %v5, %v5
-; CHECK-NEXT: vfchdb %v2, %v5, %v4
+; CHECK-NEXT: vfchdb %v1, %v5, %v4
; CHECK-NEXT: vldeb %v6, %v6
; CHECK-NEXT: vldeb %v7, %v7
-; CHECK-NEXT: vfchdb %v3, %v7, %v6
-; CHECK-NEXT: vpkg %v1, %v3, %v2
+; CHECK-NEXT: vfchdb %v2, %v7, %v6
+; CHECK-NEXT: vpkg %v1, %v2, %v1
; CHECK-NEXT: vx %v0, %v0, %v1
; CHECK-NEXT: vuplf %v1, %v0
; CHECK-NEXT: vuphf %v0, %v0
@@ -663,60 +663,60 @@ define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %va
; CHECK-NEXT: vmrhf %v7, %v26, %v26
; CHECK-NEXT: vldeb %v0, %v0
; CHECK-NEXT: vldeb %v1, %v1
-; CHECK-NEXT: vl %v16, 192(%r15), 3
-; CHECK-NEXT: vl %v17, 208(%r15), 3
-; CHECK-NEXT: vldeb %v2, %v2
; CHECK-NEXT: vl %v18, 160(%r15), 3
; CHECK-NEXT: vl %v19, 176(%r15), 3
+; CHECK-NEXT: vldeb %v2, %v2
+; CHECK-NEXT: vl %v16, 192(%r15), 3
+; CHECK-NEXT: vl %v17, 208(%r15), 3
; CHECK-NEXT: vfchdb %v0, %v1, %v0
; CHECK-NEXT: vldeb %v3, %v3
; CHECK-NEXT: vfchdb %v1, %v3, %v2
; CHECK-NEXT: vpkg %v0, %v1, %v0
+; CHECK-NEXT: vfchdb %v3, %v25, %v18
; CHECK-NEXT: vldeb %v4, %v4
; CHECK-NEXT: vldeb %v5, %v5
-; CHECK-NEXT: vfchdb %v2, %v5, %v4
-; CHECK-NEXT: vfchdb %v4, %v27, %v19
-; CHECK-NEXT: vfchdb %v5, %v25, %v18
+; CHECK-NEXT: vfchdb %v1, %v5, %v4
+; CHECK-NEXT: vl %v5, 272(%r15), 3
+; CHECK-NEXT: vfchdb %v4, %v29, %v16
+; CHECK-NEXT: vl %v16, 224(%r15), 3
; CHECK-NEXT: vldeb %v6, %v6
; CHECK-NEXT: vldeb %v7, %v7
-; CHECK-NEXT: vfchdb %v3, %v7, %v6
-; CHECK-NEXT: vfchdb %v6, %v31, %v17
-; CHECK-NEXT: vfchdb %v7, %v29, %v16
-; CHECK-NEXT: vl %v16, 224(%r15), 3
-; CHECK-NEXT: vpkg %v1, %v3, %v2
-; CHECK-NEXT: vl %v3, 272(%r15), 3
-; CHECK-NEXT: vpkg %v2, %v5, %v4
-; CHECK-NEXT: vl %v4, 240(%r15), 3
-; CHECK-NEXT: vl %v5, 256(%r15), 3
-; CHECK-NEXT: vpkg %v6, %v7, %v6
-; CHECK-NEXT: vn %v1, %v1, %v6
+; CHECK-NEXT: vfchdb %v2, %v7, %v6
+; CHECK-NEXT: vl %v6, 240(%r15), 3
+; CHECK-NEXT: vl %v7, 256(%r15), 3
+; CHECK-NEXT: vpkg %v1, %v2, %v1
+; CHECK-NEXT: vfchdb %v2, %v27, %v19
+; CHECK-NEXT: vpkg %v2, %v3, %v2
+; CHECK-NEXT: vfchdb %v3, %v31, %v17
+; CHECK-NEXT: vpkg %v3, %v4, %v3
+; CHECK-NEXT: vn %v1, %v1, %v3
; CHECK-NEXT: vn %v0, %v0, %v2
-; CHECK-NEXT: vsel %v24, %v16, %v5, %v0
-; CHECK-NEXT: vsel %v26, %v4, %v3, %v1
+; CHECK-NEXT: vsel %v24, %v16, %v7, %v0
+; CHECK-NEXT: vsel %v26, %v6, %v5, %v1
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun30:
; CHECK-Z14: # %bb.0:
-; CHECK-Z14-NEXT: vl %v0, 192(%r15), 3
-; CHECK-Z14-NEXT: vl %v1, 208(%r15), 3
-; CHECK-Z14-NEXT: vl %v2, 160(%r15), 3
-; CHECK-Z14-NEXT: vl %v3, 176(%r15), 3
-; CHECK-Z14-NEXT: vfchdb %v3, %v27, %v3
-; CHECK-Z14-NEXT: vfchdb %v2, %v25, %v2
-; CHECK-Z14-NEXT: vfchdb %v1, %v31, %v1
-; CHECK-Z14-NEXT: vfchdb %v0, %v29, %v0
-; CHECK-Z14-NEXT: vl %v4, 272(%r15), 3
-; CHECK-Z14-NEXT: vl %v5, 240(%r15), 3
-; CHECK-Z14-NEXT: vl %v6, 256(%r15), 3
-; CHECK-Z14-NEXT: vl %v7, 224(%r15), 3
+; CHECK-Z14-NEXT: vl %v4, 192(%r15), 3
+; CHECK-Z14-NEXT: vl %v5, 208(%r15), 3
+; CHECK-Z14-NEXT: vl %v6, 160(%r15), 3
+; CHECK-Z14-NEXT: vl %v7, 176(%r15), 3
+; CHECK-Z14-NEXT: vfchdb %v7, %v27, %v7
+; CHECK-Z14-NEXT: vfchdb %v6, %v25, %v6
+; CHECK-Z14-NEXT: vfchdb %v5, %v31, %v5
+; CHECK-Z14-NEXT: vfchdb %v4, %v29, %v4
+; CHECK-Z14-NEXT: vl %v0, 272(%r15), 3
+; CHECK-Z14-NEXT: vl %v1, 240(%r15), 3
+; CHECK-Z14-NEXT: vl %v2, 256(%r15), 3
+; CHECK-Z14-NEXT: vl %v3, 224(%r15), 3
; CHECK-Z14-NEXT: vfchsb %v16, %v24, %v28
; CHECK-Z14-NEXT: vfchsb %v17, %v26, %v30
-; CHECK-Z14-NEXT: vpkg %v2, %v2, %v3
-; CHECK-Z14-NEXT: vpkg %v0, %v0, %v1
-; CHECK-Z14-NEXT: vn %v0, %v17, %v0
-; CHECK-Z14-NEXT: vn %v1, %v16, %v2
-; CHECK-Z14-NEXT: vsel %v24, %v7, %v6, %v1
-; CHECK-Z14-NEXT: vsel %v26, %v5, %v4, %v0
+; CHECK-Z14-NEXT: vpkg %v6, %v6, %v7
+; CHECK-Z14-NEXT: vpkg %v4, %v4, %v5
+; CHECK-Z14-NEXT: vn %v4, %v17, %v4
+; CHECK-Z14-NEXT: vn %v5, %v16, %v6
+; CHECK-Z14-NEXT: vsel %v24, %v3, %v2, %v5
+; CHECK-Z14-NEXT: vsel %v26, %v1, %v0, %v4
; CHECK-Z14-NEXT: br %r14
%cmp0 = fcmp ogt <8 x float> %val1, %val2
%cmp1 = fcmp ogt <8 x double> %val3, %val4
@@ -771,9 +771,9 @@ define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %v
; CHECK-NEXT: vfchdb %v5, %v24, %v28
; CHECK-NEXT: vfchdb %v0, %v1, %v0
; CHECK-NEXT: vfchdb %v1, %v3, %v2
-; CHECK-NEXT: vpkg %v2, %v5, %v4
+; CHECK-NEXT: vpkg %v4, %v5, %v4
; CHECK-NEXT: vpkg %v0, %v1, %v0
-; CHECK-NEXT: vn %v0, %v2, %v0
+; CHECK-NEXT: vn %v0, %v4, %v0
; CHECK-NEXT: vsel %v24, %v29, %v31, %v0
; CHECK-NEXT: br %r14
;
@@ -804,34 +804,34 @@ define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %
; CHECK-NEXT: vldeb %v1, %v1
; CHECK-NEXT: vldeb %v2, %v2
; CHECK-NEXT: vldeb %v3, %v3
+; CHECK-NEXT: vl %v4, 176(%r15), 3
+; CHECK-NEXT: vl %v5, 160(%r15), 3
; CHECK-NEXT: vfchdb %v0, %v1, %v0
; CHECK-NEXT: vfchdb %v1, %v3, %v2
-; CHECK-NEXT: vl %v2, 160(%r15), 3
; CHECK-NEXT: vpkg %v0, %v1, %v0
-; CHECK-NEXT: vl %v1, 176(%r15), 3
-; CHECK-NEXT: vfchdb %v3, %v24, %v28
-; CHECK-NEXT: vfchdb %v4, %v26, %v30
-; CHECK-NEXT: vuphf %v5, %v0
+; CHECK-NEXT: vfchdb %v6, %v24, %v28
+; CHECK-NEXT: vfchdb %v7, %v26, %v30
+; CHECK-NEXT: vuphf %v1, %v0
; CHECK-NEXT: vuplf %v0, %v0
-; CHECK-NEXT: vn %v0, %v4, %v0
-; CHECK-NEXT: vn %v3, %v3, %v5
-; CHECK-NEXT: vsel %v24, %v29, %v2, %v3
-; CHECK-NEXT: vsel %v26, %v31, %v1, %v0
+; CHECK-NEXT: vn %v0, %v7, %v0
+; CHECK-NEXT: vn %v1, %v6, %v1
+; CHECK-NEXT: vsel %v24, %v29, %v5, %v1
+; CHECK-NEXT: vsel %v26, %v31, %v4, %v0
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun34:
; CHECK-Z14: # %bb.0:
-; CHECK-Z14-NEXT: vfchsb %v0, %v25, %v27
-; CHECK-Z14-NEXT: vl %v1, 176(%r15), 3
-; CHECK-Z14-NEXT: vl %v2, 160(%r15), 3
-; CHECK-Z14-NEXT: vfchdb %v3, %v24, %v28
-; CHECK-Z14-NEXT: vfchdb %v4, %v26, %v30
-; CHECK-Z14-NEXT: vuphf %v5, %v0
-; CHECK-Z14-NEXT: vuplf %v0, %v0
-; CHECK-Z14-NEXT: vn %v0, %v4, %v0
-; CHECK-Z14-NEXT: vn %v3, %v3, %v5
-; CHECK-Z14-NEXT: vsel %v24, %v29, %v2, %v3
-; CHECK-Z14-NEXT: vsel %v26, %v31, %v1, %v0
+; CHECK-Z14-NEXT: vfchsb %v4, %v25, %v27
+; CHECK-Z14-NEXT: vl %v0, 176(%r15), 3
+; CHECK-Z14-NEXT: vl %v1, 160(%r15), 3
+; CHECK-Z14-NEXT: vfchdb %v2, %v24, %v28
+; CHECK-Z14-NEXT: vfchdb %v3, %v26, %v30
+; CHECK-Z14-NEXT: vuphf %v5, %v4
+; CHECK-Z14-NEXT: vuplf %v4, %v4
+; CHECK-Z14-NEXT: vn %v3, %v3, %v4
+; CHECK-Z14-NEXT: vn %v2, %v2, %v5
+; CHECK-Z14-NEXT: vsel %v24, %v29, %v1, %v2
+; CHECK-Z14-NEXT: vsel %v26, %v31, %v0, %v3
; CHECK-Z14-NEXT: br %r14
%cmp0 = fcmp ogt <4 x double> %val1, %val2
%cmp1 = fcmp ogt <4 x float> %val3, %val4
diff --git a/llvm/test/CodeGen/SystemZ/vec-cmpsel-01.ll b/llvm/test/CodeGen/SystemZ/vec-cmpsel-01.ll
index fb0ef2eb0ff06..283dc1dc2b451 100644
--- a/llvm/test/CodeGen/SystemZ/vec-cmpsel-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-cmpsel-01.ll
@@ -435,11 +435,11 @@ define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x float> %val
; CHECK-NEXT: vsel %v26, %v27, %v31, %v0
; CHECK-NEXT: vldeb %v4, %v4
; CHECK-NEXT: vldeb %v5, %v5
-; CHECK-NEXT: vfchdb %v2, %v5, %v4
+; CHECK-NEXT: vfchdb %v1, %v5, %v4
; CHECK-NEXT: vldeb %v6, %v6
; CHECK-NEXT: vldeb %v7, %v7
-; CHECK-NEXT: vfchdb %v3, %v7, %v6
-; CHECK-NEXT: vpkg %v1, %v3, %v2
+; CHECK-NEXT: vfchdb %v2, %v7, %v6
+; CHECK-NEXT: vpkg %v1, %v2, %v1
; CHECK-NEXT: vsel %v24, %v25, %v29, %v1
; CHECK-NEXT: br %r14
%cmp = fcmp ogt <8 x float> %val1, %val2
diff --git a/llvm/test/CodeGen/SystemZ/vec-eval.ll b/llvm/test/CodeGen/SystemZ/vec-eval.ll
index 98f754880d0bd..bcdedcd3a407b 100644
--- a/llvm/test/CodeGen/SystemZ/vec-eval.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-eval.ll
@@ -596,10 +596,10 @@ entry:
define <16 x i8> @eval45(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval45:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: veval %v0, %v26, %v24, %v28, 1
-; CHECK-NEXT: vo %v1, %v28, %v24
-; CHECK-NEXT: veval %v0, %v0, %v24, %v26, 47
-; CHECK-NEXT: veval %v24, %v0, %v26, %v1, 47
+; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
+; CHECK-NEXT: vo %v0, %v28, %v24
+; CHECK-NEXT: veval %v1, %v1, %v24, %v26, 47
+; CHECK-NEXT: veval %v24, %v1, %v26, %v0, 47
; CHECK-NEXT: br %r14
entry:
%0 = or <16 x i8> %src3, %src1
@@ -770,10 +770,10 @@ entry:
define <16 x i8> @eval57(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval57:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: veval %v0, %v26, %v24, %v28, 1
-; CHECK-NEXT: vo %v1, %v28, %v26
-; CHECK-NEXT: veval %v0, %v0, %v26, %v24, 47
-; CHECK-NEXT: veval %v24, %v0, %v24, %v1, 47
+; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
+; CHECK-NEXT: vo %v0, %v28, %v26
+; CHECK-NEXT: veval %v1, %v1, %v26, %v24, 47
+; CHECK-NEXT: veval %v24, %v1, %v24, %v0, 47
; CHECK-NEXT: br %r14
entry:
%not = xor <16 x i8> %src1, splat(i8 -1)
@@ -1541,8 +1541,8 @@ define <16 x i8> @eval109(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vgbm %v0, 65535
; CHECK-NEXT: veval %v0, %v24, %v0, %v26, 40
-; CHECK-NEXT: vn %v1, %v26, %v24
-; CHECK-NEXT: veval %v0, %v28, %v0, %v1, 7
+; CHECK-NEXT: vn %v2, %v26, %v24
+; CHECK-NEXT: veval %v0, %v28, %v0, %v2, 7
; CHECK-NEXT: vo %v1, %v28, %v24
; CHECK-NEXT: veval %v0, %v0, %v24, %v26, 47
; CHECK-NEXT: veval %v24, %v0, %v26, %v1, 47
@@ -1754,8 +1754,8 @@ define <16 x i8> @eval121(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vgbm %v0, 65535
; CHECK-NEXT: veval %v0, %v24, %v0, %v26, 40
-; CHECK-NEXT: vn %v1, %v26, %v24
-; CHECK-NEXT: veval %v0, %v28, %v0, %v1, 7
+; CHECK-NEXT: vn %v2, %v26, %v24
+; CHECK-NEXT: veval %v0, %v28, %v0, %v2, 7
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v0, %v26, %v24, 47
; CHECK-NEXT: veval %v24, %v0, %v24, %v1, 47
@@ -2084,10 +2084,10 @@ entry:
define <16 x i8> @eval141(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval141:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: veval %v0, %v26, %v24, %v28, 1
-; CHECK-NEXT: vo %v1, %v26, %v24
-; CHECK-NEXT: veval %v0, %v0, %v24, %v26, 47
-; CHECK-NEXT: veval %v24, %v0, %v1, %v28, 143
+; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
+; CHECK-NEXT: vo %v0, %v26, %v24
+; CHECK-NEXT: veval %v1, %v1, %v24, %v26, 47
+; CHECK-NEXT: veval %v24, %v1, %v0, %v28, 143
; CHECK-NEXT: br %r14
entry:
%not1 = xor <16 x i8> %src2, splat(i8 -1)
@@ -2253,10 +2253,10 @@ entry:
define <16 x i8> @eval151(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval151:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 2
-; CHECK-NEXT: vx %v1, %v28, %v26
-; CHECK-NEXT: veval %v0, %v0, %v26, %v24, 31
-; CHECK-NEXT: veval %v24, %v0, %v1, %v24, 143
+; CHECK-NEXT: veval %v1, %v24, %v28, %v26, 2
+; CHECK-NEXT: vx %v0, %v28, %v26
+; CHECK-NEXT: veval %v1, %v1, %v26, %v24, 31
+; CHECK-NEXT: veval %v24, %v1, %v0, %v24, 143
; CHECK-NEXT: br %r14
entry:
%not1 = xor <16 x i8> %src2, splat(i8 -1)
@@ -2365,10 +2365,10 @@ entry:
define <16 x i8> @eval157(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval157:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: veval %v0, %v26, %v24, %v28, 1
-; CHECK-NEXT: vx %v1, %v28, %v26
-; CHECK-NEXT: veval %v0, %v0, %v24, %v26, 47
-; CHECK-NEXT: veval %v24, %v0, %v1, %v24, 143
+; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
+; CHECK-NEXT: vx %v0, %v28, %v26
+; CHECK-NEXT: veval %v1, %v1, %v24, %v26, 47
+; CHECK-NEXT: veval %v24, %v1, %v0, %v24, 143
; CHECK-NEXT: br %r14
entry:
%not1 = xor <16 x i8> %src2, splat(i8 -1)
@@ -2778,10 +2778,10 @@ entry:
define <16 x i8> @eval183(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval183:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 2
-; CHECK-NEXT: voc %v1, %v26, %v28
-; CHECK-NEXT: veval %v0, %v0, %v26, %v24, 31
-; CHECK-NEXT: veval %v24, %v0, %v1, %v24, 47
+; CHECK-NEXT: veval %v1, %v24, %v28, %v26, 2
+; CHECK-NEXT: voc %v0, %v26, %v28
+; CHECK-NEXT: veval %v1, %v1, %v26, %v24, 31
+; CHECK-NEXT: veval %v24, %v1, %v0, %v24, 47
; CHECK-NEXT: br %r14
entry:
%not = xor <16 x i8> %src1, splat(i8 -1)
@@ -2884,10 +2884,10 @@ entry:
define <16 x i8> @eval189(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval189:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: veval %v0, %v26, %v24, %v28, 1
-; CHECK-NEXT: voc %v1, %v26, %v28
-; CHECK-NEXT: veval %v0, %v0, %v24, %v26, 47
-; CHECK-NEXT: veval %v24, %v0, %v1, %v24, 47
+; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
+; CHECK-NEXT: voc %v0, %v26, %v28
+; CHECK-NEXT: veval %v1, %v1, %v24, %v26, 47
+; CHECK-NEXT: veval %v24, %v1, %v0, %v24, 47
; CHECK-NEXT: br %r14
entry:
%not = xor <16 x i8> %src1, splat(i8 -1)
@@ -3480,10 +3480,10 @@ define <16 x i8> @eval228(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval228:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vno %v0, %v26, %v26
-; CHECK-NEXT: veval %v1, %v24, %v28, %v26, 2
-; CHECK-NEXT: vo %v2, %v28, %v24
-; CHECK-NEXT: veval %v0, %v1, %v0, %v24, 47
-; CHECK-NEXT: veval %v24, %v0, %v26, %v2, 47
+; CHECK-NEXT: veval %v2, %v24, %v28, %v26, 2
+; CHECK-NEXT: vo %v1, %v28, %v24
+; CHECK-NEXT: veval %v0, %v2, %v0, %v24, 47
+; CHECK-NEXT: veval %v24, %v0, %v26, %v1, 47
; CHECK-NEXT: br %r14
entry:
%not = xor <16 x i8> %src1, splat(i8 -1)
@@ -3539,11 +3539,11 @@ define <16 x i8> @eval231(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval231:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vno %v0, %v26, %v26
-; CHECK-NEXT: vnc %v1, %v24, %v26
-; CHECK-NEXT: vo %v2, %v28, %v24
+; CHECK-NEXT: vnc %v2, %v24, %v26
+; CHECK-NEXT: vo %v1, %v28, %v24
; CHECK-NEXT: vsel %v0, %v26, %v0, %v24
-; CHECK-NEXT: veval %v0, %v0, %v1, %v28, 31
-; CHECK-NEXT: veval %v24, %v0, %v26, %v2, 47
+; CHECK-NEXT: veval %v0, %v0, %v2, %v28, 31
+; CHECK-NEXT: veval %v24, %v0, %v26, %v1, 47
; CHECK-NEXT: br %r14
entry:
%not = xor <16 x i8> %src1, splat(i8 -1)
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-12.ll b/llvm/test/CodeGen/SystemZ/vec-perm-12.ll
index 5f9f38d7ad038..b59eafaf0768b 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-12.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-12.ll
@@ -10,17 +10,17 @@ define <4 x i32> @f1(<4 x i32> %x, i64 %y) {
; CHECK-CODE-LABEL: f1:
; CHECK-CODE: # %bb.0:
; CHECK-CODE-NEXT: larl %r1, .LCPI0_0
-; CHECK-CODE-NEXT: vl %v0, 0(%r1), 3
-; CHECK-CODE-NEXT: vlvgf %v1, %r2, 0
-; CHECK-CODE-NEXT: vperm %v24, %v24, %v1, %v0
+; CHECK-CODE-NEXT: vl %v1, 0(%r1), 3
+; CHECK-CODE-NEXT: vlvgf %v0, %r2, 0
+; CHECK-CODE-NEXT: vperm %v24, %v24, %v0, %v1
; CHECK-CODE-NEXT: br %r14
;
; CHECK-VECTOR-LABEL: f1:
; CHECK-VECTOR: # %bb.0:
; CHECK-VECTOR-NEXT: larl %r1, .LCPI0_0
-; CHECK-VECTOR-NEXT: vl %v0, 0(%r1), 3
-; CHECK-VECTOR-NEXT: vlvgf %v1, %r2, 0
-; CHECK-VECTOR-NEXT: vperm %v24, %v24, %v1, %v0
+; CHECK-VECTOR-NEXT: vl %v1, 0(%r1), 3
+; CHECK-VECTOR-NEXT: vlvgf %v0, %r2, 0
+; CHECK-VECTOR-NEXT: vperm %v24, %v24, %v0, %v1
; CHECK-VECTOR-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll
index e67f2f631bc93..42d787d945145 100644
--- a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll
@@ -23,11 +23,11 @@ define fastcc void @test_shuffle_with_trunc() {
; CHECK: # %bb.0:
; CHECK-NEXT: lh %r1, 0
; CHECK-NEXT: l %r0, 0
-; CHECK-NEXT: larl %r2, .LCPI1_0
-; CHECK-NEXT: vl %v0, 0(%r2), 3
-; CHECK-NEXT: vlvgf %v1, %r0, 0
-; CHECK-NEXT: vlvgh %v2, %r1, 0
-; CHECK-NEXT: vperm %v0, %v1, %v2, %v0
+; CHECK-NEXT: vlvgh %v1, %r1, 0
+; CHECK-NEXT: larl %r1, .LCPI1_0
+; CHECK-NEXT: vl %v2, 0(%r1), 3
+; CHECK-NEXT: vlvgf %v0, %r0, 0
+; CHECK-NEXT: vperm %v0, %v0, %v1, %v2
; CHECK-NEXT: vst %v0, 0, 3
; CHECK-NEXT: br %r14
%1 = load i32, ptr null, align 8
diff --git a/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
index baa4c5adea6be..c3adeca45ddca 100644
--- a/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
@@ -43,9 +43,9 @@ define <2 x double> @constrained_vector_fdiv_v2f64() #0 {
; SZ13-LABEL: constrained_vector_fdiv_v2f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI1_0
-; SZ13-NEXT: larl %r2, .LCPI1_1
; SZ13-NEXT: vl %v0, 0(%r1), 3
-; SZ13-NEXT: vl %v1, 0(%r2), 3
+; SZ13-NEXT: larl %r1, .LCPI1_1
+; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfddb %v24, %v1, %v0
; SZ13-NEXT: br %r14
entry:
@@ -76,9 +76,9 @@ define <3 x float> @constrained_vector_fdiv_v3f32() #0 {
; SZ13-LABEL: constrained_vector_fdiv_v3f32:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI2_0
-; SZ13-NEXT: larl %r2, .LCPI2_1
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f1, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI2_1
+; SZ13-NEXT: lde %f1, 0(%r1)
; SZ13-NEXT: debr %f1, %f0
; SZ13-NEXT: vgmf %v2, 2, 8
; SZ13-NEXT: vgmf %v3, 1, 1
@@ -116,15 +116,15 @@ define void @constrained_vector_fdiv_v3f64(ptr %a) #0 {
;
; SZ13-LABEL: constrained_vector_fdiv_v3f64:
; SZ13: # %bb.0: # %entry
+; SZ13-NEXT: larl %r1, .LCPI3_0
+; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: ddb %f1, 16(%r2)
; SZ13-NEXT: larl %r1, .LCPI3_1
; SZ13-NEXT: vl %v0, 0(%r2), 4
-; SZ13-NEXT: vl %v1, 0(%r1), 3
-; SZ13-NEXT: vfddb %v0, %v1, %v0
-; SZ13-NEXT: larl %r1, .LCPI3_0
-; SZ13-NEXT: ld %f2, 0(%r1)
-; SZ13-NEXT: ddb %f2, 16(%r2)
+; SZ13-NEXT: vl %v2, 0(%r1), 3
+; SZ13-NEXT: std %f1, 16(%r2)
+; SZ13-NEXT: vfddb %v0, %v2, %v0
; SZ13-NEXT: vst %v0, 0(%r2), 4
-; SZ13-NEXT: std %f2, 16(%r2)
; SZ13-NEXT: br %r14
entry:
%b = load <3 x double>, ptr %a
@@ -159,12 +159,12 @@ define <4 x double> @constrained_vector_fdiv_v4f64() #0 {
; SZ13-LABEL: constrained_vector_fdiv_v4f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI4_0
-; SZ13-NEXT: larl %r2, .LCPI4_1
-; SZ13-NEXT: larl %r3, .LCPI4_2
; SZ13-NEXT: vl %v0, 0(%r1), 3
-; SZ13-NEXT: vl %v1, 0(%r2), 3
+; SZ13-NEXT: larl %r1, .LCPI4_1
+; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfddb %v26, %v1, %v0
-; SZ13-NEXT: vl %v2, 0(%r3), 3
+; SZ13-NEXT: larl %r1, .LCPI4_2
+; SZ13-NEXT: vl %v2, 0(%r1), 3
; SZ13-NEXT: vfddb %v24, %v2, %v0
; SZ13-NEXT: br %r14
entry:
@@ -331,10 +331,10 @@ define <3 x float> @constrained_vector_frem_v3f32() #0 {
; SZ13-NEXT: .cfi_def_cfa_offset 360
; SZ13-NEXT: std %f8, 192(%r15) # 8-byte Spill
; SZ13-NEXT: .cfi_offset %f8, -168
-; SZ13-NEXT: larl %r2, .LCPI7_1
; SZ13-NEXT: larl %r1, .LCPI7_0
-; SZ13-NEXT: lde %f8, 0(%r2)
; SZ13-NEXT: lde %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI7_1
+; SZ13-NEXT: lde %f8, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, fmodf at PLT
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
@@ -432,13 +432,12 @@ define void @constrained_vector_frem_v3f64(ptr %a) #0 {
; SZ13-NEXT: vgmg %v0, 1, 1
; SZ13-NEXT: # kill: def $f2d killed $f2d killed $v2
; SZ13-NEXT: brasl %r14, fmod at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI8_0
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v2, %v0
+; SZ13-NEXT: vmrhg %v0, %v1, %v0
+; SZ13-NEXT: larl %r1, .LCPI8_0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, fmod at PLT
; SZ13-NEXT: mvc 0(16,%r13), 160(%r15) # 16-byte Folded Reload
@@ -526,13 +525,12 @@ define <4 x double> @constrained_vector_frem_v4f64() #0 {
; SZ13-NEXT: vgmg %v0, 2, 11
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, fmod at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI9_1
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI9_1
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, fmod at PLT
; SZ13-NEXT: larl %r1, .LCPI9_2
@@ -598,9 +596,9 @@ define <2 x double> @constrained_vector_fmul_v2f64() #0 {
; SZ13-LABEL: constrained_vector_fmul_v2f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI11_0
-; SZ13-NEXT: larl %r2, .LCPI11_1
; SZ13-NEXT: vl %v0, 0(%r1), 3
-; SZ13-NEXT: vl %v1, 0(%r2), 3
+; SZ13-NEXT: larl %r1, .LCPI11_1
+; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfmdb %v24, %v1, %v0
; SZ13-NEXT: br %r14
entry:
@@ -630,15 +628,15 @@ define <3 x float> @constrained_vector_fmul_v3f32() #0 {
; SZ13-LABEL: constrained_vector_fmul_v3f32:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vgmf %v0, 1, 8
-; SZ13-NEXT: vgmf %v1, 2, 8
+; SZ13-NEXT: vgmf %v2, 2, 8
; SZ13-NEXT: larl %r1, .LCPI12_0
; SZ13-NEXT: larl %r2, .LCPI12_1
-; SZ13-NEXT: vgmf %v2, 1, 8
-; SZ13-NEXT: meeb %f2, 0(%r1)
-; SZ13-NEXT: meebr %f1, %f0
+; SZ13-NEXT: vgmf %v1, 1, 8
+; SZ13-NEXT: meeb %f1, 0(%r1)
+; SZ13-NEXT: meebr %f2, %f0
; SZ13-NEXT: meeb %f0, 0(%r2)
-; SZ13-NEXT: vmrhf %v0, %v1, %v0
-; SZ13-NEXT: vrepf %v1, %v2, 0
+; SZ13-NEXT: vmrhf %v0, %v2, %v0
+; SZ13-NEXT: vrepf %v1, %v1, 0
; SZ13-NEXT: vmrhg %v24, %v0, %v1
; SZ13-NEXT: br %r14
entry:
@@ -668,15 +666,15 @@ define void @constrained_vector_fmul_v3f64(ptr %a) #0 {
;
; SZ13-LABEL: constrained_vector_fmul_v3f64:
; SZ13: # %bb.0: # %entry
+; SZ13-NEXT: larl %r1, .LCPI13_0
+; SZ13-NEXT: ld %f1, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI13_1
; SZ13-NEXT: vl %v0, 0(%r2), 4
-; SZ13-NEXT: larl %r3, .LCPI13_0
-; SZ13-NEXT: vl %v1, 0(%r1), 3
-; SZ13-NEXT: ld %f2, 0(%r3)
-; SZ13-NEXT: mdb %f2, 16(%r2)
-; SZ13-NEXT: vfmdb %v0, %v1, %v0
+; SZ13-NEXT: vl %v2, 0(%r1), 3
+; SZ13-NEXT: mdb %f1, 16(%r2)
+; SZ13-NEXT: vfmdb %v0, %v2, %v0
; SZ13-NEXT: vst %v0, 0(%r2), 4
-; SZ13-NEXT: std %f2, 16(%r2)
+; SZ13-NEXT: std %f1, 16(%r2)
; SZ13-NEXT: br %r14
entry:
%b = load <3 x double>, ptr %a
@@ -711,11 +709,11 @@ define <4 x double> @constrained_vector_fmul_v4f64() #0 {
; SZ13-LABEL: constrained_vector_fmul_v4f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI14_0
-; SZ13-NEXT: larl %r2, .LCPI14_1
-; SZ13-NEXT: larl %r3, .LCPI14_2
; SZ13-NEXT: vl %v0, 0(%r1), 3
-; SZ13-NEXT: vl %v1, 0(%r2), 3
-; SZ13-NEXT: vl %v2, 0(%r3), 3
+; SZ13-NEXT: larl %r1, .LCPI14_1
+; SZ13-NEXT: vl %v1, 0(%r1), 3
+; SZ13-NEXT: larl %r1, .LCPI14_2
+; SZ13-NEXT: vl %v2, 0(%r1), 3
; SZ13-NEXT: vfmdb %v26, %v1, %v0
; SZ13-NEXT: vfmdb %v24, %v1, %v2
; SZ13-NEXT: br %r14
@@ -770,9 +768,9 @@ define <2 x double> @constrained_vector_fadd_v2f64() #0 {
; SZ13-LABEL: constrained_vector_fadd_v2f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI16_0
-; SZ13-NEXT: larl %r2, .LCPI16_1
; SZ13-NEXT: vl %v0, 0(%r1), 3
-; SZ13-NEXT: vl %v1, 0(%r2), 3
+; SZ13-NEXT: larl %r1, .LCPI16_1
+; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfadb %v24, %v1, %v0
; SZ13-NEXT: br %r14
entry:
@@ -801,14 +799,14 @@ define <3 x float> @constrained_vector_fadd_v3f32() #0 {
; SZ13-LABEL: constrained_vector_fadd_v3f32:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vgbm %v0, 61440
-; SZ13-NEXT: vgmf %v1, 1, 1
-; SZ13-NEXT: vgmf %v2, 2, 8
-; SZ13-NEXT: lzer %f3
-; SZ13-NEXT: aebr %f3, %f0
+; SZ13-NEXT: vgmf %v2, 1, 1
+; SZ13-NEXT: vgmf %v3, 2, 8
+; SZ13-NEXT: lzer %f1
; SZ13-NEXT: aebr %f1, %f0
; SZ13-NEXT: aebr %f2, %f0
-; SZ13-NEXT: vmrhf %v0, %v1, %v2
-; SZ13-NEXT: vrepf %v1, %v3, 0
+; SZ13-NEXT: aebr %f3, %f0
+; SZ13-NEXT: vmrhf %v0, %v2, %v3
+; SZ13-NEXT: vrepf %v1, %v1, 0
; SZ13-NEXT: vmrhg %v24, %v0, %v1
; SZ13-NEXT: br %r14
entry:
@@ -838,15 +836,15 @@ define void @constrained_vector_fadd_v3f64(ptr %a) #0 {
;
; SZ13-LABEL: constrained_vector_fadd_v3f64:
; SZ13: # %bb.0: # %entry
+; SZ13-NEXT: larl %r1, .LCPI18_0
+; SZ13-NEXT: ld %f1, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI18_1
; SZ13-NEXT: vl %v0, 0(%r2), 4
-; SZ13-NEXT: larl %r3, .LCPI18_0
-; SZ13-NEXT: vl %v1, 0(%r1), 3
-; SZ13-NEXT: ld %f2, 0(%r3)
-; SZ13-NEXT: adb %f2, 16(%r2)
-; SZ13-NEXT: vfadb %v0, %v1, %v0
+; SZ13-NEXT: vl %v2, 0(%r1), 3
+; SZ13-NEXT: adb %f1, 16(%r2)
+; SZ13-NEXT: vfadb %v0, %v2, %v0
; SZ13-NEXT: vst %v0, 0(%r2), 4
-; SZ13-NEXT: std %f2, 16(%r2)
+; SZ13-NEXT: std %f1, 16(%r2)
; SZ13-NEXT: br %r14
entry:
%b = load <3 x double>, ptr %a
@@ -881,11 +879,11 @@ define <4 x double> @constrained_vector_fadd_v4f64() #0 {
; SZ13-LABEL: constrained_vector_fadd_v4f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI19_0
-; SZ13-NEXT: larl %r2, .LCPI19_1
-; SZ13-NEXT: larl %r3, .LCPI19_2
; SZ13-NEXT: vl %v0, 0(%r1), 3
-; SZ13-NEXT: vl %v1, 0(%r2), 3
-; SZ13-NEXT: vl %v2, 0(%r3), 3
+; SZ13-NEXT: larl %r1, .LCPI19_1
+; SZ13-NEXT: vl %v1, 0(%r1), 3
+; SZ13-NEXT: larl %r1, .LCPI19_2
+; SZ13-NEXT: vl %v2, 0(%r1), 3
; SZ13-NEXT: vfadb %v26, %v1, %v0
; SZ13-NEXT: vfadb %v24, %v1, %v2
; SZ13-NEXT: br %r14
@@ -971,16 +969,16 @@ define <3 x float> @constrained_vector_fsub_v3f32() #0 {
; SZ13-LABEL: constrained_vector_fsub_v3f32:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vgbm %v0, 61440
-; SZ13-NEXT: vgbm %v1, 61440
-; SZ13-NEXT: vgmf %v2, 1, 1
-; SZ13-NEXT: vgbm %v3, 61440
-; SZ13-NEXT: vgmf %v4, 2, 8
-; SZ13-NEXT: lzer %f5
-; SZ13-NEXT: sebr %f1, %f5
-; SZ13-NEXT: sebr %f3, %f2
-; SZ13-NEXT: sebr %f0, %f4
-; SZ13-NEXT: vmrhf %v0, %v3, %v0
-; SZ13-NEXT: vrepf %v1, %v1, 0
+; SZ13-NEXT: vgbm %v2, 61440
+; SZ13-NEXT: vgmf %v3, 1, 1
+; SZ13-NEXT: vgbm %v4, 61440
+; SZ13-NEXT: vgmf %v5, 2, 8
+; SZ13-NEXT: lzer %f1
+; SZ13-NEXT: sebr %f2, %f1
+; SZ13-NEXT: sebr %f4, %f3
+; SZ13-NEXT: sebr %f0, %f5
+; SZ13-NEXT: vmrhf %v0, %v4, %v0
+; SZ13-NEXT: vrepf %v1, %v2, 0
; SZ13-NEXT: vmrhg %v24, %v0, %v1
; SZ13-NEXT: br %r14
entry:
@@ -1051,12 +1049,12 @@ define <4 x double> @constrained_vector_fsub_v4f64() #0 {
; SZ13-LABEL: constrained_vector_fsub_v4f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI24_0
-; SZ13-NEXT: larl %r2, .LCPI24_1
; SZ13-NEXT: vl %v0, 0(%r1), 3
-; SZ13-NEXT: vl %v1, 0(%r2), 3
-; SZ13-NEXT: vgmg %v2, 12, 10
-; SZ13-NEXT: vfsdb %v26, %v2, %v0
-; SZ13-NEXT: vfsdb %v24, %v2, %v1
+; SZ13-NEXT: larl %r1, .LCPI24_1
+; SZ13-NEXT: vl %v2, 0(%r1), 3
+; SZ13-NEXT: vgmg %v1, 12, 10
+; SZ13-NEXT: vfsdb %v26, %v1, %v0
+; SZ13-NEXT: vfsdb %v24, %v1, %v2
; SZ13-NEXT: br %r14
entry:
%sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64(
@@ -1189,10 +1187,10 @@ define <4 x double> @constrained_vector_sqrt_v4f64() #0 {
; SZ13-LABEL: constrained_vector_sqrt_v4f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI29_0
-; SZ13-NEXT: larl %r2, .LCPI29_1
; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfsqdb %v26, %v0
-; SZ13-NEXT: vl %v1, 0(%r2), 3
+; SZ13-NEXT: larl %r1, .LCPI29_1
+; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfsqdb %v24, %v1
; SZ13-NEXT: br %r14
entry:
@@ -1228,9 +1226,9 @@ define <1 x float> @constrained_vector_pow_v1f32() #0 {
; SZ13-NEXT: aghi %r15, -160
; SZ13-NEXT: .cfi_def_cfa_offset 320
; SZ13-NEXT: larl %r1, .LCPI30_0
-; SZ13-NEXT: larl %r2, .LCPI30_1
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI30_1
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, powf at PLT
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
; SZ13-NEXT: vlr %v24, %v0
@@ -1284,10 +1282,10 @@ define <2 x double> @constrained_vector_pow_v2f64() #0 {
; SZ13-NEXT: .cfi_def_cfa_offset 344
; SZ13-NEXT: std %f8, 176(%r15) # 8-byte Spill
; SZ13-NEXT: .cfi_offset %f8, -168
-; SZ13-NEXT: larl %r2, .LCPI31_1
; SZ13-NEXT: larl %r1, .LCPI31_0
-; SZ13-NEXT: ld %f8, 0(%r2)
; SZ13-NEXT: ld %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI31_1
+; SZ13-NEXT: ld %f8, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, pow at PLT
; SZ13-NEXT: larl %r1, .LCPI31_2
@@ -1360,10 +1358,10 @@ define <3 x float> @constrained_vector_pow_v3f32() #0 {
; SZ13-NEXT: .cfi_def_cfa_offset 360
; SZ13-NEXT: std %f8, 192(%r15) # 8-byte Spill
; SZ13-NEXT: .cfi_offset %f8, -168
-; SZ13-NEXT: larl %r2, .LCPI32_1
; SZ13-NEXT: larl %r1, .LCPI32_0
-; SZ13-NEXT: lde %f8, 0(%r2)
; SZ13-NEXT: lde %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI32_1
+; SZ13-NEXT: lde %f8, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, powf at PLT
; SZ13-NEXT: larl %r1, .LCPI32_2
@@ -1452,10 +1450,10 @@ define void @constrained_vector_pow_v3f64(ptr %a) #0 {
; SZ13-NEXT: .cfi_offset %f8, -168
; SZ13-NEXT: .cfi_offset %f9, -176
; SZ13-NEXT: larl %r1, .LCPI33_0
-; SZ13-NEXT: ld %f8, 0(%r1)
+; SZ13-NEXT: ld %f9, 0(%r1)
; SZ13-NEXT: vl %v0, 0(%r2), 4
-; SZ13-NEXT: ld %f9, 16(%r2)
-; SZ13-NEXT: ldr %f2, %f8
+; SZ13-NEXT: ld %f8, 16(%r2)
+; SZ13-NEXT: ldr %f2, %f9
; SZ13-NEXT: lgr %r13, %r2
; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
; SZ13-NEXT: # kill: def $f0d killed $f0d killed $v0
@@ -1463,7 +1461,7 @@ define void @constrained_vector_pow_v3f64(ptr %a) #0 {
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: vl %v0, 176(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: ldr %f2, %f8
+; SZ13-NEXT: ldr %f2, %f9
; SZ13-NEXT: vrepg %v0, %v0, 1
; SZ13-NEXT: # kill: def $f0d killed $f0d killed $v0
; SZ13-NEXT: brasl %r14, pow at PLT
@@ -1471,8 +1469,8 @@ define void @constrained_vector_pow_v3f64(ptr %a) #0 {
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vmrhg %v0, %v1, %v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f9
-; SZ13-NEXT: ldr %f2, %f8
+; SZ13-NEXT: ldr %f0, %f8
+; SZ13-NEXT: ldr %f2, %f9
; SZ13-NEXT: brasl %r14, pow at PLT
; SZ13-NEXT: mvc 0(16,%r13), 160(%r15) # 16-byte Folded Reload
; SZ13-NEXT: ld %f8, 200(%r15) # 8-byte Reload
@@ -1550,10 +1548,10 @@ define <4 x double> @constrained_vector_pow_v4f64() #0 {
; SZ13-NEXT: .cfi_def_cfa_offset 360
; SZ13-NEXT: std %f8, 192(%r15) # 8-byte Spill
; SZ13-NEXT: .cfi_offset %f8, -168
-; SZ13-NEXT: larl %r2, .LCPI34_1
; SZ13-NEXT: larl %r1, .LCPI34_0
-; SZ13-NEXT: ld %f8, 0(%r2)
; SZ13-NEXT: ld %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI34_1
+; SZ13-NEXT: ld %f8, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, pow at PLT
; SZ13-NEXT: larl %r1, .LCPI34_2
@@ -1562,13 +1560,12 @@ define <4 x double> @constrained_vector_pow_v4f64() #0 {
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, pow at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI34_3
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI34_3
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, pow at PLT
; SZ13-NEXT: larl %r1, .LCPI34_4
@@ -1822,13 +1819,12 @@ define void @constrained_vector_powi_v3f64(ptr %a) #0 {
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: lghi %r2, 3
; SZ13-NEXT: brasl %r14, __powidf2 at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI38_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI38_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: lghi %r2, 3
; SZ13-NEXT: brasl %r14, __powidf2 at PLT
; SZ13-NEXT: mvc 0(16,%r13), 160(%r15) # 16-byte Folded Reload
@@ -1908,13 +1904,12 @@ define <4 x double> @constrained_vector_powi_v4f64() #0 {
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: lghi %r2, 3
; SZ13-NEXT: brasl %r14, __powidf2 at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI39_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI39_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: lghi %r2, 3
; SZ13-NEXT: brasl %r14, __powidf2 at PLT
; SZ13-NEXT: larl %r1, .LCPI39_3
@@ -2228,13 +2223,12 @@ define <4 x double> @constrained_vector_sin_v4f64() #0 {
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, sin at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI44_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI44_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, sin at PLT
; SZ13-NEXT: larl %r1, .LCPI44_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -2545,13 +2539,12 @@ define <4 x double> @constrained_vector_cos_v4f64() #0 {
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, cos at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI49_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI49_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, cos at PLT
; SZ13-NEXT: larl %r1, .LCPI49_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -2862,13 +2855,12 @@ define <4 x double> @constrained_vector_exp_v4f64() #0 {
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, exp at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI54_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI54_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, exp at PLT
; SZ13-NEXT: larl %r1, .LCPI54_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -3179,13 +3171,12 @@ define <4 x double> @constrained_vector_exp2_v4f64() #0 {
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, exp2 at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI59_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI59_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, exp2 at PLT
; SZ13-NEXT: larl %r1, .LCPI59_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -3496,13 +3487,12 @@ define <4 x double> @constrained_vector_log_v4f64() #0 {
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, log at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI64_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI64_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, log at PLT
; SZ13-NEXT: larl %r1, .LCPI64_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -3813,13 +3803,12 @@ define <4 x double> @constrained_vector_log10_v4f64() #0 {
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, log10 at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI69_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI69_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, log10 at PLT
; SZ13-NEXT: larl %r1, .LCPI69_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -4130,13 +4119,12 @@ define <4 x double> @constrained_vector_log2_v4f64() #0 {
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, log2 at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI74_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI74_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, log2 at PLT
; SZ13-NEXT: larl %r1, .LCPI74_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -4556,9 +4544,9 @@ define <1 x float> @constrained_vector_maxnum_v1f32() #0 {
; SZ13-NEXT: aghi %r15, -160
; SZ13-NEXT: .cfi_def_cfa_offset 320
; SZ13-NEXT: larl %r1, .LCPI85_0
-; SZ13-NEXT: larl %r2, .LCPI85_1
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI85_1
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmaxf at PLT
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
; SZ13-NEXT: vlr %v24, %v0
@@ -4606,16 +4594,16 @@ define <2 x double> @constrained_vector_maxnum_v2f64() #0 {
; SZ13-NEXT: aghi %r15, -176
; SZ13-NEXT: .cfi_def_cfa_offset 336
; SZ13-NEXT: larl %r1, .LCPI86_0
-; SZ13-NEXT: larl %r2, .LCPI86_1
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI86_1
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmax at PLT
; SZ13-NEXT: larl %r1, .LCPI86_2
-; SZ13-NEXT: larl %r2, .LCPI86_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI86_3
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmax at PLT
; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -4679,10 +4667,10 @@ define <3 x float> @constrained_vector_maxnum_v3f32() #0 {
; SZ13-NEXT: .cfi_def_cfa_offset 360
; SZ13-NEXT: std %f8, 192(%r15) # 8-byte Spill
; SZ13-NEXT: .cfi_offset %f8, -168
-; SZ13-NEXT: larl %r2, .LCPI87_1
; SZ13-NEXT: larl %r1, .LCPI87_0
-; SZ13-NEXT: lde %f8, 0(%r2)
; SZ13-NEXT: lde %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI87_1
+; SZ13-NEXT: lde %f8, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, fmaxf at PLT
; SZ13-NEXT: larl %r1, .LCPI87_2
@@ -4692,11 +4680,11 @@ define <3 x float> @constrained_vector_maxnum_v3f32() #0 {
; SZ13-NEXT: ldr %f0, %f8
; SZ13-NEXT: brasl %r14, fmaxf at PLT
; SZ13-NEXT: larl %r1, .LCPI87_3
-; SZ13-NEXT: larl %r2, .LCPI87_4
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI87_4
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmaxf at PLT
; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
@@ -4777,8 +4765,8 @@ define void @constrained_vector_log10_maxnum_v3f64(ptr %a) #0 {
; SZ13-NEXT: larl %r1, .LCPI88_1
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: vl %v0, 176(%r15), 3 # 16-byte Reload
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: vrepg %v0, %v0, 1
; SZ13-NEXT: # kill: def $f0d killed $f0d killed $v0
; SZ13-NEXT: brasl %r14, fmax at PLT
@@ -4862,33 +4850,32 @@ define <4 x double> @constrained_vector_maxnum_v4f64() #0 {
; SZ13-NEXT: aghi %r15, -192
; SZ13-NEXT: .cfi_def_cfa_offset 352
; SZ13-NEXT: larl %r1, .LCPI89_0
-; SZ13-NEXT: larl %r2, .LCPI89_1
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI89_1
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmax at PLT
; SZ13-NEXT: larl %r1, .LCPI89_2
-; SZ13-NEXT: larl %r2, .LCPI89_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI89_3
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmax at PLT
-; SZ13-NEXT: vl %v3, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI89_4
-; SZ13-NEXT: larl %r2, .LCPI89_5
-; SZ13-NEXT: ld %f1, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v3
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI89_4
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI89_5
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmax at PLT
; SZ13-NEXT: larl %r1, .LCPI89_6
-; SZ13-NEXT: larl %r2, .LCPI89_7
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI89_7
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmax at PLT
; SZ13-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
; SZ13-NEXT: vl %v24, 160(%r15), 3 # 16-byte Reload
@@ -4930,9 +4917,9 @@ define <1 x float> @constrained_vector_minnum_v1f32() #0 {
; SZ13-NEXT: aghi %r15, -160
; SZ13-NEXT: .cfi_def_cfa_offset 320
; SZ13-NEXT: larl %r1, .LCPI90_0
-; SZ13-NEXT: larl %r2, .LCPI90_1
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI90_1
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fminf at PLT
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
; SZ13-NEXT: vlr %v24, %v0
@@ -4980,16 +4967,16 @@ define <2 x double> @constrained_vector_minnum_v2f64() #0 {
; SZ13-NEXT: aghi %r15, -176
; SZ13-NEXT: .cfi_def_cfa_offset 336
; SZ13-NEXT: larl %r1, .LCPI91_0
-; SZ13-NEXT: larl %r2, .LCPI91_1
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI91_1
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmin at PLT
; SZ13-NEXT: larl %r1, .LCPI91_2
-; SZ13-NEXT: larl %r2, .LCPI91_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI91_3
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmin at PLT
; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -5053,10 +5040,10 @@ define <3 x float> @constrained_vector_minnum_v3f32() #0 {
; SZ13-NEXT: .cfi_def_cfa_offset 360
; SZ13-NEXT: std %f8, 192(%r15) # 8-byte Spill
; SZ13-NEXT: .cfi_offset %f8, -168
-; SZ13-NEXT: larl %r2, .LCPI92_1
; SZ13-NEXT: larl %r1, .LCPI92_0
-; SZ13-NEXT: lde %f8, 0(%r2)
; SZ13-NEXT: lde %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI92_1
+; SZ13-NEXT: lde %f8, 0(%r1)
; SZ13-NEXT: ldr %f2, %f8
; SZ13-NEXT: brasl %r14, fminf at PLT
; SZ13-NEXT: larl %r1, .LCPI92_2
@@ -5066,11 +5053,11 @@ define <3 x float> @constrained_vector_minnum_v3f32() #0 {
; SZ13-NEXT: ldr %f0, %f8
; SZ13-NEXT: brasl %r14, fminf at PLT
; SZ13-NEXT: larl %r1, .LCPI92_3
-; SZ13-NEXT: larl %r2, .LCPI92_4
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI92_4
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fminf at PLT
; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
@@ -5145,10 +5132,10 @@ define void @constrained_vector_minnum_v3f64(ptr %a) #0 {
; SZ13-NEXT: .cfi_offset %f8, -168
; SZ13-NEXT: .cfi_offset %f9, -176
; SZ13-NEXT: larl %r1, .LCPI93_0
-; SZ13-NEXT: ld %f8, 0(%r1)
+; SZ13-NEXT: ld %f9, 0(%r1)
; SZ13-NEXT: vl %v0, 0(%r2), 4
-; SZ13-NEXT: ld %f9, 16(%r2)
-; SZ13-NEXT: ldr %f2, %f8
+; SZ13-NEXT: ld %f8, 16(%r2)
+; SZ13-NEXT: ldr %f2, %f9
; SZ13-NEXT: lgr %r13, %r2
; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
; SZ13-NEXT: # kill: def $f0d killed $f0d killed $v0
@@ -5156,7 +5143,7 @@ define void @constrained_vector_minnum_v3f64(ptr %a) #0 {
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: vl %v0, 176(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: ldr %f2, %f8
+; SZ13-NEXT: ldr %f2, %f9
; SZ13-NEXT: vrepg %v0, %v0, 1
; SZ13-NEXT: # kill: def $f0d killed $f0d killed $v0
; SZ13-NEXT: brasl %r14, fmin at PLT
@@ -5164,8 +5151,8 @@ define void @constrained_vector_minnum_v3f64(ptr %a) #0 {
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vmrhg %v0, %v1, %v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f9
-; SZ13-NEXT: ldr %f2, %f8
+; SZ13-NEXT: ldr %f0, %f8
+; SZ13-NEXT: ldr %f2, %f9
; SZ13-NEXT: brasl %r14, fmin at PLT
; SZ13-NEXT: mvc 0(16,%r13), 160(%r15) # 16-byte Folded Reload
; SZ13-NEXT: ld %f8, 200(%r15) # 8-byte Reload
@@ -5240,33 +5227,32 @@ define <4 x double> @constrained_vector_minnum_v4f64() #0 {
; SZ13-NEXT: aghi %r15, -192
; SZ13-NEXT: .cfi_def_cfa_offset 352
; SZ13-NEXT: larl %r1, .LCPI94_0
-; SZ13-NEXT: larl %r2, .LCPI94_1
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI94_1
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmin at PLT
; SZ13-NEXT: larl %r1, .LCPI94_2
-; SZ13-NEXT: larl %r2, .LCPI94_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI94_3
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmin at PLT
-; SZ13-NEXT: vl %v3, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI94_4
-; SZ13-NEXT: larl %r2, .LCPI94_5
-; SZ13-NEXT: ld %f1, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v3
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI94_4
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI94_5
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmin at PLT
; SZ13-NEXT: larl %r1, .LCPI94_6
-; SZ13-NEXT: larl %r2, .LCPI94_7
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI94_7
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, fmin at PLT
; SZ13-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
; SZ13-NEXT: vl %v24, 160(%r15), 3 # 16-byte Reload
@@ -5320,9 +5306,9 @@ define <2 x float> @constrained_vector_fptrunc_v2f64() #0 {
; SZ13-LABEL: constrained_vector_fptrunc_v2f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI96_0
-; SZ13-NEXT: larl %r2, .LCPI96_1
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f1, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI96_1
+; SZ13-NEXT: ld %f1, 0(%r1)
; SZ13-NEXT: ledbra %f0, 0, %f0, 0
; SZ13-NEXT: ledbra %f1, 0, %f1, 0
; SZ13-NEXT: vmrhf %v0, %v1, %v0
@@ -5356,15 +5342,15 @@ define void @constrained_vector_fptrunc_v3f64(ptr %src, ptr %dest) #0 {
;
; SZ13-LABEL: constrained_vector_fptrunc_v3f64:
; SZ13: # %bb.0: # %entry
-; SZ13-NEXT: vl %v0, 0(%r2), 4
-; SZ13-NEXT: ld %f1, 16(%r2)
-; SZ13-NEXT: vledb %v0, %v0, 0, 0
+; SZ13-NEXT: vl %v1, 0(%r2), 4
+; SZ13-NEXT: ld %f0, 16(%r2)
+; SZ13-NEXT: vledb %v1, %v1, 0, 0
; SZ13-NEXT: larl %r1, .LCPI97_0
-; SZ13-NEXT: ledbra %f1, 0, %f1, 0
+; SZ13-NEXT: ledbra %f0, 0, %f0, 0
; SZ13-NEXT: vl %v2, 0(%r1), 3
-; SZ13-NEXT: vperm %v0, %v0, %v0, %v2
-; SZ13-NEXT: ste %f1, 8(%r3)
-; SZ13-NEXT: vsteg %v0, 0(%r3), 0
+; SZ13-NEXT: vperm %v1, %v1, %v1, %v2
+; SZ13-NEXT: ste %f0, 8(%r3)
+; SZ13-NEXT: vsteg %v1, 0(%r3), 0
; SZ13-NEXT: br %r14
entry:
%b = load <3 x double>, ptr %src
@@ -5396,13 +5382,13 @@ define <4 x float> @constrained_vector_fptrunc_v4f64() #0 {
; SZ13-LABEL: constrained_vector_fptrunc_v4f64:
; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI98_0
-; SZ13-NEXT: larl %r2, .LCPI98_1
-; SZ13-NEXT: larl %r3, .LCPI98_2
-; SZ13-NEXT: larl %r4, .LCPI98_3
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f1, 0(%r2)
-; SZ13-NEXT: ld %f2, 0(%r3)
-; SZ13-NEXT: ld %f3, 0(%r4)
+; SZ13-NEXT: larl %r1, .LCPI98_1
+; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI98_2
+; SZ13-NEXT: ld %f2, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI98_3
+; SZ13-NEXT: ld %f3, 0(%r1)
; SZ13-NEXT: ledbra %f0, 0, %f0, 0
; SZ13-NEXT: ledbra %f1, 0, %f1, 0
; SZ13-NEXT: ledbra %f2, 0, %f2, 0
@@ -6685,13 +6671,12 @@ define <4 x double> @constrained_vector_tan_v4f64() #0 {
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, tan at PLT
-; SZ13-NEXT: vl %v2, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI127_2
-; SZ13-NEXT: ld %f1, 0(%r1)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v2
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI127_2
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: brasl %r14, tan at PLT
; SZ13-NEXT: larl %r1, .LCPI127_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -6737,9 +6722,9 @@ define <1 x float> @constrained_vector_atan2_v1f32() #0 {
; SZ13-NEXT: aghi %r15, -160
; SZ13-NEXT: .cfi_def_cfa_offset 320
; SZ13-NEXT: larl %r1, .LCPI128_0
-; SZ13-NEXT: larl %r2, .LCPI128_1
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI128_1
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2f at PLT
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
; SZ13-NEXT: vlr %v24, %v0
@@ -6789,16 +6774,16 @@ define <2 x double> @constrained_vector_atan2_v2f64() #0 {
; SZ13-NEXT: aghi %r15, -176
; SZ13-NEXT: .cfi_def_cfa_offset 336
; SZ13-NEXT: larl %r1, .LCPI129_0
-; SZ13-NEXT: larl %r2, .LCPI129_1
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI129_1
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2 at PLT
; SZ13-NEXT: larl %r1, .LCPI129_2
-; SZ13-NEXT: larl %r2, .LCPI129_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI129_3
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2 at PLT
; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
@@ -6860,23 +6845,23 @@ define <3 x float> @constrained_vector_atan2_v3f32() #0 {
; SZ13-NEXT: aghi %r15, -192
; SZ13-NEXT: .cfi_def_cfa_offset 352
; SZ13-NEXT: larl %r1, .LCPI130_0
-; SZ13-NEXT: larl %r2, .LCPI130_1
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI130_1
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2f at PLT
; SZ13-NEXT: larl %r1, .LCPI130_2
-; SZ13-NEXT: larl %r2, .LCPI130_3
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI130_3
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2f at PLT
; SZ13-NEXT: larl %r1, .LCPI130_4
-; SZ13-NEXT: larl %r2, .LCPI130_5
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: lde %f0, 0(%r1)
-; SZ13-NEXT: lde %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI130_5
+; SZ13-NEXT: lde %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2f at PLT
; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0s killed $f0s def $v0
@@ -7054,33 +7039,32 @@ define <4 x double> @constrained_vector_atan2_v4f64() #0 {
; SZ13-NEXT: aghi %r15, -192
; SZ13-NEXT: .cfi_def_cfa_offset 352
; SZ13-NEXT: larl %r1, .LCPI132_0
-; SZ13-NEXT: larl %r2, .LCPI132_1
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI132_1
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2 at PLT
; SZ13-NEXT: larl %r1, .LCPI132_2
-; SZ13-NEXT: larl %r2, .LCPI132_3
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI132_3
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2 at PLT
-; SZ13-NEXT: vl %v3, 160(%r15), 3 # 16-byte Reload
-; SZ13-NEXT: larl %r1, .LCPI132_4
-; SZ13-NEXT: larl %r2, .LCPI132_5
-; SZ13-NEXT: ld %f1, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
-; SZ13-NEXT: vmrhg %v0, %v0, %v3
+; SZ13-NEXT: vmrhg %v0, %v0, %v1
+; SZ13-NEXT: larl %r1, .LCPI132_4
; SZ13-NEXT: vst %v0, 160(%r15), 3 # 16-byte Spill
-; SZ13-NEXT: ldr %f0, %f1
+; SZ13-NEXT: ld %f0, 0(%r1)
+; SZ13-NEXT: larl %r1, .LCPI132_5
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2 at PLT
; SZ13-NEXT: larl %r1, .LCPI132_6
-; SZ13-NEXT: larl %r2, .LCPI132_7
; SZ13-NEXT: # kill: def $f0d killed $f0d def $v0
; SZ13-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
; SZ13-NEXT: ld %f0, 0(%r1)
-; SZ13-NEXT: ld %f2, 0(%r2)
+; SZ13-NEXT: larl %r1, .LCPI132_7
+; SZ13-NEXT: ld %f2, 0(%r1)
; SZ13-NEXT: brasl %r14, atan2 at PLT
; SZ13-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
; SZ13-NEXT: vl %v24, 160(%r15), 3 # 16-byte Reload
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