[llvm] [AArch64] Fix correctness of FORM_TRANSPOSED_REG_TUPLE expansions (PR #205528)

Sander de Smalen via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 29 05:15:34 PDT 2026


================
@@ -1282,26 +1282,114 @@ bool AArch64ExpandPseudoImpl::expandMultiVecPseudo(
   return true;
 }
 
+struct Copy {
+  Register Dst;
+  Register Src;
+  int SrcTupleIdx = -1;
+};
+
 bool AArch64ExpandPseudoImpl::expandFormTuplePseudo(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI, unsigned Size) {
   assert((Size == 2 || Size == 4) && "Invalid Tuple Size");
-  MachineInstr &MI = *MBBI;
-  Register ReturnTuple = MI.getOperand(0).getReg();
 
   const TargetRegisterInfo *TRI =
       MBB.getParent()->getSubtarget().getRegisterInfo();
+
+  MachineInstr &MI = *MBBI;
+  DebugLoc DL = MI.getDebugLoc();
+  Register Tuple = MI.getOperand(0).getReg();
+
+  // Collect the copies required to form the tuple. Count if any tuple members
+  // appear as operands to the FORM_TRANSPOSED_REG_TUPLE. If a destination
+  // also appears as a source operand, we can't write to that register until
+  // we've handled the other copies that use it.
+
+  Copy Copies[4] = {};
+  unsigned Users[4] = {};
+
+  for (unsigned I = 0; I < Size; ++I) {
+    Register Dst = TRI->getSubReg(Tuple, AArch64::zsub0 + I);
+    Register Src = MI.getOperand(I + 1).getReg();
+
+    Copies[I] = {Dst, Src};
+
+    if (Dst != Src && TRI->isSubRegister(Tuple, Src)) {
+      int SrcTupleIdx = TRI->getSubRegIndex(Tuple, Src) - AArch64::zsub0;
+      Copies[I].SrcTupleIdx = SrcTupleIdx;
+      ++Users[SrcTupleIdx];
----------------
sdesmalen-arm wrote:

>> i.e., where the source register is in the destination tuple and the destination sub-reg is in source tuple
> This does not imply a swap is required (this exists in all cases that need reordering).

Can you give a counter example? The example I was thinking of was e.g. `z0, z1, z2 = pseudo z2, z1, z0`, where source register `z2` is in the destination tuple and `z0` (the corresponding destination sub-reg) is also an operand in the source tuple. This cannot be covered by reordering, but must be covered by swaps.

https://github.com/llvm/llvm-project/pull/205528


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