[llvm] [X86] Move more vector.reduce.add subvector pattern tests to PhaseOrdering/X86/horizontal-reduce-add.ll (PR #206467)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 29 05:14:04 PDT 2026
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/206467
CodeGen test coverage is already in vector-reduce-add-subvector.ll
>From 7d0e81150cd323fa7051911a1429f834ae7beb8f Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 29 Jun 2026 13:12:57 +0100
Subject: [PATCH] [X86] Move more vector.reduce.add subvector pattern tests to
PhaseOrdering/X86/horizontal-reduce-add.ll
CodeGen test coverage is already in vector-reduce-add-subvector.ll
---
llvm/test/CodeGen/X86/phaddsub-extract.ll | 86 -------------------
.../X86/horizontal-reduce-add.ll | 32 +++++++
2 files changed, 32 insertions(+), 86 deletions(-)
diff --git a/llvm/test/CodeGen/X86/phaddsub-extract.ll b/llvm/test/CodeGen/X86/phaddsub-extract.ll
index b38a10c7e4263..4ddb8a9494894 100644
--- a/llvm/test/CodeGen/X86/phaddsub-extract.ll
+++ b/llvm/test/CodeGen/X86/phaddsub-extract.ll
@@ -1669,92 +1669,6 @@ define i32 @extract_extract01_v4i32_add_i32_uses3(<4 x i32> %x, ptr %p1, ptr %p2
; PR33758: https://bugs.llvm.org/show_bug.cgi?id=33758
-define i32 @partial_reduction_add_v8i32(<8 x i32> %x) {
-; SSE3-SLOW-LABEL: partial_reduction_add_v8i32:
-; SSE3-SLOW: # %bb.0:
-; SSE3-SLOW-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; SSE3-SLOW-NEXT: paddd %xmm0, %xmm1
-; SSE3-SLOW-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; SSE3-SLOW-NEXT: paddd %xmm1, %xmm0
-; SSE3-SLOW-NEXT: movd %xmm0, %eax
-; SSE3-SLOW-NEXT: retq
-;
-; SSE3-FAST-LABEL: partial_reduction_add_v8i32:
-; SSE3-FAST: # %bb.0:
-; SSE3-FAST-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; SSE3-FAST-NEXT: paddd %xmm0, %xmm1
-; SSE3-FAST-NEXT: phaddd %xmm1, %xmm1
-; SSE3-FAST-NEXT: movd %xmm1, %eax
-; SSE3-FAST-NEXT: retq
-;
-; AVX-SLOW-LABEL: partial_reduction_add_v8i32:
-; AVX-SLOW: # %bb.0:
-; AVX-SLOW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX-SLOW-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-SLOW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX-SLOW-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-SLOW-NEXT: vmovd %xmm0, %eax
-; AVX-SLOW-NEXT: vzeroupper
-; AVX-SLOW-NEXT: retq
-;
-; AVX-FAST-LABEL: partial_reduction_add_v8i32:
-; AVX-FAST: # %bb.0:
-; AVX-FAST-NEXT: vphaddd %xmm0, %xmm0, %xmm0
-; AVX-FAST-NEXT: vphaddd %xmm0, %xmm0, %xmm0
-; AVX-FAST-NEXT: vmovd %xmm0, %eax
-; AVX-FAST-NEXT: vzeroupper
-; AVX-FAST-NEXT: retq
- %x23 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
- %x0213 = add <8 x i32> %x, %x23
- %x13 = shufflevector <8 x i32> %x0213, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
- %x0123 = add <8 x i32> %x0213, %x13
- %r = extractelement <8 x i32> %x0123, i32 0
- ret i32 %r
-}
-
-define i32 @partial_reduction_add_v16i32(<16 x i32> %x) {
-; SSE3-SLOW-LABEL: partial_reduction_add_v16i32:
-; SSE3-SLOW: # %bb.0:
-; SSE3-SLOW-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; SSE3-SLOW-NEXT: paddd %xmm0, %xmm1
-; SSE3-SLOW-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; SSE3-SLOW-NEXT: paddd %xmm1, %xmm0
-; SSE3-SLOW-NEXT: movd %xmm0, %eax
-; SSE3-SLOW-NEXT: retq
-;
-; SSE3-FAST-LABEL: partial_reduction_add_v16i32:
-; SSE3-FAST: # %bb.0:
-; SSE3-FAST-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; SSE3-FAST-NEXT: paddd %xmm0, %xmm1
-; SSE3-FAST-NEXT: phaddd %xmm1, %xmm1
-; SSE3-FAST-NEXT: movd %xmm1, %eax
-; SSE3-FAST-NEXT: retq
-;
-; AVX-SLOW-LABEL: partial_reduction_add_v16i32:
-; AVX-SLOW: # %bb.0:
-; AVX-SLOW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX-SLOW-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-SLOW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX-SLOW-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-SLOW-NEXT: vmovd %xmm0, %eax
-; AVX-SLOW-NEXT: vzeroupper
-; AVX-SLOW-NEXT: retq
-;
-; AVX-FAST-LABEL: partial_reduction_add_v16i32:
-; AVX-FAST: # %bb.0:
-; AVX-FAST-NEXT: vphaddd %xmm0, %xmm0, %xmm0
-; AVX-FAST-NEXT: vphaddd %xmm0, %xmm0, %xmm0
-; AVX-FAST-NEXT: vmovd %xmm0, %eax
-; AVX-FAST-NEXT: vzeroupper
-; AVX-FAST-NEXT: retq
- %x23 = shufflevector <16 x i32> %x, <16 x i32> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
- %x0213 = add <16 x i32> %x, %x23
- %x13 = shufflevector <16 x i32> %x0213, <16 x i32> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
- %x0123 = add <16 x i32> %x0213, %x13
- %r = extractelement <16 x i32> %x0123, i32 0
- ret i32 %r
-}
-
define i32 @partial_reduction_sub_v8i32(<8 x i32> %x) {
; SSE3-SLOW-LABEL: partial_reduction_sub_v8i32:
; SSE3-SLOW: # %bb.0:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-add.ll b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-add.ll
index cf456f86b4ac5..5487d6fce8271 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-add.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-add.ll
@@ -102,3 +102,35 @@ define i32 @PR37890_v16i32(<16 x i32> %a) {
%e = extractelement <2 x i32> %sum3, i32 0
ret i32 %e
}
+
+; PR33758: https://bugs.llvm.org/show_bug.cgi?id=33758
+
+define i32 @partial_reduction_add_v8i32(<8 x i32> %x) {
+; CHECK-LABEL: define i32 @partial_reduction_add_v8i32(
+; CHECK-SAME: <8 x i32> [[X:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[X]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %x23 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %x0213 = add <8 x i32> %x, %x23
+ %x13 = shufflevector <8 x i32> %x0213, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %x0123 = add <8 x i32> %x0213, %x13
+ %r = extractelement <8 x i32> %x0123, i32 0
+ ret i32 %r
+}
+
+define i32 @partial_reduction_add_v16i32(<16 x i32> %x) {
+; CHECK-LABEL: define i32 @partial_reduction_add_v16i32(
+; CHECK-SAME: <16 x i32> [[X:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[X]], <16 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %x23 = shufflevector <16 x i32> %x, <16 x i32> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %x0213 = add <16 x i32> %x, %x23
+ %x13 = shufflevector <16 x i32> %x0213, <16 x i32> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %x0123 = add <16 x i32> %x0213, %x13
+ %r = extractelement <16 x i32> %x0123, i32 0
+ ret i32 %r
+}
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