[llvm] [PeepholeOptimizer] Add REG_SEQUENCE subregister use folding (PR #205795)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 29 04:39:03 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Frederik Harwath (frederik-h)
<details>
<summary>Changes</summary>
Rewrite uses of REG_SEQUENCE subregisters to directly use source registers when safe. This eliminates unnecessary copies and can enable optimizations in subsequent passes that cannot handle REG_SEQUENCE instructions (e.g. AMDGPU si-peephole-sdwa). A new target isOperandLegal target hook (using the preexisting function on AMDGPU) is added to verify register class constraints.
---
Patch is 709.57 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/205795.diff
69 Files Affected:
- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+15)
- (modified) llvm/lib/CodeGen/PeepholeOptimizer.cpp (+154)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+10-3)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll (+144-144)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll (+19-19)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll (+70-72)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/and_or.ll (+30-28)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll (+41-31)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll (+20-10)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll (+20-10)
- (modified) llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll (+22-22)
- (modified) llvm/test/CodeGen/AMDGPU/div_v2i128.ll (+106-106)
- (modified) llvm/test/CodeGen/AMDGPU/ds_write2.ll (+22-24)
- (modified) llvm/test/CodeGen/AMDGPU/frem.ll (+59-61)
- (modified) llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll (+6-2)
- (modified) llvm/test/CodeGen/AMDGPU/indirect-call.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll (+4-8)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll (+3-6)
- (modified) llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll (+29-27)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll (+9-8)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll (+8-7)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll (+12-10)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll (+14-7)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll (+4-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll (+20-10)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll (+16-8)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll (+24-12)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll (+8-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll (+24-12)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll (+8-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll (+10-5)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll (+88-180)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i1.ll (+243-261)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i16.ll (+56-56)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i8.ll (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/load-local-i16.ll (+324-324)
- (modified) llvm/test/CodeGen/AMDGPU/memmove-var-size.ll (+169-167)
- (modified) llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll (+81-146)
- (modified) llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll (+108-68)
- (modified) llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll (+108-68)
- (modified) llvm/test/CodeGen/AMDGPU/optimize-compare.mir (+1-3)
- (modified) llvm/test/CodeGen/AMDGPU/or3.ll (+2-14)
- (modified) llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir (+2-11)
- (modified) llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir (-5)
- (added) llvm/test/CodeGen/AMDGPU/peephole-regseq-fold.mir (+309)
- (added) llvm/test/CodeGen/AMDGPU/sdwa-peephole-reg-sequence.mir (+114)
- (modified) llvm/test/CodeGen/AMDGPU/sibling-call.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll (+900-1155)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll (+10-9)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll (+49-41)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll (+12-11)
- (modified) llvm/test/CodeGen/Thumb2/mve-clmul.ll (+207-208)
- (modified) llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll (+16-24)
- (modified) llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll (+26-37)
- (modified) llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll (+4-6)
- (modified) llvm/test/CodeGen/Thumb2/mve-shuffle-fp16.ll (+12-11)
- (modified) llvm/test/CodeGen/Thumb2/mve-shuffle.ll (+31-29)
- (modified) llvm/test/CodeGen/Thumb2/mve-vabdus.ll (+11-11)
- (modified) llvm/test/CodeGen/Thumb2/mve-vld3.ll (+71-66)
- (modified) llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll (+10-18)
- (added) llvm/test/CodeGen/X86/peephole-reg-sequence.mir (+28)
- (modified) llvm/utils/git/code-format-helper.py (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 03f3bf26d0608..d0bd66fce7508 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -614,6 +614,21 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
: RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
};
+ /// Check if \p MO can be used as operand \p OpIdx for \p MI.
+ ///
+ /// \param MI The instruction to validate against.
+ /// \param OpIdx The operand position to check.
+ /// \param MO The operand to validate. Does not need to have a parent.
+ /// If nullptr, checks MI.getOperand(OpIdx).
+ ///
+ /// \returns true if the operand would be legal at the given position.
+ ///
+ /// \note The generic implementation returns true.
+ virtual bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
+ const MachineOperand *MO) const {
+ return true;
+ }
+
/// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
/// and \p DefIdx.
/// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index ec8a0336a2105..d9c3823be5e32 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -63,6 +63,21 @@
// =>
// b = bitcast A <-- cross-bank copy
// C = copy A <-- same-bank copy
+//
+// - Fold REG_SEQUENCE subregister uses:
+//
+// Replace uses of subregisters of registers defined by
+// REG_SEQUENCE instructions with direct uses of the source
+// registers.
+//
+// Example:
+// A = REG_SEQUENCE B, sub0, C, sub1
+// D = ADD A.sub0, E
+// =>
+// A = REG_SEQUENCE B, sub0, C, sub1
+// D = ADD B, E
+//
+// Eliminate the REG_SEQUENCE if all uses are folded.
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/PeepholeOptimizer.h"
@@ -121,6 +136,10 @@ static cl::opt<bool> DisableNAPhysCopyOpt(
"disable-non-allocatable-phys-copy-opt", cl::Hidden, cl::init(false),
cl::desc("Disable non-allocatable physical register copy optimization"));
+static cl::opt<bool> DisablePeepholeRegSeqFold(
+ "disable-peephole-regseq-fold", cl::Hidden, cl::init(false),
+ cl::desc("Disable REG_SEQUENCE subregister use folding"));
+
// Limit the number of PHI instructions to process
// in PeepholeOptimizer::getNextSource.
static cl::opt<unsigned>
@@ -142,6 +161,10 @@ STATISTIC(NumSelects, "Number of selects optimized");
STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
STATISTIC(NumNAPhysCopies, "Number of non-allocatable physical copies removed");
+STATISTIC(NumRegSeqUsesRewritten,
+ "Number of REG_SEQUENCE subregister uses rewritten");
+STATISTIC(NumRegSeqEliminated,
+ "Number of REG_SEQUENCE instructions eliminated");
namespace {
@@ -457,6 +480,8 @@ class PeepholeOptimizer : private MachineFunction::Delegate {
bool optimizeUncoalescableCopy(MachineInstr &MI,
SmallPtrSetImpl<MachineInstr *> &LocalMIs);
bool optimizeRecurrence(MachineInstr &PHI);
+ bool foldRegSequenceUses(MachineInstr &MI, bool &ShouldEraseMI);
+ bool canRewriteRegSequenceSubRegUse(MachineOperand &UseMO, RegSubRegPair Src);
bool findNextSource(const TargetRegisterClass *DefRC, unsigned DefSubReg,
RegSubRegPair RegSubReg, RewriteMapTy &RewriteMap);
bool isMoveImmediate(MachineInstr &MI, SmallSet<Register, 4> &ImmDefRegs,
@@ -1739,6 +1764,119 @@ bool PeepholeOptimizerLegacy::runOnMachineFunction(MachineFunction &MF) {
return Impl.run(MF);
}
+/// Check if a REG_SEQUENCE subregister use can be safely rewritten to use
+/// the source register directly.
+bool PeepholeOptimizer::canRewriteRegSequenceSubRegUse(MachineOperand &UseMO,
+ RegSubRegPair Src) {
+ if (!Src.Reg.isValid() || !Src.Reg.isVirtual())
+ return false;
+
+ MachineInstr *UseMI = UseMO.getParent();
+ Register DstReg = UseMO.getReg();
+
+ // Instructions, e.g. AMDGPU S_MOVRELS_B32, may require specific
+ // subregister relationships with implicit operands. Replacing the
+ // REG_SEQUENCE use with one of the source of its subregisters can
+ // violate these constraints.
+ if (UseMI->hasRegisterImplicitUseOperand(DstReg) || UseMI->isInlineAsm())
+ return false;
+
+ const MCInstrDesc &UseDesc = UseMI->getDesc();
+ unsigned OpNo = UseMI->getOperandNo(&UseMO);
+ if (OpNo >= UseDesc.getNumOperands()) {
+ assert(UseDesc.isVariadic() &&
+ "Explicit op beyond getNumOperands() implies UseMI variadic");
+ // No target specific legality check possible/necessary.
+ return true;
+ }
+
+ const TargetRegisterClass *SrcRC = MRI->getRegClass(Src.Reg);
+ const TargetRegisterClass *OpRC = TII->getRegClass(UseDesc, OpNo);
+
+ if (OpRC) {
+ const TargetRegisterClass *ConstrainRC =
+ Src.SubReg ? TRI->getMatchingSuperRegClass(SrcRC, OpRC, Src.SubReg)
+ : OpRC;
+ if (!ConstrainRC || !MRI->constrainRegClass(Src.Reg, ConstrainRC))
+ return false;
+ }
+
+ // Check target-specific operand legality on a temporary MO.
+ // Kill/undef flags do not reflect the actual MO, but this should
+ // not matter for legality.
+ MachineOperand MO = MachineOperand::CreateReg(Src.Reg, /*isDef=*/false);
+ MO.setSubReg(Src.SubReg);
+ if (TII->isOperandLegal(*UseMI, OpNo, &MO))
+ return true;
+
+ MRI->setRegClass(Src.Reg, SrcRC); // Undo constrainRegClass.
+ return false;
+}
+
+/// Fold uses of REG_SEQUENCE subregisters to directly use the source registers.
+///
+/// Example: %8 = V_ADD_CO_U32_e32 %4, %7.sub0
+/// where %7 = REG_SEQUENCE %5, sub0, %6, sub1
+/// becomes: %8 = V_ADD_CO_U32_e32 %4, %5
+bool PeepholeOptimizer::foldRegSequenceUses(MachineInstr &MI,
+ bool &ShouldEraseMI) {
+ assert(MI.isRegSequence() && "Expected REG_SEQUENCE instruction");
+ ShouldEraseMI = false;
+
+ if (DisablePeepholeRegSeqFold)
+ return false;
+
+ Register DstReg = MI.getOperand(0).getReg();
+
+ bool Changed = false;
+ for (auto UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
+ UI != UE;) {
+ MachineOperand &UseMO = *UI;
+ ++UI; // advance before modifying ops to avoid invalidation
+
+ unsigned UseSubReg = UseMO.getSubReg();
+ if (UseSubReg == 0 || UseMO.isUndef())
+ continue;
+
+ // Find the matching source in the REG_SEQUENCE operands.
+ // REG_SEQUENCE format: dst, src0, subidx0, src1, subidx1, ...
+ MachineOperand *SrcOp = nullptr;
+ for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
+ if (MI.getOperand(i + 1).getImm() == UseSubReg) {
+ SrcOp = &MI.getOperand(i);
+ break;
+ }
+ }
+
+ if (!SrcOp)
+ continue;
+
+ Register SrcReg = SrcOp->getReg();
+ unsigned SrcSubReg = SrcOp->getSubReg();
+ if (!canRewriteRegSequenceSubRegUse(UseMO, {SrcReg, SrcSubReg}))
+ continue;
+
+ SrcOp->setIsKill(false);
+ MRI->clearKillFlags(SrcReg);
+
+ UseMO.setReg(SrcReg);
+ UseMO.setSubReg(SrcSubReg);
+ UseMO.setIsUndef(SrcOp->isUndef());
+ UseMO.setIsKill(false);
+
+ Changed = true;
+ ++NumRegSeqUsesRewritten;
+ }
+
+ if (Changed && MRI->use_nodbg_empty(DstReg)) {
+ MRI->markUsesInDebugValueAsUndef(DstReg);
+ ShouldEraseMI = true;
+ ++NumRegSeqEliminated;
+ }
+
+ return Changed;
+}
+
bool PeepholeOptimizer::run(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
@@ -1865,6 +2003,22 @@ bool PeepholeOptimizer::run(MachineFunction &MF) {
if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(*MI)) {
// MI is just rewritten.
Changed = true;
+
+ if (!MI->isRegSequence())
+ continue;
+ // Allow REG_SEQUENCE use folding to run.
+ }
+
+ if (MI->isRegSequence()) {
+ bool ShouldEraseMI;
+ if (foldRegSequenceUses(*MI, ShouldEraseMI)) {
+ if (ShouldEraseMI) {
+ LocalMIs.erase(MI);
+ MI->eraseFromParent();
+ }
+ Changed = true;
+ }
+ // Always continue. No further REG_SEQUENCE opts.
continue;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 48953cee43956..d1562bf331115 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6281,7 +6281,8 @@ void SIInstrInfo::swapOperands(MachineInstr &Inst) const {
bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
const MCOperandInfo &OpInfo,
- const MachineOperand &MO) const {
+ const MachineOperand &MO,
+ const MachineFunction *MF) const {
if (!MO.isReg())
return false;
@@ -6294,7 +6295,13 @@ bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
if (MO.getSubReg()) {
- const MachineFunction *MF = MO.getParent()->getMF();
+ if (!MF) {
+ const MachineInstr *Parent = MO.getParent();
+ if (!Parent)
+ return false;
+ MF = Parent->getMF();
+ }
+
const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF);
if (!SuperRC)
return false;
@@ -6325,7 +6332,7 @@ bool SIInstrInfo::isLegalRegOperand(const MachineInstr &MI, unsigned OpIdx,
}
}
- if (!isLegalRegOperand(MRI, OpInfo, MO))
+ if (!isLegalRegOperand(MRI, OpInfo, MO, MI.getMF()))
return false;
// check Accumulate GPR operand
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1d67c8664ff44..18c38626e4826 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1463,7 +1463,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// Check if \p MO is a legal operand if it was the \p OpIdx Operand
/// for \p MI.
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
- const MachineOperand *MO = nullptr) const;
+ const MachineOperand *MO = nullptr) const override;
/// Check if \p MO would be a valid operand for the given operand
/// definition \p OpInfo. Note this does not attempt to validate constant bus
@@ -1476,8 +1476,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// given operand description or operand index.
/// The operand index version provide more legality checks
bool isLegalRegOperand(const MachineRegisterInfo &MRI,
- const MCOperandInfo &OpInfo,
- const MachineOperand &MO) const;
+ const MCOperandInfo &OpInfo, const MachineOperand &MO,
+ const MachineFunction *MF = nullptr) const;
bool isLegalRegOperand(const MachineInstr &MI, unsigned OpIdx,
const MachineOperand &MO) const;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 2d5fc5cf22425..14660b524a6d5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -154920,23 +154920,23 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_b32 v71, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_b32 v70, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v81, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_b32 v80, off, s32
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr141_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr139_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr138_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr137_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
@@ -154944,40 +154944,40 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr142_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr137_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr138_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr152_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr143_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr140_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
@@ -154997,7 +154997,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
@@ -155010,10 +155010,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
@@ -155021,12 +155021,12 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
@@ -155049,48 +155049,48 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[133:134], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[29:30]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[101:102], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v15
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 24, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 8, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 24, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v104, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 24, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 8, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 24, v4...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/205795
More information about the llvm-commits
mailing list