[llvm] [SystemZ] Limit latency scheduling to SUs with latency of at least 5. (PR #206459)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 29 04:17:53 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-systemz
Author: Jonas Paulsson (JonPsson1)
<details>
<summary>Changes</summary>
The latency reduction heuristic is highly effective, but it seems preferred
to not "move everything around", but rather focus on instructions that have
somewhat longer latency. The basic idea behind this is that the input order
is fairly good to begin with and not just "any random order", so it should
not be disturbed unnecessarily.
---
Patch is 178.51 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206459.diff
47 Files Affected:
- (modified) llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp (+2-1)
- (modified) llvm/test/CodeGen/SystemZ/args-22.ll (+22-22)
- (modified) llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll (+8-8)
- (modified) llvm/test/CodeGen/SystemZ/bswap-09.ll (+12-12)
- (modified) llvm/test/CodeGen/SystemZ/bswap-10.ll (+5-5)
- (modified) llvm/test/CodeGen/SystemZ/call-zos-vec.ll (+9-9)
- (modified) llvm/test/CodeGen/SystemZ/canonicalize-vars.ll (+18-18)
- (modified) llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/dag-combine-05.ll (+10-10)
- (modified) llvm/test/CodeGen/SystemZ/dag-combine-07.ll (+2-2)
- (modified) llvm/test/CodeGen/SystemZ/fold-masked-merge.ll (+9-9)
- (modified) llvm/test/CodeGen/SystemZ/fp-copysign-03.ll (+6-6)
- (modified) llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll (+10-10)
- (modified) llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll (+41-41)
- (modified) llvm/test/CodeGen/SystemZ/fp-half.ll (+3-3)
- (modified) llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-explicit-regs-zEC12.ll (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/inline-asm-fp-int-casting-zEC12.ll (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/int-cmp-65.ll (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/int-conv-14.ll (+10-10)
- (modified) llvm/test/CodeGen/SystemZ/int-conv-15.ll (+6-6)
- (modified) llvm/test/CodeGen/SystemZ/int-mul-13.ll (+4-4)
- (modified) llvm/test/CodeGen/SystemZ/int-uadd-14.ll (+25-25)
- (modified) llvm/test/CodeGen/SystemZ/int-usub-13.ll (+25-25)
- (modified) llvm/test/CodeGen/SystemZ/knownbits-intrinsics-binop.ll (+120-119)
- (modified) llvm/test/CodeGen/SystemZ/misched-prera-cmp-elim.mir (+4-3)
- (modified) llvm/test/CodeGen/SystemZ/misched-prera-latencies.mir (+9-11)
- (modified) llvm/test/CodeGen/SystemZ/misched-prera-loads.mir (+20-31)
- (modified) llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir (+1-1)
- (modified) llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll (+2-2)
- (modified) llvm/test/CodeGen/SystemZ/risbg-04.ll (+9-12)
- (modified) llvm/test/CodeGen/SystemZ/rot-03.ll (+11-11)
- (modified) llvm/test/CodeGen/SystemZ/shift-12.ll (+15-15)
- (modified) llvm/test/CodeGen/SystemZ/shift-13.ll (+39-39)
- (modified) llvm/test/CodeGen/SystemZ/shift-14.ll (+39-39)
- (modified) llvm/test/CodeGen/SystemZ/shift-15.ll (+39-39)
- (modified) llvm/test/CodeGen/SystemZ/shift-16.ll (+46-46)
- (modified) llvm/test/CodeGen/SystemZ/shift-17.ll (+64-64)
- (modified) llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll (+8-8)
- (modified) llvm/test/CodeGen/SystemZ/soft-float-args.ll (+4-6)
- (modified) llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll (+40-40)
- (modified) llvm/test/CodeGen/SystemZ/vec-args-04.ll (+8-8)
- (modified) llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll (+99-99)
- (modified) llvm/test/CodeGen/SystemZ/vec-cmpsel-01.ll (+3-3)
- (modified) llvm/test/CodeGen/SystemZ/vec-eval.ll (+40-40)
- (modified) llvm/test/CodeGen/SystemZ/vec-perm-12.ll (+6-6)
- (modified) llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll (+5-5)
- (modified) llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll (+225-241)
``````````diff
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
index fe22ceac5fce7..221904798f20c 100644
--- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
@@ -80,7 +80,8 @@ bool SystemZPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
return TryCand.Reason != NoCand;
}
- if (!RegionPolicy.DisableLatencyHeuristic)
+ if (!RegionPolicy.DisableLatencyHeuristic &&
+ std::max(TryCand.SU->Latency, Cand.SU->Latency) >= 5)
if (const SUnit *HigherSU =
TryCand.SU->getHeight() > Cand.SU->getHeight() ? TryCand.SU
: TryCand.SU->getHeight() < Cand.SU->getHeight() ? Cand.SU
diff --git a/llvm/test/CodeGen/SystemZ/args-22.ll b/llvm/test/CodeGen/SystemZ/args-22.ll
index 0d20cd1ebc7c1..388a0e3784c00 100644
--- a/llvm/test/CodeGen/SystemZ/args-22.ll
+++ b/llvm/test/CodeGen/SystemZ/args-22.ll
@@ -124,8 +124,8 @@ define void @arg1(%Ty1 %A) {
; VECTOR-NEXT: lgrl %r1, Dst at GOT
; VECTOR-NEXT: vrepib %v1, 8
; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
-; VECTOR-NEXT: vsrlb %v1, %v0, %v1
-; VECTOR-NEXT: vsteg %v1, 0(%r1), 1
+; VECTOR-NEXT: vsrlb %v0, %v0, %v1
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty1 %A, ptr @Dst
ret void
@@ -351,14 +351,14 @@ define void @arg3(%Ty3 %A) {
;
; VECTOR-LABEL: arg3:
; VECTOR: # %bb.0:
-; VECTOR-NEXT: vl %v0, 0(%r2), 3
-; VECTOR-NEXT: vl %v1, 0(%r3), 3
+; VECTOR-NEXT: vl %v0, 0(%r3), 3
; VECTOR-NEXT: lgrl %r1, Dst at GOT
-; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
-; VECTOR-NEXT: vrepib %v2, 8
-; VECTOR-NEXT: vsrlb %v2, %v0, %v2
-; VECTOR-NEXT: vst %v1, 16(%r1), 3
-; VECTOR-NEXT: vsteg %v2, 0(%r1), 1
+; VECTOR-NEXT: vl %v1, 0(%r2), 3
+; VECTOR-NEXT: vsteb %v1, 8(%r1), 15
+; VECTOR-NEXT: vst %v0, 16(%r1), 3
+; VECTOR-NEXT: vrepib %v0, 8
+; VECTOR-NEXT: vsrlb %v0, %v1, %v0
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty3 %A, ptr @Dst
ret void
@@ -402,11 +402,11 @@ define void @call3() {
; VECTOR-NEXT: vlrepg %v1, 0(%r1)
; VECTOR-NEXT: vrepib %v2, 8
; VECTOR-NEXT: vslb %v1, %v1, %v2
-; VECTOR-NEXT: vl %v2, 16(%r1), 3
; VECTOR-NEXT: vo %v0, %v0, %v1
+; VECTOR-NEXT: vl %v1, 16(%r1), 3
; VECTOR-NEXT: la %r2, 176(%r15)
; VECTOR-NEXT: la %r3, 160(%r15)
-; VECTOR-NEXT: vst %v2, 160(%r15), 3
+; VECTOR-NEXT: vst %v1, 160(%r15), 3
; VECTOR-NEXT: vst %v0, 176(%r15), 3
; VECTOR-NEXT: brasl %r14, Fnptr at PLT
; VECTOR-NEXT: lmg %r14, %r15, 304(%r15)
@@ -810,10 +810,10 @@ define void @arg6(%Ty6 %A) {
; VECTOR-NEXT: vsteb %v1, 24(%r1), 15
; VECTOR-NEXT: vrepib %v2, 8
; VECTOR-NEXT: vsteb %v0, 8(%r1), 15
-; VECTOR-NEXT: vsrlb %v3, %v1, %v2
-; VECTOR-NEXT: vsrlb %v2, %v0, %v2
-; VECTOR-NEXT: vsteg %v3, 16(%r1), 1
-; VECTOR-NEXT: vsteg %v2, 0(%r1), 1
+; VECTOR-NEXT: vsrlb %v1, %v1, %v2
+; VECTOR-NEXT: vsrlb %v0, %v0, %v2
+; VECTOR-NEXT: vsteg %v1, 16(%r1), 1
+; VECTOR-NEXT: vsteg %v0, 0(%r1), 1
; VECTOR-NEXT: br %r14
store %Ty6 %A, ptr @Dst
ret void
@@ -854,17 +854,17 @@ define void @call6() {
; VECTOR-NEXT: aghi %r15, -192
; VECTOR-NEXT: .cfi_def_cfa_offset 352
; VECTOR-NEXT: lgrl %r1, Src at GOT
-; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vgbm %v1, 0
; VECTOR-NEXT: vleb %v1, 8(%r1), 15
; VECTOR-NEXT: vlrepg %v2, 0(%r1)
-; VECTOR-NEXT: vleb %v0, 24(%r1), 15
-; VECTOR-NEXT: vlrepg %v3, 16(%r1)
-; VECTOR-NEXT: vrepib %v4, 8
-; VECTOR-NEXT: vslb %v2, %v2, %v4
-; VECTOR-NEXT: vslb %v3, %v3, %v4
+; VECTOR-NEXT: vrepib %v3, 8
+; VECTOR-NEXT: vslb %v2, %v2, %v3
+; VECTOR-NEXT: vgbm %v0, 0
; VECTOR-NEXT: vo %v1, %v1, %v2
-; VECTOR-NEXT: vo %v0, %v0, %v3
+; VECTOR-NEXT: vleb %v0, 24(%r1), 15
+; VECTOR-NEXT: vlrepg %v2, 16(%r1)
+; VECTOR-NEXT: vslb %v2, %v2, %v3
+; VECTOR-NEXT: vo %v0, %v0, %v2
; VECTOR-NEXT: la %r2, 176(%r15)
; VECTOR-NEXT: la %r3, 160(%r15)
; VECTOR-NEXT: vst %v0, 160(%r15), 3
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
index b7d76f4e12098..09edd6eb227af 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
@@ -111,11 +111,11 @@ define i128 @atomicrmw_nand(ptr %src, i128 %b) {
; CHECK-NEXT: vlvgp %v1, %r0, %r1
; CHECK-NEXT: .LBB4_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vnn %v2, %v1, %v0
; CHECK-NEXT: vlgvg %r1, %v1, 1
; CHECK-NEXT: vlgvg %r0, %v1, 0
-; CHECK-NEXT: vlgvg %r5, %v2, 1
-; CHECK-NEXT: vlgvg %r4, %v2, 0
+; CHECK-NEXT: vnn %v1, %v1, %v0
+; CHECK-NEXT: vlgvg %r5, %v1, 1
+; CHECK-NEXT: vlgvg %r4, %v1, 0
; CHECK-NEXT: cdsg %r0, %r4, 0(%r3)
; CHECK-NEXT: vlvgp %v1, %r0, %r1
; CHECK-NEXT: jl .LBB4_1
@@ -335,10 +335,10 @@ define i128 @atomicrmw_uinc_wrap(ptr %src, i128 %b) {
; CHECK-LABEL: atomicrmw_uinc_wrap:
; CHECK: # %bb.0:
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: larl %r4, .LCPI11_0
-; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: lpq %r0, 0(%r3)
; CHECK-NEXT: vlvgp %v2, %r0, %r1
+; CHECK-NEXT: larl %r1, .LCPI11_0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
; CHECK-NEXT: j .LBB11_2
; CHECK-NEXT: .LBB11_1: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB11_2 Depth=1
@@ -376,11 +376,11 @@ define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) {
; CHECK-LABEL: atomicrmw_udec_wrap:
; CHECK: # %bb.0:
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: larl %r4, .LCPI12_0
-; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vgbm %v2, 65535
; CHECK-NEXT: lpq %r0, 0(%r3)
; CHECK-NEXT: vlvgp %v3, %r0, %r1
-; CHECK-NEXT: vgbm %v2, 65535
+; CHECK-NEXT: larl %r1, .LCPI12_0
+; CHECK-NEXT: vl %v1, 0(%r1), 3
; CHECK-NEXT: j .LBB12_2
; CHECK-NEXT: .LBB12_1: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
diff --git a/llvm/test/CodeGen/SystemZ/bswap-09.ll b/llvm/test/CodeGen/SystemZ/bswap-09.ll
index e8468acaee431..a2d8273c89695 100644
--- a/llvm/test/CodeGen/SystemZ/bswap-09.ll
+++ b/llvm/test/CodeGen/SystemZ/bswap-09.ll
@@ -9,14 +9,14 @@ declare i128 @llvm.bswap.i128(i128 %a)
define i128 @f1(i128 %a, i128 %b, i128 %c) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r3), 3
; CHECK-NEXT: larl %r1, .LCPI0_0
+; CHECK-NEXT: vaq %v1, %v2, %v1
; CHECK-NEXT: vl %v2, 0(%r1), 3
-; CHECK-NEXT: vl %v3, 0(%r5), 3
+; CHECK-NEXT: vl %v0, 0(%r5), 3
+; CHECK-NEXT: vperm %v1, %v1, %v1, %v2
; CHECK-NEXT: vaq %v0, %v1, %v0
-; CHECK-NEXT: vperm %v0, %v0, %v0, %v2
-; CHECK-NEXT: vaq %v0, %v0, %v3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%in = add i128 %a, %b
@@ -32,9 +32,9 @@ define i128 @f2(i128 %a, i128 %b) {
; CHECK-NEXT: vl %v0, 0(%r4), 3
; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: larl %r1, .LCPI1_0
-; CHECK-NEXT: vl %v2, 0(%r1), 3
; CHECK-NEXT: vaq %v0, %v1, %v0
-; CHECK-NEXT: vperm %v0, %v0, %v0, %v2
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vperm %v0, %v0, %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%in = add i128 %a, %b
@@ -47,11 +47,11 @@ define i128 @f3(i128 %a, i128 %b) {
; CHECK-LABEL: f3:
; CHECK: # %bb.0:
; CHECK-NEXT: larl %r1, .LCPI2_0
-; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vl %v1, 0(%r1), 3
-; CHECK-NEXT: vl %v2, 0(%r4), 3
-; CHECK-NEXT: vperm %v0, %v0, %v0, %v1
-; CHECK-NEXT: vaq %v0, %v0, %v2
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v2, 0(%r1), 3
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vperm %v1, %v1, %v1, %v2
+; CHECK-NEXT: vaq %v0, %v1, %v0
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%swapped = call i128 @llvm.bswap.i128(i128 %a)
diff --git a/llvm/test/CodeGen/SystemZ/bswap-10.ll b/llvm/test/CodeGen/SystemZ/bswap-10.ll
index 465c666808958..6de2970b80e2e 100644
--- a/llvm/test/CodeGen/SystemZ/bswap-10.ll
+++ b/llvm/test/CodeGen/SystemZ/bswap-10.ll
@@ -9,14 +9,14 @@ declare i128 @llvm.bswap.i128(i128 %a)
define i128 @f1(i128 %a, i128 %b, i128 %c) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vl %v2, 0(%r3), 3
; CHECK-NEXT: larl %r1, .LCPI0_0
+; CHECK-NEXT: vaq %v1, %v2, %v1
; CHECK-NEXT: vl %v2, 0(%r1), 3
-; CHECK-NEXT: vl %v3, 0(%r5), 3
+; CHECK-NEXT: vl %v0, 0(%r5), 3
+; CHECK-NEXT: vperm %v1, %v1, %v1, %v2
; CHECK-NEXT: vaq %v0, %v1, %v0
-; CHECK-NEXT: vperm %v0, %v0, %v0, %v2
-; CHECK-NEXT: vaq %v0, %v0, %v3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
%in = add i128 %a, %b
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vec.ll b/llvm/test/CodeGen/SystemZ/call-zos-vec.ll
index 32d29cb8ebc08..20bf2687c957e 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-vec.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-vec.ll
@@ -9,15 +9,15 @@ entry:
}
; CHECK-LABEL: sum_vecs1
-; CHECK: vaf 0,24,25
-; CHECK: vaf 0,0,26
-; CHECK: vaf 0,0,27
-; CHECK: vaf 0,0,28
-; CHECK: vaf 0,0,29
-; CHECK: vl 1,2304(4),4
-; CHECK: vaf 0,0,30
-; CHECK: vaf 0,0,31
-; CHECK: vaf 24,0,1
+; CHECK: vaf 1,24,25
+; CHECK: vaf 1,1,26
+; CHECK: vaf 1,1,27
+; CHECK: vaf 1,1,28
+; CHECK: vaf 1,1,29
+; CHECK: vl 0,2304(4),4
+; CHECK: vaf 1,1,30
+; CHECK: vaf 1,1,31
+; CHECK: vaf 24,1,0
define <4 x i32> @sum_vecs1(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8, <4 x i32> %v9) {
entry:
%add0 = add <4 x i32> %v1, %v2
diff --git a/llvm/test/CodeGen/SystemZ/canonicalize-vars.ll b/llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
index e7e9bbc207af2..e6659d385ae5f 100644
--- a/llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
+++ b/llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
@@ -129,13 +129,13 @@ define <8 x half> @canonicalize_v8f16(<8 x half> %a) nounwind {
; Z16-NEXT: vgmf %v1, 2, 8
; Z16-NEXT: meebr %f0, %f1
; Z16-NEXT: brasl %r14, __truncsfhf2 at PLT
-; Z16-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vl %v2, 192(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
; Z16-NEXT: # kill: def $f0h killed $f0h def $v0
-; Z16-NEXT: vreph %v1, %v1, 5
-; Z16-NEXT: vmrhh %v0, %v0, %v2
+; Z16-NEXT: vmrhh %v0, %v0, %v1
; Z16-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
-; Z16-NEXT: ldr %f0, %f1
+; Z16-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vreph %v0, %v0, 5
+; Z16-NEXT: # kill: def $f0h killed $f0h killed $v0
; Z16-NEXT: brasl %r14, __extendhfsf2 at PLT
; Z16-NEXT: vgmf %v1, 2, 8
; Z16-NEXT: meebr %f0, %f1
@@ -150,13 +150,13 @@ define <8 x half> @canonicalize_v8f16(<8 x half> %a) nounwind {
; Z16-NEXT: meebr %f0, %f1
; Z16-NEXT: brasl %r14, __truncsfhf2 at PLT
; Z16-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vl %v2, 192(%r15), 3 # 16-byte Reload
; Z16-NEXT: # kill: def $f0h killed $f0h def $v0
-; Z16-NEXT: vmrhh %v1, %v0, %v1
+; Z16-NEXT: vmrhh %v0, %v0, %v1
+; Z16-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vmrhf %v0, %v0, %v1
+; Z16-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
; Z16-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vmrhf %v1, %v1, %v2
; Z16-NEXT: vreph %v0, %v0, 3
-; Z16-NEXT: vst %v1, 192(%r15), 3 # 16-byte Spill
; Z16-NEXT: # kill: def $f0h killed $f0h killed $v0
; Z16-NEXT: brasl %r14, __extendhfsf2 at PLT
; Z16-NEXT: vgmf %v1, 2, 8
@@ -262,13 +262,13 @@ define void @canonicalize_ptr_v8f16(ptr %out) nounwind {
; Z16-NEXT: vgmf %v1, 2, 8
; Z16-NEXT: meebr %f0, %f1
; Z16-NEXT: brasl %r14, __truncsfhf2 at PLT
-; Z16-NEXT: vl %v1, 160(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vl %v2, 192(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
; Z16-NEXT: # kill: def $f0h killed $f0h def $v0
-; Z16-NEXT: vreph %v1, %v1, 5
-; Z16-NEXT: vmrhh %v0, %v0, %v2
+; Z16-NEXT: vmrhh %v0, %v0, %v1
; Z16-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
-; Z16-NEXT: ldr %f0, %f1
+; Z16-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vreph %v0, %v0, 5
+; Z16-NEXT: # kill: def $f0h killed $f0h killed $v0
; Z16-NEXT: brasl %r14, __extendhfsf2 at PLT
; Z16-NEXT: vgmf %v1, 2, 8
; Z16-NEXT: meebr %f0, %f1
@@ -283,13 +283,13 @@ define void @canonicalize_ptr_v8f16(ptr %out) nounwind {
; Z16-NEXT: meebr %f0, %f1
; Z16-NEXT: brasl %r14, __truncsfhf2 at PLT
; Z16-NEXT: vl %v1, 176(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vl %v2, 192(%r15), 3 # 16-byte Reload
; Z16-NEXT: # kill: def $f0h killed $f0h def $v0
-; Z16-NEXT: vmrhh %v1, %v0, %v1
+; Z16-NEXT: vmrhh %v0, %v0, %v1
+; Z16-NEXT: vl %v1, 192(%r15), 3 # 16-byte Reload
+; Z16-NEXT: vmrhf %v0, %v0, %v1
+; Z16-NEXT: vst %v0, 192(%r15), 3 # 16-byte Spill
; Z16-NEXT: vl %v0, 160(%r15), 3 # 16-byte Reload
-; Z16-NEXT: vmrhf %v1, %v1, %v2
; Z16-NEXT: vreph %v0, %v0, 3
-; Z16-NEXT: vst %v1, 192(%r15), 3 # 16-byte Spill
; Z16-NEXT: # kill: def $f0h killed $f0h killed $v0
; Z16-NEXT: brasl %r14, __extendhfsf2 at PLT
; Z16-NEXT: vgmf %v1, 2, 8
diff --git a/llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll b/llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll
index 40c138b84cd40..5f4b1dbf1bc10 100644
--- a/llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll
+++ b/llvm/test/CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll
@@ -7,8 +7,8 @@
define void @fun(i32 %Arg) {
; CHECK-LABEL: fun:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhi %r0, 0
; CHECK-NEXT: ahi %r2, 1
+; CHECK-NEXT: lhi %r0, 0
; CHECK-NEXT: cijlh %r0, 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: tmll %r2, 16
diff --git a/llvm/test/CodeGen/SystemZ/dag-combine-05.ll b/llvm/test/CodeGen/SystemZ/dag-combine-05.ll
index 692d74250c1a0..60528ad67d039 100644
--- a/llvm/test/CodeGen/SystemZ/dag-combine-05.ll
+++ b/llvm/test/CodeGen/SystemZ/dag-combine-05.ll
@@ -9,18 +9,18 @@
define void @fun(i16 %arg0, ptr %src, ptr %dst) {
; CHECK-LABEL: fun:
; CHECK: # %bb.0: # %bb
-; CHECK-NEXT: llh %r0, 0(%r3)
-; CHECK-NEXT: llhr %r1, %r2
-; CHECK-NEXT: chi %r1, 9616
+; CHECK-NEXT: llhr %r0, %r2
+; CHECK-NEXT: llh %r2, 0(%r3)
+; CHECK-NEXT: chi %r0, 9616
; CHECK-NEXT: lhi %r1, 0
; CHECK-NEXT: lochil %r1, 1
-; CHECK-NEXT: afi %r0, 65535
-; CHECK-NEXT: llhr %r2, %r0
-; CHECK-NEXT: lhi %r3, 0
-; CHECK-NEXT: cr %r2, %r0
-; CHECK-NEXT: lochilh %r3, 1
-; CHECK-NEXT: ar %r1, %r3
-; CHECK-NEXT: st %r1, 0(%r4)
+; CHECK-NEXT: afi %r2, 65535
+; CHECK-NEXT: llhr %r3, %r2
+; CHECK-NEXT: lhi %r0, 0
+; CHECK-NEXT: cr %r3, %r2
+; CHECK-NEXT: lochilh %r0, 1
+; CHECK-NEXT: ar %r0, %r1
+; CHECK-NEXT: st %r0, 0(%r4)
; CHECK-NEXT: br %r14
bb:
%tmp = icmp ult i16 %arg0, 9616
diff --git a/llvm/test/CodeGen/SystemZ/dag-combine-07.ll b/llvm/test/CodeGen/SystemZ/dag-combine-07.ll
index 4c65a5371583a..7dd76b61846ef 100644
--- a/llvm/test/CodeGen/SystemZ/dag-combine-07.ll
+++ b/llvm/test/CodeGen/SystemZ/dag-combine-07.ll
@@ -11,11 +11,11 @@ define void @func_5(ptr %Dst) {
; CHECK-LABEL: func_5:
; CHECK: # %bb.0:
; CHECK-NEXT: lgrl %r1, G2 at GOT
-; CHECK-NEXT: lgrl %r3, G1 at GOT
; CHECK-NEXT: llihl %r0, 50
; CHECK-NEXT: oill %r0, 2
; CHECK-NEXT: stg %r0, 0(%r1)
-; CHECK-NEXT: stg %r0, 0(%r3)
+; CHECK-NEXT: lgrl %r1, G1 at GOT
+; CHECK-NEXT: stg %r0, 0(%r1)
; CHECK-NEXT: mvhi 0(%r2), 2
; CHECK-NEXT: br %r14
store i64 214748364802, ptr @G2, align 8
diff --git a/llvm/test/CodeGen/SystemZ/fold-masked-merge.ll b/llvm/test/CodeGen/SystemZ/fold-masked-merge.ll
index 86edaeda71e94..c014345507f69 100644
--- a/llvm/test/CodeGen/SystemZ/fold-masked-merge.ll
+++ b/llvm/test/CodeGen/SystemZ/fold-masked-merge.ll
@@ -96,17 +96,17 @@ define i32 @not_a_masked_merge0(i32 %a0, i32 %a1, i32 %a2) {
; NO-MISC3-LABEL: not_a_masked_merge0:
; NO-MISC3: # %bb.0:
; NO-MISC3-NEXT: lcr %r0, %r2
-; NO-MISC3-NEXT: nr %r2, %r3
+; NO-MISC3-NEXT: nr %r3, %r2
; NO-MISC3-NEXT: nr %r0, %r4
-; NO-MISC3-NEXT: or %r2, %r0
+; NO-MISC3-NEXT: ork %r2, %r3, %r0
; NO-MISC3-NEXT: br %r14
;
; MISC3-LABEL: not_a_masked_merge0:
; MISC3: # %bb.0:
; MISC3-NEXT: lcr %r0, %r2
-; MISC3-NEXT: nr %r2, %r3
+; MISC3-NEXT: nr %r3, %r2
; MISC3-NEXT: nr %r0, %r4
-; MISC3-NEXT: or %r2, %r0
+; MISC3-NEXT: ork %r2, %r3, %r0
; MISC3-NEXT: br %r14
%and0 = and i32 %a0, %a1
%not_a_not = sub i32 0, %a0
@@ -162,10 +162,10 @@ define i32 @not_a_masked_merge2(i32 %a0, i32 %a1, i32 %a2) {
define i32 @not_a_masked_merge3(i32 %a0, i32 %a1, i32 %a2) {
; NO-MISC3-LABEL: not_a_masked_merge3:
; NO-MISC3: # %bb.0:
-; NO-MISC3-NEXT: xr %r4, %r2
-; NO-MISC3-NEXT: nr %r2, %r3
-; NO-MISC3-NEXT: xilf %r4, 4294967295
-; NO-MISC3-NEXT: or %r2, %r4
+; NO-MISC3-NEXT: nr %r3, %r2
+; NO-MISC3-NEXT: xr %r2, %r4
+; NO-MISC3-NEXT: xilf %r2, 4294967295
+; NO-MISC3-NEXT: or %r2, %r3
; NO-MISC3-NEXT: br %r14
;
; MISC3-LABEL: not_a_masked_merge3:
@@ -238,8 +238,8 @@ define i32 @masked_merge_no_transform1(i32 %a0, i32 %a1, i32 %a2, ptr %p1) {
; MISC3: # %bb.0:
; MISC3-NEXT: nrk %r0, %r2, %r3
; MISC3-NEXT: ncrk %r1, %r4, %r2
-; MISC3-NEXT: or %r0, %r1
; MISC3-NEXT: xilf %r2, 4294967295
+; MISC3-NEXT: or %r0, %r1
; MISC3-NEXT: st %r2, 0(%r5)
; MISC3-NEXT: lr %r2, %r0
; MISC3-NEXT: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll b/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
index d1997e98fbe68..c2c5889a689e4 100644
--- a/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
@@ -209,16 +209,16 @@ define fp128 @f13(fp128 %a, float %b) {
;
; Z16-LABEL: f13:
; Z16: # %bb.0:
+; Z16-NEXT: vl %v1, 0(%r3), 3
; Z16-NEXT: vlgvf %r0, %v0, 0
-; Z16-NEXT: vl %v0, 0(%r3), 3
; Z16-NEXT: tmlh %r0, 32768
; Z16-NEXT: je .LBB13_2
; Z16-NEXT: # %bb.1:
-; Z16-NEXT: wflnxb %v0, %v0
+; Z16-NEXT: wflnxb %v0, %v1
; Z16-NEXT: vst %v0, 0(%r2), 3
; Z16-NEXT: br %r14
; Z16-NEXT: .LBB13_2:
-; Z16-NEXT: wflpxb %v0, %v0
+; Z16-NEXT: wflpxb %v0, %v1
; Z16-NEXT: vst %v0, 0(%r2), 3
; Z16-NEXT: br %r14
%b128 = fpext float %b to fp128
@@ -239,16 +239,16 @@ define fp128 @f14(fp128 %a, double %b) {
;
; Z16-LABEL: f14:
; Z16: # %bb.0:
+; Z16-NEXT: vl %v1, 0(%r3), 3
; Z16-NEXT: lgdr %r0, %f0
-; Z16-NEXT: vl %v0, 0(%r3), 3
; Z16-NEXT: tmhh %r0, 32768
; Z16-NEXT: je .LBB14_2
; Z16-NEXT: # %bb.1:
-; Z16-NEXT: wflnxb %v0, %v0
+; Z16-NEXT: wflnxb %v0, %v1
; Z16-NEXT: vst %v0, 0(%r2), 3
; Z16-NEXT: br %r14
; Z16-NEXT: .LBB14_2:
-; Z16-NEXT: wflpxb %v0, %v0
+; Z16-NEXT: wflpxb %v0, %v1
; Z16-NEXT: vst %v0, 0(%r2), 3
; Z16-NEXT: br %r14
%b128 = fpext double %b to fp128
diff --git a/llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll b/llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll
index f141ee0599222..825472299d028 100644
--- a/llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-half-vector-binops.ll
@@ -198,10 +198,10 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: std %f8, 240(%r15) # 8-byte Spill
; VECTOR-NEXT: .cfi_offset %f8, -168
; VECTOR-NEXT: vl %v0, 16(%r2), 3
+; VECTOR-NEXT: mvc 160(16,%r15), 0(%r2) # 16-byte Folded Spill
; VECTOR-NEXT: lgr %r13, %r3
; VECTOR-NEXT: vst %v0, 176(%r15), 3 # 16-byte Spill
; VECTOR-NEXT: vreph %v0, %v0, 7
-; VECTOR-NEXT: mvc 160(16,%r15), 0(%r2) # 16-byte Folded Spill
; VECTOR-NEXT: # kill: def $f0h killed $f0h killed $v0
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: ldr %f8, %f0
@@ -224,13 +224,13 @@ define void @fun0(ptr %Src, ptr %Dst) {
; VECTOR-NEXT: brasl %r14, __extendhfsf2 at PLT
; VECTOR-NEXT: aebr %f0, %f8
; VECTOR-NEXT: brasl %r14, __truncsfhf2 at PLT
-; VECTOR-NEXT: vl %v1, 176(%r15), 3 # 16-b...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206459
More information about the llvm-commits
mailing list