[llvm] Add intrinsics support in narrow interleave group (PR #206455)
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llvm-commits at lists.llvm.org
Mon Jun 29 04:05:32 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-vectorizers
Author: Kamlesh Kumar (kamleshbhalui)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/206455.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp (+30-9)
- (added) llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll (+158)
``````````diff
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 1a10da2f1d3bf..a09c92043e801 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -5775,13 +5775,14 @@ static bool canNarrowLoad(VPSingleDefRecipe *WideMember0, unsigned OpIdx,
return false;
}
-static bool canNarrowOps(ArrayRef<VPValue *> Ops, bool IsScalable) {
+static bool canNarrowOps(ArrayRef<VPValue *> Ops, bool IsScalable,
+ const TargetTransformInfo &TTI) {
SmallVector<VPValue *> Ops0;
auto *WideMember0 = dyn_cast<VPRecipeWithIRFlags>(Ops[0]);
if (!WideMember0)
return false;
for (VPValue *V : Ops) {
- if (!isa<VPWidenRecipe, VPWidenCastRecipe>(V))
+ if (!isa<VPWidenRecipe, VPWidenCastRecipe, VPWidenIntrinsicRecipe>(V))
return false;
auto *R = cast<VPRecipeWithIRFlags>(V);
if (getOpcodeOrIntrinsicID(R) != getOpcodeOrIntrinsicID(WideMember0))
@@ -5797,7 +5798,16 @@ static bool canNarrowOps(ArrayRef<VPValue *> Ops, bool IsScalable) {
for (VPValue *Op : Ops)
OpsI.push_back(Op->getDefiningRecipe()->getOperand(Idx));
- if (canNarrowOps(OpsI, IsScalable))
+ auto *WideIntrinsic0 = dyn_cast<VPWidenIntrinsicRecipe>(WideMember0);
+ if (WideIntrinsic0 &&
+ isVectorIntrinsicWithScalarOpAtArg(
+ WideIntrinsic0->getVectorIntrinsicID(), Idx, &TTI)) {
+ if (!all_of(OpsI, equal_to(OpsI.front())))
+ return false;
+ continue;
+ }
+
+ if (canNarrowOps(OpsI, IsScalable, TTI))
continue;
if (any_of(enumerate(OpsI), [WideMember0, Idx, IsScalable](const auto &P) {
@@ -5851,8 +5861,9 @@ isConsecutiveInterleaveGroup(VPInterleaveRecipe *InterleaveR,
for (ElementCount VF : VFs) {
unsigned MinVal = VF.getKnownMinValue();
unsigned GroupSize = GroupElementTy->getScalarSizeInBits() * MinVal;
- if (IG->getFactor() == MinVal && GroupSize == GetVectorBitWidthForVF(VF))
+ if (IG->getFactor() == MinVal && GroupSize == GetVectorBitWidthForVF(VF)) {
return {VF};
+ }
}
return std::nullopt;
}
@@ -5871,7 +5882,8 @@ static bool isAlreadyNarrow(VPValue *VPV) {
// Preheader.
static VPValue *narrowInterleaveGroupOp(ArrayRef<VPValue *> Members,
SmallPtrSetImpl<VPValue *> &NarrowedOps,
- VPBasicBlock *Preheader) {
+ VPBasicBlock *Preheader,
+ const TargetTransformInfo &TTI) {
VPValue *V = Members.front();
if (NarrowedOps.contains(V))
return V;
@@ -5893,7 +5905,7 @@ static VPValue *narrowInterleaveGroupOp(ArrayRef<VPValue *> Members,
return V;
VPRecipeBase *R = V->getDefiningRecipe();
- if (isa<VPWidenRecipe, VPWidenCastRecipe>(R)) {
+ if (isa<VPWidenRecipe, VPWidenCastRecipe, VPWidenIntrinsicRecipe>(R)) {
auto *WideMember0 = cast<VPRecipeWithIRFlags>(R);
for (VPValue *Member : Members.drop_front())
WideMember0->intersectFlags(*cast<VPRecipeWithIRFlags>(Member));
@@ -5901,8 +5913,17 @@ static VPValue *narrowInterleaveGroupOp(ArrayRef<VPValue *> Members,
SmallVector<VPValue *> OpsI;
for (VPValue *Member : Members)
OpsI.push_back(Member->getDefiningRecipe()->getOperand(Idx));
+ auto *WideIntrinsic0 = dyn_cast<VPWidenIntrinsicRecipe>(WideMember0);
+ if (WideIntrinsic0 &&
+ isVectorIntrinsicWithScalarOpAtArg(
+ WideIntrinsic0->getVectorIntrinsicID(), Idx, &TTI)) {
+ assert(all_of(OpsI, equal_to(OpsI.front())) &&
+ "scalar intrinsic operands must match");
+ WideMember0->setOperand(Idx, OpsI.front());
+ continue;
+ }
WideMember0->setOperand(
- Idx, narrowInterleaveGroupOp(OpsI, NarrowedOps, Preheader));
+ Idx, narrowInterleaveGroupOp(OpsI, NarrowedOps, Preheader, TTI));
}
return V;
}
@@ -6038,7 +6059,7 @@ VPlanTransforms::narrowInterleaveGroups(VPlan &Plan,
// Check if all values feeding InterleaveR are matching wide recipes, which
// operands that can be narrowed.
if (!canNarrowOps(InterleaveR->getStoredValues(),
- VFToOptimize->isScalable()))
+ VFToOptimize->isScalable(), TTI))
return nullptr;
StoreGroups.push_back(InterleaveR);
}
@@ -6071,7 +6092,7 @@ VPlanTransforms::narrowInterleaveGroups(VPlan &Plan,
// Narrow operation tree rooted at store groups.
for (auto *StoreGroup : StoreGroups) {
VPValue *Res = narrowInterleaveGroupOp(StoreGroup->getStoredValues(),
- NarrowedOps, Preheader);
+ NarrowedOps, Preheader, TTI);
auto *SI =
cast<StoreInst>(StoreGroup->getInterleaveGroup()->getInsertPos());
auto *S = new VPWidenStoreRecipe(*SI, StoreGroup->getAddr(), Res, nullptr,
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll
new file mode 100644
index 0000000000000..5b457b6c3f2da
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll
@@ -0,0 +1,158 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph:" --version 5
+; RUN: opt -p loop-vectorize -S -force-vector-interleave=1 %s | FileCheck %s
+
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx"
+
+
+define void @powi_two_fields_same_exponent(ptr noalias %src, ptr noalias %dst, i64 %n) {
+; CHECK-LABEL: define void @powi_two_fields_same_exponent(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = load <2 x double>, ptr [[TMP2]], align 8
+; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC3]], i32 2)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[TMP0]], i32 0
+; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[TMP6]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP0]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br [[EXIT:label %.*]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %src.0 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 0
+ %x0 = load double, ptr %src.0, align 8
+ %p0 = call double @llvm.powi.f64.i32(double %x0, i32 2)
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %p0, ptr %dst.0, align 8
+ %src.1 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 1
+ %x1 = load double, ptr %src.1, align 8
+ %p1 = call double @llvm.powi.f64.i32(double %x1, i32 2)
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %p1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+exit:
+ ret void
+}
+
+
+define void @powi_two_fields_different_exponent(ptr noalias %src, ptr noalias %dst, i64 %n) {
+; CHECK-LABEL: define void @powi_two_fields_different_exponent(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP0]], align 8
+; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC]], i32 2)
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC1]], i32 3)
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP2]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %src.0 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 0
+ %x0 = load double, ptr %src.0, align 8
+ %p0 = call double @llvm.powi.f64.i32(double %x0, i32 2)
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %p0, ptr %dst.0, align 8
+ %src.1 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 1
+ %x1 = load double, ptr %src.1, align 8
+ %p1 = call double @llvm.powi.f64.i32(double %x1, i32 3)
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %p1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+exit:
+ ret void
+}
+
+
+define void @pow_two_fields_two_vector_operands(ptr noalias %lhs, ptr noalias %rhs, ptr noalias %dst, i64 %n) {
+; CHECK-LABEL: define void @pow_two_fields_two_vector_operands(
+; CHECK-SAME: ptr noalias [[LHS:%.*]], ptr noalias [[RHS:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds { double, double }, ptr [[LHS]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds { double, double }, ptr [[RHS]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x double>, ptr [[TMP1]], align 8
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> [[WIDE_LOAD]], <2 x double> [[WIDE_LOAD1]])
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[TMP3]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br [[EXIT:label %.*]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %lhs.0 = getelementptr inbounds { double, double }, ptr %lhs, i64 %iv, i32 0
+ %x0 = load double, ptr %lhs.0, align 8
+ %rhs.0 = getelementptr inbounds { double, double }, ptr %rhs, i64 %iv, i32 0
+ %y0 = load double, ptr %rhs.0, align 8
+ %p0 = call double @llvm.pow.f64(double %x0, double %y0)
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %p0, ptr %dst.0, align 8
+ %lhs.1 = getelementptr inbounds { double, double }, ptr %lhs, i64 %iv, i32 1
+ %x1 = load double, ptr %lhs.1, align 8
+ %rhs.1 = getelementptr inbounds { double, double }, ptr %rhs, i64 %iv, i32 1
+ %y1 = load double, ptr %rhs.1, align 8
+ %p1 = call double @llvm.pow.f64(double %x1, double %y1)
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %p1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+exit:
+ ret void
+}
+
+
+declare double @llvm.powi.f64.i32(double, i32)
+declare double @llvm.pow.f64(double, double)
``````````
</details>
https://github.com/llvm/llvm-project/pull/206455
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