[llvm] [CodeGen] Mark the undefined sub-registers of a tuple as IMPLICIT_DEF in two address instruction pass (PR #206442)
Vikram Hegde via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 29 02:39:01 PDT 2026
https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/206442
None
>From f7423db8423ab319d8fc6adcb6b10ea291452844 Mon Sep 17 00:00:00 2001
From: vikhegde <vikram.hegde at amd.com>
Date: Mon, 29 Jun 2026 14:54:29 +0530
Subject: [PATCH] [CodeGen] Mark the undefined sub-registers of a tuple as
IMPLICIT_DEF in two address instruction pass
---
llvm/lib/CodeGen/RegisterCoalescer.cpp | 47 +-
.../lib/CodeGen/TwoAddressInstructionPass.cpp | 62 +-
.../AArch64/aarch64-matrix-umull-smull.ll | 1 +
llvm/test/CodeGen/AArch64/arm64-dup.ll | 1 +
.../CodeGen/AArch64/arm64-neon-aba-abd.ll | 6 +
llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll | 2 +
llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll | 36 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 70 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll | 19 -
.../bug_shuffle_vector_to_scalar.ll | 3 +
.../GlobalISel/clamp-fmed3-const-combine.ll | 1 +
.../GlobalISel/clamp-minmax-const-combine.ll | 2 +
.../GlobalISel/combine-fma-add-fma-mul.ll | 4 +
.../AMDGPU/GlobalISel/combine-fma-sub-mul.ll | 4 +
.../AMDGPU/GlobalISel/extractelement.ll | 26 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll | 3 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll | 1 +
llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll | 1 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll | 9 +
.../GlobalISel/fmed3-min-max-const-combine.ll | 4 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll | 3 +
.../AMDGPU/GlobalISel/fmin3-fmax3-combine.ll | 2 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll | 3 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 1 +
.../test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll | 6 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 204 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 216 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll | 3 +
.../AMDGPU/GlobalISel/insertelement.i8.ll | 2 +
.../AMDGPU/GlobalISel/insertelement.ll | 92 +-
.../AMDGPU/GlobalISel/intrinsic-trunc.ll | 1 +
.../CodeGen/AMDGPU/GlobalISel/llvm.abs.ll | 7 +
.../AMDGPU/GlobalISel/llvm.amdgcn.fract.ll | 2 +
.../llvm.amdgcn.image.atomic.dim.ll | 30 +
.../llvm.amdgcn.image.load.1d.d16.ll | 8 +
.../llvm.amdgcn.image.store.2d.d16.ll | 3 +
.../GlobalISel/llvm.amdgcn.interp.inreg.ll | 8 +
.../CodeGen/AMDGPU/GlobalISel/llvm.powi.ll | 1 +
.../AMDGPU/GlobalISel/load-uniform-in-vgpr.ll | 22 +
llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 56 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll | 1 +
.../AMDGPU/GlobalISel/min3-max3-combine.ll | 8 +
.../AMDGPU/GlobalISel/mul-known-bits.i64.ll | 4 +
llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll | 54 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll | 36 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 31 +-
.../CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll | 439 +-
.../CodeGen/AMDGPU/GlobalISel/sext_inreg.ll | 30 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll | 5 +-
.../CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 1 +
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 23 +-
.../AMDGPU/GlobalISel/strict_fma.f32.ll | 6 +
llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll | 2 +
.../GlobalISel/true16-merge-values-s16.ll | 2 +
.../test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll | 11 +
.../test/CodeGen/AMDGPU/GlobalISel/usubsat.ll | 11 +
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 10788 ++++++++++------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 112 +
.../CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll | 352 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll | 2 +
.../CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll | 458 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll | 194 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 2532 ++--
.../CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll | 566 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 5128 ++++++--
.../CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll | 24 +
.../CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll | 378 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll | 1024 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll | 472 +
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 3622 ++++--
.../CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll | 3344 ++++-
.../CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll | 2904 ++++-
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 56 +
.../CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll | 2456 +++-
.../CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll | 1992 ++-
.../CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll | 1544 ++-
.../CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll | 1440 ++-
.../CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 712 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 418 +-
.../CodeGen/AMDGPU/any_extend_vector_inreg.ll | 78 +-
.../AMDGPU/atomic_optimizations_buffer.ll | 8 +
.../atomic_optimizations_global_pointer.ll | 32 +
.../atomic_optimizations_local_pointer.ll | 6 +
.../AMDGPU/atomic_optimizations_raw_buffer.ll | 8 +
.../atomic_optimizations_struct_buffer.ll | 8 +
.../test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll | 12 +
llvm/test/CodeGen/AMDGPU/bf16-math.ll | 5 +
llvm/test/CodeGen/AMDGPU/bf16.ll | 345 +-
llvm/test/CodeGen/AMDGPU/bitop3.ll | 3 +
llvm/test/CodeGen/AMDGPU/br_cc.f16.ll | 4 +
llvm/test/CodeGen/AMDGPU/bswap.ll | 23 +-
.../build-vector-packed-partial-undef.ll | 146 +-
llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 10 +
...-avoid-coalesce-class-with-no-registers.ll | 15 +
.../CodeGen/AMDGPU/coexec-rewrite-mfma.ll | 236 +
llvm/test/CodeGen/AMDGPU/ctpop64.ll | 1 +
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 18 +-
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 9 +
.../CodeGen/AMDGPU/div-rem-by-constant-64.ll | 36 +-
llvm/test/CodeGen/AMDGPU/div_i128.ll | 4 +-
llvm/test/CodeGen/AMDGPU/div_v2i128.ll | 104 +-
.../CodeGen/AMDGPU/extract-subvector-16bit.ll | 144 +
llvm/test/CodeGen/AMDGPU/extract-subvector.ll | 144 +
.../CodeGen/AMDGPU/extract_vector_dynelt.ll | 16 +-
.../test/CodeGen/AMDGPU/fcanonicalize.bf16.ll | 45 +-
llvm/test/CodeGen/AMDGPU/fcanonicalize.ll | 4 +
llvm/test/CodeGen/AMDGPU/fcmp.f16.ll | 2 +
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 142 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 100 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll | 2 +
llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll | 2 +
.../fix-sgpr-copies-vgpr16-to-spgr32.ll | 1 +
llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll | 2 +
llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll | 186 +-
.../CodeGen/AMDGPU/flat-scratch-i8-i16.ll | 18 +
llvm/test/CodeGen/AMDGPU/fma.f16.ll | 8 +
llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll | 1 +
llvm/test/CodeGen/AMDGPU/fmaximum.ll | 8 +
llvm/test/CodeGen/AMDGPU/fmaximum3.ll | 4 +
llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll | 1 +
llvm/test/CodeGen/AMDGPU/fmaxnum.ll | 18 +-
llvm/test/CodeGen/AMDGPU/fmed3.ll | 2 +
llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll | 1 +
llvm/test/CodeGen/AMDGPU/fminimum.ll | 8 +
llvm/test/CodeGen/AMDGPU/fminimum3.ll | 4 +
llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll | 1 +
llvm/test/CodeGen/AMDGPU/fminnum.ll | 18 +-
llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll | 50 +
llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll | 1 +
llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll | 1 +
llvm/test/CodeGen/AMDGPU/fneg.bf16.ll | 1 +
llvm/test/CodeGen/AMDGPU/fpext-free.ll | 39 +-
llvm/test/CodeGen/AMDGPU/fptoi.i128.ll | 33 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll | 13 +
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 158 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll | 13 +
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 240 +-
llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll | 13 +
llvm/test/CodeGen/AMDGPU/fptrunc.ll | 6 +
llvm/test/CodeGen/AMDGPU/frem.ll | 67 +
llvm/test/CodeGen/AMDGPU/fshr.ll | 2 +
.../CodeGen/AMDGPU/function-args-inreg.ll | 199 +-
llvm/test/CodeGen/AMDGPU/function-args.ll | 305 +-
.../AMDGPU/gfx-callable-argument-types.ll | 461 +-
.../CodeGen/AMDGPU/global-atomicrmw-fadd.ll | 10 +
.../AMDGPU/global-extload-gfx11plus.ll | 4 +
llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll | 1 +
llvm/test/CodeGen/AMDGPU/global-saddr-load.ll | 288 +-
llvm/test/CodeGen/AMDGPU/gws_agpr.ll | 12 +
llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll | 4 +
.../identical-subrange-spill-infloop.ll | 301 +-
llvm/test/CodeGen/AMDGPU/idot4s.ll | 20 +-
llvm/test/CodeGen/AMDGPU/idot4u.ll | 4 +
.../CodeGen/AMDGPU/indirect-addressing-si.ll | 50 +
.../CodeGen/AMDGPU/insert_vector_dynelt.ll | 4 +
.../insert_waitcnt_for_precise_memory.ll | 3 +
.../CodeGen/AMDGPU/integer-mad-patterns.ll | 247 +-
.../CodeGen/AMDGPU/invalid-cast-load-i1.ll | 1 +
llvm/test/CodeGen/AMDGPU/itofp.i128.ll | 234 +-
llvm/test/CodeGen/AMDGPU/kernel-args.ll | 3 +
.../AMDGPU/kernel-argument-dag-lowering.ll | 13 +-
.../test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll | 94 +-
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll | 2 +
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll | 452 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll | 7 +
.../llvm.amdgcn.image.atomic.dim.gfx90a.ll | 8 +
.../AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll | 107 -
.../llvm.amdgcn.image.gather4.a16.dim.ll | 26 +-
.../AMDGPU/llvm.amdgcn.image.msaa.load.ll | 2 +
.../llvm.amdgcn.image.sample.g16.encode.ll | 94 +-
.../AMDGPU/llvm.amdgcn.image.sample.g16.ll | 158 +-
.../AMDGPU/llvm.amdgcn.image.sample.noret.ll | 12 +-
.../AMDGPU/llvm.amdgcn.interp.inreg.ll | 217 +-
.../AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll | 2 +
.../AMDGPU/llvm.amdgcn.permlane.bcast.ll | 32 +-
.../AMDGPU/llvm.amdgcn.permlane.down.ll | 32 +-
.../CodeGen/AMDGPU/llvm.amdgcn.permlane.ll | 296 +-
.../CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll | 32 +-
.../AMDGPU/llvm.amdgcn.permlane.xor.ll | 32 +-
.../CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll | 4 +
.../llvm.amdgcn.raw.ptr.buffer.store.bf16.ll | 2 +
.../CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll | 1 +
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll | 117 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll | 117 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll | 117 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll | 117 +-
.../CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll | 1 +
.../CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll | 3 +
.../AMDGPU/llvm.amdgcn.struct.buffer.store.ll | 2 +
.../AMDGPU/llvm.amdgcn.waitcnt.out.order.ll | 6 +
.../AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll | 245 +-
.../llvm.amdgcn.wmma.imod.gfx1250.w32.ll | 16 +
.../CodeGen/AMDGPU/llvm.amdgcn.writelane.ll | 4 +
.../test/CodeGen/AMDGPU/llvm.fptrunc.round.ll | 86 +-
llvm/test/CodeGen/AMDGPU/llvm.frexp.ll | 36 +
llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll | 9 +
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 12 +
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 12 +
llvm/test/CodeGen/AMDGPU/llvm.log2.ll | 9 +
llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll | 4 +
llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll | 4 +
llvm/test/CodeGen/AMDGPU/llvm.round.ll | 8 +
llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll | 47 +-
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 3025 +++--
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll | 1415 +-
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll | 1157 +-
llvm/test/CodeGen/AMDGPU/load-global-i16.ll | 1059 +-
llvm/test/CodeGen/AMDGPU/load-global-i8.ll | 1388 +-
llvm/test/CodeGen/AMDGPU/lrint.ll | 1 +
llvm/test/CodeGen/AMDGPU/lround.ll | 13 +-
llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll | 1218 +-
llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll | 115 +-
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 114 +-
llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll | 117 +-
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll | 103 +-
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 1308 +-
llvm/test/CodeGen/AMDGPU/mad_64_32.ll | 13 +-
llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll | 43 +-
llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll | 6 +
llvm/test/CodeGen/AMDGPU/min.ll | 2 +
llvm/test/CodeGen/AMDGPU/minimummaximum.ll | 47 +-
llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll | 6 +
llvm/test/CodeGen/AMDGPU/minmax.ll | 16 +
.../CodeGen/AMDGPU/mul24-pass-ordering.ll | 13 +-
llvm/test/CodeGen/AMDGPU/packed-fp32.ll | 58 +-
.../AMDGPU/pseudo-scalar-transcendental.ll | 5 +
llvm/test/CodeGen/AMDGPU/r600-export-fix.ll | 58 +-
.../AMDGPU/reassoc-mul-add-1-to-mad.ll | 6 +
...rename-independent-subregs-unused-lanes.ll | 50 +-
llvm/test/CodeGen/AMDGPU/repeated-divisor.ll | 1 +
.../AMDGPU/rewrite-vgpr-mfma-to-agpr.ll | 11 +
llvm/test/CodeGen/AMDGPU/roundeven.ll | 1 +
llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll | 2 +
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 10 +-
llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 1030 +-
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll | 4 +
.../AMDGPU/sext-divergence-driven-isel.ll | 1 +
.../AMDGPU/sext-in-reg-vector-shuffle.ll | 2 +
.../AMDGPU/shufflevector.v2f32.v2f32.ll | 66 +-
.../AMDGPU/shufflevector.v2f32.v3f32.ll | 125 +-
.../AMDGPU/shufflevector.v2f32.v4f32.ll | 108 +-
.../AMDGPU/shufflevector.v2f32.v8f32.ll | 292 +-
.../AMDGPU/shufflevector.v2i32.v2i32.ll | 66 +-
.../AMDGPU/shufflevector.v2i32.v3i32.ll | 125 +-
.../AMDGPU/shufflevector.v2i32.v4i32.ll | 108 +-
.../AMDGPU/shufflevector.v2i32.v8i32.ll | 292 +-
.../AMDGPU/shufflevector.v2i64.v2i64.ll | 84 +-
.../AMDGPU/shufflevector.v2i64.v3i64.ll | 174 +-
.../AMDGPU/shufflevector.v2i64.v4i64.ll | 174 +-
.../AMDGPU/shufflevector.v2i64.v8i64.ll | 420 +-
.../CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll | 84 +-
.../CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll | 174 +-
.../CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll | 174 +-
.../CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll | 66 +-
.../CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll | 125 +-
.../CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll | 108 +-
.../CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll | 292 +-
.../AMDGPU/shufflevector.v3bf16.v2bf16.ll | 27 +
.../AMDGPU/shufflevector.v3bf16.v3bf16.ll | 36 +
.../AMDGPU/shufflevector.v3bf16.v4bf16.ll | 51 +
.../AMDGPU/shufflevector.v3f16.v2f16.ll | 27 +
.../AMDGPU/shufflevector.v3f16.v3f16.ll | 36 +
.../AMDGPU/shufflevector.v3f16.v4f16.ll | 51 +
.../AMDGPU/shufflevector.v3f32.v2f32.ll | 217 +-
.../AMDGPU/shufflevector.v3f32.v3f32.ll | 230 +-
.../AMDGPU/shufflevector.v3f32.v4f32.ll | 317 +-
.../AMDGPU/shufflevector.v3i16.v2i16.ll | 27 +
.../AMDGPU/shufflevector.v3i16.v3i16.ll | 36 +
.../AMDGPU/shufflevector.v3i16.v4i16.ll | 51 +
.../AMDGPU/shufflevector.v3i32.v2i32.ll | 217 +-
.../AMDGPU/shufflevector.v3i32.v3i32.ll | 230 +-
.../AMDGPU/shufflevector.v3i32.v4i32.ll | 317 +-
.../AMDGPU/shufflevector.v3i64.v2i64.ll | 194 +-
.../AMDGPU/shufflevector.v3i64.v3i64.ll | 276 +-
.../AMDGPU/shufflevector.v3i64.v4i64.ll | 426 +-
.../CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll | 194 +-
.../CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll | 276 +-
.../CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll | 426 +-
.../CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll | 217 +-
.../CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll | 230 +-
.../CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll | 317 +-
.../AMDGPU/shufflevector.v4bf16.v2bf16.ll | 186 +-
.../AMDGPU/shufflevector.v4bf16.v3bf16.ll | 84 +-
.../AMDGPU/shufflevector.v4bf16.v4bf16.ll | 114 +-
.../AMDGPU/shufflevector.v4f16.v2f16.ll | 186 +-
.../AMDGPU/shufflevector.v4f16.v3f16.ll | 84 +-
.../AMDGPU/shufflevector.v4f16.v4f16.ll | 114 +-
.../AMDGPU/shufflevector.v4f32.v2f32.ll | 311 +-
.../AMDGPU/shufflevector.v4f32.v3f32.ll | 534 +-
.../AMDGPU/shufflevector.v4f32.v4f32.ll | 599 +-
.../AMDGPU/shufflevector.v4i16.v2i16.ll | 186 +-
.../AMDGPU/shufflevector.v4i16.v3i16.ll | 84 +-
.../AMDGPU/shufflevector.v4i16.v4i16.ll | 114 +-
.../AMDGPU/shufflevector.v4i32.v2i32.ll | 303 +-
.../AMDGPU/shufflevector.v4i32.v3i32.ll | 534 +-
.../AMDGPU/shufflevector.v4i32.v4i32.ll | 599 +-
.../AMDGPU/shufflevector.v4i64.v2i64.ll | 272 +-
.../AMDGPU/shufflevector.v4i64.v3i64.ll | 458 +-
.../AMDGPU/shufflevector.v4i64.v4i64.ll | 630 +-
.../CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll | 272 +-
.../CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll | 458 +-
.../CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll | 630 +-
.../CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll | 303 +-
.../CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll | 534 +-
.../CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll | 599 +-
.../AMDGPU/si-triv-disjoint-mem-access.ll | 34 +-
llvm/test/CodeGen/AMDGPU/sign_extend.ll | 2 +
.../CodeGen/AMDGPU/spill-vector-superclass.ll | 5 +-
.../splitkit-getsubrangeformask-phi-extend.ll | 2642 ++--
llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | 1 +
llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll | 93 +-
llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll | 1 +
llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll | 93 +-
llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll | 1 +
llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll | 95 +-
llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll | 4 +
.../AMDGPU/subreg-coalescer-undef-use.ll | 13 +-
.../true16-imm-folded-to-0-regression.ll | 2 +
.../twoaddr-regsequence-keep-copy-on-use.mir | 51 +-
llvm/test/CodeGen/AMDGPU/uaddo.ll | 1 +
.../AMDGPU/undef-handling-crash-in-ra.ll | 8 +
.../AMDGPU/undefined-subreg-liverange.ll | 46 -
.../AMDGPU/uniform-vgpr-to-sgpr-return.ll | 1 +
llvm/test/CodeGen/AMDGPU/usubo.ll | 1 +
llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll | 4 +
llvm/test/CodeGen/AMDGPU/v_pack.ll | 2 +
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 12 +
llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll | 20 +
llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll | 2 +
.../test/CodeGen/AMDGPU/vector-reduce-fadd.ll | 10 +
.../test/CodeGen/AMDGPU/vector-reduce-fmax.ll | 15 +
.../test/CodeGen/AMDGPU/vector-reduce-fmin.ll | 15 +
.../CodeGen/AMDGPU/vector-reduce-fminimum.ll | 10 +
.../test/CodeGen/AMDGPU/vector-reduce-fmul.ll | 10 +
llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll | 202 +-
llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll | 2 +
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 102 +-
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 102 +-
llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll | 2 +
.../test/CodeGen/AMDGPU/vector_rebroadcast.ll | 2 +
.../CodeGen/AMDGPU/vector_shuffle.packed.ll | 53 +-
...wmma-gfx12-w32-f16-f32-matrix-modifiers.ll | 52 +-
.../AMDGPU/wmma-gfx12-w32-iu-modifiers.ll | 6 +
llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll | 10 +
...wmma-gfx12-w64-f16-f32-matrix-modifiers.ll | 120 +-
.../AMDGPU/wmma-gfx12-w64-iu-modifiers.ll | 9 +
llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll | 11 +
.../ARM/armv8.2a-fp16-vector-intrinsics.ll | 4 +
.../test/CodeGen/ARM/bf16-intrinsics-ld-st.ll | 8 +
llvm/test/CodeGen/ARM/llvm.exp10.ll | 1 +
llvm/test/CodeGen/ARM/vector-DAGCombine.ll | 1 +
llvm/test/CodeGen/ARM/vldlane.ll | 29 +-
llvm/test/CodeGen/ARM/vstlane.ll | 8 +
.../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 4 +
llvm/test/CodeGen/Thumb2/mve-clmul.ll | 294 +-
.../mve-complex-deinterleaving-f32-add.ll | 2 +
.../mve-complex-deinterleaving-f32-mul.ll | 2 +
.../mve-complex-deinterleaving-mixed-cases.ll | 151 +-
...ve-complex-deinterleaving-uniform-cases.ll | 142 +-
.../CodeGen/Thumb2/mve-fptosi-sat-vector.ll | 7 +-
.../CodeGen/Thumb2/mve-fptoui-sat-vector.ll | 7 +-
llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll | 2 +
.../Thumb2/mve-laneinterleaving-cost.ll | 9 +
.../CodeGen/Thumb2/mve-laneinterleaving.ll | 65 +-
llvm/test/CodeGen/Thumb2/mve-masked-load.ll | 22 +-
llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 14 +-
llvm/test/CodeGen/Thumb2/mve-shuffle.ll | 80 +-
llvm/test/CodeGen/Thumb2/mve-vabdus.ll | 28 +-
llvm/test/CodeGen/Thumb2/mve-vld2.ll | 4 +
llvm/test/CodeGen/Thumb2/mve-vld3.ll | 874 +-
llvm/test/CodeGen/Thumb2/mve-vld4.ll | 28 +-
llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll | 20 +-
llvm/test/CodeGen/Thumb2/mve-vst3.ll | 392 +-
.../CodeGen/Thumb2/mve-zext-masked-load.ll | 20 +-
...-sequence-compose-supports-subreg-index.ll | 2 +
375 files changed, 62294 insertions(+), 21414 deletions(-)
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 4b4ba2144f964..3e12c8b215b24 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -2668,6 +2668,11 @@ class JoinVals {
/// %dst = COPY %src <-- This value is a copy of a pruned value.
bool isPrunedValue(unsigned ValNo, JoinVals &Other);
+ /// Return true if \p ImpDef is a sub-register IMPLICIT_DEF that materializes
+ /// a real undef lane consumed by a later same-block, non-undef full-register
+ /// (e.g. tied / read-modify-write) use of its register.
+ bool isSubRegLaneProvider(const MachineInstr *ImpDef) const;
+
public:
JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask,
SmallVectorImpl<VNInfo *> &newVNInfo, const CoalescerPair &cp,
@@ -2820,6 +2825,32 @@ bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
return Orig0->def == Orig1->def && Reg0 == Reg1;
}
+bool JoinVals::isSubRegLaneProvider(const MachineInstr *ImpDef) const {
+ if (!ImpDef || !ImpDef->isImplicitDef())
+ return false;
+ const MachineOperand &DefMO = ImpDef->getOperand(0);
+ if (DefMO.getSubReg() == 0)
+ return false;
+ Register DefReg = DefMO.getReg();
+ const MachineRegisterInfo &MRI = ImpDef->getMF()->getRegInfo();
+ const MachineBasicBlock *MBB = ImpDef->getParent();
+ SlotIndex ImpDefIdx = Indexes->getInstructionIndex(*ImpDef);
+ for (const MachineOperand &MO : MRI.use_nodbg_operands(DefReg)) {
+ // We are looking for a tied (read-modify-write) full-register use later in
+ // the same block. it reads every lane
+ // - including the undef lane this IMPLICIT_DEF provides - and then
+ // redefines the register in place.
+ if (MO.isUndef() || MO.getSubReg() != 0 || !MO.isTied())
+ continue;
+ const MachineInstr *UseMI = MO.getParent();
+ if (UseMI->getParent() != MBB)
+ continue;
+ if (Indexes->getInstructionIndex(*UseMI) > ImpDefIdx)
+ return true;
+ }
+ return false;
+}
+
JoinVals::ConflictResolution JoinVals::analyzeValue(unsigned ValNo,
JoinVals &Other) {
Val &V = Vals[ValNo];
@@ -2845,7 +2876,9 @@ JoinVals::ConflictResolution JoinVals::analyzeValue(unsigned ValNo,
V.WriteLanes = V.ValidLanes = LaneBitmask::getLane(0);
if (DefMI->isImplicitDef()) {
V.ValidLanes = LaneBitmask::getNone();
- V.ErasableImplicitDef = true;
+ // A sub-register IMPLICIT_DEF read by a same-block full-register use is
+ // a real lane provider, not a disposable placeholder; keep it.
+ V.ErasableImplicitDef = !isSubRegLaneProvider(DefMI);
}
} else {
bool Redef = false;
@@ -2884,7 +2917,10 @@ JoinVals::ConflictResolution JoinVals::analyzeValue(unsigned ValNo,
//
// Clearing the valid lanes is deferred until it is sure this can be
// erased.
- V.ErasableImplicitDef = true;
+ //
+ // A sub-register IMPLICIT_DEF read by a same-block full-register use is
+ // a real lane provider, not a disposable placeholder; keep it.
+ V.ErasableImplicitDef = !isSubRegLaneProvider(DefMI);
}
}
}
@@ -2983,7 +3019,12 @@ JoinVals::ConflictResolution JoinVals::analyzeValue(unsigned ValNo,
return CR_Replace;
// Check for simple erasable conflicts.
- if (DefMI->isImplicitDef())
+ //
+ // A sub-register IMPLICIT_DEF that materializes a real undef lane consumed by
+ // a same-block full-register use must not be erased here: it overlaps the
+ // neighbouring lane's data value, but writes a disjoint lane, so let the
+ // lane-based resolution below (CR_Replace) handle it instead of erasing it.
+ if (DefMI->isImplicitDef() && !isSubRegLaneProvider(DefMI))
return CR_Erase;
// Include the non-conflict where DefMI is a coalescable copy that kills
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index fb3014d87f40a..648f310c9b539 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -2055,13 +2055,40 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
}
}
+ MachineBasicBlock::iterator EndMBBI =
+ std::next(MachineBasicBlock::iterator(MI));
+
// If there are no live intervals information, we scan the use list once
// in order to find which subregisters are used.
+ bool HasFullRegUse = false;
+ bool IsFullyUndef = true;
+ for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
+ if (!MI.getOperand(i).isUndef()) {
+ IsFullyUndef = false;
+ break;
+ }
+
+ if (IsFullyUndef) {
+ LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
+ MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
+ for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
+ MI.removeOperand(j);
+
+ return;
+ }
+
LaneBitmask UsedLanes = LaneBitmask::getNone();
if (!LIS) {
for (MachineOperand &Use : MRI->use_nodbg_operands(DstReg)) {
if (unsigned SubReg = Use.getSubReg())
UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
+ else {
+ for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
+ unsigned SubIdx = MI.getOperand(i + 1).getImm();
+ UsedLanes |= TRI->getSubRegIndexLaneMask(SubIdx);
+ }
+ break;
+ }
}
}
@@ -2074,8 +2101,8 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
// Nothing needs to be inserted for undef operands.
// Unless there are no live intervals, and they are used at a later
// instruction as operand.
+ LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubIdx);
if (UseMO.isUndef()) {
- LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubIdx);
if (LIS || (UsedLanes & LaneMask).none()) {
UndefLanes |= LaneMask;
continue;
@@ -2094,11 +2121,18 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
break;
}
- // Insert the sub-register copy.
- MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
- TII->get(TargetOpcode::COPY))
- .addReg(DstReg, RegState::Define, SubIdx)
- .add(UseMO);
+ MachineInstr *CopyMI = nullptr;
+ if (UseMO.isUndef() && !(UsedLanes & LaneMask).none()) {
+ CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
+ TII->get(TargetOpcode::IMPLICIT_DEF))
+ .addReg(DstReg, RegState::Define, SubIdx);
+ } else {
+ // Insert the sub-register copy.
+ CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
+ TII->get(TargetOpcode::COPY))
+ .addReg(DstReg, RegState::Define, SubIdx)
+ .add(UseMO);
+ }
// The first def needs an undef flag because there is no live register
// before it.
@@ -2116,15 +2150,6 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
LLVM_DEBUG(dbgs() << "Inserted: " << *CopyMI);
}
- MachineBasicBlock::iterator EndMBBI =
- std::next(MachineBasicBlock::iterator(MI));
-
- if (!DefEmitted) {
- LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
- MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
- for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
- MI.removeOperand(j);
- } else {
if (LIS) {
// Force live interval recomputation if we moved to a partial definition
// of the register. Undef flags must be propagate to uses of undefined
@@ -2150,9 +2175,8 @@ void TwoAddressInstructionImpl::eliminateRegSequence(
LLVM_DEBUG(dbgs() << "Eliminated: " << MI);
MI.eraseFromParent();
- }
- // Udpate LiveIntervals.
- if (LIS)
- LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);
+ // Udpate LiveIntervals.
+ if (LIS)
+ LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);
}
diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
index 79e428cdf7fca..71a90e5d12c4f 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
@@ -207,6 +207,7 @@ define void @matrix_mul_double_shuffle(i32 %N, ptr nocapture %C, ptr nocapture r
; CHECK-GI-NEXT: fmov s2, w9
; CHECK-GI-NEXT: mov w9, w0
; CHECK-GI-NEXT: add w0, w0, #8
+; CHECK-GI-NEXT: // implicit-def: $q3
; CHECK-GI-NEXT: lsl x9, x9, #2
; CHECK-GI-NEXT: tbl v2.16b, { v2.16b, v3.16b }, v1.16b
; CHECK-GI-NEXT: mul v2.4s, v0.4s, v2.4s
diff --git a/llvm/test/CodeGen/AArch64/arm64-dup.ll b/llvm/test/CodeGen/AArch64/arm64-dup.ll
index 49fb6c98e223f..d93aa7a59e646 100644
--- a/llvm/test/CodeGen/AArch64/arm64-dup.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-dup.ll
@@ -513,6 +513,7 @@ define void @disguised_dup(<4 x float> %x, ptr %p1, ptr %p2) {
; CHECK-GI-NEXT: adrp x8, .LCPI38_1
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI38_1]
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: adrp x8, .LCPI38_0
; CHECK-GI-NEXT: tbl.16b v0, { v0, v1 }, v2
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI38_0]
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
index 9ffda5b9b0af9..7e1524a914fda 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
@@ -491,6 +491,7 @@ define <4 x i32> @test_sabd_knownbits_vec4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI43_0]
; CHECK-GI-NEXT: movi v3.2d, #0x0000ff000000ff
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b
; CHECK-GI-NEXT: ret
@@ -522,6 +523,7 @@ define <4 x i32> @knownbits_sabd_and_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI44_0]
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
@@ -549,6 +551,7 @@ define <4 x i32> @knownbits_sabd_and_or_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v3.16b
; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-GI-NEXT: uabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
@@ -586,6 +589,7 @@ define <4 x i32> @knownbits_sabd_and_xor_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: eor v0.16b, v0.16b, v3.16b
; CHECK-GI-NEXT: eor v1.16b, v1.16b, v3.16b
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
@@ -614,6 +618,7 @@ define <4 x i32> @knownbits_sabd_and_shl_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #17
; CHECK-GI-NEXT: shl v1.4s, v1.4s, #17
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
@@ -650,6 +655,7 @@ define <4 x i32> @knownbits_sabd_and_mul_mask(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-GI-NEXT: mul v1.4s, v1.4s, v2.4s
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI48_0]
; CHECK-GI-NEXT: sabd v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: // implicit-def: $q1
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-GI-NEXT: ret
%1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
index 262254c8a9cf7..0539becd43133 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
@@ -86,6 +86,7 @@ define i16 @v_add_i16(i16 %a, i16 %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_add_i16:
@@ -96,6 +97,7 @@ define i16 @v_add_i16(i16 %a, i16 %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = add i16 %a, %b
ret i16 %c
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
index 3a1977f69f71c..c17b1a8688421 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
@@ -470,6 +470,7 @@ define i16 @v_andn2_i16(i16 %src0, i16 %src1) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v1.l, -1
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_andn2_i16:
@@ -979,14 +980,33 @@ define <3 x i16> @v_andn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {
; GFX9-NEXT: v_and_b32_e32 v1, v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_andn2_v3i16:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX10PLUS-NEXT: v_xor_b32_e32 v3, -11, v3
-; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v3
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_andn2_v3i16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX10-NEXT: v_xor_b32_e32 v3, -11, v3
+; GFX10-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX10-NEXT: v_and_b32_e32 v1, v1, v3
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_andn2_v3i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v3, -11, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_andn2_v3i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v3, -11, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -11>
%and = and <3 x i16> %src0, %not.src1
ret <3 x i16> %and
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index f3358b7cbff84..c63a2e87124db 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -40,6 +40,7 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -87,6 +88,7 @@ define i8 @v_ashr_i8_7(i8 %value) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 7, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -644,6 +646,7 @@ define i16 @v_ashr_i16(i16 %value, i16 %amount) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ashr_i16:
@@ -685,6 +688,7 @@ define i16 @v_ashr_i16_15(i16 %value) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 15, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ashr_i16_15:
@@ -754,6 +758,7 @@ define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {
; GFX11-TRUE16-LABEL: ashr_i16_sv:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v0.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: ashr_i16_sv:
@@ -791,6 +796,7 @@ define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) {
; GFX11-TRUE16-LABEL: ashr_i16_vs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, s0, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: ashr_i16_vs:
@@ -1914,21 +1920,23 @@ define i65 @v_ashr_i65_33(i65 %value) {
define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
; GCN-LABEL: s_ashr_i65:
; GCN: ; %bb.0:
-; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
-; GCN-NEXT: s_sub_i32 s10, s3, 64
-; GCN-NEXT: s_sub_i32 s8, 64, s3
-; GCN-NEXT: s_cmp_lt_u32 s3, 64
+; GCN-NEXT: s_mov_b32 s4, s3
+; GCN-NEXT: ; implicit-def: $sgpr3
+; GCN-NEXT: s_sub_i32 s10, s4, 64
+; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GCN-NEXT: s_sub_i32 s8, 64, s4
+; GCN-NEXT: s_cmp_lt_u32 s4, 64
; GCN-NEXT: s_cselect_b32 s11, 1, 0
-; GCN-NEXT: s_cmp_eq_u32 s3, 0
+; GCN-NEXT: s_cmp_eq_u32 s4, 0
; GCN-NEXT: s_cselect_b32 s12, 1, 0
-; GCN-NEXT: s_ashr_i64 s[6:7], s[4:5], s3
-; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3
-; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8
-; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GCN-NEXT: s_ashr_i32 s7, s5, 31
-; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], s10
+; GCN-NEXT: s_ashr_i64 s[6:7], s[2:3], s4
+; GCN-NEXT: s_lshr_b64 s[4:5], s[0:1], s4
+; GCN-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
+; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
+; GCN-NEXT: s_ashr_i32 s7, s3, 31
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], s10
; GCN-NEXT: s_cmp_lg_u32 s11, 0
-; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; GCN-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s12, 0
; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s11, 0
@@ -1937,25 +1945,27 @@ define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
;
; GFX10PLUS-LABEL: s_ashr_i65:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
-; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 64
-; GFX10PLUS-NEXT: s_sub_i32 s2, 64, s3
-; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64
+; GFX10PLUS-NEXT: s_mov_b32 s4, s3
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
+; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX10PLUS-NEXT: s_sub_i32 s10, s4, 64
+; GFX10PLUS-NEXT: s_sub_i32 s5, 64, s4
+; GFX10PLUS-NEXT: s_cmp_lt_u32 s4, 64
; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s4, 0
; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0
-; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s3
-; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s2
-; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[4:5], s3
+; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s4
+; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[2:3], s5
+; GFX10PLUS-NEXT: s_ashr_i64 s[4:5], s[2:3], s4
; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX10PLUS-NEXT: s_ashr_i32 s3, s5, 31
-; GFX10PLUS-NEXT: s_ashr_i64 s[4:5], s[4:5], s10
+; GFX10PLUS-NEXT: s_ashr_i32 s5, s3, 31
+; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[2:3], s10
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s2, s3
+; GFX10PLUS-NEXT: s_cselect_b32 s2, s4, s5
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = ashr i65 %value, %amount
ret i65 %result
@@ -1964,8 +1974,9 @@ define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
; GCN-LABEL: s_ashr_i65_33:
; GCN: ; %bb.0:
-; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GCN-NEXT: ; implicit-def: $sgpr3
; GCN-NEXT: s_lshr_b32 s4, s1, 1
+; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
; GCN-NEXT: s_or_b32 s0, s0, s4
; GCN-NEXT: s_ashr_i32 s2, s3, 1
@@ -1973,8 +1984,9 @@ define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
;
; GFX10PLUS-LABEL: s_ashr_i65_33:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 1
+; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 1
; GFX10PLUS-NEXT: s_or_b32 s0, s0, s4
@@ -2066,7 +2078,11 @@ define <4 x i2> @v_ashr_v4i2(<4 x i2> %value, <4 x i2> %amount) {
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v4.l, v0.l
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v1.l, v0.h, v1.l
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v2.l, v1.h, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v3.l, v2.h, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ashr_v4i2:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
index b8b953143c7e8..4ee6f1a9f216a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
@@ -402,12 +402,6 @@ define amdgpu_ps i16 @s_bswap_i16(i16 inreg %src) {
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_bswap_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s0, 0xc0c0001
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
%bswap = call i16 @llvm.bswap.i16(i16 %src)
ret i16 %bswap
}
@@ -434,12 +428,6 @@ define i16 @v_bswap_i16(i16 %src) {
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0001
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_bswap_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
-; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
ret i16 %bswap
}
@@ -545,13 +533,6 @@ define i32 @v_bswap_i16_sext_to_i32(i16 %src) {
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_bswap_i16_sext_to_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
-; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = sext i16 %bswap to i32
ret i32 %zext
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll
index 53ce942d4e8f7..08b66e4b3bdd8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll
@@ -10,6 +10,9 @@ define amdgpu_gs <4 x float> @_amdgpu_gs_main() {
; CHECK-NEXT: v_mov_b32_e32 v0, 16
; CHECK-NEXT: ds_read2_b32 v[3:4], v0 offset1:1
; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: ; implicit-def: $sgpr5
+; CHECK-NEXT: ; implicit-def: $sgpr6
+; CHECK-NEXT: ; implicit-def: $sgpr7
; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: s_mov_b32 s2, s0
; CHECK-NEXT: s_mov_b32 s3, s0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
index d00c4169fd6e7..c29f856c1940a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
@@ -52,6 +52,7 @@ define half @test_fmed3_f16_known_nnan_ieee_false(half %a) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, 2.0 clamp
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_fmed3_f16_known_nnan_ieee_false:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
index 75be830fc8a77..c0c91db03a536 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
@@ -82,6 +82,7 @@ define half @test_min_K1max_ValK0_f16(half %a) #2 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, 2.0 clamp
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_min_K1max_ValK0_f16:
@@ -234,6 +235,7 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, 2.0 clamp
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_max_K0min_ValK1_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
index c575bc4e5e129..6d84540b4740c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
@@ -160,6 +160,7 @@ define half @test_half_add_mul(half %a, half %b, half %c, half %d, half %e) {
; GFX11-CONTRACT-TRUE16: ; %bb.0: ; %.entry
; GFX11-CONTRACT-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v2.l, v3.l
+; GFX11-CONTRACT-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-CONTRACT-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v0.l, v1.l
; GFX11-CONTRACT-TRUE16-NEXT: v_mov_b32_e32 v0, v4
@@ -181,6 +182,7 @@ define half @test_half_add_mul(half %a, half %b, half %c, half %d, half %e) {
; GFX11-DENORM-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-DENORM-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-DENORM-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-DENORM-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-DENORM-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
; GFX11-DENORM-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -237,6 +239,7 @@ define half @test_half_add_mul_rhs(half %a, half %b, half %c, half %d, half %e)
; GFX11-CONTRACT-TRUE16: ; %bb.0: ; %.entry
; GFX11-CONTRACT-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v2.l, v3.l
+; GFX11-CONTRACT-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-CONTRACT-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v0.l, v1.l
; GFX11-CONTRACT-TRUE16-NEXT: v_mov_b32_e32 v0, v4
@@ -258,6 +261,7 @@ define half @test_half_add_mul_rhs(half %a, half %b, half %c, half %d, half %e)
; GFX11-DENORM-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-DENORM-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-DENORM-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-DENORM-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-DENORM-TRUE16-NEXT: v_add_f16_e32 v0.l, v4.l, v0.l
; GFX11-DENORM-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
index d170ec4975edf..56dfc160ccd97 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
@@ -173,6 +173,7 @@ define half @test_half_sub_mul(half %x, half %y, half %z) {
; GFX11-CONTRACT-TRUE16: ; %bb.0: ; %.entry
; GFX11-CONTRACT-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-CONTRACT-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, -v2.l
+; GFX11-CONTRACT-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-CONTRACT-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-CONTRACT-FAKE16-LABEL: test_half_sub_mul:
@@ -185,6 +186,7 @@ define half @test_half_sub_mul(half %x, half %y, half %z) {
; GFX11-DENORM-TRUE16: ; %bb.0: ; %.entry
; GFX11-DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-DENORM-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-DENORM-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-DENORM-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DENORM-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
; GFX11-DENORM-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -246,6 +248,7 @@ define half @test_half_sub_mul_rhs(half %x, half %y, half %z) {
; GFX11-CONTRACT-TRUE16: ; %bb.0: ; %.entry
; GFX11-CONTRACT-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-CONTRACT-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v1.l, v2.l
+; GFX11-CONTRACT-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-CONTRACT-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-CONTRACT-FAKE16-LABEL: test_half_sub_mul_rhs:
@@ -258,6 +261,7 @@ define half @test_half_sub_mul_rhs(half %x, half %y, half %z) {
; GFX11-DENORM-TRUE16: ; %bb.0: ; %.entry
; GFX11-DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-DENORM-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-DENORM-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-DENORM-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DENORM-TRUE16-NEXT: v_sub_f16_e32 v0.l, v2.l, v0.l
; GFX11-DENORM-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
index 22cd226bf9b4c..67992ac8b44e9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
@@ -2745,29 +2745,32 @@ define amdgpu_ps double @dyn_extract_v7f64_v_s(<7 x double> %vec, i32 inreg %sel
; GPRIDX-LABEL: dyn_extract_v7f64_v_s:
; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1
+; GPRIDX-NEXT: ; implicit-def: $vgpr14_vgpr15
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
-; GPRIDX-NEXT: v_mov_b32_e32 v14, v0
+; GPRIDX-NEXT: v_mov_b32_e32 v16, v0
; GPRIDX-NEXT: v_mov_b32_e32 v0, v1
; GPRIDX-NEXT: s_set_gpr_idx_off
-; GPRIDX-NEXT: v_readfirstlane_b32 s0, v14
+; GPRIDX-NEXT: v_readfirstlane_b32 s0, v16
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v0
; GPRIDX-NEXT: ; return to shader part epilog
;
; MOVREL-LABEL: dyn_extract_v7f64_v_s:
; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
-; MOVREL-NEXT: v_movrels_b32_e32 v14, v0
+; MOVREL-NEXT: ; implicit-def: $vgpr14_vgpr15
+; MOVREL-NEXT: v_movrels_b32_e32 v16, v0
; MOVREL-NEXT: v_movrels_b32_e32 v0, v1
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v14
+; MOVREL-NEXT: v_readfirstlane_b32 s0, v16
; MOVREL-NEXT: v_readfirstlane_b32 s1, v0
; MOVREL-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_extract_v7f64_v_s:
; GFX10PLUS: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1
-; GFX10PLUS-NEXT: v_movrels_b32_e32 v14, v0
+; GFX10PLUS-NEXT: ; implicit-def: $vgpr14_vgpr15
+; GFX10PLUS-NEXT: v_movrels_b32_e32 v16, v0
; GFX10PLUS-NEXT: v_movrels_b32_e32 v0, v1
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v14
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v16
; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v0
; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
@@ -2793,6 +2796,7 @@ define amdgpu_ps double @dyn_extract_v7f64_s_s(<7 x double> inreg %vec, i32 inre
; GCN-NEXT: s_mov_b32 s11, s13
; GCN-NEXT: s_mov_b32 s12, s14
; GCN-NEXT: s_mov_b32 s13, s15
+; GCN-NEXT: ; implicit-def: $sgpr14_sgpr15
; GCN-NEXT: s_movrels_b64 s[0:1], s[0:1]
; GCN-NEXT: ; return to shader part epilog
;
@@ -2813,6 +2817,7 @@ define amdgpu_ps double @dyn_extract_v7f64_s_s(<7 x double> inreg %vec, i32 inre
; GFX10PLUS-NEXT: s_mov_b32 s11, s13
; GFX10PLUS-NEXT: s_mov_b32 s12, s14
; GFX10PLUS-NEXT: s_mov_b32 s13, s15
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr14_sgpr15
; GFX10PLUS-NEXT: s_movrels_b64 s[0:1], s[0:1]
; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
@@ -3324,6 +3329,7 @@ define amdgpu_ps float @dyn_extract_v15f32_const_s_s(i32 inreg %sel) {
; GCN-NEXT: s_mov_b32 s7, 4.0
; GCN-NEXT: s_mov_b32 s6, 0x40400000
; GCN-NEXT: s_mov_b32 s5, 2.0
+; GCN-NEXT: ; implicit-def: $sgpr19
; GCN-NEXT: s_movrels_b32 s0, s4
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: ; return to shader part epilog
@@ -3346,6 +3352,7 @@ define amdgpu_ps float @dyn_extract_v15f32_const_s_s(i32 inreg %sel) {
; GFX10PLUS-NEXT: s_mov_b32 s7, 4.0
; GFX10PLUS-NEXT: s_mov_b32 s6, 0x40400000
; GFX10PLUS-NEXT: s_mov_b32 s5, 2.0
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr19
; GFX10PLUS-NEXT: s_movrels_b32 s0, s4
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0
; GFX10PLUS-NEXT: ; return to shader part epilog
@@ -3556,6 +3563,7 @@ entry:
define amdgpu_ps float @dyn_extract_v15f32_v_s(<15 x float> %vec, i32 inreg %sel) {
; GPRIDX-LABEL: dyn_extract_v15f32_v_s:
; GPRIDX: ; %bb.0: ; %entry
+; GPRIDX-NEXT: ; implicit-def: $vgpr15
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0)
; GPRIDX-NEXT: v_mov_b32_e32 v0, v0
; GPRIDX-NEXT: s_set_gpr_idx_off
@@ -3564,12 +3572,14 @@ define amdgpu_ps float @dyn_extract_v15f32_v_s(<15 x float> %vec, i32 inreg %sel
; MOVREL-LABEL: dyn_extract_v15f32_v_s:
; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 m0, s2
+; MOVREL-NEXT: ; implicit-def: $vgpr15
; MOVREL-NEXT: v_movrels_b32_e32 v0, v0
; MOVREL-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: dyn_extract_v15f32_v_s:
; GFX10PLUS: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: s_mov_b32 m0, s2
+; GFX10PLUS-NEXT: ; implicit-def: $vgpr15
; GFX10PLUS-NEXT: v_movrels_b32_e32 v0, v0
; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
@@ -3596,6 +3606,7 @@ define amdgpu_ps float @dyn_extract_v15f32_s_s(<15 x float> inreg %vec, i32 inre
; GCN-NEXT: s_mov_b32 s12, s14
; GCN-NEXT: s_mov_b32 s13, s15
; GCN-NEXT: s_mov_b32 s14, s16
+; GCN-NEXT: ; implicit-def: $sgpr15
; GCN-NEXT: s_movrels_b32 s0, s0
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: ; return to shader part epilog
@@ -3618,6 +3629,7 @@ define amdgpu_ps float @dyn_extract_v15f32_s_s(<15 x float> inreg %vec, i32 inre
; GFX10PLUS-NEXT: s_mov_b32 s12, s14
; GFX10PLUS-NEXT: s_mov_b32 s13, s15
; GFX10PLUS-NEXT: s_mov_b32 s14, s16
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr15
; GFX10PLUS-NEXT: s_movrels_b32 s0, s0
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0
; GFX10PLUS-NEXT: ; return to shader part epilog
@@ -3645,6 +3657,7 @@ define amdgpu_ps float @dyn_extract_v15f32_s_s_offset3(<15 x float> inreg %vec,
; GCN-NEXT: s_mov_b32 s12, s14
; GCN-NEXT: s_mov_b32 s13, s15
; GCN-NEXT: s_mov_b32 s14, s16
+; GCN-NEXT: ; implicit-def: $sgpr15
; GCN-NEXT: s_movrels_b32 s0, s3
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: ; return to shader part epilog
@@ -3667,6 +3680,7 @@ define amdgpu_ps float @dyn_extract_v15f32_s_s_offset3(<15 x float> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s12, s14
; GFX10PLUS-NEXT: s_mov_b32 s13, s15
; GFX10PLUS-NEXT: s_mov_b32 s14, s16
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr15
; GFX10PLUS-NEXT: s_movrels_b32 s0, s3
; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0
; GFX10PLUS-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
index b42982a7993de..3a7154e69b24f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
@@ -13,6 +13,7 @@ define amdgpu_ps half @fadd_s16_uniform(half inreg %a, half inreg %b) {
; GFX11-TRUE16-LABEL: fadd_s16_uniform:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, s0, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fadd_s16_uniform:
@@ -34,6 +35,7 @@ define amdgpu_ps half @fadd_s16_div(half %a, half %b) {
; GFX11-TRUE16-LABEL: fadd_s16_div:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: fadd_s16_div:
@@ -44,6 +46,7 @@ define amdgpu_ps half @fadd_s16_div(half %a, half %b) {
; GFX12-TRUE16-LABEL: fadd_s16_div:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: ; return to shader part epilog
%fadd = fadd half %a, %b
ret half %fadd
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
index d973d95596312..5f4cfee733b4d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
@@ -83,6 +83,7 @@ define half @fceil_s16_v(half %val) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_ceil_f16_e32 v0.l, v0.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.ceil.f16(half %val)
ret half %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
index ae2e590f0b5c3..5392af5aa7dd8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
@@ -83,6 +83,7 @@ define half @ffloor_s16_v(half %val) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_floor_f16_e32 v0.l, v0.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.floor.f16(half %val)
ret half %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
index df5477756460e..a7df670e6f05d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
@@ -153,6 +153,7 @@ define half @v_fma_f16(half %x, half %y, half %z) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -170,6 +171,7 @@ define half @v_fma_f16(half %x, half %y, half %z) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
+; GFX12-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-NEXT: v_mov_b32_e32 v0, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%fma = call half @llvm.fma.f16(half %x, half %y, half %z)
@@ -215,6 +217,7 @@ define half @v_fma_f16_fneg_lhs(half %x, half %y, half %z) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fma_f16_fneg_lhs:
@@ -231,6 +234,7 @@ define half @v_fma_f16_fneg_lhs(half %x, half %y, half %z) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_fma_f16 v0.l, -v0.l, v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg half %x
%fma = call half @llvm.fma.f16(half %neg.x, half %y, half %z)
@@ -276,6 +280,7 @@ define half @v_fma_f16_fneg_rhs(half %x, half %y, half %z) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fma_f16_fneg_rhs:
@@ -292,6 +297,7 @@ define half @v_fma_f16_fneg_rhs(half %x, half %y, half %z) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_fma_f16 v0.l, v0.l, -v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.y = fneg half %y
%fma = call half @llvm.fma.f16(half %x, half %neg.y, half %z)
@@ -337,6 +343,7 @@ define half @v_fma_f16_fneg_add(half %x, half %y, half %z) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, -v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fma_f16_fneg_add:
@@ -353,6 +360,7 @@ define half @v_fma_f16_fneg_add(half %x, half %y, half %z) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_fma_f16 v0.l, v0.l, v1.l, -v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.z = fneg half %z
%fma = call half @llvm.fma.f16(half %x, half %y, half %neg.z)
@@ -1507,6 +1515,7 @@ define amdgpu_ps half @fma_s16_uniform(half inreg %a, half inreg %b, half inreg
; GFX11-TRUE16-LABEL: fma_s16_uniform:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_fmac_f16_e64 v0.l, s0, s1
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
index 3c16b0ccc7c1f..60282708e7712 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
@@ -105,6 +105,7 @@ define half @test_min_K1max_ValK0_f16(half %a) #0 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_med3_num_f16 v0.l, v0.l, 2.0, 4.0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -153,6 +154,7 @@ define half @test_min_K1max_K0Val_f16(half %a) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_med3_num_f16 v0.l, v0.l, 2.0, 4.0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_min_K1max_K0Val_f16:
@@ -264,6 +266,7 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_med3_num_f16 v0.l, v0.l, 2.0, 4.0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_max_K0min_ValK1_f16:
@@ -308,6 +311,7 @@ define half @test_max_K0min_K1Val_f16(half %a) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_med3_num_f16 v0.l, v0.l, 2.0, 4.0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_max_K0min_K1Val_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
index f8f589b00e8c7..5bc9a2d8ddda0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
@@ -13,6 +13,7 @@ define amdgpu_ps half @fmed3_s16_uniform(half inreg %a, half inreg %b, half inre
; GFX12-LABEL: fmed3_s16_uniform:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_med3_num_f16 v0.l, s0, s1, v0.l
; GFX12-NEXT: ; return to shader part epilog
@@ -32,6 +33,7 @@ define amdgpu_ps half @fmed3_s16_uniform_salu_use(half inreg %a, half inreg %b,
; GFX12-LABEL: fmed3_s16_uniform_salu_use:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_med3_num_f16 v0.l, s0, s1, v0.l
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
@@ -54,6 +56,7 @@ define amdgpu_ps half @fmed3_s16_div(half %a, half %b, half %c) {
; GFX12-LABEL: fmed3_s16_div:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_med3_num_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: ; return to shader part epilog
%result = call half @llvm.amdgcn.fmed3.f16(half %a, half %b, half %c)
ret half %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
index e035f19ace914..9f5219167250a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
@@ -621,6 +621,7 @@ define half @fmaximum3_f16(half %a, half %b, half %c) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_maximum3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%m1 = call half @llvm.maximum.f16(half %a, half %b)
%m2 = call half @llvm.maximum.f16(half %m1, half %c)
@@ -647,6 +648,7 @@ define half @fminimum3_f16(half %a, half %b, half %c) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_minimum3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%m1 = call half @llvm.minimum.f16(half %a, half %b)
%m2 = call half @llvm.minimum.f16(half %m1, half %c)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
index 8e7a804677331..f4ca19a9e76bb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
@@ -13,6 +13,7 @@ define amdgpu_ps half @fmul_s16_uniform(half inreg %a, half inreg %b) {
; GFX11-TRUE16-LABEL: fmul_s16_uniform:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, s0, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fmul_s16_uniform:
@@ -34,6 +35,7 @@ define amdgpu_ps half @fmul_s16_div(half %a, half %b) {
; GFX11-TRUE16-LABEL: fmul_s16_div:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: fmul_s16_div:
@@ -44,6 +46,7 @@ define amdgpu_ps half @fmul_s16_div(half %a, half %b) {
; GFX12-TRUE16-LABEL: fmul_s16_div:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: ; return to shader part epilog
%result = fmul half %a, %b
ret half %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index 74d05644908eb..190a855a26cdf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -382,6 +382,7 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
index f8c1fc2416cd8..d69826765fc57 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
@@ -15,6 +15,7 @@ define amdgpu_ps half @fptrunc_f32_to_f16_uniform(float inreg %a) {
; GFX11-TRUE16-LABEL: fptrunc_f32_to_f16_uniform:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fptrunc_f32_to_f16_uniform:
@@ -45,6 +46,7 @@ define amdgpu_ps half @fptrunc_f32_to_f16_div(float %a) {
; GFX11-TRUE16-LABEL: fptrunc_f32_to_f16_div:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: fptrunc_f32_to_f16_div:
@@ -55,6 +57,7 @@ define amdgpu_ps half @fptrunc_f32_to_f16_div(float %a) {
; GFX12-TRUE16-LABEL: fptrunc_f32_to_f16_div:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: fptrunc_f32_to_f16_div:
@@ -69,6 +72,7 @@ define amdgpu_ps half @fptrunc_f32_to_f16_div(float %a) {
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
%result = fptrunc float %a to half
ret half %result
@@ -445,6 +449,8 @@ define amdgpu_ps <2 x half> @fptrunc_v2f32_to_v2f16_uniform(<2 x float> inreg %a
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 9d3302a996ebd..76422893427e0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -272,8 +272,9 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: s_mul_i32 s5, s4, -7
; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, -7, v[2:3]
+; GFX9-NEXT: v_mul_hi_u32 v4, v2, s4
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, -7, v[2:3]
; GFX9-NEXT: v_add_u32_e32 v3, -7, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
@@ -299,11 +300,12 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
+; GFX10-NEXT: ; implicit-def: $vgpr3
; GFX10-NEXT: s_mul_i32 s5, s4, -7
; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v3, -7, v[2:3]
+; GFX10-NEXT: v_mul_hi_u32 v4, v2, s4
+; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v4, -7, v[2:3]
; GFX10-NEXT: v_add_nc_u32_e32 v3, -7, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
@@ -332,17 +334,18 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: s_mul_i32 s1, s0, -7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_mul_hi_u32 s1, s0, s1
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_hi_u32 v5, v2, s0
-; GFX11-TRUE16-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
+; GFX11-TRUE16-NEXT: v_mul_hi_u32 v6, v2, s0
+; GFX11-TRUE16-NEXT: v_mad_u64_u32 v[4:5], null, v6, -7, v[2:3]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -7, v3
-; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -7, v4
+; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, -7, v2
; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
@@ -356,6 +359,7 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshl_i7:
@@ -372,17 +376,18 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: s_mul_i32 s1, s0, -7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_mul_hi_u32 s1, s0, s1
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, s1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mul_hi_u32 v5, v2, s0
-; GFX11-FAKE16-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
+; GFX11-FAKE16-NEXT: v_mul_hi_u32 v6, v2, s0
+; GFX11-FAKE16-NEXT: v_mad_u64_u32 v[4:5], null, v6, -7, v[2:3]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -7, v3
-; GFX11-FAKE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -7, v4
+; GFX11-FAKE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v4
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, -7, v2
; GFX11-FAKE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
@@ -529,6 +534,7 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshl_i8:
@@ -642,6 +648,7 @@ define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 4, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshl_i8_4:
@@ -749,6 +756,7 @@ define i8 @v_fshl_i8_5(i8 %lhs, i8 %rhs) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 3, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshl_i8_5:
@@ -1038,6 +1046,7 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshl_v2i8:
@@ -1580,15 +1589,19 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, v1.l, v9.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v2.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v1.h, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.h, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xff, v0, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
@@ -1903,7 +1916,7 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_not_b32_e32 v4, 23
+; GFX9-NEXT: v_not_b32_e32 v5, 23
; GFX9-NEXT: v_bfe_u32 v1, v1, 1, 23
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
@@ -1911,8 +1924,9 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v4, v[2:3]
+; GFX9-NEXT: v_mul_hi_u32 v4, v2, s4
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v5, v[2:3]
; GFX9-NEXT: v_add_u32_e32 v3, 0xffffffe8, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
@@ -1936,11 +1950,12 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
+; GFX10-NEXT: ; implicit-def: $vgpr3
; GFX10-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, 0xffffffe8, v3, v[2:3]
+; GFX10-NEXT: v_mul_hi_u32 v4, v2, s4
+; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, 0xffffffe8, v4, v[2:3]
; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
@@ -1967,17 +1982,18 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: v_mul_hi_u32 v5, v2, s0
+; GFX11-NEXT: v_mul_hi_u32 v6, v2, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, 0xffffffe8, v5, v[2:3]
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xffffffe8, v3
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v3
+; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, 0xffffffe8, v6, v[2:3]
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xffffffe8, v4
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2847,32 +2863,34 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_not_b32_e32 v8, 23
; GFX9-NEXT: v_bfe_u32 v2, v2, 1, 23
-; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX9-NEXT: v_bfe_u32 v3, v3, 1, 23
-; GFX9-NEXT: v_readfirstlane_b32 s4, v6
+; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v6
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v4
+; GFX9-NEXT: v_readfirstlane_b32 s4, v7
; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX9-NEXT: s_add_i32 s6, s4, s5
-; GFX9-NEXT: v_mul_hi_u32 v6, v4, s6
-; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, v8, v[4:5]
+; GFX9-NEXT: v_mul_hi_u32 v4, v6, s6
+; GFX9-NEXT: ; implicit-def: $vgpr7
+; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v4, v8, v[6:7]
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v5
-; GFX9-NEXT: v_mul_hi_u32 v5, v4, s6
-; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
+; GFX9-NEXT: v_mul_hi_u32 v7, v4, s6
+; GFX9-NEXT: v_add_u32_e32 v5, 0xffffffe8, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v8, v[4:5]
-; GFX9-NEXT: v_sub_u32_e32 v7, 23, v6
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v7
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 0xffffffe8, v5
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX9-NEXT: v_sub_u32_e32 v6, 23, v5
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffffff, v5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v8, v[4:5]
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v5, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, v9, v2
; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
@@ -2891,42 +2909,44 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX10-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX10-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX10-NEXT: v_readfirstlane_b32 s4, v6
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v5
+; GFX10-NEXT: ; implicit-def: $vgpr5
; GFX10-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: v_mul_hi_u32 v6, v4, s4
-; GFX10-NEXT: v_mul_hi_u32 v8, v5, s4
-; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, 0xffffffe8, v6, v[4:5]
-; GFX10-NEXT: v_mad_u64_u32 v[4:5], s4, 0xffffffe8, v8, v[5:6]
-; GFX10-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v6
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
-; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v4
+; GFX10-NEXT: v_mul_hi_u32 v7, v4, s4
+; GFX10-NEXT: v_mul_hi_u32 v8, v6, s4
+; GFX10-NEXT: v_mad_u64_u32 v[4:5], s4, 0xffffffe8, v7, v[4:5]
+; GFX10-NEXT: ; implicit-def: $vgpr7
+; GFX10-NEXT: v_mad_u64_u32 v[5:6], s4, 0xffffffe8, v8, v[6:7]
+; GFX10-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
-; GFX10-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v4
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
+; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v5
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX10-NEXT: v_and_b32_e32 v7, 0xffffff, v7
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, v5, v2
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, v4, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v7, v3
-; GFX10-NEXT: v_lshl_or_b32 v1, v1, v4, v3
+; GFX10-NEXT: v_lshl_or_b32 v1, v1, v5, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshl_v2i24:
@@ -2934,52 +2954,56 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX11-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX11-NEXT: v_bfe_u32 v3, v3, 1, 23
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v8, v4, s0
-; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, 0xffffffe8, v8, v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0xffffffe8, v6
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v6
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
-; GFX11-NEXT: v_mul_hi_u32 v9, v5, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, 0xffffffe8, v9, v[5:6]
+; GFX11-NEXT: v_mul_hi_u32 v7, v4, s0
+; GFX11-NEXT: v_mul_hi_u32 v10, v6, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, 0xffffffe8, v7, v[4:5]
+; GFX11-NEXT: ; implicit-def: $vgpr7
+; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, 0xffffffe8, v10, v[6:7]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v8
; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v7
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v7
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 0xffffffe8, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v5
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_and_b32 v4, 0xffffff, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
+; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v7 :: v_dual_and_b32 v5, 0xffffff, v5
; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX11-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v7, 0xffffff, v7
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, v4, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, v5, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b32_e32 v3, v7, v3
-; GFX11-NEXT: v_lshl_or_b32 v1, v1, v5, v3
+; GFX11-NEXT: v_lshl_or_b32 v1, v1, v4, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i24> @llvm.fshl.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
ret <2 x i24> %result
@@ -3906,6 +3930,7 @@ define i16 @v_fshl_i16(i16 %lhs, i16 %rhs, i16 %amt) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v0.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshl_i16:
@@ -3965,6 +3990,7 @@ define i16 @v_fshl_i16_4(i16 %lhs, i16 %rhs) {
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 12, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshl_i16_4:
@@ -4019,6 +4045,7 @@ define i16 @v_fshl_i16_5(i16 %lhs, i16 %rhs) {
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 11, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshl_i16_5:
@@ -4094,6 +4121,7 @@ define amdgpu_ps half @v_fshl_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v0.h, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: v_fshl_i16_ssv:
@@ -4161,6 +4189,7 @@ define amdgpu_ps half @v_fshl_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 1, v0.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 s2, 15, s1
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, s2, v0.l
@@ -4235,6 +4264,7 @@ define amdgpu_ps half @v_fshl_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, s2, v0.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 s1, 15, s1
; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 9d3a2accf3119..a60e3f61909b7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -274,8 +274,9 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: s_mul_i32 s5, s4, -7
; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, -7, v[2:3]
+; GFX9-NEXT: v_mul_hi_u32 v4, v2, s4
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, -7, v[2:3]
; GFX9-NEXT: v_add_u32_e32 v3, -7, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
@@ -301,11 +302,12 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
+; GFX10-NEXT: ; implicit-def: $vgpr3
; GFX10-NEXT: s_mul_i32 s5, s4, -7
; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v3, -7, v[2:3]
+; GFX10-NEXT: v_mul_hi_u32 v4, v2, s4
+; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v4, -7, v[2:3]
; GFX10-NEXT: v_add_nc_u32_e32 v3, -7, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
@@ -334,17 +336,18 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: s_mul_i32 s1, s0, -7
; GFX11-TRUE16-NEXT: s_mul_hi_u32 s1, s0, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_mul_hi_u32 v5, v2, s0
+; GFX11-TRUE16-NEXT: v_mul_hi_u32 v6, v2, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -7, v3
-; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
+; GFX11-TRUE16-NEXT: v_mad_u64_u32 v[4:5], null, v6, -7, v[2:3]
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -7, v4
+; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, -7, v2
; GFX11-TRUE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -357,6 +360,7 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_i7:
@@ -373,17 +377,18 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-FAKE16-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: s_mul_i32 s1, s0, -7
; GFX11-FAKE16-NEXT: s_mul_hi_u32 s1, s0, s1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, s1
-; GFX11-FAKE16-NEXT: v_mul_hi_u32 v5, v2, s0
+; GFX11-FAKE16-NEXT: v_mul_hi_u32 v6, v2, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -7, v3
-; GFX11-FAKE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
+; GFX11-FAKE16-NEXT: v_mad_u64_u32 v[4:5], null, v6, -7, v[2:3]
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -7, v4
+; GFX11-FAKE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, -7, v2
; GFX11-FAKE16-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -528,6 +533,7 @@ define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_i8:
@@ -640,6 +646,7 @@ define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 4, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_i8_4:
@@ -747,6 +754,7 @@ define i8 @v_fshr_i8_5(i8 %lhs, i8 %rhs) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 5, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_i8_5:
@@ -1036,6 +1044,7 @@ define i16 @v_fshr_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_v2i8:
@@ -1589,15 +1598,19 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v3.h, v6.l, v9.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v2.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xff, v7
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xff, v0, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -1920,7 +1933,7 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_not_b32_e32 v4, 23
+; GFX9-NEXT: v_not_b32_e32 v5, 23
; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
@@ -1929,8 +1942,9 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v4, v[2:3]
+; GFX9-NEXT: v_mul_hi_u32 v4, v2, s4
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v5, v[2:3]
; GFX9-NEXT: v_add_u32_e32 v3, 0xffffffe8, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
@@ -1955,11 +1969,12 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v3
+; GFX10-NEXT: ; implicit-def: $vgpr3
; GFX10-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: v_mul_hi_u32 v3, v2, s4
-; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, 0xffffffe8, v3, v[2:3]
+; GFX10-NEXT: v_mul_hi_u32 v4, v2, s4
+; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, 0xffffffe8, v4, v[2:3]
; GFX10-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
@@ -1987,17 +2002,18 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: v_mul_hi_u32 v5, v2, s0
+; GFX11-NEXT: v_mul_hi_u32 v6, v2, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, 0xffffffe8, v5, v[2:3]
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xffffffe8, v3
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v3
+; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, 0xffffffe8, v6, v[2:3]
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xffffffe8, v4
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0xffffffe8, v2
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2871,34 +2887,36 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_not_b32_e32 v8, 23
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v6
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v4
; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s4, v6
+; GFX9-NEXT: v_readfirstlane_b32 s4, v7
; GFX9-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX9-NEXT: s_add_i32 s6, s4, s5
-; GFX9-NEXT: v_mul_hi_u32 v6, v4, s6
-; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v6, v8, v[4:5]
+; GFX9-NEXT: v_mul_hi_u32 v4, v6, s6
+; GFX9-NEXT: ; implicit-def: $vgpr7
+; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v4, v8, v[6:7]
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v5
-; GFX9-NEXT: v_mul_hi_u32 v5, v4, s6
-; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
+; GFX9-NEXT: v_mul_hi_u32 v7, v4, s6
+; GFX9-NEXT: v_add_u32_e32 v5, 0xffffffe8, v6
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_add_u32_e32 v7, 0xffffffe8, v6
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v6
-; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v5, v8, v[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_sub_u32_e32 v7, 23, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 0xffffffe8, v5
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX9-NEXT: v_sub_u32_e32 v6, 23, v5
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffffff, v5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff, v7
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, v6, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, v7, v2
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v8, v[4:5]
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, v9, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2
; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffe8, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
@@ -2917,44 +2935,46 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX10-NEXT: v_readfirstlane_b32 s4, v6
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v5
+; GFX10-NEXT: ; implicit-def: $vgpr5
; GFX10-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: v_mul_hi_u32 v6, v4, s4
-; GFX10-NEXT: v_mul_hi_u32 v8, v5, s4
-; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, 0xffffffe8, v6, v[4:5]
-; GFX10-NEXT: v_mad_u64_u32 v[4:5], s4, 0xffffffe8, v8, v[5:6]
-; GFX10-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v6
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
-; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v4
+; GFX10-NEXT: v_mul_hi_u32 v7, v4, s4
+; GFX10-NEXT: v_mul_hi_u32 v8, v6, s4
+; GFX10-NEXT: v_mad_u64_u32 v[4:5], s4, 0xffffffe8, v7, v[4:5]
+; GFX10-NEXT: ; implicit-def: $vgpr7
+; GFX10-NEXT: v_mad_u64_u32 v[5:6], s4, 0xffffffe8, v8, v[6:7]
+; GFX10-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
-; GFX10-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v5
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v4
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
+; GFX10-NEXT: v_sub_nc_u32_e32 v6, 23, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v2, v5, v2
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v7
-; GFX10-NEXT: v_lshrrev_b32_e32 v3, v4, v3
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffffff, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v7, 23, v5
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffffff, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v3, v5, v3
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v6, v2
-; GFX10-NEXT: v_lshl_or_b32 v1, v1, v5, v3
+; GFX10-NEXT: v_lshl_or_b32 v1, v1, v4, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_v2i24:
@@ -2962,53 +2982,57 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
; GFX11-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_lshlrev_b32 v1, 1, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_mul_i32 s1, s0, 0xffffffe8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_hi_u32 v8, v4, s0
-; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, 0xffffffe8, v8, v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0xffffffe8, v6
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v6
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
-; GFX11-NEXT: v_mul_hi_u32 v9, v5, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, 0xffffffe8, v9, v[5:6]
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_hi_u32 v7, v4, s0
+; GFX11-NEXT: v_mul_hi_u32 v10, v6, s0
+; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, 0xffffffe8, v7, v[4:5]
+; GFX11-NEXT: ; implicit-def: $vgpr7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, 0xffffffe8, v10, v[6:7]
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v7
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v7
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 0xffffffe8, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v7, 0xffffffe8, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 0xffffffe8, v5
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v5
-; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_and_b32 v4, 0xffffff, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_nc_u32_e32 v7, 0xffffffe8, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_sub_nc_u32_e32 v6, 23, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v7 :: v_dual_and_b32 v5, 0xffffff, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v6, 0xffffff, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, v4, v2
+; GFX11-NEXT: v_sub_nc_u32_e32 v7, 23, v4
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshrrev_b32_e32 v2, v5, v2
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffffff, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, v5, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX11-NEXT: v_lshl_or_b32 v0, v0, v6, v2
-; GFX11-NEXT: v_lshl_or_b32 v1, v1, v4, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_lshl_or_b32 v1, v1, v5, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt)
ret <2 x i24> %result
@@ -3613,6 +3637,7 @@ define i16 @v_fshr_i16(i16 %lhs, i16 %rhs, i16 %amt) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_i16:
@@ -3672,6 +3697,7 @@ define i16 @v_fshr_i16_4(i16 %lhs, i16 %rhs) {
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 4, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_i16_4:
@@ -3726,6 +3752,7 @@ define i16 @v_fshr_i16_5(i16 %lhs, i16 %rhs) {
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, 5, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_i16_5:
@@ -3797,6 +3824,7 @@ define amdgpu_ps half @v_fshr_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt)
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v0.h, s0
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: v_fshr_i16_ssv:
@@ -3864,6 +3892,7 @@ define amdgpu_ps half @v_fshr_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt)
; GFX11-TRUE16-NEXT: s_and_not1_b32 s1, 15, s1
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, s2, v0.l
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
@@ -3937,6 +3966,7 @@ define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX11-TRUE16-NEXT: s_and_not1_b32 s2, 15, s1
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 15
; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, s2, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
index 9a329c68f003c..eeb7041da9300 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
@@ -13,6 +13,7 @@ define amdgpu_ps half @fsub_s16_uniform(half inreg %a, half inreg %b) {
; GFX11-TRUE16-LABEL: fsub_s16_uniform:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_sub_f16_e64 v0.l, s0, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: fsub_s16_uniform:
@@ -34,6 +35,7 @@ define amdgpu_ps half @fsub_s16_div(half %a, half %b) {
; GFX11-TRUE16-LABEL: fsub_s16_div:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: fsub_s16_div:
@@ -44,6 +46,7 @@ define amdgpu_ps half @fsub_s16_div(half %a, half %b) {
; GFX12-TRUE16-LABEL: fsub_s16_div:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: ; return to shader part epilog
%fsub = fsub half %a, %b
ret half %fsub
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
index 852c2188fb731..eaef1326d7c17 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
@@ -736,6 +736,7 @@ define amdgpu_ps void @insertelement_v_v2i8_s_v(ptr addrspace(1) %ptr, i8 inreg
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: global_load_u16 v0, v[0:1], off
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -963,6 +964,7 @@ define amdgpu_ps void @insertelement_v_v2i8_v_v(ptr addrspace(1) %ptr, i8 %val,
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: global_load_u16 v0, v[0:1], off
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
index cc433d210f985..f8e982da12b53 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
@@ -7284,6 +7284,7 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg
; GPRIDX-NEXT: s_mov_b32 s11, s13
; GPRIDX-NEXT: s_mov_b32 s12, s14
; GPRIDX-NEXT: s_mov_b32 s13, s15
+; GPRIDX-NEXT: ; implicit-def: $sgpr14_sgpr15
; GPRIDX-NEXT: v_mov_b32_e32 v17, s15
; GPRIDX-NEXT: v_mov_b32_e32 v16, s14
; GPRIDX-NEXT: v_mov_b32_e32 v15, s13
@@ -7337,6 +7338,7 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: ; implicit-def: $sgpr14_sgpr15
; GFX10-NEXT: v_mov_b32_e32 v17, s15
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: s_lshl_b32 m0, s16, 1
@@ -7388,6 +7390,7 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg
; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: ; implicit-def: $sgpr14_sgpr15
; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: s_lshl_b32 m0, s16, 1
@@ -7431,6 +7434,7 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg
; GFX8-NEXT: s_mov_b32 s11, s13
; GFX8-NEXT: s_mov_b32 s12, s14
; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: ; implicit-def: $sgpr14_sgpr15
; GFX8-NEXT: v_mov_b32_e32 v17, s15
; GFX8-NEXT: v_mov_b32_e32 v16, s14
; GFX8-NEXT: v_mov_b32_e32 v15, s13
@@ -7487,6 +7491,7 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GPRIDX-NEXT: s_mov_b32 s11, s13
; GPRIDX-NEXT: s_mov_b32 s12, s14
; GPRIDX-NEXT: s_mov_b32 s13, s15
+; GPRIDX-NEXT: ; implicit-def: $sgpr14_sgpr15
; GPRIDX-NEXT: v_mov_b32_e32 v18, s15
; GPRIDX-NEXT: v_mov_b32_e32 v17, s14
; GPRIDX-NEXT: v_mov_b32_e32 v16, s13
@@ -7556,6 +7561,7 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: ; implicit-def: $sgpr14_sgpr15
; GFX10-NEXT: v_mov_b32_e32 v18, s15
; GFX10-NEXT: v_mov_b32_e32 v17, s14
; GFX10-NEXT: v_mov_b32_e32 v16, s13
@@ -7625,6 +7631,7 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: ; implicit-def: $sgpr14_sgpr15
; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
@@ -7683,6 +7690,7 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GFX8-NEXT: s_mov_b32 s11, s13
; GFX8-NEXT: s_mov_b32 s12, s14
; GFX8-NEXT: s_mov_b32 s13, s15
+; GFX8-NEXT: ; implicit-def: $sgpr14_sgpr15
; GFX8-NEXT: v_mov_b32_e32 v18, s15
; GFX8-NEXT: v_mov_b32_e32 v17, s14
; GFX8-NEXT: v_mov_b32_e32 v16, s13
@@ -7743,11 +7751,13 @@ entry:
define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_s(<7 x double> %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f64_v_v_s:
; GPRIDX: ; %bb.0: ; %entry
+; GPRIDX-NEXT: v_mov_b32_e32 v16, v14
+; GPRIDX-NEXT: v_mov_b32_e32 v17, v15
+; GPRIDX-NEXT: ; implicit-def: $vgpr14_vgpr15
; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1
-; GPRIDX-NEXT: v_mov_b32_e32 v16, v15
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
-; GPRIDX-NEXT: v_mov_b32_e32 v0, v14
-; GPRIDX-NEXT: v_mov_b32_e32 v1, v16
+; GPRIDX-NEXT: v_mov_b32_e32 v0, v16
+; GPRIDX-NEXT: v_mov_b32_e32 v1, v17
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1
@@ -7765,34 +7775,61 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_s(<7 x double> %vec,
; GPRIDX-NEXT: v_readfirstlane_b32 s13, v13
; GPRIDX-NEXT: ; return to shader part epilog
;
-; GFX10PLUS-LABEL: dyn_insertelement_v7f64_v_v_s:
-; GFX10PLUS: ; %bb.0: ; %entry
-; GFX10PLUS-NEXT: v_mov_b32_e32 v16, v15
-; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1
-; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v14
-; GFX10PLUS-NEXT: v_movreld_b32_e32 v1, v16
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12
-; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13
-; GFX10PLUS-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v7f64_v_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: v_mov_b32_e32 v16, v14
+; GFX10-NEXT: v_mov_b32_e32 v17, v15
+; GFX10-NEXT: s_lshl_b32 m0, s2, 1
+; GFX10-NEXT: ; implicit-def: $vgpr14_vgpr15
+; GFX10-NEXT: v_movreld_b32_e32 v0, v16
+; GFX10-NEXT: v_movreld_b32_e32 v1, v17
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v7f64_v_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v17, v15
+; GFX11-NEXT: s_lshl_b32 m0, s2, 1
+; GFX11-NEXT: ; implicit-def: $vgpr14_vgpr15
+; GFX11-NEXT: v_movreld_b32_e32 v0, v16
+; GFX11-NEXT: v_movreld_b32_e32 v1, v17
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_readfirstlane_b32 s2, v2
+; GFX11-NEXT: v_readfirstlane_b32 s3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s4, v4
+; GFX11-NEXT: v_readfirstlane_b32 s5, v5
+; GFX11-NEXT: v_readfirstlane_b32 s6, v6
+; GFX11-NEXT: v_readfirstlane_b32 s7, v7
+; GFX11-NEXT: v_readfirstlane_b32 s8, v8
+; GFX11-NEXT: v_readfirstlane_b32 s9, v9
+; GFX11-NEXT: v_readfirstlane_b32 s10, v10
+; GFX11-NEXT: v_readfirstlane_b32 s11, v11
+; GFX11-NEXT: v_readfirstlane_b32 s12, v12
+; GFX11-NEXT: v_readfirstlane_b32 s13, v13
+; GFX11-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: dyn_insertelement_v7f64_v_v_s:
; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: v_mov_b32_e32 v16, v14
+; GFX8-NEXT: v_mov_b32_e32 v17, v15
+; GFX8-NEXT: ; implicit-def: $vgpr14_vgpr15
; GFX8-NEXT: s_lshl_b32 m0, s2, 1
-; GFX8-NEXT: v_mov_b32_e32 v16, v15
-; GFX8-NEXT: v_movreld_b32_e32 v0, v14
-; GFX8-NEXT: v_movreld_b32_e32 v1, v16
+; GFX8-NEXT: v_movreld_b32_e32 v0, v16
+; GFX8-NEXT: v_movreld_b32_e32 v1, v17
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: v_readfirstlane_b32 s2, v2
@@ -8567,6 +8604,7 @@ define void @insert_very_small_from_very_large(<32 x i16> %L3, ptr %ptr) {
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_lshrrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: v_and_b16 v0.l, v0.l, 1
; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
; GFX11-NEXT: v_and_b32_e32 v0, 3, v0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
index 0d70c2d68607d..d39e6a0ecfd08 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
@@ -83,6 +83,7 @@ define half @intrinsic_trunc_s16_v(half %val) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.trunc.f16(half %val)
ret half %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
index e2e7e28b35564..650e5568b1eb0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
@@ -131,6 +131,7 @@ define i16 @abs_vgpr_i16(i16 %arg) {
; GFX1250-REAL16-NEXT: v_sub_nc_u16 v0.h, 0, v0.l
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_max_i16 v0.l, v0.l, v0.h
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
ret i16 %res
@@ -348,12 +349,14 @@ define <2 x i8> @abs_vgpr_v2i8(<2 x i8> %arg) {
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_bfe_i32 v2, v0, 0, 8
; GFX1250-REAL16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-REAL16-NEXT: v_sub_nc_u16 v0.l, 0, v2.l
; GFX1250-REAL16-NEXT: v_sub_nc_u16 v0.h, 0, v1.l
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-REAL16-NEXT: v_max_i16 v0.l, v2.l, v0.l
; GFX1250-REAL16-NEXT: v_max_i16 v1.l, v1.l, v0.h
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
ret <2 x i8> %res
@@ -450,6 +453,7 @@ define <3 x i8> @abs_vgpr_v3i8(<3 x i8> %arg) {
; GFX1250-REAL16-NEXT: v_bfe_i32 v3, v0, 0, 8
; GFX1250-REAL16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX1250-REAL16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-REAL16-NEXT: v_sub_nc_u16 v0.l, 0, v3.l
; GFX1250-REAL16-NEXT: v_sub_nc_u16 v0.h, 0, v1.l
@@ -459,6 +463,8 @@ define <3 x i8> @abs_vgpr_v3i8(<3 x i8> %arg) {
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-REAL16-NEXT: v_max_i16 v1.l, v1.l, v0.h
; GFX1250-REAL16-NEXT: v_max_i16 v2.l, v2.l, v1.h
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
ret <3 x i8> %res
@@ -669,6 +675,7 @@ define <3 x i16> @abs_vgpr_v3i16(<3 x i16> %arg) {
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-REAL16-NEXT: v_pk_max_i16 v0, v0, v2
; GFX1250-REAL16-NEXT: v_max_i16 v1.l, v1.l, v1.h
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
ret <3 x i16> %res
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
index afb7733b79352..c256ddd480730 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
@@ -9,6 +9,7 @@ define amdgpu_ps half @s_fract_f16(half inreg %src) {
; GFX12-LABEL: s_fract_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_fract_f16_e32 v0.l, s0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: s_add_f16 s0, s0, s0
@@ -24,6 +25,7 @@ define amdgpu_ps half @v_fract_f16(half %src) {
; GFX12-LABEL: v_fract_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_fract_f16_e32 v0.l, v0.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.l
; GFX12-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
index 09e1fca3f2677..f8d7fcea63d93 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
@@ -61,6 +61,7 @@ define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_swap v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -152,6 +153,7 @@ define amdgpu_ps float @atomic_add_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_add v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -243,6 +245,7 @@ define amdgpu_ps float @atomic_sub_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_sub v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -334,6 +337,7 @@ define amdgpu_ps float @atomic_smin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_smin v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -425,6 +429,7 @@ define amdgpu_ps float @atomic_umin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_umin v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -516,6 +521,7 @@ define amdgpu_ps float @atomic_smax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_smax v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -607,6 +613,7 @@ define amdgpu_ps float @atomic_umax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_umax v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -698,6 +705,7 @@ define amdgpu_ps float @atomic_and_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_and v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -789,6 +797,7 @@ define amdgpu_ps float @atomic_or_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_or v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -880,6 +889,7 @@ define amdgpu_ps float @atomic_xor_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_xor v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -971,6 +981,7 @@ define amdgpu_ps float @atomic_inc_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_inc v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -1062,6 +1073,7 @@ define amdgpu_ps float @atomic_dec_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_dec v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -1152,6 +1164,7 @@ define amdgpu_ps float @atomic_cmpswap_i32_1d(<8 x i32> inreg %rsrc, i32 %cmp, i
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -1239,6 +1252,7 @@ define amdgpu_ps void @atomic_cmpswap_i32_1d_no_return(<8 x i32> inreg %rsrc, i3
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 unorm
; GFX90A-NEXT: s_endpgm
;
@@ -1976,6 +1990,7 @@ define amdgpu_ps float @atomic_add_i32_1d_slc(<8 x i32> inreg %rsrc, i32 %data,
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_add v0, v2, s[0:7] dmask:0x1 unorm glc slc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2066,6 +2081,7 @@ define amdgpu_ps <2 x float> @atomic_swap_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2156,6 +2172,7 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d(<8 x i32> inreg %rsrc, i64 %data
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2246,6 +2263,7 @@ define amdgpu_ps <2 x float> @atomic_sub_i64_1d(<8 x i32> inreg %rsrc, i64 %data
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_sub v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2336,6 +2354,7 @@ define amdgpu_ps <2 x float> @atomic_smin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_smin v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2426,6 +2445,7 @@ define amdgpu_ps <2 x float> @atomic_umin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_umin v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2516,6 +2536,7 @@ define amdgpu_ps <2 x float> @atomic_smax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_smax v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2606,6 +2627,7 @@ define amdgpu_ps <2 x float> @atomic_umax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_umax v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2696,6 +2718,7 @@ define amdgpu_ps <2 x float> @atomic_and_i64_1d(<8 x i32> inreg %rsrc, i64 %data
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2786,6 +2809,7 @@ define amdgpu_ps <2 x float> @atomic_or_i64_1d(<8 x i32> inreg %rsrc, i64 %data,
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2876,6 +2900,7 @@ define amdgpu_ps <2 x float> @atomic_xor_i64_1d(<8 x i32> inreg %rsrc, i64 %data
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -2966,6 +2991,7 @@ define amdgpu_ps <2 x float> @atomic_inc_i64_1d(<8 x i32> inreg %rsrc, i64 %data
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_inc v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -3056,6 +3082,7 @@ define amdgpu_ps <2 x float> @atomic_dec_i64_1d(<8 x i32> inreg %rsrc, i64 %data
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_dec v[0:1], v2, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -3146,6 +3173,7 @@ define amdgpu_ps <2 x float> @atomic_cmpswap_i64_1d(<8 x i32> inreg %rsrc, i64 %
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -3233,6 +3261,7 @@ define amdgpu_ps void @atomic_cmpswap_i64_1d_no_return(<8 x i32> inreg %rsrc, i6
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf unorm
; GFX90A-NEXT: s_endpgm
;
@@ -3949,6 +3978,7 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d_slc(<8 x i32> inreg %rsrc, i64 %
; GFX90A-NEXT: s_mov_b32 s5, s7
; GFX90A-NEXT: s_mov_b32 s6, s8
; GFX90A-NEXT: s_mov_b32 s7, s9
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 unorm glc slc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
index 5b2513bd2db97..3410afda0f9b4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
@@ -74,6 +74,7 @@ define amdgpu_ps half @load_1d_f16_x(<8 x i32> inreg %rsrc, i32 %s) {
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm d16
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
@@ -88,6 +89,7 @@ define amdgpu_ps half @load_1d_f16_x(<8 x i32> inreg %rsrc, i32 %s) {
; GFX12-NEXT: s_mov_b32 s6, s8
; GFX12-NEXT: s_mov_b32 s7, s9
; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D d16
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: ; return to shader part epilog
%v = call half @llvm.amdgcn.image.load.1d.half.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -162,6 +164,7 @@ define amdgpu_ps half @load_1d_f16_y(<8 x i32> inreg %rsrc, i32 %s) {
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm d16
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
@@ -176,6 +179,7 @@ define amdgpu_ps half @load_1d_f16_y(<8 x i32> inreg %rsrc, i32 %s) {
; GFX12-NEXT: s_mov_b32 s6, s8
; GFX12-NEXT: s_mov_b32 s7, s9
; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D d16
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: ; return to shader part epilog
%v = call half @llvm.amdgcn.image.load.1d.half.i32(i32 2, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -250,6 +254,7 @@ define amdgpu_ps half @load_1d_f16_z(<8 x i32> inreg %rsrc, i32 %s) {
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_1D unorm d16
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
@@ -264,6 +269,7 @@ define amdgpu_ps half @load_1d_f16_z(<8 x i32> inreg %rsrc, i32 %s) {
; GFX12-NEXT: s_mov_b32 s6, s8
; GFX12-NEXT: s_mov_b32 s7, s9
; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_1D d16
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: ; return to shader part epilog
%v = call half @llvm.amdgcn.image.load.1d.half.i32(i32 4, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
@@ -338,6 +344,7 @@ define amdgpu_ps half @load_1d_f16_w(<8 x i32> inreg %rsrc, i32 %s) {
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm d16
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
;
@@ -352,6 +359,7 @@ define amdgpu_ps half @load_1d_f16_w(<8 x i32> inreg %rsrc, i32 %s) {
; GFX12-NEXT: s_mov_b32 s6, s8
; GFX12-NEXT: s_mov_b32 s7, s9
; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D d16
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: ; return to shader part epilog
%v = call half @llvm.amdgcn.image.load.1d.half.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
index d07eadcd64146..8f4cecbbd0087 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
@@ -61,6 +61,7 @@ define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX81-NEXT: s_mov_b32 s5, s7
; GFX81-NEXT: s_mov_b32 s6, s8
; GFX81-NEXT: s_mov_b32 s7, s9
+; GFX81-NEXT: ; implicit-def: $vgpr3
; GFX81-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm d16
; GFX81-NEXT: s_endpgm
call void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
@@ -135,6 +136,8 @@ define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX81-NEXT: s_mov_b32 s5, s7
; GFX81-NEXT: s_mov_b32 s6, s8
; GFX81-NEXT: s_mov_b32 s7, s9
+; GFX81-NEXT: ; implicit-def: $vgpr4
+; GFX81-NEXT: ; implicit-def: $vgpr5
; GFX81-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm d16
; GFX81-NEXT: s_endpgm
call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
index 51baf892a15be..5445a92b895c4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
@@ -208,6 +208,7 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: v_interp_f16:
@@ -244,6 +245,7 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: v_interp_f16:
@@ -290,6 +292,7 @@ define amdgpu_ps half @v_interp_rtz_f16(float inreg %i, float inreg %j, i32 inre
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: v_interp_rtz_f16:
@@ -326,6 +329,7 @@ define amdgpu_ps half @v_interp_rtz_f16(float inreg %i, float inreg %j, i32 inre
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: v_interp_rtz_f16:
@@ -367,6 +371,7 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: v_interp_f16_imm_params:
@@ -386,6 +391,7 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v2, v3 wait_exp:7
@@ -515,6 +521,7 @@ define amdgpu_ps half @s_interp_rtz_f16(float inreg %p, float inreg %j, float in
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v0.l, v1, v2 wait_exp:7
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -531,6 +538,7 @@ define amdgpu_ps half @s_interp_rtz_f16(float inreg %p, float inreg %j, float in
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v0.l, v1, v2 wait_exp:7
; GFX12-TRUE16-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
index 46070dd5d8c68..f64ff07e1cfd7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
@@ -50,6 +50,7 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
index f25904350d8d9..cb56ac2575698 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
@@ -31,10 +31,12 @@ define amdgpu_ps void @load_uniform_P1_i16_b16_gfx12(ptr addrspace(1) inreg %ptr
; GFX11-True16-LABEL: load_uniform_P1_i16_b16_gfx12:
; GFX11-True16: ; %bb.0:
; GFX11-True16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-True16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-True16-NEXT: s_clause 0x1
; GFX11-True16-NEXT: global_load_d16_b16 v3, v2, s[0:1]
; GFX11-True16-NEXT: global_load_d16_b16 v2, v2, s[2:3] glc dlc
; GFX11-True16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-True16-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
@@ -61,10 +63,12 @@ define amdgpu_ps void @load_uniform_P1_i16_b16_gfx12(ptr addrspace(1) inreg %ptr
; GFX12-True16-LABEL: load_uniform_P1_i16_b16_gfx12:
; GFX12-True16: ; %bb.0:
; GFX12-True16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-True16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-True16-NEXT: s_clause 0x1
; GFX12-True16-NEXT: global_load_d16_b16 v3, v2, s[0:1]
; GFX12-True16-NEXT: global_load_d16_b16 v2, v2, s[2:3] scope:SCOPE_SYS
; GFX12-True16-NEXT: s_wait_loadcnt 0x0
+; GFX12-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-True16-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-True16-NEXT: s_add_co_i32 s0, s0, s1
@@ -115,10 +119,12 @@ define amdgpu_ps void @load_uniform_P1_i16_b16_gfx11(ptr addrspace(1) inreg %ptr
; GFX11-True16-LABEL: load_uniform_P1_i16_b16_gfx11:
; GFX11-True16: ; %bb.0:
; GFX11-True16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-True16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-True16-NEXT: s_clause 0x1
; GFX11-True16-NEXT: global_load_d16_b16 v3, v2, s[0:1]
; GFX11-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1] glc dlc
; GFX11-True16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-True16-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
@@ -148,6 +154,7 @@ define amdgpu_ps void @load_uniform_P1_i16_b16_gfx11(ptr addrspace(1) inreg %ptr
; GFX12-True16-NEXT: s_load_u16 s2, s[0:1], 0x0
; GFX12-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1] scope:SCOPE_SYS
; GFX12-True16-NEXT: s_wait_loadcnt 0x0
+; GFX12-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-True16-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-True16-NEXT: s_wait_kmcnt 0x0
; GFX12-True16-NEXT: s_add_co_i32 s0, s2, s0
@@ -197,10 +204,12 @@ define amdgpu_ps void @load_uniform_P1_i16_anyextending_gfx12(ptr addrspace(1) i
; GFX11-True16-LABEL: load_uniform_P1_i16_anyextending_gfx12:
; GFX11-True16: ; %bb.0:
; GFX11-True16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-True16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-True16-NEXT: s_clause 0x1
; GFX11-True16-NEXT: global_load_d16_b16 v3, v2, s[0:1]
; GFX11-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1] glc dlc
; GFX11-True16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-True16-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
@@ -227,10 +236,12 @@ define amdgpu_ps void @load_uniform_P1_i16_anyextending_gfx12(ptr addrspace(1) i
; GFX12-True16-LABEL: load_uniform_P1_i16_anyextending_gfx12:
; GFX12-True16: ; %bb.0:
; GFX12-True16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-True16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-True16-NEXT: s_clause 0x1
; GFX12-True16-NEXT: global_load_d16_b16 v3, v2, s[0:1]
; GFX12-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1] scope:SCOPE_SYS
; GFX12-True16-NEXT: s_wait_loadcnt 0x0
+; GFX12-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-True16-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-True16-NEXT: s_add_co_i32 s0, s0, s1
@@ -281,10 +292,12 @@ define amdgpu_ps void @load_uniform_P1_i16_anyextending_gfx11(ptr addrspace(1) i
; GFX11-True16-LABEL: load_uniform_P1_i16_anyextending_gfx11:
; GFX11-True16: ; %bb.0:
; GFX11-True16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-True16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-True16-NEXT: s_clause 0x1
; GFX11-True16-NEXT: global_load_d16_b16 v3, v2, s[0:1]
; GFX11-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1] glc dlc
; GFX11-True16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-True16-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
@@ -314,6 +327,7 @@ define amdgpu_ps void @load_uniform_P1_i16_anyextending_gfx11(ptr addrspace(1) i
; GFX12-True16-NEXT: s_load_u16 s2, s[0:1], 0x0
; GFX12-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1] scope:SCOPE_SYS
; GFX12-True16-NEXT: s_wait_loadcnt 0x0
+; GFX12-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-True16-NEXT: v_readfirstlane_b32 s0, v2
; GFX12-True16-NEXT: s_wait_kmcnt 0x0
; GFX12-True16-NEXT: s_add_co_i32 s0, s2, s0
@@ -1251,9 +1265,11 @@ define amdgpu_ps void @load_uniform_P4_i16_b16_gfx12(ptr addrspace(4) inreg %ptr
; GFX11-True16-LABEL: load_uniform_P4_i16_b16_gfx12:
; GFX11-True16: ; %bb.0:
; GFX11-True16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-True16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-True16-NEXT: s_clause 0x1
; GFX11-True16-NEXT: global_load_d16_b16 v3, v2, s[0:1]
; GFX11-True16-NEXT: global_load_d16_b16 v2, v2, s[2:3] glc dlc
+; GFX11-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-True16-NEXT: s_waitcnt vmcnt(1)
; GFX11-True16-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-True16-NEXT: s_waitcnt vmcnt(0)
@@ -1285,6 +1301,7 @@ define amdgpu_ps void @load_uniform_P4_i16_b16_gfx12(ptr addrspace(4) inreg %ptr
; GFX12-True16-NEXT: v_mov_b32_e32 v2, 0
; GFX12-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1]
; GFX12-True16-NEXT: s_load_u16 s0, s[2:3], 0x0
+; GFX12-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-True16-NEXT: s_wait_loadcnt 0x0
; GFX12-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-True16-NEXT: s_wait_kmcnt 0x0
@@ -1337,6 +1354,7 @@ define amdgpu_ps void @load_uniform_P4_i16_b16_gfx11(ptr addrspace(4) inreg %ptr
; GFX11-True16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1]
; GFX11-True16-NEXT: s_load_b32 s0, s[0:1], 0x0
+; GFX11-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-True16-NEXT: s_waitcnt vmcnt(0)
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_waitcnt lgkmcnt(0)
@@ -1412,9 +1430,11 @@ define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx12(ptr addrspace(4) i
; GFX11-True16-LABEL: load_uniform_P4_i16_anyextending_gfx12:
; GFX11-True16: ; %bb.0:
; GFX11-True16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-True16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-True16-NEXT: s_clause 0x1
; GFX11-True16-NEXT: global_load_d16_b16 v3, v2, s[0:1]
; GFX11-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1] glc dlc
+; GFX11-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-True16-NEXT: s_waitcnt vmcnt(1)
; GFX11-True16-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-True16-NEXT: s_waitcnt vmcnt(0)
@@ -1446,6 +1466,7 @@ define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx12(ptr addrspace(4) i
; GFX12-True16-NEXT: v_mov_b32_e32 v2, 0
; GFX12-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1]
; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0
+; GFX12-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-True16-NEXT: s_wait_loadcnt 0x0
; GFX12-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-True16-NEXT: s_wait_kmcnt 0x0
@@ -1498,6 +1519,7 @@ define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx11(ptr addrspace(4) i
; GFX11-True16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-True16-NEXT: global_load_d16_b16 v2, v2, s[0:1]
; GFX11-True16-NEXT: s_load_b32 s0, s[0:1], 0x0
+; GFX11-True16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-True16-NEXT: s_waitcnt vmcnt(0)
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
index 5436cd09bf265..23c59157bae14 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
@@ -1821,20 +1821,22 @@ define i65 @v_lshr_i65_33(i65 %value) {
define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) {
; GCN-LABEL: s_lshr_i65:
; GCN: ; %bb.0:
-; GCN-NEXT: s_and_b64 s[4:5], s[2:3], 1
-; GCN-NEXT: s_sub_i32 s10, s3, 64
-; GCN-NEXT: s_sub_i32 s8, 64, s3
-; GCN-NEXT: s_cmp_lt_u32 s3, 64
+; GCN-NEXT: s_mov_b32 s4, s3
+; GCN-NEXT: ; implicit-def: $sgpr3
+; GCN-NEXT: s_sub_i32 s10, s4, 64
+; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 1
+; GCN-NEXT: s_sub_i32 s8, 64, s4
+; GCN-NEXT: s_cmp_lt_u32 s4, 64
; GCN-NEXT: s_cselect_b32 s11, 1, 0
-; GCN-NEXT: s_cmp_eq_u32 s3, 0
+; GCN-NEXT: s_cmp_eq_u32 s4, 0
; GCN-NEXT: s_cselect_b32 s12, 1, 0
-; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s3
-; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3
-; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8
-; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s10
+; GCN-NEXT: s_lshr_b64 s[6:7], s[2:3], s4
+; GCN-NEXT: s_lshr_b64 s[4:5], s[0:1], s4
+; GCN-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
+; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
+; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GCN-NEXT: s_cmp_lg_u32 s11, 0
-; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; GCN-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s12, 0
; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s11, 0
@@ -1843,24 +1845,26 @@ define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) {
;
; GFX10PLUS-LABEL: s_lshr_i65:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_and_b64 s[4:5], s[2:3], 1
-; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 64
-; GFX10PLUS-NEXT: s_sub_i32 s2, 64, s3
-; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64
+; GFX10PLUS-NEXT: s_mov_b32 s4, s3
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
+; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[2:3], 1
+; GFX10PLUS-NEXT: s_sub_i32 s10, s4, 64
+; GFX10PLUS-NEXT: s_sub_i32 s5, 64, s4
+; GFX10PLUS-NEXT: s_cmp_lt_u32 s4, 64
; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s4, 0
; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0
-; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s3
-; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s2
-; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[4:5], s3
+; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s4
+; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[2:3], s5
+; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[2:3], s4
; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
-; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[4:5], s10
+; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s2, 0
+; GFX10PLUS-NEXT: s_cselect_b32 s2, s4, 0
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = lshr i65 %value, %amount
ret i65 %result
@@ -1869,8 +1873,9 @@ define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) {
define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) {
; GCN-LABEL: s_lshr_i65_33:
; GCN: ; %bb.0:
-; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 1
+; GCN-NEXT: ; implicit-def: $sgpr3
; GCN-NEXT: s_lshr_b32 s4, s1, 1
+; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 1
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
; GCN-NEXT: s_or_b32 s0, s0, s4
; GCN-NEXT: s_mov_b32 s2, 0
@@ -1878,8 +1883,9 @@ define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) {
;
; GFX10PLUS-LABEL: s_lshr_i65_33:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[2:3], 1
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 1
+; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[2:3], 1
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
; GFX10PLUS-NEXT: s_mov_b32 s2, 0
; GFX10PLUS-NEXT: s_or_b32 s0, s0, s4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
index 0126efeba3e74..476fbe8e625d1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
@@ -113,6 +113,7 @@ define amdgpu_ps void @mad_i64_div(i64 %a, i64 %b, ptr addrspace(1) %out) {
; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v0, v2, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mad_u64_u32 v[9:10], null, v0, v3, v[7:8]
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, v1, v2, v[9:10]
; GFX11-NEXT: global_store_b64 v[4:5], v[6:7], off
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
index c5ba1991679c5..0cc0b4b34b790 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/min3-max3-combine.ll
@@ -328,6 +328,7 @@ define i16 @test_smin3_i16(i16 %a, i16 %b, i16 %c) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_min3_i16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i16 @llvm.smin.i16(i16 %a, i16 %b)
%min2 = call i16 @llvm.smin.i16(i16 %min1, i16 %c)
@@ -349,6 +350,7 @@ define i16 @test_smin3_i16_with_constants(i16 %a, i16 %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_min3_i16 v0.l, v0.l, v1.l, 7
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i16 @llvm.smin.i16(i16 %a, i16 %b)
%min2 = call i16 @llvm.smin.i16(i16 %min1, i16 7)
@@ -370,6 +372,7 @@ define i16 @test_smax3_i16(i16 %a, i16 %b, i16 %c) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max3_i16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call i16 @llvm.smax.i16(i16 %a, i16 %b)
%max2 = call i16 @llvm.smax.i16(i16 %max1, i16 %c)
@@ -391,6 +394,7 @@ define i16 @test_smax3_i16_with_constants(i16 %a, i16 %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max3_i16 v0.l, v0.l, v1.l, 7
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call i16 @llvm.smax.i16(i16 %a, i16 %b)
%max2 = call i16 @llvm.smax.i16(i16 %max1, i16 7)
@@ -412,6 +416,7 @@ define i16 @test_umin3_i16(i16 %a, i16 %b, i16 %c) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_min3_u16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i16 @llvm.umin.i16(i16 %a, i16 %b)
%min2 = call i16 @llvm.umin.i16(i16 %min1, i16 %c)
@@ -433,6 +438,7 @@ define i16 @test_umin3_i16_with_constants(i16 %a, i16 %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_min3_u16 v0.l, v0.l, v1.l, 7
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%min1 = call i16 @llvm.umin.i16(i16 %a, i16 %b)
%min2 = call i16 @llvm.umin.i16(i16 %min1, i16 7)
@@ -454,6 +460,7 @@ define i16 @test_umax3_i16(i16 %a, i16 %b, i16 %c) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max3_u16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call i16 @llvm.umax.i16(i16 %a, i16 %b)
%max2 = call i16 @llvm.umax.i16(i16 %max1, i16 %c)
@@ -475,6 +482,7 @@ define i16 @test_umax3_i16_with_constants(i16 %a, i16 %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max3_u16 v0.l, v0.l, v1.l, 7
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%max1 = call i16 @llvm.umax.i16(i16 %a, i16 %b)
%max2 = call i16 @llvm.umax.i16(i16 %max1, i16 7)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
index d77776479aa3f..39072e8fe60d8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
@@ -16,6 +16,7 @@ define amdgpu_kernel void @v_mul_i64_no_zext(ptr addrspace(1) %out, ptr addrspac
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v2, v4, 0
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s0, v2, v5, v[1:2]
+; GFX10-NEXT: ; implicit-def: $vgpr2
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s0, v3, v4, v[1:2]
; GFX10-NEXT: global_store_dwordx2 v6, v[0:1], s[2:3]
; GFX10-NEXT: s_endpgm
@@ -34,6 +35,7 @@ define amdgpu_kernel void @v_mul_i64_no_zext(ptr addrspace(1) %out, ptr addrspac
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v4, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v2, v5, v[1:2]
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v3, v4, v[6:7]
; GFX11-NEXT: global_store_b64 v8, v[0:1], s[2:3]
; GFX11-NEXT: s_endpgm
@@ -388,6 +390,7 @@ define amdgpu_kernel void @v_mul_i64_partially_masked_src0(ptr addrspace(1) %out
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v5, v3, 0
; GFX10-NEXT: v_mad_u64_u32 v[4:5], s2, v5, v4, v[1:2]
; GFX10-NEXT: v_and_b32_e32 v1, 0xf00f, v2
+; GFX10-NEXT: ; implicit-def: $vgpr5
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s2, v1, v3, v[4:5]
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
@@ -412,6 +415,7 @@ define amdgpu_kernel void @v_mul_i64_partially_masked_src0(ptr addrspace(1) %out
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v7, v3, 0
; GFX11-NEXT: v_mad_u64_u32 v[5:6], null, v7, v4, v[1:2]
; GFX11-NEXT: v_and_b32_e32 v4, 0xf00f, v2
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v4, v3, v[5:6]
; GFX11-NEXT: v_mov_b32_e32 v2, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
index 976fef0e3807e..750b68b27346a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
@@ -70,6 +70,7 @@ define i16 @v_mul_i16(i16 %num, i16 %den) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_mul_i16:
@@ -308,6 +309,7 @@ define signext i16 @v_mul_i16_signext(i16 signext %num, i16 signext %den) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -820,6 +822,7 @@ define i64 @v_mul_i64(i64 %num, i64 %den) {
; GFX10-NEXT: v_mov_b32_e32 v5, v1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0
; GFX10-NEXT: v_mad_u64_u32 v[3:4], s4, v4, v3, v[1:2]
+; GFX10-NEXT: ; implicit-def: $vgpr4
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v5, v2, v[3:4]
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -830,6 +833,7 @@ define i64 @v_mul_i64(i64 %num, i64 %den) {
; GFX11-NEXT: v_mov_b32_e32 v6, v1
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v5, 0
; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, v4, v3, v[1:2]
+; GFX11-NEXT: ; implicit-def: $vgpr8
; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v6, v5, v[7:8]
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1052,10 +1056,12 @@ define i96 @v_mul_i96(i96 %num, i96 %den) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v6, v0
; GFX10-NEXT: v_mov_b32_e32 v7, v1
+; GFX10-NEXT: ; implicit-def: $vgpr1
; GFX10-NEXT: v_mov_b32_e32 v8, v3
; GFX10-NEXT: v_mul_lo_u32 v0, v6, v5
; GFX10-NEXT: v_mad_u64_u32 v[9:10], s4, v7, v4, v[0:1]
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v6, v8, 0
+; GFX10-NEXT: ; implicit-def: $vgpr10
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s4, v2, v8, v[9:10]
; GFX10-NEXT: v_mad_u64_u32 v[9:10], s4, v6, v4, v[1:2]
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v7, v8, v[9:10]
@@ -1065,10 +1071,12 @@ define i96 @v_mul_i96(i96 %num, i96 %den) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1
+; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v9, v3
; GFX11-NEXT: v_mul_lo_u32 v0, v6, v5
; GFX11-NEXT: v_mad_u64_u32 v[10:11], null, v7, v4, v[0:1]
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v6, v9, 0
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v8, v9, v[10:11]
; GFX11-NEXT: v_mad_u64_u32 v[10:11], null, v6, v4, v[1:2]
; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v7, v9, v[10:11]
@@ -1082,12 +1090,14 @@ define i96 @v_mul_i96(i96 %num, i96 %den) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1
+; GFX12-NEXT: ; implicit-def: $vgpr1
; GFX12-NEXT: v_mov_b32_e32 v8, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_mul_lo_u32 v0, v6, v5
; GFX12-NEXT: v_mad_co_u64_u32 v[9:10], null, v7, v4, v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v6, v8, 0
+; GFX12-NEXT: ; implicit-def: $vgpr10
; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, v2, v8, v[9:10]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_mad_co_u64_u32 v[9:10], null, v6, v4, v[1:2]
@@ -1121,12 +1131,14 @@ define i96 @v_mul_i96(i96 %num, i96 %den) {
; GFX13-NEXT: s_wait_bvhcnt 0x0
; GFX13-NEXT: s_wait_kmcnt 0x0
; GFX13-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1
+; GFX13-NEXT: ; implicit-def: $vgpr1
; GFX13-NEXT: v_mov_b32_e32 v8, v3
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX13-NEXT: v_mul_lo_u32 v0, v6, v5
; GFX13-NEXT: v_mad_co_u64_u32 v[9:10], null, v7, v4, v[0:1]
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX13-NEXT: v_mad_co_u64_u32 v[0:1], null, v6, v8, 0
+; GFX13-NEXT: ; implicit-def: $vgpr10
; GFX13-NEXT: v_mad_co_u64_u32 v[2:3], null, v2, v8, v[9:10]
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX13-NEXT: v_mad_co_u64_u32 v[9:10], null, v6, v4, v[1:2]
@@ -1438,6 +1450,7 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX7-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v11, v[13:14]
; GFX7-NEXT: v_addc_u32_e64 v3, s[4:5], v3, v6, s[4:5]
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
+; GFX7-NEXT: ; implicit-def: $vgpr4
; GFX7-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v10, v5, v[3:4]
; GFX7-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v12, v11, v[6:7]
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -1460,6 +1473,7 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX8-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v11, v[13:14]
; GFX8-NEXT: v_addc_u32_e64 v3, s[4:5], v3, v6, s[4:5]
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
+; GFX8-NEXT: ; implicit-def: $vgpr4
; GFX8-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v10, v5, v[3:4]
; GFX8-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v12, v11, v[6:7]
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -1482,6 +1496,7 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX9-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v9, v11, v[13:14]
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], v3, v6, s[4:5]
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr4
; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v10, v5, v[3:4]
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v12, v11, v[6:7]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1502,8 +1517,10 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX10-NEXT: v_mad_u64_u32 v[12:13], vcc_lo, v8, v5, v[1:2]
; GFX10-NEXT: v_mad_u64_u32 v[1:2], s4, v9, v4, v[12:13]
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s4, v3, v7, s4
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v6, vcc_lo
-; GFX10-NEXT: v_mad_u64_u32 v[5:6], s4, v10, v5, v[3:4]
+; GFX10-NEXT: ; implicit-def: $vgpr7
+; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v3, v6, vcc_lo
+; GFX10-NEXT: v_mad_u64_u32 v[5:6], s4, v10, v5, v[6:7]
+; GFX10-NEXT: ; implicit-def: $vgpr6
; GFX10-NEXT: v_mad_u64_u32 v[3:4], s4, v11, v4, v[5:6]
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -1523,7 +1540,9 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX11-NEXT: v_mad_u64_u32 v[1:2], s0, v9, v11, v[13:14]
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v6, s0
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v4, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr4
; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v10, v5, v[3:4]
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v12, v11, v[6:7]
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
@@ -1550,10 +1569,12 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, s0
+; GFX12-NEXT: ; implicit-def: $vgpr7
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v6, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, v3, v6, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], null, v10, v5, v[3:4]
+; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], null, v10, v5, v[6:7]
+; GFX12-NEXT: ; implicit-def: $vgpr6
; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v11, v4, v[5:6]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -1608,9 +1629,11 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX13-NEXT: v_mad_co_u64_u32 v[1:2], s0, v9, v4, v[12:13]
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX13-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, s0
-; GFX13-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v6, vcc_lo
+; GFX13-NEXT: ; implicit-def: $vgpr7
+; GFX13-NEXT: v_add_co_ci_u32_e64 v6, null, v3, v6, vcc_lo
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX13-NEXT: v_mad_co_u64_u32 v[5:6], null, v10, v5, v[3:4]
+; GFX13-NEXT: v_mad_co_u64_u32 v[5:6], null, v10, v5, v[6:7]
+; GFX13-NEXT: ; implicit-def: $vgpr6
; GFX13-NEXT: v_mad_co_u64_u32 v[3:4], null, v11, v4, v[5:6]
; GFX13-NEXT: s_set_pc_i64 s[30:31]
%result = mul i128 %num, %den
@@ -3078,6 +3101,7 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX7-NEXT: v_addc_u32_e32 v0, vcc, v0, v26, vcc
; GFX7-NEXT: v_addc_u32_e64 v0, vcc, v0, v27, s[6:7]
; GFX7-NEXT: v_addc_u32_e64 v0, vcc, v0, v25, s[4:5]
+; GFX7-NEXT: ; implicit-def: $vgpr1
; GFX7-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v7, v8, v[0:1]
; GFX7-NEXT: v_mov_b32_e32 v0, v16
; GFX7-NEXT: v_mov_b32_e32 v1, v11
@@ -3145,6 +3169,7 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX8-NEXT: v_addc_u32_e32 v0, vcc, v0, v26, vcc
; GFX8-NEXT: v_addc_u32_e64 v0, vcc, v0, v27, s[6:7]
; GFX8-NEXT: v_addc_u32_e64 v0, vcc, v0, v25, s[4:5]
+; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v7, v8, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v0, v16
; GFX8-NEXT: v_mov_b32_e32 v1, v11
@@ -3212,6 +3237,7 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v0, v26, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v0, vcc, v0, v27, s[6:7]
; GFX9-NEXT: v_addc_co_u32_e64 v0, vcc, v0, v25, s[4:5]
+; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v7, v8, v[0:1]
; GFX9-NEXT: v_mov_b32_e32 v0, v16
; GFX9-NEXT: v_mov_b32_e32 v1, v11
@@ -3281,13 +3307,14 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s6, v10, v14, s6
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s6, v25, v15, s6
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s6, v7, v20, s6
+; GFX10-NEXT: ; implicit-def: $vgpr10
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s6, v7, v9, s9
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s6, v7, v18, s8
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s6, v7, v30, s7
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v7, v29, s4
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v7, v26, s5
-; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v27, vcc_lo
-; GFX10-NEXT: v_mad_u64_u32 v[7:8], s4, v22, v8, v[7:8]
+; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v7, v27, vcc_lo
+; GFX10-NEXT: v_mad_u64_u32 v[7:8], s4, v22, v8, v[9:10]
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_mul_i256:
@@ -3349,6 +3376,7 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, s2, v10, v12, s2
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s2, v26, v13, s2
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v15, s2
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v14, s5
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v18, s4
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v31, s3
@@ -3447,6 +3475,7 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX12-NEXT: v_add_co_ci_u32_e64 v6, s2, v25, v15, s2
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v20, s2
+; GFX12-NEXT: ; implicit-def: $vgpr10
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v9, s5
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v18, s4
@@ -3456,9 +3485,9 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v26, s1
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v27, vcc_lo
+; GFX12-NEXT: v_add_co_ci_u32_e64 v9, null, v7, v27, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_mad_co_u64_u32 v[7:8], null, v22, v8, v[7:8]
+; GFX12-NEXT: v_mad_co_u64_u32 v[7:8], null, v22, v8, v[9:10]
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_mul_i256:
@@ -3632,6 +3661,7 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX13-NEXT: v_add_co_ci_u32_e64 v6, s2, v25, v15, s2
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX13-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v20, s2
+; GFX13-NEXT: ; implicit-def: $vgpr10
; GFX13-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v9, s5
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX13-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v18, s4
@@ -3640,8 +3670,8 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX13-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v29, s0
; GFX13-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v26, s1
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX13-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v27, vcc_lo
-; GFX13-NEXT: v_mad_co_u64_u32 v[7:8], null, v22, v8, v[7:8]
+; GFX13-NEXT: v_add_co_ci_u32_e64 v9, null, v7, v27, vcc_lo
+; GFX13-NEXT: v_mad_co_u64_u32 v[7:8], null, v22, v8, v[9:10]
; GFX13-NEXT: s_set_pc_i64 s[30:31]
%result = mul i256 %num, %den
ret i256 %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
index daefb43cc901b..540cfa08c47b7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
@@ -470,6 +470,7 @@ define i16 @v_orn2_i16(i16 %src0, i16 %src1) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v1.l, -1
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_orn2_i16:
@@ -978,14 +979,33 @@ define <3 x i16> @v_orn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10PLUS-LABEL: v_orn2_v3i16:
-; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX10PLUS-NEXT: v_xor_b32_e32 v3, -11, v3
-; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX10PLUS-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_orn2_v3i16:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX10-NEXT: v_xor_b32_e32 v3, -11, v3
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_orn2_v3i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v3, -11, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_orn2_v3i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v3, -11, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -11>
%or = or <3 x i16> %src0, %not.src1
ret <3 x i16> %or
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index baa3f4d9c051b..b17200d3520a3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -61,6 +61,7 @@ define i7 @v_saddsat_i7(i7 %lhs, i7 %rhs) {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 9, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 9, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, v0.l, v0.h clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 9, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -136,6 +137,7 @@ define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 9
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, s0, s1 clamp
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: s_sext_i32_i16 s0, s0
@@ -210,6 +212,7 @@ define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, v0.l, v0.h clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -285,6 +288,7 @@ define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 8
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, s0, s1 clamp
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: s_sext_i32_i16 s0, s0
@@ -418,6 +422,7 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_saddsat_v2i8:
@@ -785,10 +790,12 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v2, 8, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_i16 v1, v2, v1 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v2
@@ -2828,6 +2835,7 @@ define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, v0.l, v1.l clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_saddsat_i16:
@@ -2886,6 +2894,7 @@ define amdgpu_ps i16 @s_saddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX11-TRUE16-LABEL: s_saddsat_i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, s0, s1 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -2938,6 +2947,7 @@ define amdgpu_ps half @saddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX11-TRUE16-LABEL: saddsat_i16_sv:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, s0, v0.l clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: saddsat_i16_sv:
@@ -2988,6 +2998,7 @@ define amdgpu_ps half @saddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX11-TRUE16-LABEL: saddsat_i16_vs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, v0.l, s0 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: saddsat_i16_vs:
@@ -4488,19 +4499,21 @@ define amdgpu_ps i48 @s_saddsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_add_u32 s4, s0, s2
; GFX6-NEXT: s_addc_u32 s5, s1, s3
+; GFX6-NEXT: ; implicit-def: $sgpr1
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
+; GFX6-NEXT: ; implicit-def: $sgpr3
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: s_cselect_b32 s3, 1, 0
+; GFX6-NEXT: s_cselect_b32 s6, 1, 0
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x300000
; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[0:1], 0
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
; GFX6-NEXT: s_cselect_b32 s0, 1, 0
; GFX6-NEXT: s_ashr_i32 s1, s7, 31
-; GFX6-NEXT: s_xor_b32 s2, s0, s3
+; GFX6-NEXT: s_xor_b32 s2, s0, s6
; GFX6-NEXT: s_ashr_i32 s0, s7, 15
; GFX6-NEXT: s_addk_i32 s1, 0x8000
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
@@ -4511,19 +4524,21 @@ define amdgpu_ps i48 @s_saddsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s4, s0, s2
; GFX8-NEXT: s_addc_u32 s5, s1, s3
+; GFX8-NEXT: ; implicit-def: $sgpr1
+; GFX8-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
+; GFX8-NEXT: ; implicit-def: $sgpr3
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: s_cselect_b32 s3, 1, 0
+; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x300000
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[0:1], 0
; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_ashr_i32 s1, s7, 31
-; GFX8-NEXT: s_xor_b32 s2, s0, s3
+; GFX8-NEXT: s_xor_b32 s2, s0, s6
; GFX8-NEXT: s_ashr_i32 s0, s7, 15
; GFX8-NEXT: s_addk_i32 s1, 0x8000
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
@@ -4581,6 +4596,7 @@ define amdgpu_ps <2 x float> @saddsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v3, v1, vcc
+; GFX6-NEXT: ; implicit-def: $sgpr1
; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 16
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -4600,6 +4616,7 @@ define amdgpu_ps <2 x float> @saddsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v3, v1, vcc
+; GFX8-NEXT: ; implicit-def: $sgpr1
; GFX8-NEXT: v_bfe_i32 v3, v4, 0, 16
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -4674,6 +4691,7 @@ define amdgpu_ps <2 x float> @saddsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX6-LABEL: saddsat_i48_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: ; implicit-def: $sgpr1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v1, v3, vcc
@@ -4695,6 +4713,7 @@ define amdgpu_ps <2 x float> @saddsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX8-LABEL: saddsat_i48_vs:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: ; implicit-def: $sgpr1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v1, v3, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
index 3aefbd95fe581..0bf8d103e1180 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
@@ -363,6 +363,7 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: s_xor_b64 s[0:1], s[0:1], s[6:7]
; CHECK-NEXT: s_xor_b64 s[6:7], s[8:9], s[0:1]
; CHECK-NEXT: s_sub_u32 s0, s6, s0
+; CHECK-NEXT: ; implicit-def: $sgpr1
; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: .LBB1_2:
@@ -1947,266 +1948,266 @@ define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; GISEL-LABEL: v_sdiv_v2i64_pow2_shl_denom:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: v_mov_b32_e32 v11, 0x1000
-; GISEL-NEXT: v_mov_b32_e32 v12, 0
-; GISEL-NEXT: v_lshl_b64 v[7:8], v[11:12], v4
-; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v8
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v4
-; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v8, v4, vcc
-; GISEL-NEXT: v_xor_b32_e32 v8, v5, v4
-; GISEL-NEXT: v_xor_b32_e32 v5, v7, v4
-; GISEL-NEXT: v_cvt_f32_u32_e32 v7, v8
-; GISEL-NEXT: v_cvt_f32_u32_e32 v9, v5
-; GISEL-NEXT: v_sub_i32_e32 v15, vcc, 0, v8
+; GISEL-NEXT: v_mov_b32_e32 v7, 0x1000
+; GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GISEL-NEXT: v_lshl_b64 v[9:10], v[7:8], v4
+; GISEL-NEXT: v_lshl_b64 v[7:8], v[7:8], v6
+; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v10
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v9, v4
+; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v10, v4, vcc
+; GISEL-NEXT: v_xor_b32_e32 v10, v5, v4
+; GISEL-NEXT: v_xor_b32_e32 v5, v9, v4
+; GISEL-NEXT: v_cvt_f32_u32_e32 v9, v10
+; GISEL-NEXT: v_cvt_f32_u32_e32 v11, v5
+; GISEL-NEXT: v_sub_i32_e32 v15, vcc, 0, v10
; GISEL-NEXT: v_subb_u32_e32 v17, vcc, 0, v5, vcc
-; GISEL-NEXT: v_mac_f32_e32 v7, 0x4f800000, v9
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v7, v7
-; GISEL-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; GISEL-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
-; GISEL-NEXT: v_trunc_f32_e32 v13, v9
-; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v13
-; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GISEL-NEXT: v_mac_f32_e32 v9, 0x4f800000, v11
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v9, v9
+; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v8
+; GISEL-NEXT: v_mul_f32_e32 v9, 0x5f7ffffc, v9
+; GISEL-NEXT: v_mul_f32_e32 v11, 0x2f800000, v9
+; GISEL-NEXT: v_trunc_f32_e32 v13, v11
+; GISEL-NEXT: v_mac_f32_e32 v9, 0xcf800000, v13
+; GISEL-NEXT: v_cvt_u32_f32_e32 v9, v9
; GISEL-NEXT: v_cvt_u32_f32_e32 v16, v13
-; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v15, v7, 0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v15, v16, v[10:11]
-; GISEL-NEXT: v_mul_hi_u32 v18, v7, v9
-; GISEL-NEXT: v_mul_lo_u32 v19, v16, v9
-; GISEL-NEXT: v_mul_hi_u32 v20, v16, v9
-; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v17, v7, v[13:14]
-; GISEL-NEXT: v_mul_lo_u32 v10, v7, v9
-; GISEL-NEXT: v_mul_hi_u32 v14, v7, v9
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v18, v10
+; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v15, v9, 0
+; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v15, v16, v[12:13]
+; GISEL-NEXT: v_mul_hi_u32 v18, v9, v11
+; GISEL-NEXT: v_mul_lo_u32 v19, v16, v11
+; GISEL-NEXT: v_mul_hi_u32 v20, v16, v11
+; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v17, v9, v[13:14]
+; GISEL-NEXT: v_mul_lo_u32 v12, v9, v11
+; GISEL-NEXT: v_mul_hi_u32 v14, v9, v11
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v18, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v19
-; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10
-; GISEL-NEXT: v_mul_lo_u32 v13, v16, v9
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v19
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT: v_mul_lo_u32 v13, v16, v11
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v20, v14
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v18, v14
-; GISEL-NEXT: v_mul_hi_u32 v9, v16, v9
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10
+; GISEL-NEXT: v_mul_hi_u32 v11, v16, v11
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
-; GISEL-NEXT: v_add_i32_e32 v18, vcc, v7, v10
-; GISEL-NEXT: v_addc_u32_e32 v19, vcc, v16, v9, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v15, v18, 0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v15, v19, v[10:11]
-; GISEL-NEXT: v_mul_hi_u32 v7, v18, v9
-; GISEL-NEXT: v_lshl_b64 v[11:12], v[11:12], v6
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT: v_add_i32_e32 v18, vcc, v9, v12
+; GISEL-NEXT: v_addc_u32_e32 v19, vcc, v16, v11, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v15, v18, 0
+; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v15, v19, v[12:13]
+; GISEL-NEXT: v_mul_hi_u32 v9, v18, v11
; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v17, v18, v[13:14]
-; GISEL-NEXT: v_mul_lo_u32 v13, v19, v9
-; GISEL-NEXT: v_mul_hi_u32 v9, v19, v9
-; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v12
-; GISEL-NEXT: v_mul_lo_u32 v10, v18, v15
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
-; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v1
-; GISEL-NEXT: v_add_i32_e64 v0, s[4:5], v0, v7
-; GISEL-NEXT: v_xor_b32_e32 v16, v0, v7
+; GISEL-NEXT: v_mul_lo_u32 v13, v19, v11
+; GISEL-NEXT: v_mul_hi_u32 v11, v19, v11
+; GISEL-NEXT: v_mul_lo_u32 v12, v18, v15
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
+; GISEL-NEXT: v_ashrrev_i32_e32 v9, 31, v1
+; GISEL-NEXT: v_add_i32_e64 v0, s[4:5], v0, v9
+; GISEL-NEXT: v_xor_b32_e32 v17, v0, v9
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_mul_hi_u32 v13, v18, v15
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v0
-; GISEL-NEXT: v_mul_lo_u32 v10, v19, v15
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v12, v0
+; GISEL-NEXT: v_mul_lo_u32 v12, v19, v15
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v13, v19, v15
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v9, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v11, v0
+; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v18, v0
-; GISEL-NEXT: v_addc_u32_e64 v1, s[4:5], v1, v7, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v19, v9, vcc
-; GISEL-NEXT: v_mul_hi_u32 v10, v16, v0
-; GISEL-NEXT: v_mul_lo_u32 v13, v16, v9
-; GISEL-NEXT: v_xor_b32_e32 v15, v1, v7
-; GISEL-NEXT: v_mul_lo_u32 v1, v15, v0
-; GISEL-NEXT: v_mul_hi_u32 v0, v15, v0
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; GISEL-NEXT: v_addc_u32_e64 v1, s[4:5], v1, v9, s[4:5]
+; GISEL-NEXT: v_addc_u32_e32 v11, vcc, v19, v11, vcc
+; GISEL-NEXT: v_mul_hi_u32 v12, v17, v0
+; GISEL-NEXT: v_mul_lo_u32 v13, v17, v11
+; GISEL-NEXT: v_xor_b32_e32 v1, v1, v9
+; GISEL-NEXT: v_mul_lo_u32 v14, v1, v0
+; GISEL-NEXT: v_mul_hi_u32 v0, v1, v0
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v10, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v10, v16, v9
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1
-; GISEL-NEXT: v_mul_lo_u32 v13, v15, v9
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT: v_mul_hi_u32 v14, v17, v11
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT: v_mul_lo_u32 v13, v1, v11
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v14
+; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v13
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v0, v1
-; GISEL-NEXT: v_mul_hi_u32 v9, v15, v9
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v8, v17, 0
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v13
-; GISEL-NEXT: v_add_i32_e32 v18, vcc, v9, v10
-; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v8, v18, v[1:2]
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v16, v0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v5, v17, v[9:10]
-; GISEL-NEXT: v_subb_u32_e64 v16, s[4:5], v15, v13, vcc
-; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v15, v13
-; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v6
-; GISEL-NEXT: v_addc_u32_e64 v11, s[4:5], v12, v6, s[4:5]
-; GISEL-NEXT: v_xor_b32_e32 v10, v9, v6
-; GISEL-NEXT: v_xor_b32_e32 v9, v11, v6
-; GISEL-NEXT: v_cvt_f32_u32_e32 v11, v10
-; GISEL-NEXT: v_cvt_f32_u32_e32 v12, v9
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v12
+; GISEL-NEXT: v_mul_hi_u32 v15, v1, v11
+; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v10, v0, 0
+; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT: v_add_i32_e32 v18, vcc, v15, v13
+; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[4:5], v10, v18, v[12:13]
+; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v17, v11
+; GISEL-NEXT: v_xor_b32_e32 v9, v9, v4
+; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v5, v0, v[13:14]
+; GISEL-NEXT: v_subb_u32_e64 v16, s[4:5], v1, v15, vcc
+; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v15
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v7, v6
+; GISEL-NEXT: v_addc_u32_e64 v12, s[4:5], v8, v6, s[4:5]
+; GISEL-NEXT: v_xor_b32_e32 v8, v7, v6
+; GISEL-NEXT: v_xor_b32_e32 v7, v12, v6
+; GISEL-NEXT: v_cvt_f32_u32_e32 v12, v8
+; GISEL-NEXT: v_cvt_f32_u32_e32 v13, v7
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v8
-; GISEL-NEXT: v_mac_f32_e32 v11, 0x4f800000, v12
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v11, v11
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
-; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v8
-; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v11
-; GISEL-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GISEL-NEXT: v_trunc_f32_e32 v1, v1
-; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v0
-; GISEL-NEXT: v_sub_i32_e64 v20, s[6:7], 0, v10
-; GISEL-NEXT: v_cvt_u32_f32_e32 v19, v1
-; GISEL-NEXT: v_subb_u32_e64 v21, s[6:7], 0, v9, s[6:7]
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v20, v8, 0
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v15, v5
-; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[6:7], v20, v19, v[1:2]
-; GISEL-NEXT: v_mul_hi_u32 v1, v8, v0
-; GISEL-NEXT: v_mad_u64_u32 v[13:14], s[6:7], v21, v8, v[11:12]
-; GISEL-NEXT: v_mul_lo_u32 v11, v8, v13
-; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], v1, v11
-; GISEL-NEXT: v_mul_lo_u32 v11, v19, v0
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7]
-; GISEL-NEXT: v_mul_hi_u32 v0, v19, v0
-; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], v1, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[8:9]
-; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v15, v5
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v16, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[8:9]
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v10
+; GISEL-NEXT: v_mac_f32_e32 v12, 0x4f800000, v13
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v12, v12
+; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v11, v10
+; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v10
+; GISEL-NEXT: v_mul_f32_e32 v10, 0x5f7ffffc, v12
+; GISEL-NEXT: v_mul_f32_e32 v11, 0x2f800000, v10
+; GISEL-NEXT: v_trunc_f32_e32 v11, v11
+; GISEL-NEXT: v_mac_f32_e32 v10, 0xcf800000, v11
+; GISEL-NEXT: v_cvt_u32_f32_e32 v17, v10
+; GISEL-NEXT: v_sub_i32_e64 v20, s[6:7], 0, v8
+; GISEL-NEXT: v_cvt_u32_f32_e32 v19, v11
+; GISEL-NEXT: v_subb_u32_e64 v21, s[6:7], 0, v7, s[6:7]
+; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v20, v17, 0
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v1, v5
+; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v20, v19, v[11:12]
+; GISEL-NEXT: v_mul_hi_u32 v11, v17, v10
+; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[6:7], v21, v17, v[12:13]
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v16, v5
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v17
-; GISEL-NEXT: v_cndmask_b32_e64 v5, v14, v15, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v14, vcc, 0, v18, vcc
+; GISEL-NEXT: v_mul_lo_u32 v12, v17, v14
+; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12
+; GISEL-NEXT: v_mul_lo_u32 v12, v19, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[6:7]
+; GISEL-NEXT: v_mul_hi_u32 v10, v19, v10
+; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[8:9]
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v5
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[8:9], v16, v5
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v0
+; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[8:9]
+; GISEL-NEXT: v_addc_u32_e32 v12, vcc, 0, v18, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v15, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v15, vcc, 1, v11
-; GISEL-NEXT: v_addc_u32_e32 v16, vcc, 0, v14, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[6:7]
-; GISEL-NEXT: v_cndmask_b32_e32 v11, v11, v15, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v12, v1
-; GISEL-NEXT: v_mul_hi_u32 v12, v8, v13
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v12
-; GISEL-NEXT: v_mul_lo_u32 v12, v19, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v13, v19, v13
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v15, v12
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v12, v1
-; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v8, v0
-; GISEL-NEXT: v_addc_u32_e32 v13, vcc, v19, v1, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v20, v12, 0
+; GISEL-NEXT: v_addc_u32_e32 v16, vcc, 0, v12, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; GISEL-NEXT: v_cndmask_b32_e32 v8, v17, v11, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v11, v18, v14, vcc
-; GISEL-NEXT: v_xor_b32_e32 v14, v7, v4
-; GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v20, v13, v[1:2]
-; GISEL-NEXT: v_xor_b32_e32 v1, v8, v14
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v15, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
+; GISEL-NEXT: v_mul_hi_u32 v13, v17, v14
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; GISEL-NEXT: v_mul_lo_u32 v13, v19, v14
+; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT: v_mul_hi_u32 v14, v19, v14
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v15, v13
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v14, v11
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v17, v10
+; GISEL-NEXT: v_addc_u32_e32 v14, vcc, v19, v11, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v20, v13, 0
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GISEL-NEXT: v_cndmask_b32_e32 v12, v18, v12, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v0, v5, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v20, v14, v[11:12]
+; GISEL-NEXT: v_xor_b32_e32 v11, v5, v9
; GISEL-NEXT: v_ashrrev_i32_e32 v15, 31, v3
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v15
-; GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v21, v12, v[4:5]
-; GISEL-NEXT: v_mul_hi_u32 v4, v12, v0
-; GISEL-NEXT: v_xor_b32_e32 v16, v2, v15
-; GISEL-NEXT: v_mul_lo_u32 v2, v13, v0
-; GISEL-NEXT: v_mul_lo_u32 v5, v12, v7
-; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v15, vcc
-; GISEL-NEXT: v_mul_hi_u32 v0, v13, v0
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v4, v12, v7
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GISEL-NEXT: v_mul_lo_u32 v5, v13, v7
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; GISEL-NEXT: v_xor_b32_e32 v12, v12, v9
+; GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v21, v13, v[0:1]
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v2, v15
+; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v3, v15, vcc
+; GISEL-NEXT: v_mul_hi_u32 v2, v13, v10
+; GISEL-NEXT: v_mul_lo_u32 v3, v13, v4
+; GISEL-NEXT: v_xor_b32_e32 v16, v0, v15
+; GISEL-NEXT: v_mul_lo_u32 v0, v14, v10
+; GISEL-NEXT: v_mul_hi_u32 v5, v13, v4
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GISEL-NEXT: v_mul_hi_u32 v2, v14, v10
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v3, v0
+; GISEL-NEXT: v_mul_lo_u32 v3, v14, v4
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GISEL-NEXT: v_mul_hi_u32 v5, v13, v7
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, v5, v3
+; GISEL-NEXT: v_mul_hi_u32 v4, v14, v4
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v2, v0
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v12, v0
-; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v13, v2, vcc
-; GISEL-NEXT: v_mul_hi_u32 v4, v16, v0
-; GISEL-NEXT: v_mul_lo_u32 v5, v16, v2
-; GISEL-NEXT: v_xor_b32_e32 v12, v3, v15
-; GISEL-NEXT: v_mul_lo_u32 v3, v12, v0
-; GISEL-NEXT: v_mul_hi_u32 v0, v12, v0
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v13, v0
+; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v14, v2, vcc
+; GISEL-NEXT: v_mul_hi_u32 v3, v16, v0
+; GISEL-NEXT: v_mul_lo_u32 v4, v16, v2
+; GISEL-NEXT: v_xor_b32_e32 v13, v1, v15
+; GISEL-NEXT: v_mul_lo_u32 v1, v13, v0
+; GISEL-NEXT: v_mul_hi_u32 v0, v13, v0
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v1, vcc, v3, v1
+; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GISEL-NEXT: v_mul_hi_u32 v3, v16, v2
+; GISEL-NEXT: v_add_i32_e32 v1, vcc, v4, v1
+; GISEL-NEXT: v_mul_lo_u32 v4, v13, v2
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GISEL-NEXT: v_mul_hi_u32 v4, v16, v2
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; GISEL-NEXT: v_mul_lo_u32 v5, v12, v2
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v0, v3
-; GISEL-NEXT: v_mul_hi_u32 v5, v12, v2
-; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v13, 0
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v3, v4
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v0, v1
+; GISEL-NEXT: v_mul_hi_u32 v1, v13, v2
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v14, 0
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v4, v0
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v5, v0
-; GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v17, v[3:4]
-; GISEL-NEXT: v_xor_b32_e32 v11, v11, v14
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v1, v14
-; GISEL-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v9, v13, v[4:5]
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v11, v14, vcc
+; GISEL-NEXT: v_add_i32_e32 v17, vcc, v1, v0
+; GISEL-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v17, v[3:4]
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v11, v9
+; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v12, v9, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v7, v14, v[4:5]
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v16, v2
-; GISEL-NEXT: v_subb_u32_e64 v3, s[4:5], v12, v7, vcc
-; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], v12, v7
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v9
-; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v4, v9, vcc
+; GISEL-NEXT: v_subb_u32_e64 v3, s[4:5], v13, v9, vcc
+; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], v13, v9
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v7
+; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v4, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v10
-; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v9
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v8
+; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v7
; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[4:5]
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v13
-; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v17, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v4, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v9, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v14
+; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v17, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v4, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v8
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v4, v9
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v4, v7
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v5
-; GISEL-NEXT: v_addc_u32_e32 v8, vcc, 0, v7, vcc
+; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v9, v7, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v13, v2, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc
; GISEL-NEXT: v_xor_b32_e32 v4, v15, v6
; GISEL-NEXT: v_xor_b32_e32 v2, v2, v4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
index 8b68f4aef2a0c..00260e2ec5cd5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
@@ -1194,11 +1194,13 @@ define i64 @v_sext_inreg_i64_31(i64 %value) {
define amdgpu_ps i64 @s_sext_inreg_i64_3(i64 inreg %value) {
; GCN-LABEL: s_sext_inreg_i64_3:
; GCN: ; %bb.0:
+; GCN-NEXT: ; implicit-def: $sgpr1
; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3d0000
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_sext_inreg_i64_3:
; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr1
; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3d0000
; GFX10PLUS-NEXT: ; return to shader part epilog
%shl = shl i64 %value, 3
@@ -1209,11 +1211,13 @@ define amdgpu_ps i64 @s_sext_inreg_i64_3(i64 inreg %value) {
define amdgpu_ps i64 @s_sext_inreg_i64_63(i64 inreg %value) {
; GCN-LABEL: s_sext_inreg_i64_63:
; GCN: ; %bb.0:
+; GCN-NEXT: ; implicit-def: $sgpr1
; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x10000
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_sext_inreg_i64_63:
; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr1
; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x10000
; GFX10PLUS-NEXT: ; return to shader part epilog
%shl = shl i64 %value, 63
@@ -1224,11 +1228,13 @@ define amdgpu_ps i64 @s_sext_inreg_i64_63(i64 inreg %value) {
define amdgpu_ps i64 @s_sext_inreg_i64_33(i64 inreg %value) {
; GCN-LABEL: s_sext_inreg_i64_33:
; GCN: ; %bb.0:
+; GCN-NEXT: ; implicit-def: $sgpr1
; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x1f0000
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_sext_inreg_i64_33:
; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr1
; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x1f0000
; GFX10PLUS-NEXT: ; return to shader part epilog
%shl = shl i64 %value, 33
@@ -1254,11 +1260,13 @@ define amdgpu_ps i64 @s_sext_inreg_i64_32(i64 inreg %value) {
define amdgpu_ps i64 @s_sext_inreg_i64_31(i64 inreg %value) {
; GCN-LABEL: s_sext_inreg_i64_31:
; GCN: ; %bb.0:
+; GCN-NEXT: ; implicit-def: $sgpr1
; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x210000
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_sext_inreg_i64_31:
; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr1
; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x210000
; GFX10PLUS-NEXT: ; return to shader part epilog
%shl = shl i64 %value, 31
@@ -1307,12 +1315,16 @@ define <2 x i64> @v_sext_inreg_v2i64_31(<2 x i64> %value) {
define amdgpu_ps <2 x i64> @s_sext_inreg_v2i64_30(<2 x i64> inreg %value) {
; GCN-LABEL: s_sext_inreg_v2i64_30:
; GCN: ; %bb.0:
+; GCN-NEXT: ; implicit-def: $sgpr1
+; GCN-NEXT: ; implicit-def: $sgpr3
; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x220000
; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x220000
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_sext_inreg_v2i64_30:
; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr1
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x220000
; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x220000
; GFX10PLUS-NEXT: ; return to shader part epilog
@@ -1324,6 +1336,7 @@ define amdgpu_ps <2 x i64> @s_sext_inreg_v2i64_30(<2 x i64> inreg %value) {
define i65 @v_sext_inreg_i65_22(i65 %value) {
; GFX6-LABEL: v_sext_inreg_i65_22:
; GFX6: ; %bb.0:
+; GFX6-NEXT: ; implicit-def: $vgpr3
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 22
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 10, v1
@@ -1338,6 +1351,7 @@ define i65 @v_sext_inreg_i65_22(i65 %value) {
;
; GFX8-LABEL: v_sext_inreg_i65_22:
; GFX8: ; %bb.0:
+; GFX8-NEXT: ; implicit-def: $vgpr3
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 10, v1
@@ -1352,6 +1366,7 @@ define i65 @v_sext_inreg_i65_22(i65 %value) {
;
; GFX9-LABEL: v_sext_inreg_i65_22:
; GFX9: ; %bb.0:
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 10, v1
@@ -1365,6 +1380,7 @@ define i65 @v_sext_inreg_i65_22(i65 %value) {
;
; GFX10PLUS-LABEL: v_sext_inreg_i65_22:
; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: ; implicit-def: $vgpr3
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]
; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 10, v1
@@ -1436,24 +1452,28 @@ define i65 @v_sext_inreg_i65_33(i65 %value) {
define amdgpu_ps i65 @s_sext_inreg_i65_18(i65 inreg %value) {
; GCN-LABEL: s_sext_inreg_i65_18:
; GCN: ; %bb.0:
+; GCN-NEXT: ; implicit-def: $sgpr3
+; GCN-NEXT: s_mov_b32 s4, 0
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], 18
; GCN-NEXT: s_lshr_b32 s3, s1, 14
; GCN-NEXT: s_or_b32 s2, s2, s3
-; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GCN-NEXT: ; implicit-def: $sgpr3
; GCN-NEXT: s_bfe_u64 s[0:1], s[0:1], 0x2e0000
+; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GCN-NEXT: s_lshl_b32 s5, s2, 14
-; GCN-NEXT: s_mov_b32 s4, 0
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 18
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_sext_inreg_i65_18:
; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
+; GFX10PLUS-NEXT: s_mov_b32 s4, 0
; GFX10PLUS-NEXT: s_lshl_b64 s[2:3], s[2:3], 18
; GFX10PLUS-NEXT: s_lshr_b32 s3, s1, 14
; GFX10PLUS-NEXT: s_bfe_u64 s[0:1], s[0:1], 0x2e0000
; GFX10PLUS-NEXT: s_or_b32 s2, s2, s3
-; GFX10PLUS-NEXT: s_mov_b32 s4, 0
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX10PLUS-NEXT: s_lshl_b32 s5, s2, 14
; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[2:3], 18
@@ -1471,8 +1491,9 @@ define amdgpu_ps i65 @s_sext_inreg_i65_33(i65 inreg %value) {
; GCN-NEXT: s_mov_b32 s2, 0
; GCN-NEXT: s_lshr_b64 s[4:5], s[0:1], 31
; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
-; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GCN-NEXT: ; implicit-def: $sgpr3
; GCN-NEXT: s_bfe_u32 s4, s0, 0x1f0000
+; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
; GCN-NEXT: s_or_b32 s0, s0, s4
; GCN-NEXT: s_ashr_i32 s2, s3, 1
@@ -1484,6 +1505,7 @@ define amdgpu_ps i65 @s_sext_inreg_i65_33(i65 inreg %value) {
; GFX10PLUS-NEXT: s_mov_b32 s2, 0
; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[0:1], 31
; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GFX10PLUS-NEXT: ; implicit-def: $sgpr3
; GFX10PLUS-NEXT: s_bfe_u32 s4, s0, 0x1f0000
; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
index 3e78f48e37a50..da9720cc34141 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
@@ -161,9 +161,10 @@ define i64 @v_mul_i64_i32(i32 %a, i32 %b) {
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v3, 0
; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, v2, v6, v[1:2]
-; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v2
+; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v2
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v5, v3, v[4:5]
+; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, v6, v3, v[4:5]
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_mul_i64_i32:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
index fba617616b374..3be681ed84865 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -360,6 +360,7 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
; CHECK-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]
; CHECK-NEXT: s_sub_u32 s0, s6, s0
+; CHECK-NEXT: ; implicit-def: $sgpr1
; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: .LBB1_2:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 26d853a389285..80dcb575d52d6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -61,6 +61,7 @@ define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 9, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 9, v1.l
; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, v0.l, v0.h clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 9, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -136,6 +137,7 @@ define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 9
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, s0, s1 clamp
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: s_sext_i32_i16 s0, s0
@@ -210,6 +212,7 @@ define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, v0.l, v0.h clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -285,6 +288,7 @@ define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 8
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, s0, s1 clamp
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: s_sext_i32_i16 s0, s0
@@ -418,6 +422,7 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ssubsat_v2i8:
@@ -785,10 +790,12 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v2, 8, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_sub_i16 v1, v2, v1 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v2
@@ -2832,6 +2839,7 @@ define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, v0.l, v1.l clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ssubsat_i16:
@@ -2890,6 +2898,7 @@ define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX11-TRUE16-LABEL: s_ssubsat_i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, s0, s1 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -2942,6 +2951,7 @@ define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX11-TRUE16-LABEL: ssubsat_i16_sv:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, s0, v0.l clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: ssubsat_i16_sv:
@@ -2992,6 +3002,7 @@ define amdgpu_ps half @ssubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX11-TRUE16-LABEL: ssubsat_i16_vs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, v0.l, s0 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: ssubsat_i16_vs:
@@ -4492,6 +4503,8 @@ define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s4, s0, s2
; GFX6-NEXT: s_subb_u32 s5, s1, s3
+; GFX6-NEXT: ; implicit-def: $sgpr3
+; GFX6-NEXT: ; implicit-def: $sgpr1
; GFX6-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x300000
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
@@ -4515,6 +4528,8 @@ define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s4, s0, s2
; GFX8-NEXT: s_subb_u32 s5, s1, s3
+; GFX8-NEXT: ; implicit-def: $sgpr3
+; GFX8-NEXT: ; implicit-def: $sgpr1
; GFX8-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x300000
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
@@ -4585,8 +4600,9 @@ define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc
-; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
+; GFX6-NEXT: ; implicit-def: $sgpr1
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 16
; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[0:1], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
@@ -4604,8 +4620,9 @@ define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc
-; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
+; GFX8-NEXT: ; implicit-def: $sgpr1
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_bfe_i32 v3, v4, 0, 16
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[0:1], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
@@ -4680,6 +4697,7 @@ define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc
+; GFX6-NEXT: ; implicit-def: $sgpr1
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 16
@@ -4699,6 +4717,7 @@ define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc
+; GFX8-NEXT: ; implicit-def: $sgpr1
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_bfe_i32 v3, v4, 0, 16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
index 8ecd0820d7f51..fc820c4434195 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
@@ -271,10 +271,13 @@ define void @v_constained_fma_v3f32_fpexcept_strict_uni(<3 x float> inreg %x, <3
; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[18:19]
; GFX942-NEXT: s_mov_b32 s6, s17
; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[0:1], v[2:3], v[4:5]
+; GFX942-NEXT: ; implicit-def: $sgpr7
+; GFX942-NEXT: ; implicit-def: $sgpr21
; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[20:21]
; GFX942-NEXT: v_readfirstlane_b32 s0, v2
; GFX942-NEXT: v_readfirstlane_b32 s1, v3
; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[2:3], v[2:3], v[4:5]
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s2, v2
@@ -352,8 +355,11 @@ define void @v_constained_fma_v3f32_fpexcept_strict_div(<3 x float> %x, <3 x flo
; GFX942-NEXT: v_mov_b32_e32 v12, v3
; GFX942-NEXT: v_mov_b32_e32 v13, v4
; GFX942-NEXT: v_mov_b32_e32 v4, v5
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: v_mov_b32_e32 v14, v9
; GFX942-NEXT: v_mov_b32_e32 v15, v10
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[12:13], v[6:7]
; GFX942-NEXT: v_pk_fma_f32 v[2:3], v[2:3], v[4:5], v[8:9]
; GFX942-NEXT: global_store_dwordx3 v[14:15], v[0:2], off
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
index daeb7753c94d9..5f32ad8f65f0b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
@@ -86,6 +86,7 @@ define i16 @v_sub_i16(i16 %a, i16 %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sub_nc_u16 v0.l, v0.l, v1.l
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_sub_i16:
@@ -96,6 +97,7 @@ define i16 @v_sub_i16(i16 %a, i16 %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_sub_nc_u16 v0.l, v0.l, v1.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = sub i16 %a, %b
ret i16 %c
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
index e03c164803b51..3b685f3d89ed5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
@@ -38,6 +38,7 @@ define amdgpu_ps i48 @test_merge_values_vgpr(<3 x i16> %src0, <3 x i16> %src1) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v0, v0, v2
; GFX11-NEXT: v_and_b32_e32 v1, v1, v3
+; GFX11-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1
@@ -50,6 +51,7 @@ define amdgpu_ps i48 @test_merge_values_vgpr(<3 x i16> %src0, <3 x i16> %src1) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_and_b32_e32 v0, v0, v2
; GFX12-NEXT: v_and_b32_e32 v1, v1, v3
+; GFX12-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: v_readfirstlane_b32 s1, v1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
index 01ffdecdd81f7..568c7d54f1b3c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -51,6 +51,7 @@ define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 9, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 9, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 9, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -113,6 +114,7 @@ define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 9
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, s0, s1 clamp
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
@@ -177,6 +179,7 @@ define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -239,6 +242,7 @@ define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 8
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, s0, s1 clamp
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
@@ -340,6 +344,7 @@ define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -680,10 +685,12 @@ define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v2, 8, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v2, v1 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v2
@@ -2036,6 +2043,7 @@ define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_uaddsat_i16:
@@ -2081,6 +2089,7 @@ define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX11-TRUE16-LABEL: s_uaddsat_i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, s0, s1 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -2122,6 +2131,7 @@ define amdgpu_ps half @uaddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX11-TRUE16-LABEL: uaddsat_i16_sv:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, s0, v0.l clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: uaddsat_i16_sv:
@@ -2162,6 +2172,7 @@ define amdgpu_ps half @uaddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX11-TRUE16-LABEL: uaddsat_i16_vs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, s0 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: uaddsat_i16_vs:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
index a9d67dae1d1de..8d1708343f1ab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -50,6 +50,7 @@ define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 9, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 9, v1.l
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, v0.h clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 9, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -111,6 +112,7 @@ define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 9
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, s0, s1 clamp
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
@@ -174,6 +176,7 @@ define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, v0.h clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -235,6 +238,7 @@ define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 8
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, s0, s1 clamp
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
@@ -334,6 +338,7 @@ define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -668,10 +673,12 @@ define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v2, 8, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_sub_u16 v1, v2, v1 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v2
@@ -1953,6 +1960,7 @@ define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, v1.l clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_usubsat_i16:
@@ -1997,6 +2005,7 @@ define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX11-TRUE16-LABEL: s_usubsat_i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, s0, s1 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -2037,6 +2046,7 @@ define amdgpu_ps half @usubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX11-TRUE16-LABEL: usubsat_i16_sv:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, s0, v0.l clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: usubsat_i16_sv:
@@ -2076,6 +2086,7 @@ define amdgpu_ps half @usubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX11-TRUE16-LABEL: usubsat_i16_vs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, s0 clamp
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: usubsat_i16_vs:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 2d5fc5cf22425..d3b9a99d6ae1e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -7223,47 +7223,80 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v3.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v65, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v55, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v65, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v7.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v66, v66, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v54, v64, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v64, v65, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v66, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v55, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v54, 16, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v53, v54, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -7273,15 +7306,27 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v53, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
@@ -7291,13 +7336,25 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
@@ -7307,13 +7364,25 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
@@ -7323,13 +7392,25 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
@@ -7341,15 +7422,30 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
@@ -15818,8 +15914,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:376
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:372
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:368
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:364
@@ -15828,118 +15924,118 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:352
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:348
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:340
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:336
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:336
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:332
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:328
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:324
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:304
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:272
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:268
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:264
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:248
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:244
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:224
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:192
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:184
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:180
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:168
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:164
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:144
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v40, off, s32 offset:64
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v42, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v45, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v57, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:388
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v60, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v75.l, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v76.l, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v77.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v78.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.l, v23.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v89.l, v22.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v90.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v92.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v91.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v91.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v92.l, v19.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v93.l, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v94.l, v17.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v95.l, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v104.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.l, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.l, v12.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v108.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v110.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v110.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v111.l, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v120.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v121.l, v6.l
@@ -15957,103 +16053,231 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v127, v126, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v125, v124, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v123, v122, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v121, v120, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v107, v105, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v106, v104, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v107, v106, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v105, v104, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v95, v94, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v111, v109, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v110, v108, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v93, v91, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v92, v90, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v89, v79, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v88, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v111, v110, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v109, v108, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v93, v92, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v91, v90, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v89, v88, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v79, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v76, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v75, v73, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v75, v74, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v74, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v61, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v62, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v73, v72, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v61, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v59, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v57, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v56, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v45, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v44, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v57, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v47, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v45, v44, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v43, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v41, v40, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v183, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v179, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v178, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v183, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v181, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v179, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v177, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v164, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v161, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v160, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v163, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v161, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v151, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v147, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v146, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v134, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v147, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v145, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v133, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v131, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v129, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v128, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v117, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v116, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v129, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v117, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v115, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v113, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v24, 16, v23
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v26, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v102, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v99, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v98, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v101, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v87, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v84, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v81, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v80, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v83, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v81, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v71, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v26
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v25, v29, 16, v28
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v31, 16, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v67, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v66, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v67, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v55, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v54, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v54, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v48, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v39, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v34, v36, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v30, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v48, 16, v31
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v35, 16, v37
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v32, 16, v33
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v32, 16, v34
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16
@@ -16063,114 +16287,114 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
@@ -16179,8 +16403,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: .LBB14_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -16202,22 +16426,22 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v111.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v110.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v109.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v109.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v110.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v108.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v107.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v106.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v105.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v95.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v3.h, v2.h
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v105.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v106.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v104.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v92.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v91.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v90.l
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v89.l, 3
@@ -16226,26 +16450,26 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v94.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v93.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v5.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v88.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v79.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, v77.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.h, v4.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v91.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v74.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v92.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v73.l, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v72.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v63.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v61.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v4.h
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v5.h
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v79.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v88.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v7.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v78.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, v59.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v56.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v47.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v6.h
; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v7.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v76.l
@@ -16255,42 +16479,42 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v45.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.l, v6.h
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v7.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v73.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v44.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v74.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v43.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v41.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v182.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v181.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v180.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v61.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v62.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v9.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v60.l
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v13.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, v179.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v8.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v178.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v177.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.h, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v10.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v58.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, v57.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, v167.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v164.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v163.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v162.l
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v9.h, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v47.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v56.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v161.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v149.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v10.l, v9.h
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v43.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v44.l
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v12.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, v145.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v144.l
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, v135.l, 3
@@ -16299,25 +16523,25 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v40.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v183.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v18.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, v134.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, v133.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, v131.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v11.h, v12.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v12.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v181.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, v128.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v182.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, v119.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v118.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, v117.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, v116.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v14.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v177.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v178.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v14.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v176.l
; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v20.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, v113.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v13.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, v101.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.h, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v166.l
@@ -16327,43 +16551,43 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, v99.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v15.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v163.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v164.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, v97.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, v87.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, v84.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, v83.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v82.l
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.l, v14.h
; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v16.l, v15.h
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v151.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v160.l
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v17.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v150.l
; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v25.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, v81.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v16.l, v15.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, v80.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, v71.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.l, v16.h
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v17.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v148.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v147.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, v65.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v28.h, 8, v64.l
; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v17.l, v16.h
; GFX11-TRUE16-NEXT: v_and_b16 v17.l, 0xff, v17.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v145.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v146.l
; GFX11-TRUE16-NEXT: v_and_b16 v28.l, 0xff, v28.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.h, 8, v53.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_or_b16 v17.l, v17.h, v17.l
; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v18.h, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v19.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v134.l
; GFX11-TRUE16-NEXT: v_and_b16 v19.l, 0xff, v19.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v132.l
; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v28.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v18.l, v18.h, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v29.l
; GFX11-TRUE16-NEXT: v_or_b16 v18.h, v19.h, v19.l
@@ -16375,39 +16599,39 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v29.l, v29.h, v29.l
; GFX11-TRUE16-NEXT: v_or_b16 v19.l, v19.h, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v19.h, 0xff, v20.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v119.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v128.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, v38.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, v36.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v33.h, v34.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v33.l, v33.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.h, 8, v37.l
; GFX11-TRUE16-NEXT: v_or_b16 v19.h, v20.l, v19.h
; GFX11-TRUE16-NEXT: v_or_b16 v20.l, v21.l, v20.h
; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v21.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v115.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v116.l
; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v22.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v114.l
; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v35.l
; GFX11-TRUE16-NEXT: v_or_b16 v20.h, v21.l, v20.h
; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_or_b16 v21.l, v22.l, v21.h
; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v22.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v112.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, v103.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v33.l
-; GFX11-TRUE16-NEXT: v_and_b16 v33.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_and_b16 v33.l, 0xff, v33.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v21.h, v22.l, v21.h
; GFX11-TRUE16-NEXT: v_and_b16 v22.l, 0xff, v22.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v101.l
-; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v34.l, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v33.l, v31.h
-; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v32.l, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v102.l
+; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v33.h, v31.l
+; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v34.l, v31.h
+; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v32.l, v33.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v22.l, v22.h, v22.l
; GFX11-TRUE16-NEXT: v_or_b16 v22.h, v23.h, v23.l
; GFX11-TRUE16-NEXT: v_and_b16 v23.l, 0xff, v24.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v24.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v96.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v0.h
@@ -16423,7 +16647,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.h, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v25.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v83.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v84.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v3.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v4.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v4.h
@@ -16431,7 +16655,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v25.l, v24.h
; GFX11-TRUE16-NEXT: v_or_b16 v25.l, v26.l, v25.h
; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v26.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v80.l
; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v27.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v5.h
@@ -16447,7 +16671,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v8.l
; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v26.h
; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v27.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.h, 8, v66.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v8.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v9.h
@@ -20439,30 +20663,30 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:296
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:280
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:276
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:272
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:268
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:260
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:256
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:248
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:244
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:240
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:236
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:216
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:200
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:196
@@ -20470,41 +20694,41 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:180
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:176
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:168
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:156
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:136
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
@@ -20518,38 +20742,148 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -20560,10 +20894,10 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v134, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -20600,7 +20934,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v54, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
@@ -20630,13 +20964,13 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v135, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v160, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
@@ -20652,13 +20986,13 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v99, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v98, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, v23, v24
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v103, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
@@ -20670,13 +21004,13 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v80, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
@@ -20692,9 +21026,9 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
@@ -20802,7 +21136,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
@@ -20817,7 +21151,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
@@ -20860,20 +21194,20 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v147
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v146
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v145
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v134
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v132
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v129
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v128
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v119
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v117
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v114
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v135, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v112, 0xc0c0004
@@ -20905,20 +21239,20 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v103
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v101
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v98
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v96
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v85
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v84
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v80
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v70
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v68, 0xc0c0004
@@ -20950,22 +21284,22 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v67
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v66
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v65
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v55
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v54
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 3, v49
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v36, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
@@ -20973,7 +21307,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v33
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v32
@@ -42204,47 +42538,80 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB36_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v3.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v65, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v55, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v65, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v7.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v66, v66, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v54, v64, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v64, v65, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v66, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v55, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v54, 16, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v53, v54, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -42254,15 +42621,27 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v53, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
@@ -42272,13 +42651,25 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
@@ -42288,13 +42679,25 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
@@ -42304,13 +42707,25 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
@@ -42322,15 +42737,30 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
@@ -51706,8 +52136,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:376
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:372
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:368
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:364
@@ -51716,118 +52146,118 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:352
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:348
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:340
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:336
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:336
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:332
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:328
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:324
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:304
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:272
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:268
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:264
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:248
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:244
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:224
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:192
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:184
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:180
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:168
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:164
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:144
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v40, off, s32 offset:64
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v42, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v45, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v57, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:388
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v60, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v75.l, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v76.l, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v77.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v78.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.l, v23.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v89.l, v22.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v90.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v92.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v91.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v91.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v92.l, v19.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v93.l, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v94.l, v17.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v95.l, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v104.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.l, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.l, v12.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v108.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v110.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v110.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v111.l, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v120.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v121.l, v6.l
@@ -51845,103 +52275,231 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB38_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v127, v126, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v125, v124, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v123, v122, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v121, v120, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v107, v105, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v106, v104, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v107, v106, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v105, v104, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v95, v94, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v111, v109, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v110, v108, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v93, v91, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v92, v90, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v89, v79, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v88, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v111, v110, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v109, v108, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v93, v92, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v91, v90, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v89, v88, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v79, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v76, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v75, v73, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v75, v74, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v74, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v61, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v62, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v73, v72, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v61, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v59, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v57, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v56, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v45, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v44, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v57, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v47, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v45, v44, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v43, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v41, v40, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v183, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v179, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v178, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v183, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v181, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v179, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v177, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v164, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v161, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v160, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v163, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v161, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v151, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v147, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v146, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v134, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v147, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v145, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v133, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v131, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v129, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v128, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v117, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v116, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v129, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v117, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v115, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v113, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v24, 16, v23
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v26, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v102, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v99, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v98, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v101, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v87, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v84, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v81, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v80, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v83, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v81, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v71, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v26
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v25, v29, 16, v28
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v31, 16, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v67, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v66, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v67, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v55, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v54, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v54, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v48, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v39, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v34, v36, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v30, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v48, 16, v31
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v35, 16, v37
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v32, 16, v33
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v32, 16, v34
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16
@@ -51951,114 +52509,114 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
@@ -52067,8 +52625,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: .LBB38_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -52090,22 +52648,22 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v111.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v110.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v109.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v109.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v110.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v108.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v107.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v106.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v105.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v95.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v3.h, v2.h
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v105.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v106.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v104.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v92.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v91.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v90.l
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v89.l, 3
@@ -52114,26 +52672,26 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v94.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v93.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v5.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v88.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v79.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, v77.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.h, v4.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v91.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v74.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v92.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v73.l, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v72.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v63.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v61.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v4.h
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v5.h
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v79.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v88.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v7.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v78.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, v59.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v56.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v47.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v6.h
; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v7.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v76.l
@@ -52143,42 +52701,42 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v45.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.l, v6.h
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v7.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v73.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v44.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v74.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v43.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v41.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v182.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v181.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v180.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v61.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v62.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v9.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v60.l
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v13.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, v179.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v8.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v178.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v177.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.h, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v10.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v58.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, v57.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, v167.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v164.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v163.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v162.l
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v9.h, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v47.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v56.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v161.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v149.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v10.l, v9.h
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v43.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v44.l
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v12.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, v145.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v144.l
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, v135.l, 3
@@ -52187,25 +52745,25 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v40.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v183.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v18.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, v134.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, v133.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, v131.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v11.h, v12.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v12.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v181.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, v128.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v182.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, v119.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v118.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, v117.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, v116.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v14.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v177.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v178.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v14.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v176.l
; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v20.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, v113.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v13.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, v101.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.h, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v166.l
@@ -52215,43 +52773,43 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, v99.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v15.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v163.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v164.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, v97.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, v87.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, v84.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, v83.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v82.l
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.l, v14.h
; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v16.l, v15.h
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v151.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v160.l
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v17.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v150.l
; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v25.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, v81.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v16.l, v15.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, v80.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, v71.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.l, v16.h
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v17.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v148.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v147.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, v65.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v28.h, 8, v64.l
; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v17.l, v16.h
; GFX11-TRUE16-NEXT: v_and_b16 v17.l, 0xff, v17.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v145.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v146.l
; GFX11-TRUE16-NEXT: v_and_b16 v28.l, 0xff, v28.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.h, 8, v53.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_or_b16 v17.l, v17.h, v17.l
; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v18.h, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v19.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v134.l
; GFX11-TRUE16-NEXT: v_and_b16 v19.l, 0xff, v19.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v132.l
; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v28.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v18.l, v18.h, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v29.l
; GFX11-TRUE16-NEXT: v_or_b16 v18.h, v19.h, v19.l
@@ -52263,39 +52821,39 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v29.l, v29.h, v29.l
; GFX11-TRUE16-NEXT: v_or_b16 v19.l, v19.h, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v19.h, 0xff, v20.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v119.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v128.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, v38.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, v36.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v33.h, v34.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v33.l, v33.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.h, 8, v37.l
; GFX11-TRUE16-NEXT: v_or_b16 v19.h, v20.l, v19.h
; GFX11-TRUE16-NEXT: v_or_b16 v20.l, v21.l, v20.h
; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v21.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v115.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v116.l
; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v22.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v114.l
; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v35.l
; GFX11-TRUE16-NEXT: v_or_b16 v20.h, v21.l, v20.h
; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_or_b16 v21.l, v22.l, v21.h
; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v22.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v112.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, v103.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v33.l
-; GFX11-TRUE16-NEXT: v_and_b16 v33.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_and_b16 v33.l, 0xff, v33.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v21.h, v22.l, v21.h
; GFX11-TRUE16-NEXT: v_and_b16 v22.l, 0xff, v22.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v101.l
-; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v34.l, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v33.l, v31.h
-; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v32.l, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v102.l
+; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v33.h, v31.l
+; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v34.l, v31.h
+; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v32.l, v33.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v22.l, v22.h, v22.l
; GFX11-TRUE16-NEXT: v_or_b16 v22.h, v23.h, v23.l
; GFX11-TRUE16-NEXT: v_and_b16 v23.l, 0xff, v24.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v24.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v96.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v0.h
@@ -52311,7 +52869,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.h, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v25.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v83.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v84.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v3.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v4.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v4.h
@@ -52319,7 +52877,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v25.l, v24.h
; GFX11-TRUE16-NEXT: v_or_b16 v25.l, v26.l, v25.h
; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v26.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v80.l
; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v27.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v5.h
@@ -52335,7 +52893,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v8.l
; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v26.h
; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v27.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.h, 8, v66.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v8.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v9.h
@@ -56327,30 +56885,30 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:296
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:280
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:276
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:272
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:268
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:260
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:256
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:248
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:244
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:240
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:236
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:216
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:200
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:196
@@ -56358,41 +56916,41 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:180
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:176
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:168
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:156
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:136
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
@@ -56406,38 +56964,148 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -56448,10 +57116,10 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v134, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -56488,7 +57156,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v54, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
@@ -56518,13 +57186,13 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v135, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v160, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
@@ -56540,13 +57208,13 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v99, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v98, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, v23, v24
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v103, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
@@ -56558,13 +57226,13 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v80, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
@@ -56580,9 +57248,9 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
@@ -56690,7 +57358,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
@@ -56705,7 +57373,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
@@ -56748,20 +57416,20 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v147
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v146
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v145
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v134
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v132
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v129
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v128
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v119
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v117
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v114
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v135, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v112, 0xc0c0004
@@ -56793,20 +57461,20 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v103
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v101
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v98
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v96
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v85
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v84
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v80
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v70
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v68, 0xc0c0004
@@ -56838,22 +57506,22 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v67
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v66
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v65
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v55
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v54
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 3, v49
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v36, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
@@ -56861,7 +57529,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v33
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v32
@@ -76979,47 +77647,80 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB56_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v3.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v65, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v55, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v65, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v7.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v66, v66, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v54, v64, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v64, v65, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v66, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v55, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v54, 16, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v53, v54, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -77029,15 +77730,27 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v53, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
@@ -77047,13 +77760,25 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
@@ -77063,13 +77788,25 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
@@ -77079,13 +77816,25 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
@@ -77097,15 +77846,30 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
@@ -85596,8 +86360,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:376
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:372
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:368
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:364
@@ -85606,118 +86370,118 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:352
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:348
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:340
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:336
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:336
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:332
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:328
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:324
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:304
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:272
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:268
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:264
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:248
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:244
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:224
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:192
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:184
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:180
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:168
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:164
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:144
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v40, off, s32 offset:64
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v42, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v45, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v57, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:388
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v60, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v75.l, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v76.l, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v77.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v78.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.l, v23.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v89.l, v22.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v90.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v92.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v91.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v91.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v92.l, v19.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v93.l, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v94.l, v17.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v95.l, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v104.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.l, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.l, v12.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v108.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v110.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v110.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v111.l, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v120.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v121.l, v6.l
@@ -85735,103 +86499,231 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v127, v126, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v125, v124, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v123, v122, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v121, v120, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v107, v105, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v106, v104, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v107, v106, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v105, v104, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v95, v94, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v111, v109, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v110, v108, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v93, v91, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v92, v90, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v89, v79, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v88, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v111, v110, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v109, v108, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v93, v92, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v91, v90, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v89, v88, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v79, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v76, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v75, v73, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v75, v74, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v74, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v61, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v62, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v73, v72, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v61, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v59, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v57, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v56, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v45, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v44, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v57, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v47, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v45, v44, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v43, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v41, v40, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v183, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v179, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v178, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v183, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v181, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v179, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v177, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v164, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v161, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v160, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v163, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v161, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v151, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v147, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v146, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v134, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v147, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v145, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v133, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v131, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v129, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v128, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v117, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v116, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v129, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v117, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v115, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v113, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v24, 16, v23
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v26, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v102, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v99, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v98, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v101, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v87, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v84, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v81, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v80, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v83, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v81, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v71, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v26
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v25, v29, 16, v28
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v31, 16, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v67, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v66, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v67, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v55, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v54, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v54, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v48, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v39, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v34, v36, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v30, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v48, 16, v31
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v35, 16, v37
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v32, 16, v33
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v32, 16, v34
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16
@@ -85841,114 +86733,114 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
@@ -85957,8 +86849,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: .LBB58_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -85980,22 +86872,22 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v111.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v110.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v109.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v109.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v110.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v108.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v107.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v106.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v105.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v95.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v3.h, v2.h
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v105.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v106.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v104.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v92.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v91.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v90.l
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v89.l, 3
@@ -86004,26 +86896,26 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v94.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v93.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v5.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v88.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v79.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, v77.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.h, v4.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v91.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v74.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v92.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v73.l, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v72.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v63.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v61.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v4.h
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v5.h
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v79.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v88.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v7.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v78.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, v59.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v56.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v47.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v6.h
; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v7.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v76.l
@@ -86033,42 +86925,42 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v45.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.l, v6.h
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v7.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v73.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v44.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v74.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v43.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v41.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v182.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v181.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v180.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v61.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v62.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v9.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v60.l
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v13.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, v179.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v8.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v178.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v177.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.h, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v10.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v58.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, v57.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, v167.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v164.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v163.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v162.l
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v9.h, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v47.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v56.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v161.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v149.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v10.l, v9.h
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v43.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v44.l
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v12.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, v145.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v144.l
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, v135.l, 3
@@ -86077,25 +86969,25 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v40.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v183.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v18.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, v134.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, v133.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, v131.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v11.h, v12.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v12.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v181.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, v128.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v182.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, v119.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v118.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, v117.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, v116.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v14.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v177.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v178.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v14.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v176.l
; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v20.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, v113.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v13.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, v101.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.h, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v166.l
@@ -86105,43 +86997,43 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, v99.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v15.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v163.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v164.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, v97.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, v87.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, v84.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, v83.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v82.l
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.l, v14.h
; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v16.l, v15.h
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v151.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v160.l
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v17.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v150.l
; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v25.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, v81.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v16.l, v15.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, v80.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, v71.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.l, v16.h
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v17.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v148.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v147.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, v65.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v28.h, 8, v64.l
; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v17.l, v16.h
; GFX11-TRUE16-NEXT: v_and_b16 v17.l, 0xff, v17.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v145.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v146.l
; GFX11-TRUE16-NEXT: v_and_b16 v28.l, 0xff, v28.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.h, 8, v53.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_or_b16 v17.l, v17.h, v17.l
; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v18.h, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v19.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v134.l
; GFX11-TRUE16-NEXT: v_and_b16 v19.l, 0xff, v19.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v132.l
; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v28.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v18.l, v18.h, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v29.l
; GFX11-TRUE16-NEXT: v_or_b16 v18.h, v19.h, v19.l
@@ -86153,39 +87045,39 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v29.l, v29.h, v29.l
; GFX11-TRUE16-NEXT: v_or_b16 v19.l, v19.h, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v19.h, 0xff, v20.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v119.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v128.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, v38.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, v36.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v33.h, v34.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v33.l, v33.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.h, 8, v37.l
; GFX11-TRUE16-NEXT: v_or_b16 v19.h, v20.l, v19.h
; GFX11-TRUE16-NEXT: v_or_b16 v20.l, v21.l, v20.h
; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v21.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v115.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v116.l
; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v22.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v114.l
; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v35.l
; GFX11-TRUE16-NEXT: v_or_b16 v20.h, v21.l, v20.h
; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_or_b16 v21.l, v22.l, v21.h
; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v22.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v112.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, v103.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v33.l
-; GFX11-TRUE16-NEXT: v_and_b16 v33.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_and_b16 v33.l, 0xff, v33.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v21.h, v22.l, v21.h
; GFX11-TRUE16-NEXT: v_and_b16 v22.l, 0xff, v22.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v101.l
-; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v34.l, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v33.l, v31.h
-; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v32.l, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v102.l
+; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v33.h, v31.l
+; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v34.l, v31.h
+; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v32.l, v33.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v22.l, v22.h, v22.l
; GFX11-TRUE16-NEXT: v_or_b16 v22.h, v23.h, v23.l
; GFX11-TRUE16-NEXT: v_and_b16 v23.l, 0xff, v24.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v24.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v96.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v0.h
@@ -86201,7 +87093,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.h, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v25.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v83.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v84.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v3.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v4.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v4.h
@@ -86209,7 +87101,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v25.l, v24.h
; GFX11-TRUE16-NEXT: v_or_b16 v25.l, v26.l, v25.h
; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v26.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v80.l
; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v27.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v5.h
@@ -86225,7 +87117,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v8.l
; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v26.h
; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v27.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.h, 8, v66.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v8.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v9.h
@@ -90217,30 +91109,30 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:296
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:280
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:276
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:272
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:268
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:260
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:256
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:248
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:244
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:240
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:236
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:216
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:200
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:196
@@ -90248,41 +91140,41 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:180
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:176
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:168
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:156
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:136
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
@@ -90296,38 +91188,148 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -90338,10 +91340,10 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v134, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -90378,7 +91380,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v54, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
@@ -90408,13 +91410,13 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v135, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v160, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
@@ -90430,13 +91432,13 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v99, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v98, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, v23, v24
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v103, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
@@ -90448,13 +91450,13 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v80, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
@@ -90470,9 +91472,9 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
@@ -90580,7 +91582,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
@@ -90595,7 +91597,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
@@ -90638,20 +91640,20 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v147
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v146
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v145
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v134
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v132
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v129
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v128
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v119
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v117
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v114
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v135, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v112, 0xc0c0004
@@ -90683,20 +91685,20 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v103
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v101
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v98
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v96
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v85
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v84
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v80
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v70
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v68, 0xc0c0004
@@ -90728,22 +91730,22 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v67
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v66
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v65
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v55
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v54
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 3, v49
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v36, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
@@ -90751,7 +91753,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v33
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v32
@@ -108997,47 +109999,80 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB72_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v3.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v65, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v55, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v65, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v7.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v66, v66, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v54, v64, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v64, v65, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v66, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v55, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v54, 16, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v53, v54, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -109047,15 +110082,27 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v53, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
@@ -109065,13 +110112,25 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
@@ -109081,13 +110140,25 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
@@ -109097,13 +110168,25 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
@@ -109115,15 +110198,30 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
@@ -118551,8 +119649,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:376
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:372
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:368
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:364
@@ -118561,118 +119659,118 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:352
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:348
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:340
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:336
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:336
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:332
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:328
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:324
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:304
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:272
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:268
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:264
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:248
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:244
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:224
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:192
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:184
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:180
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:168
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:164
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:144
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v40, off, s32 offset:64
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v42, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v45, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v47, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v57, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:388
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v60, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v75.l, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v76.l, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v77.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v78.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.l, v23.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v89.l, v22.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v90.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v92.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v91.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v91.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v92.l, v19.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v93.l, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v94.l, v17.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v95.l, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v104.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.l, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.l, v12.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v108.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v110.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v110.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v111.l, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v120.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v121.l, v6.l
@@ -118690,103 +119788,231 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB74_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v127, v126, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v125, v124, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v123, v122, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v121, v120, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v107, v105, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v106, v104, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v107, v106, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v105, v104, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v95, v94, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v111, v109, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v110, v108, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v93, v91, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v92, v90, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v89, v79, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v88, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v111, v110, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v109, v108, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v93, v92, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v91, v90, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v89, v88, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v79, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v76, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v75, v73, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v75, v74, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v74, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v61, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v62, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v73, v72, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v61, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v59, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v57, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v56, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v45, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v44, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v57, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v47, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v45, v44, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v43, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v41, v40, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v183, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v179, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v178, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v183, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v181, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v179, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v177, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v164, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v161, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v160, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v163, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v161, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v151, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v147, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v146, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v134, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v147, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v145, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v133, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v131, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v129, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v128, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v117, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v116, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v129, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v117, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v115, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v113, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v24, 16, v23
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v26, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v102, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v99, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v98, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v101, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v87, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v84, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v81, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v80, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v83, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v81, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v71, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v26
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v25, v29, 16, v28
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v31, 16, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v67, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v66, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v67, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v55, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v54, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v54, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v48, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v39, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v34, v36, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v30, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v48, 16, v31
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v35, 16, v37
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v32, 16, v33
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v32, 16, v34
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16
@@ -118796,114 +120022,114 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
@@ -118912,8 +120138,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: .LBB74_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -118935,22 +120161,22 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v111.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v110.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v109.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v109.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v110.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v108.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v107.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v106.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v105.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v95.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v3.h, v2.h
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v105.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v106.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v104.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v92.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v91.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v90.l
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v89.l, 3
@@ -118959,26 +120185,26 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v94.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v93.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v5.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v88.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v79.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, v77.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.h, v4.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v91.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v74.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v92.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v73.l, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v72.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v63.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v61.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v4.h
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v5.h
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v79.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v88.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v7.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v78.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, v59.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v56.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v47.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v6.h
; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v7.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v76.l
@@ -118988,42 +120214,42 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v45.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.l, v6.h
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v7.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v73.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v44.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v74.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v43.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v41.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v182.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v181.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v180.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v61.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v62.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v9.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v60.l
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v13.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, v179.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v8.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v178.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v177.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.h, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v10.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v58.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, v57.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, v167.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v164.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v163.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v162.l
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v9.h, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v47.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v56.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v161.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v149.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v10.l, v9.h
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v43.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v44.l
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v12.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, v145.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v144.l
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, v135.l, 3
@@ -119032,25 +120258,25 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v40.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v183.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v18.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, v134.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, v133.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, v131.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v11.h, v12.l, v11.h
; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v12.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v181.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, v128.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v182.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, v119.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v118.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, v117.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, v116.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.h, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v14.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v177.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v178.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v14.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v176.l
; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v20.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, v113.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v13.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, v101.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.h, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v166.l
@@ -119060,43 +120286,43 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, v99.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v15.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v163.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v164.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, v97.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, v87.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, v84.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, v83.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v82.l
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.l, v14.h
; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v16.l, v15.h
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v151.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v160.l
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v17.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v150.l
; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v25.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, v81.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v16.l, v15.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, v80.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, v71.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.l, v16.h
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v17.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v148.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, v147.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, v69.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, v65.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v28.h, 8, v64.l
; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v17.l, v16.h
; GFX11-TRUE16-NEXT: v_and_b16 v17.l, 0xff, v17.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v145.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v146.l
; GFX11-TRUE16-NEXT: v_and_b16 v28.l, 0xff, v28.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v29.h, 8, v53.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v30.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_or_b16 v17.l, v17.h, v17.l
; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v18.h, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v19.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v134.l
; GFX11-TRUE16-NEXT: v_and_b16 v19.l, 0xff, v19.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v132.l
; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v28.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v18.l, v18.h, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v29.l
; GFX11-TRUE16-NEXT: v_or_b16 v18.h, v19.h, v19.l
@@ -119108,39 +120334,39 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v29.l, v29.h, v29.l
; GFX11-TRUE16-NEXT: v_or_b16 v19.l, v19.h, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v19.h, 0xff, v20.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v119.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v128.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, v38.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, v36.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v33.h, v34.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v33.l, v33.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.h, 8, v37.l
; GFX11-TRUE16-NEXT: v_or_b16 v19.h, v20.l, v19.h
; GFX11-TRUE16-NEXT: v_or_b16 v20.l, v21.l, v20.h
; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v21.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v115.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v116.l
; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v22.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v114.l
; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v35.l
; GFX11-TRUE16-NEXT: v_or_b16 v20.h, v21.l, v20.h
; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_or_b16 v21.l, v22.l, v21.h
; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v22.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v112.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, v103.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v33.l
-; GFX11-TRUE16-NEXT: v_and_b16 v33.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v34.l
+; GFX11-TRUE16-NEXT: v_and_b16 v33.l, 0xff, v33.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v21.h, v22.l, v21.h
; GFX11-TRUE16-NEXT: v_and_b16 v22.l, 0xff, v22.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v101.l
-; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v34.l, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v33.l, v31.h
-; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v32.l, v33.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v102.l
+; GFX11-TRUE16-NEXT: v_or_b16 v31.l, v33.h, v31.l
+; GFX11-TRUE16-NEXT: v_or_b16 v31.h, v34.l, v31.h
+; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v32.l, v33.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v22.l, v22.h, v22.l
; GFX11-TRUE16-NEXT: v_or_b16 v22.h, v23.h, v23.l
; GFX11-TRUE16-NEXT: v_and_b16 v23.l, 0xff, v24.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v24.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v96.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v0.h
@@ -119156,7 +120382,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.h, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v25.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v83.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v84.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v3.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v4.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v4.h
@@ -119164,7 +120390,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v25.l, v24.h
; GFX11-TRUE16-NEXT: v_or_b16 v25.l, v26.l, v25.h
; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v26.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v80.l
; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v27.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v5.h
@@ -119180,7 +120406,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v8.l
; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v26.h
; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v27.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.h, 8, v66.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v8.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v9.h
@@ -123172,30 +124398,30 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:296
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:280
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:276
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:272
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:268
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:260
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:256
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:248
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:244
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:240
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:236
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:216
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:200
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:196
@@ -123203,41 +124429,41 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:180
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:176
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:168
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:156
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:136
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
@@ -123251,38 +124477,148 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -123293,10 +124629,10 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v134, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -123333,7 +124669,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v54, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
@@ -123363,13 +124699,13 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v135, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v160, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
@@ -123385,13 +124721,13 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v99, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v98, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, v23, v24
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v103, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
@@ -123403,13 +124739,13 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v80, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
@@ -123425,9 +124761,9 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
@@ -123535,7 +124871,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
@@ -123550,7 +124886,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
@@ -123593,20 +124929,20 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v147
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v146
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v145
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v134
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v132
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v129
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v128
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v119
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v117
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v114
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v135, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v112, 0xc0c0004
@@ -123638,20 +124974,20 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v103
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v101
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v98
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v96
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v85
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v84
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v80
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v70
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v68, 0xc0c0004
@@ -123683,22 +125019,22 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v67
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v66
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v65
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v55
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v54
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 3, v49
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v36, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
@@ -123706,7 +125042,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v33
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v32
@@ -143522,169 +144858,164 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:376
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:372
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:372
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:368
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:364
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:364
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:360
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:356
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:356
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:352
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:348
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:348
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:344
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:340
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:336
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:332
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:332
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:328
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:324
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:188
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:388
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v28.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v163.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v75.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v72.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v77.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v56.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v0.l
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(62)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.l, 8, v69.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.h, 8, v69.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.l, 8, v68.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.l, 8, v66.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v65.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(27)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.h, 8, v52.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v53.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v54.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v55.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v64.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v53.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v54.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v55.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v65.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v71.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v71.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v71.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.l, 8, v70.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.h, 8, v31.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.h, 8, v31.l
@@ -143694,241 +145025,321 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB88_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v130, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v165, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v45, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v72, v167, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v73, v40, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v57, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v60, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v37.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v160, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v44, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v48.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v77, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v177, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v75, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v40, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v58, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v41, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v49.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v39.h
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v55.l
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v50.h
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v49.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v65.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v66.h
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v50.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v65.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v68.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v58, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v149, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.h
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v78, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v146, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v55.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.h
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v64.h
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v79, v76, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v119, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v129, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v64.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v64.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v83, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v144, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v65.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v65.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v131, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v119, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v96, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v118, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v114, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v99, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v115, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v130, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v103, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v179, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v117, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v133, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v74, v56, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v44, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v128, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v146, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v59, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v181, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v100, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v60, v43, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v161, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v39.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v57, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v87, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v61, v182, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v43, v167, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v48.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v113, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v134, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v45, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v180, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v101, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v147, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v46, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.h
-; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.l
+; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v32.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v164, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.h
-; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v38.h
-; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v178, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v62, v47, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v63, v47, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v29.h, v69.l
-; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v39.h
-; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v33.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v39.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v30.l, v71.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v59, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v135, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v68.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v67.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v67.h
+; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v66.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v151, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v69.h
; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.l, v70.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v74, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v160, v103, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.h
; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v31.l, v71.l
; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v31.h, v70.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v78, v75, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v161, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v52.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v52.h
-; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v66.l
-; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v66.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v55.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v64.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
@@ -143939,174 +145350,172 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB88_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v78.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v39.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v161.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v74.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v43.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v134.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v71.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v71.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v70.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v46.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v103.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v69.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v72.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v69.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v70.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v61.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v144.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v59.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v135.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.l, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v67.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v183.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v99.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v66.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v180.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v101.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v44.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.l, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v128.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v55.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v151.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v66.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v176.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v167.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v179.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v116.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v133.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v161.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v96.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v130.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v145.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v100.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v85.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v118.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v149.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v83.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v132.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v129.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v148.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v114.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v144.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v145.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v115.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v113.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v103.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v119.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v102.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v148.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v112.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v99.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v129.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v85.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v146.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v118.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v112.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v149.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v131.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v117.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v86.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v79.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v65.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v65.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v76.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
@@ -144114,122 +145523,122 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v78.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v73.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v62.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.l, 3
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v63.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v58.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v56.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v179.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v58.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v41.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v52.l, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v52.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v60.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v166.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v44.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v63.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v41.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v164.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v47.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v61.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v40.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v181.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v182.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v166.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v163.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v57.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v178.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v164.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v178.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v181.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v60.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v162.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v43.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v177.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v75.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v73.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v46.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v132.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v177.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v135.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v40.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v128.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v176.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v59.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v160.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v45.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v130.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v117.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v72.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v74.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v114.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v180.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v183.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v167.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v87.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v165.l
; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v100.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v56.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v32.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v33.l, v1.h
@@ -148560,130 +149969,240 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:260
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB89_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v179
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s12, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s8, 8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v166
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
@@ -148693,373 +150212,373 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s62, s58, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s61, s47, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s43, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s14, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v178
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s72, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s73, s57, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s60, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s45, s13, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v177
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s5, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s6, v8
; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s15, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s59, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s46, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s44, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v181
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v151
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v118
; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s41, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s10, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s7, 8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v176
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v119
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v149
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v161
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v148, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v146, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v165, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v135, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v145, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v128, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v162, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v116, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v160, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v113, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v150, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v102, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v147, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v134, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v99, v70, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v49
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v131, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v129
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v86
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v81
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v50
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v67
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v117, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v65
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v103
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v37
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v51
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v33
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v64
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v38
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v98, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v55
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v71
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v36
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v53
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v85, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v54, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB89_3
; GFX11-TRUE16-NEXT: .LBB89_2: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v166
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v54
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v71
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v85
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v133, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v51
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v179
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v162
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v129, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v87
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v64
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v102, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v149
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v67
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v132, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v167
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v144
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v103
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v69
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v117
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v101, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v81
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v87, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v129
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v135
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v147
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v113
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v150
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v130
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v128
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v162
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v103
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v66
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v164
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v146
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v97
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v165
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v148
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v50
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v149
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v151
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v114
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v68
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s15, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s40, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s41, s11, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s45, s13, v1
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s60, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s12, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s44, s9, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s42, s14, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s5, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s7, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s74, s72, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s59, s46, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, s40, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, s26, s27, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s56, s43, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s61, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v83, s26, s27, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v69, s2, s3, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v70, s18, s19, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v85, s2, s3, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v86, s18, s19, v1
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v71, s16, s17, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s0, s1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v54
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v67
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v69
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v70
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v87, s16, s17, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v96, s0, s1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v80, 0x300, v80
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v83, 0x300, v83
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v86, 0x300, v86
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v97, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v80
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v85.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v87.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v101.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.h, v132.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v102.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v87
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v96
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v85.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v86.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v97.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v84.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v80.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v82.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v81.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v71.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v70.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v69.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v68.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v67.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v65.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v64.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v50.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v49.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v39.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
; GFX11-TRUE16-NEXT: .LBB89_3: ; %end
; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
@@ -154805,234 +156324,242 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:252
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:248
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:244
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:240
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:236
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:232
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:228
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:224
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:220
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:216
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:212
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:208
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:204
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:200
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:196
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:192
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:188
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:184
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:180
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:176
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:172
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:168
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:164
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:160
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:156
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:152
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:148
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:144
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:140
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:136
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:132
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:112
-; GFX11-TRUE16-NEXT: s_clause 0x18 ; 100-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:128
+; GFX11-TRUE16-NEXT: s_clause 0x1c ; 116-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:108
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:104
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:100
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:96
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:92
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:88
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:84
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:80
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:76
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:72
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:68
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:64
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:60
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:56
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:52
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:48
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:44
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:40
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:36
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:32
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:28
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:24
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:20
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:16
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_b32 v71, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_b32 v70, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr141_lo16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v113, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_b32 v112, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr156_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr155_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr154_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr152_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr141_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr140_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr139_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr138_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr137_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr138_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr143_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr142_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr137_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr152_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr143_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr140_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
@@ -155041,136 +156568,136 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB90_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[99:100], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[116:117], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[100:101], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[117:118], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[130:131], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[133:134], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[101:102], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v104, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v136, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v138, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v139, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v141, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[146:147], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[84:85], 24, v[27:28]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[147:148], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[85:86], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v105, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v127, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v137, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v139, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v141, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v152, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v154, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v155, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v156, 8, v1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v71
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v71
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 24, v113
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 8, v113
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v70
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v106, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v123, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[134:135], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[82:83], 24, v[70:71]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[97:98], 24, v[25:26]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[102:103], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[118:119], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[131:132], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v112
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[98:99], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[102:103], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[116:117], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[130:131], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[134:135], 24, v[7:8]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[148:149], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[112:113]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[70:71], 24, v[29:30]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[82:83], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[114:115], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[128:129], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.h, v1.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.h, v1.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.h, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v2.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v4.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v6.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.h, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v7.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.h, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.h, v8.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v94.h, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.h, v9.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.h, v10.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v127.h, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.h, v11.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.h, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.h, v12.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v142.h, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.h, v13.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v137.h, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.h, v14.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v152.h, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v79.h, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.h, v6.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.h, v7.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.h, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v123.h, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.h, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v104.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.h, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v138.h, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.h, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v121.h, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.h, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v143.h, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.h, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v136.h, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.h, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v153.h, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.h, v15.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v143.h, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v142.h, v16.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.h, v16.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.h, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v150.h, v17.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v17.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.h, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.h, v18.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v148.h, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.h, v19.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.h, v19.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.h, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v151.h, v20.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.h, v20.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v150.h, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.h, v21.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.h, v21.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v149.h, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v161.h, v22.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v22.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.h, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.h, v23.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.h, v23.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v151.h, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v163.h, v24.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.h, v24.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.h, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v25.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.h, v25.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v161.h, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.h, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.h, v26.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.h, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.h, v27.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v163.h, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.h, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.h, v28.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.h, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.h, v29.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.h, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.h, v30.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.h, v70.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.h, v71.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v112.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.h, v112.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v113.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.h, v113.h
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
@@ -155186,7 +156713,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113
; GFX11-TRUE16-NEXT: .LBB90_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB90_4
@@ -155222,9 +156749,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v20
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v32
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v146, v37, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v32
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v150, v37, v49, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v33
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
@@ -155242,8 +156769,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.l, v146.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v147, v33, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.l, v150.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v151, v33, v35, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v36, 0x7fff
@@ -155252,16 +156779,17 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v17, v34, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v34.l, v147.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 8, v31
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v34.l, v151.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[128:129], 24, v[31:32]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v31
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v148, v17, v33, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v160, v17, v33, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v20, v35 :: v_dual_and_b32 v20, 0xffff0000, v21
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 24, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v123, 8, v34
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 24, v34
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 8, v34
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_lshlrev_b32 v22, 16, v22
@@ -155272,7 +156800,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v149, v19, v35 :: v_dual_lshlrev_b32 v22, 16, v24
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v161, v19, v35 :: v_dual_lshlrev_b32 v22, 16, v24
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
@@ -155291,10 +156819,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v36.l, v149.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v36.l, v161.h
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v150, v17, v24 :: v_dual_lshlrev_b32 v21, 16, v23
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v162, v17, v24 :: v_dual_lshlrev_b32 v21, 16, v23
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v23
@@ -155308,9 +156836,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v106, 24, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 8, v36
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v151, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 24, v36
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v36
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v163, v19, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
@@ -155324,10 +156852,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v38.l, v151.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v33.l, v148.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v38.l, v163.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v33.l, v160.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v160, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v164, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
@@ -155341,9 +156869,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 8, v33
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v161, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[114:115], 24, v[33:34]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 8, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v165, v19, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
@@ -155356,10 +156885,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.l, v150.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.l, v161.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.l, v162.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.l, v165.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v162, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v167, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
@@ -155372,10 +156901,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 24, v49
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v49
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 8, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v163, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v167.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v49
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v49
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v166, v19, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
@@ -155388,10 +156917,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v51.l, v163.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 24, v38
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v164, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 24, v38
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v38
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 8, v35
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v176, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
@@ -155404,14 +156933,12 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v71
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 24, v51
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v51
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v165, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v177, v19, v23 :: v_dual_lshlrev_b32 v22, 16, v113
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v71
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v113
; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v53, v17, v24
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
@@ -155420,14 +156947,14 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v70
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v37.l, v160.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v53.l, v165.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v166, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v112
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v53.l, v177.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v178, v17, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v70
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v112
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_cndmask_b32 v52, v19, v24
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
@@ -155436,10 +156963,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v53
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v53
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 8, v37
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v167, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v37.l, v164.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v53
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v53
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v179, v19, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
@@ -155452,10 +156979,11 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v55.l, v167.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v55.l, v179.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v37
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v176, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v180, v17, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
@@ -155468,11 +156996,11 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v55
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v55
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 24, v55
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 8, v55
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v20, 16, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v177, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v41, v19, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -155485,10 +157013,11 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v65.l, v177.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v41.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[82:83], 24, v[48:49]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 8, v48
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v178, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v46, v17, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
@@ -155503,48 +157032,48 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v162.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v138, 24, v65
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v179, v2, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v154, 24, v65
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v155, 8, v65
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v47, v2, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v17, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v67, v1, v20
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v69, v1, v20
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v17, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v67.l, v179.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v51.l, v166.h
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v50.l, v164.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 24, v67
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v180, v1, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v50.l, v176.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v47.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v61, v1, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v2, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v2, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 8, v67
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v61.h
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v139, 8, v65
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v50
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 8, v48
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v181, v2, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[84:85], 24, v[50:51]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[85:86], 24, v[37:38]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[35:36]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v2, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v69, v1, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v81, v1, v18, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
@@ -155552,28 +157081,28 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v69.l, v181.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v182, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 24, v69
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v79, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 24, v69
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v1, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v141, 8, v69
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v80, v1, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v2, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v68.l, v182.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v79.h
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v88, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v81, v1, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v97, v1, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
@@ -155582,30 +157111,29 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v52.l, v166.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v44.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v80, v1, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v52.l, v178.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v88.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v96, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v106, v4, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v62.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v63, v1, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v54.l, v180.h
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v104, v1, v4 :: v_dual_lshlrev_b32 v1, 16, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v85, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v101, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
@@ -155613,41 +157141,41 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v13
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v63.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v54.l, v176.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[130:131], 24, v[68:69]
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v84, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v104.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v106.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[54:55]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v100, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[52:53]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[97:98], 24, v[48:49]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[134:135], 24, v[96:97]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[70:71], 24, v[52:53]
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v94, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v123, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v94.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v105, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v123.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v121, v1, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[116:117], 24, v[84:85]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[130:131], 24, v[100:101]
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v115, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v119, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v105.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[117:118], 24, v[80:81]
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v114, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v121.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v105, 24, v101
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v118, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v4 :: v_dual_add_f32 v3, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
@@ -155656,8 +157184,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v64.l, v178.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v127, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v46.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v138, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -155665,19 +157193,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v129, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v133, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v137, v6, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v136, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v137.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v128, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v62.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v132, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v16
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
@@ -155685,11 +157213,11 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v66.l, v180.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v127.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v136.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v118.l, v138.h
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v142, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v143, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
@@ -155698,135 +157226,202 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v142.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v143, v2, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v143.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v142, v2, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[99:100], 24, v[128:129]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[100:101], 24, v[50:51]
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v152, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[146:147], 24, v[80:81]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[147:148], 24, v[68:69]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v153, v7, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v10, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[133:134], 24, v[66:67]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[101:102], 24, v[37:38]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[114:115]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[102:103], 24, v[132:133]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[116:117], 24, v[118:119]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[148:149], 24, v[64:65]
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v145, v4, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v143.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[134:135], 24, v[64:65]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[82:83], 24, v[54:55]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[102:103], 24, v[35:36]
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v142.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 24, v133
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v133
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 8, v132
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v144, v2, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.l, v152.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[118:119], 24, v[33:34]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[131:132], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 24, v145
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 8, v145
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[144:145]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v144
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 24, v129
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 8, v129
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v128
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 24, v115
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 8, v115
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v114
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 24, v85
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 8, v85
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v84
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 24, v81
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v81
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v104, 8, v80
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 8, v69
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v68
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v136, 8, v66
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v141, 8, v64
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v54
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v52
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.l, v153.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 24, v145
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v145
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 24, v119
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 8, v119
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[98:99], 24, v[144:145]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v144
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v118
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 8, v101
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 8, v100
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 24, v97
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 8, v97
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 8, v96
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v127, 24, v81
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v137, 8, v81
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v139, 8, v80
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v152, 8, v68
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v156, 8, v64
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v54
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v52
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 24, v51
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v51
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v50
; GFX11-TRUE16-NEXT: .LBB90_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v1.l, v178.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v46.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v64.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v3.l, v177.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v41.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v65.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v5.l, v180.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v141, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v139, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v138, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v67.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v7.l, v182.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr156_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr155_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr154_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v61.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v156, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v155, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v154, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr152_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v69.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v79.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v68.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v80.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v5, v136, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v66.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v5.l, v179.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v121, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v120, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v122, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v9.l, v181.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v69.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v81.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v5, v152, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v68.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v47.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr141_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr140_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr139_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v62.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v140, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v139, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v141, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v81.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr137_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v97.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v9, v111, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v10, v109, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v62.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v80.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v44.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v84.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v9, v137, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v10, v127, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v106.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v96.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v88.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v100.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v8, v104, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v9, v117, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v10, v95, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v11, v93, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v94.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v63.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v8, v125, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v9, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v10, v124, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v11, v122, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v123.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v104.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v114.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v118.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v11, v90, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v12, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v88, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v85.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v127.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v105.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v115.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v78, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v76, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v11, v109, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v12, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v107, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v101.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v13.l, v138.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v121.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v119.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v105, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v94, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v10, 16, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v5.l, v142.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v5.l, v143.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v6.l, v128.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v7.l, v137.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v8.l, v129.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v9.l, v152.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v6.l, v132.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v7.l, v136.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v8.l, v133.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v9.l, v153.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v10.l, v144.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v11.l, v143.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v11.l, v142.h
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v12.l, v145.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v13.l, v146.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v13.l, v150.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v31.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v74, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v59, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v99, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v140, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v35.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v92, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v90, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v78, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v76, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v74, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v72, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v59, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v57, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v126, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v128, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v16, 16, v15
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
@@ -155835,74 +157430,133 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v39.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v32.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v12.l, v148.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v12.l, v160.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v33.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v14.l, v147.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v14.l, v151.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v34.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v16.l, v150.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v35.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v18.l, v149.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v16.l, v162.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v18.l, v161.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v36.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v126, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v125, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v124, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v123, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v110, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v108, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v102, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v107, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v106, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v48.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v120, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v111, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v110, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v108, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v95, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v93, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v91, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v89, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v17, 16, v16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v19, 16, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v15.l, v160.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v15.l, v164.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v37.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v17.l, v151.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v17.l, v163.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v38.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v19.l, v162.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v48.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v21.l, v161.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v19.l, v167.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v21.l, v165.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v49.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v23.l, v164.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v23.l, v176.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v50.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v92, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v91, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v89, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v79, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v77, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v53.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v77, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v75, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v73, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v63, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v58, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v84, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v18, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v20, 16, v19
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v22, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v20.l, v163.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v20.l, v166.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v51.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v24, 16, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v22.l, v166.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v22.l, v178.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v52.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v24.l, v165.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v53.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v26.l, v176.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v24.l, v177.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v26.l, v180.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v54.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.l, v167.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.l, v179.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v55.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v61, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v40, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v45, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v44, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v43, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v40, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v25, 16, v24
@@ -155916,64 +157570,68 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112
; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:136
-; GFX11-TRUE16-NEXT: s_clause 0x18 ; 100-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:188
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:136
+; GFX11-TRUE16-NEXT: s_clause 0x1c ; 116-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:252
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -170180,169 +171838,164 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:376
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:372
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:372
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:368
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:364
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:364
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:360
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:356
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:356
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:352
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:348
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:348
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:344
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:340
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:336
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:332
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:332
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:328
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:324
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:188
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:388
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v28.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v163.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v75.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v72.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v77.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v56.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v0.l
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(62)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.l, 8, v69.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.h, 8, v69.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.l, 8, v68.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.l, 8, v66.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v65.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(27)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.h, 8, v52.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v53.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v54.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v55.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v64.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v53.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v54.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v55.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v65.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v71.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v71.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v71.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.l, 8, v70.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.h, 8, v31.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.h, 8, v31.l
@@ -170352,241 +172005,321 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB92_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v130, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v165, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v45, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v72, v167, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v73, v40, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v57, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v60, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v37.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v160, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v44, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v48.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v77, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v177, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v75, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v40, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v58, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v41, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v49.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v39.h
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v55.l
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v50.h
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v49.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v65.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v66.h
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v50.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v65.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v68.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v58, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v149, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.h
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v78, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v146, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v55.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.h
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v64.h
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v79, v76, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v119, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v129, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v64.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v64.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v83, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v144, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v65.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v65.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v131, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v119, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v96, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v118, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v114, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v99, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v115, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v130, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v103, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v179, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v117, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v133, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v74, v56, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v44, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v128, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v146, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v59, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v181, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v100, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v60, v43, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v161, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v39.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v57, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v87, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v61, v182, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v43, v167, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v48.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v113, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v134, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v45, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v180, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v101, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v147, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v46, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.h
-; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.l
+; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v32.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v164, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.h
-; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v38.h
-; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v178, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v62, v47, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v63, v47, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v29.h, v69.l
-; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v39.h
-; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v33.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v39.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v30.l, v71.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v59, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v135, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v68.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v67.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v67.h
+; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v66.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v151, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v69.h
; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.l, v70.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v74, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v160, v103, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.h
; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v31.l, v71.l
; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v31.h, v70.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v78, v75, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v161, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v52.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v52.h
-; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v66.l
-; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v66.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v55.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v64.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
@@ -170597,174 +172330,172 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB92_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v78.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v39.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v161.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v74.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v43.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v134.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v71.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v71.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v70.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v46.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v103.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v69.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v72.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v69.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v70.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v61.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v144.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v59.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v135.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.l, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v67.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v183.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v99.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v66.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v180.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v101.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v44.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.l, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v128.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v55.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v151.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v66.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v176.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v167.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v179.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v116.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v133.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v161.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v96.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v130.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v145.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v100.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v85.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v118.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v149.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v83.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v132.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v129.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v148.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v114.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v144.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v145.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v115.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v113.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v103.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v119.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v102.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v148.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v112.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v99.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v129.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v85.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v146.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v118.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v112.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v149.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v131.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v117.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v86.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v79.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v65.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v65.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v76.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
@@ -170772,122 +172503,122 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v78.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v73.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v62.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.l, 3
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v63.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v58.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v56.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v179.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v58.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v41.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v52.l, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v52.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v60.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v166.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v44.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v63.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v41.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v164.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v47.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v61.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v40.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v181.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v182.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v166.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v163.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v57.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v178.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v164.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v178.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v181.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v60.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v162.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v43.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v177.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v75.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v73.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v46.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v132.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v177.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v135.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v40.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v128.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v176.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v59.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v160.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v45.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v130.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v117.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v72.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v74.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v114.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v180.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v183.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v167.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v87.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v165.l
; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v100.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v56.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v32.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v33.l, v1.h
@@ -175362,130 +177093,240 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:260
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB93_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v179
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s12, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s8, 8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v166
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
@@ -175495,373 +177336,373 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s62, s58, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s61, s47, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s43, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s14, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v178
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s72, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s73, s57, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s60, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s45, s13, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v177
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s5, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s6, v8
; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s15, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s59, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s46, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s44, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v181
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v151
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v118
; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s41, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s10, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s7, 8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v176
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v119
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v149
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v161
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v148, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v146, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v165, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v135, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v145, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v128, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v162, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v116, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v160, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v113, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v150, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v102, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v147, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v134, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v99, v70, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v49
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v131, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v129
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v86
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v81
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v50
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v67
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v117, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v65
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v103
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v37
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v51
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v33
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v64
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v38
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v98, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v55
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v71
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v36
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v53
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v85, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v54, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB93_3
; GFX11-TRUE16-NEXT: .LBB93_2: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v166
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v54
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v71
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v85
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v133, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v51
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v179
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v162
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v129, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v87
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v64
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v102, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v149
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v67
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v132, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v167
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v144
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v103
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v69
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v117
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v101, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v81
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v87, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v129
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v135
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v147
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v113
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v150
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v130
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v128
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v162
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v103
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v66
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v164
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v146
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v97
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v165
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v148
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v50
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v149
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v151
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v114
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v68
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s15, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s40, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s41, s11, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s45, s13, v1
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s60, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s12, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s44, s9, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s42, s14, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s5, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s7, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s74, s72, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s59, s46, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, s40, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, s26, s27, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s56, s43, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s61, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v83, s26, s27, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v69, s2, s3, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v70, s18, s19, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v85, s2, s3, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v86, s18, s19, v1
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v71, s16, s17, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s0, s1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v54
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v67
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v69
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v70
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v87, s16, s17, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v96, s0, s1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v80, 0x300, v80
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v83, 0x300, v83
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v86, 0x300, v86
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v97, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v80
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v85.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v87.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v101.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.h, v132.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v102.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v87
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v96
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v85.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v86.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v97.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v84.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v80.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v82.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v81.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v71.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v70.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v69.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v68.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v67.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v65.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v64.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v50.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v49.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v39.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
; GFX11-TRUE16-NEXT: .LBB93_3: ; %end
; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
@@ -180336,69 +182177,69 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -180409,69 +182250,69 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[70:71], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[7:8]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v17
; GFX11-TRUE16-NEXT: .LBB94_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB94_4
@@ -180480,161 +182321,206 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[70:71], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v17
; GFX11-TRUE16-NEXT: .LBB94_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v1.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v2.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v4.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v50, v164, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v53, v53, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v53, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v6.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v7.h
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v55, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v8.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v50, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v53, v53, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v53, 16, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v55, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v50, v117, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v51, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v54, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v67, v69, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v4.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v51, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v5.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v54, 16, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v6.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v67, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v7.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v8.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v68, v68, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v54, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v66, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v51, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v66, v67, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v68, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v54, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v65, 16, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v11.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v66, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v54, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v52, v65, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v51, 16, v9
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v51, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v113, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v102, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v54, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.h
@@ -180643,14 +182529,26 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v20.h
@@ -180659,14 +182557,26 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v24.h
@@ -180675,13 +182585,25 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v114, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
@@ -180693,16 +182615,31 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v99, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v24, 16, v26
@@ -191029,169 +192966,164 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:392
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:384
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:380
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v75, off, s32 offset:376
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:372
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:380
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:376
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:372
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:368
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:364
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:364
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v70, off, s32 offset:360
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:356
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:356
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:352
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:348
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v46, off, s32 offset:344
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v74, off, s32 offset:340
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:348
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:344
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:340
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:336
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:332
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:332
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v69, off, s32 offset:328
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:324
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v61, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v72, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:316
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v67, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v183, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v59, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:260
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v44, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v43, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:188
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:132
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v68, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:388
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v65, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v66, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v71, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v76, off, s32 offset:88
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v79, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v73, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v77, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v62, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v78, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v56, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v63, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v58, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v41, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v28.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v163.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v75.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v72.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v77.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v56.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v0.l
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(62)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.l, 8, v69.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v69.h, 8, v69.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.l, 8, v68.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.l, 8, v66.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(33)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v65.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.h, 8, v67.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v67.l, 8, v67.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v68.h, 8, v68.h
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(27)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v52.h, 8, v52.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v53.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v54.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v55.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.h, 8, v55.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v64.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.h, 8, v53.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.h, 8, v54.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v53.l, 8, v55.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v55.l, 8, v64.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v54.l, 8, v65.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v66.h, 8, v66.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.l, 8, v71.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v64.h, 8, v71.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.l, 8, v71.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v65.h, 8, v71.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.l, 8, v70.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v70.h, 8, v31.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v71.h, 8, v31.l
@@ -191201,241 +193133,321 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v130, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v165, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v45, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v72, v167, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v73, v40, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v57, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v60, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v37.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v160, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v44, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v48.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v77, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v177, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v75, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v51.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v40, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v58, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v41, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v53.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v49.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v39.h
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v55.l
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v50.h
-; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v49.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v65.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.h
+; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v13.h, v66.h
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v51.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v50.l
-; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v65.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v63, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v98, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.h, v68.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v58, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v149, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v77, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v54.h
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v53.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v78, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v146, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v55.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.h
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v64.h
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v54.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v79, v76, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v119, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v129, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v64.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v64.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v83, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v144, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v65.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v65.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v131, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v119, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v96, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v149, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v118, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v114, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v99, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v163, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v115, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v130, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v103, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v179, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v117, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v133, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v74, v56, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v148, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v44, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v128, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v25.l, 0xff, v34.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v146, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v59, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v181, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v100, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v27.h, 0xff, v34.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v60, v43, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v161, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v39.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v57, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v87, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v29.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v61, v182, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v43, v167, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v48.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v113, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v134, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v30.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v45, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v180, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v101, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v147, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v46, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.h
-; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v25.l, v67.l
+; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_and_b16 v27.l, 0xff, v32.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v164, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.h
-; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v38.h
-; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v178, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v27.h, v68.l
+; GFX11-TRUE16-NEXT: v_and_b16 v28.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT: v_and_b16 v29.l, 0xff, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v62, v47, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v63, v47, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v29.h, v69.l
-; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v39.h
-; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.l, 0xff, v36.l
+; GFX11-TRUE16-NEXT: v_and_b16 v31.h, 0xff, v33.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v37.l
-; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.h
-; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v39.l
+; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v32.l
; GFX11-TRUE16-NEXT: v_or_b16 v32.l, v30.l, v71.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v59, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v135, v99, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v68.l
-; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v67.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v72, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v26.l, v26.h, v67.h
+; GFX11-TRUE16-NEXT: v_or_b16 v26.h, v27.l, v66.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v151, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: v_or_b16 v28.l, v28.h, v69.h
; GFX11-TRUE16-NEXT: v_or_b16 v28.h, v29.l, v70.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v74, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v160, v103, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.h
; GFX11-TRUE16-NEXT: v_or_b16 v30.l, v31.l, v71.l
; GFX11-TRUE16-NEXT: v_or_b16 v30.h, v31.h, v70.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v78, v75, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v161, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v52.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v52.h
-; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v66.l
-; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v66.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.l, v24.l, v55.h
+; GFX11-TRUE16-NEXT: v_or_b16 v24.h, v24.h, v64.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
@@ -191446,174 +193458,172 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v78.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v48.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v39.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v75.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v161.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v36.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v74.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v43.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v160.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v134.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v71.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v71.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v31.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v70.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v46.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v103.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v36.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v30.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v69.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v72.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v151.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v29.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v69.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v70.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v61.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v144.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v35.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v28.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v59.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v135.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.l, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v68.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v67.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v183.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v99.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v27.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v66.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.h, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v26.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v67.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v180.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v101.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v25.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v44.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.l, v0.h
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v128.l, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v55.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v151.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v66.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v176.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v24.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v167.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v179.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v116.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v133.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v161.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v23.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v150.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v96.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v134.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v163.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v130.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v145.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v100.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v131.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v85.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v118.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v149.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v83.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v132.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v22.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v129.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v148.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v114.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v21.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v144.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v145.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v115.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v113.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v116.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v103.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v119.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v102.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v20.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v148.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v86.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v112.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v99.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v129.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v115.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v19.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v85.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v146.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v118.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v18.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v112.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v82.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v149.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v83.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v131.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v117.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v86.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v17.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v50.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v68.h, v1.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v79.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v64.h, v1.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.h, 3
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v65.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v65.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v76.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
@@ -191621,122 +193631,122 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v65.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v66.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v78.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v64.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v48.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v49.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v73.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v62.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v54.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v38.l, 3
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v55.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v54.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v63.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v58.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v37.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v53.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v56.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v179.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v53.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v58.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v41.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v52.l, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v52.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v60.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v166.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v44.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v62.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v63.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v41.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v164.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v47.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v57.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v61.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v40.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v181.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v182.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v166.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v45.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v163.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v57.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v178.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v164.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v42.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v178.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v181.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v60.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v133.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v162.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v43.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v177.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v75.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v165.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v73.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v147.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v46.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v132.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v177.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v135.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v40.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v128.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v176.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v146.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v59.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v160.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v113.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v77.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v45.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v130.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v117.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v72.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v32.h, v74.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v114.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v180.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v32.l, 8, v183.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v97.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.l, 8, v167.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v87.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v33.h, 8, v165.l
; GFX11-TRUE16-NEXT: v_and_b16 v32.h, 0xff, v32.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v100.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v34.l, 8, v56.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v32.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v33.l, v1.h
@@ -196211,130 +198221,240 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:260
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB97_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v179
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s12, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s8, 8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v166
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
@@ -196344,373 +198464,373 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s62, s58, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s61, s47, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s43, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s14, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v178
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s72, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s73, s57, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s60, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s45, s13, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v177
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s5, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s6, v8
; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s15, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s59, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s46, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s44, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v181
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v151
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v118
; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s41, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s10, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s7, 8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v176
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v119
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v149
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v161
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v148, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v146, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v165, v144, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v135, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v145, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v128, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v162, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v116, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v160, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v113, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v150, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v102, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v147, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v134, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v99, v70, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v49
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v131, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v129
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v86
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v81
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v50
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v67
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v117, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v65
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v103
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v37
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v51
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v33
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v64
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v38
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v98, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v55
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v71
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v36
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v53
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v85, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v54, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB97_3
; GFX11-TRUE16-NEXT: .LBB97_2: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v166
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v54
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v71
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v85
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v133, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v51
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v179
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v162
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v129, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v87
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v64
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v102, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v149
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v67
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v132, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v167
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v144
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v103
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v69
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v117
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v101, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v81
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v87, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v129
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v135
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v147
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v113
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v150
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v130
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v128
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v162
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v103
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v66
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v164
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v146
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v97
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v165
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v148
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v50
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v149
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v151
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v114
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v68
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s15, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s40, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s41, s11, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s45, s13, v1
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s60, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s12, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s44, s9, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s42, s14, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s5, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s7, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s74, s72, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s59, s46, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, s40, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, s26, s27, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s56, s43, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s61, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v83, s26, s27, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v69, s2, s3, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v70, s18, s19, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v85, s2, s3, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v86, s18, s19, v1
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v71, s16, s17, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s0, s1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v54
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v67
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v69
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v70
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v87, s16, s17, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v96, s0, s1, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v80, 0x300, v80
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v83, 0x300, v83
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v86, 0x300, v86
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v97, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v80
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v85.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v87.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v101.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.h, v132.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v102.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v87
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v96
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v85.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v86.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v97.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v84.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v80.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v82.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v81.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v71.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v70.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v69.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v68.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v67.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v65.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v64.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v50.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v49.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v39.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
; GFX11-TRUE16-NEXT: .LBB97_3: ; %end
; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
@@ -201304,69 +203424,69 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -201377,69 +203497,69 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[70:71], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[7:8]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v17
; GFX11-TRUE16-NEXT: .LBB98_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB98_4
@@ -201448,161 +203568,206 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_add_u16 v31, v31, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[70:71], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v17
; GFX11-TRUE16-NEXT: .LBB98_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v1.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v2.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v4.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v50, v164, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v53, v53, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v53, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v6.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v7.h
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v55, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v8.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v50, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v53, v53, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v53, 16, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v55, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v50, v117, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v51, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v54, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v67, v69, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v4.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v51, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v5.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v54, 16, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v6.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v67, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v7.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v8.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v68, v68, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v54, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v66, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v51, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v66, v67, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v68, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v54, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v65, 16, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v11.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v66, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v54, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v52, v65, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v51, 16, v9
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v51, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v113, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v102, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v54, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.h
@@ -201611,14 +203776,26 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v20.h
@@ -201627,14 +203804,26 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v24.h
@@ -201643,13 +203832,25 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v114, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
@@ -201661,16 +203862,31 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v99, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v24, 16, v26
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 7e231f48de12a..5c3ffbdedade4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -4292,13 +4292,29 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB26_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -8819,13 +8835,29 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -12931,13 +12963,29 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB70_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -16681,13 +16729,29 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB86_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -20200,13 +20264,29 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB98_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -23196,13 +23276,29 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB106_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -25501,13 +25597,29 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB110_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
index c09389ef700ac..e95b492ee9454 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
@@ -457,14 +457,28 @@ define <10 x i16> @bitcast_v5i32_to_v10i16(<5 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB4_4
+; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB4_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB4_2
+; VI-NEXT: .LBB4_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -474,14 +488,28 @@ define <10 x i16> @bitcast_v5i32_to_v10i16(<5 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB4_4
+; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB4_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB4_2
+; GFX9-NEXT: .LBB4_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -491,15 +519,28 @@ define <10 x i16> @bitcast_v5i32_to_v10i16(<5 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB4_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB4_4
+; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB4_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB4_2
+; GFX11-NEXT: .LBB4_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -586,6 +627,9 @@ define inreg <10 x i16> @bitcast_v5i32_to_v10i16_scalar(<5 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -609,6 +653,9 @@ define inreg <10 x i16> @bitcast_v5i32_to_v10i16_scalar(<5 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -634,6 +681,9 @@ define inreg <10 x i16> @bitcast_v5i32_to_v10i16_scalar(<5 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1047,14 +1097,28 @@ define <10 x half> @bitcast_v5i32_to_v10f16(<5 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB8_4
+; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB8_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB8_2
+; VI-NEXT: .LBB8_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1064,14 +1128,28 @@ define <10 x half> @bitcast_v5i32_to_v10f16(<5 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB8_4
+; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB8_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB8_2
+; GFX9-NEXT: .LBB8_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1081,15 +1159,28 @@ define <10 x half> @bitcast_v5i32_to_v10f16(<5 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB8_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB8_4
+; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB8_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB8_2
+; GFX11-NEXT: .LBB8_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1176,6 +1267,9 @@ define inreg <10 x half> @bitcast_v5i32_to_v10f16_scalar(<5 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1199,6 +1293,9 @@ define inreg <10 x half> @bitcast_v5i32_to_v10f16_scalar(<5 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1224,6 +1321,9 @@ define inreg <10 x half> @bitcast_v5i32_to_v10f16_scalar(<5 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1676,14 +1776,28 @@ define <10 x i16> @bitcast_v5f32_to_v10i16(<5 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB12_4
+; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB12_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB12_2
+; VI-NEXT: .LBB12_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1693,14 +1807,28 @@ define <10 x i16> @bitcast_v5f32_to_v10i16(<5 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB12_4
+; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB12_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB12_2
+; GFX9-NEXT: .LBB12_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1710,13 +1838,26 @@ define <10 x i16> @bitcast_v5f32_to_v10i16(<5 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB12_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB12_4
+; GFX11-NEXT: .LBB12_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB12_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-NEXT: .LBB12_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1752,14 +1893,14 @@ define inreg <10 x i16> @bitcast_v5f32_to_v10i16_scalar(<5 x float> inreg %a, i3
; SI-NEXT: .LBB13_2: ; %cmp.true
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
+; SI-NEXT: v_lshr_b64 v[5:6], v[2:3], 16
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
-; SI-NEXT: v_lshr_b64 v[7:8], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[8:9], v[0:1], 16
-; SI-NEXT: v_lshr_b64 v[5:6], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[4:5], 16
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; SI-NEXT: s_branch .LBB13_5
; SI-NEXT: .LBB13_3:
; SI-NEXT: ; implicit-def: $sgpr8
@@ -1774,26 +1915,26 @@ define inreg <10 x i16> @bitcast_v5f32_to_v10i16_scalar(<5 x float> inreg %a, i3
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
-; SI-NEXT: v_mov_b32_e32 v6, s12
+; SI-NEXT: v_mov_b32_e32 v7, s12
; SI-NEXT: v_mov_b32_e32 v9, s13
-; SI-NEXT: v_mov_b32_e32 v5, s6
+; SI-NEXT: v_mov_b32_e32 v6, s6
; SI-NEXT: v_mov_b32_e32 v8, s8
-; SI-NEXT: v_mov_b32_e32 v7, s4
+; SI-NEXT: v_mov_b32_e32 v5, s4
; SI-NEXT: .LBB13_5: ; %end
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v6
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v2, v2, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v2, v2, v6
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v3, v3, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT: v_or_b32_e32 v0, v0, v8
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
+; SI-NEXT: v_or_b32_e32 v1, v1, v7
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1810,6 +1951,9 @@ define inreg <10 x i16> @bitcast_v5f32_to_v10i16_scalar(<5 x float> inreg %a, i3
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB13_3:
; VI-NEXT: s_branch .LBB13_2
@@ -1837,6 +1981,9 @@ define inreg <10 x i16> @bitcast_v5f32_to_v10i16_scalar(<5 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB13_3:
; GFX9-NEXT: s_branch .LBB13_2
@@ -1867,6 +2014,9 @@ define inreg <10 x i16> @bitcast_v5f32_to_v10i16_scalar(<5 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB13_3:
; GFX11-NEXT: s_branch .LBB13_2
@@ -2281,14 +2431,28 @@ define <10 x half> @bitcast_v5f32_to_v10f16(<5 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB16_4
+; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB16_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB16_2
+; VI-NEXT: .LBB16_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2298,14 +2462,28 @@ define <10 x half> @bitcast_v5f32_to_v10f16(<5 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB16_4
+; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB16_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB16_2
+; GFX9-NEXT: .LBB16_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -2315,13 +2493,26 @@ define <10 x half> @bitcast_v5f32_to_v10f16(<5 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v5
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB16_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB16_4
+; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB16_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-NEXT: .LBB16_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2357,14 +2548,14 @@ define inreg <10 x half> @bitcast_v5f32_to_v10f16_scalar(<5 x float> inreg %a, i
; SI-NEXT: .LBB17_2: ; %cmp.true
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
+; SI-NEXT: v_lshr_b64 v[5:6], v[2:3], 16
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
-; SI-NEXT: v_lshr_b64 v[7:8], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[8:9], v[0:1], 16
-; SI-NEXT: v_lshr_b64 v[5:6], v[4:5], 16
+; SI-NEXT: v_lshr_b64 v[6:7], v[4:5], 16
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; SI-NEXT: s_branch .LBB17_5
; SI-NEXT: .LBB17_3:
; SI-NEXT: ; implicit-def: $sgpr8
@@ -2379,26 +2570,26 @@ define inreg <10 x half> @bitcast_v5f32_to_v10f16_scalar(<5 x float> inreg %a, i
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
-; SI-NEXT: v_mov_b32_e32 v6, s12
+; SI-NEXT: v_mov_b32_e32 v7, s12
; SI-NEXT: v_mov_b32_e32 v9, s13
-; SI-NEXT: v_mov_b32_e32 v5, s6
+; SI-NEXT: v_mov_b32_e32 v6, s6
; SI-NEXT: v_mov_b32_e32 v8, s8
-; SI-NEXT: v_mov_b32_e32 v7, s4
+; SI-NEXT: v_mov_b32_e32 v5, s4
; SI-NEXT: .LBB17_5: ; %end
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v1, v1, v6
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v2, v2, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v9
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v2, v2, v6
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v9
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v3, v3, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT: v_or_b32_e32 v0, v0, v8
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
+; SI-NEXT: v_or_b32_e32 v1, v1, v7
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2415,6 +2606,9 @@ define inreg <10 x half> @bitcast_v5f32_to_v10f16_scalar(<5 x float> inreg %a, i
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB17_3:
; VI-NEXT: s_branch .LBB17_2
@@ -2442,6 +2636,9 @@ define inreg <10 x half> @bitcast_v5f32_to_v10f16_scalar(<5 x float> inreg %a, i
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB17_3:
; GFX9-NEXT: s_branch .LBB17_2
@@ -2472,6 +2669,9 @@ define inreg <10 x half> @bitcast_v5f32_to_v10f16_scalar(<5 x float> inreg %a, i
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB17_3:
; GFX11-NEXT: s_branch .LBB17_2
@@ -2990,6 +3190,9 @@ define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v8
; VI-NEXT: v_or_b32_e32 v1, v1, v7
; VI-NEXT: v_or_b32_e32 v0, v0, v6
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -3007,6 +3210,9 @@ define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3025,6 +3231,9 @@ define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3171,6 +3380,9 @@ define inreg <10 x half> @bitcast_v10i16_to_v10f16_scalar(<10 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB21_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -3194,6 +3406,9 @@ define inreg <10 x half> @bitcast_v10i16_to_v10f16_scalar(<10 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -3224,6 +3439,9 @@ define inreg <10 x half> @bitcast_v10i16_to_v10f16_scalar(<10 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -3351,6 +3569,9 @@ define <10 x i16> @bitcast_v10f16_to_v10i16(<10 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_or_b32_e32 v1, v7, v1
; VI-NEXT: v_or_b32_e32 v0, v5, v0
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -3369,6 +3590,9 @@ define <10 x i16> @bitcast_v10f16_to_v10i16(<10 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3387,6 +3611,9 @@ define <10 x i16> @bitcast_v10f16_to_v10i16(<10 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3529,6 +3756,9 @@ define inreg <10 x i16> @bitcast_v10f16_to_v10i16_scalar(<10 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v2, v2, v8
; VI-NEXT: v_or_b32_e32 v1, v1, v7
; VI-NEXT: v_or_b32_e32 v0, v5, v6
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB23_3:
; VI-NEXT: s_branch .LBB23_2
@@ -3557,6 +3787,9 @@ define inreg <10 x i16> @bitcast_v10f16_to_v10i16_scalar(<10 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB23_3:
; GFX9-NEXT: s_branch .LBB23_2
@@ -3587,6 +3820,9 @@ define inreg <10 x i16> @bitcast_v10f16_to_v10i16_scalar(<10 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: ; implicit-def: $vgpr5
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB23_3:
; GFX11-NEXT: s_branch .LBB23_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
index 30193251552ae..2987965b71c49 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
@@ -353,6 +353,7 @@ define inreg i16 @bitcast_f16_to_i16_scalar(half inreg %a, i32 inreg %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB3_4
; GFX11-TRUE16-NEXT: .LBB3_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, 0x200, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB3_3:
; GFX11-TRUE16-NEXT: s_branch .LBB3_2
@@ -1008,6 +1009,7 @@ define inreg bfloat @bitcast_f16_to_bf16_scalar(half inreg %a, i32 inreg %b) #0
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_4
; GFX11-TRUE16-NEXT: .LBB9_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, 0x200, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB9_3:
; GFX11-TRUE16-NEXT: s_branch .LBB9_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
index 647b212d4d0bf..12324dfa0f992 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
@@ -1300,15 +1300,27 @@ define <12 x i16> @bitcast_v6i32_to_v12i16(<6 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB12_4
+; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB12_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB12_2
+; VI-NEXT: .LBB12_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1318,15 +1330,27 @@ define <12 x i16> @bitcast_v6i32_to_v12i16(<6 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB12_4
+; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB12_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB12_2
+; GFX9-NEXT: .LBB12_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1336,16 +1360,27 @@ define <12 x i16> @bitcast_v6i32_to_v12i16(<6 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB12_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB12_4
+; GFX11-NEXT: .LBB12_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB12_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-NEXT: .LBB12_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1441,6 +1476,8 @@ define inreg <12 x i16> @bitcast_v6i32_to_v12i16_scalar(<6 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB13_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1466,6 +1503,8 @@ define inreg <12 x i16> @bitcast_v6i32_to_v12i16_scalar(<6 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB13_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1493,6 +1532,8 @@ define inreg <12 x i16> @bitcast_v6i32_to_v12i16_scalar(<6 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1949,15 +1990,27 @@ define <12 x half> @bitcast_v6i32_to_v12f16(<6 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB16_4
+; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB16_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB16_2
+; VI-NEXT: .LBB16_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1967,15 +2020,27 @@ define <12 x half> @bitcast_v6i32_to_v12f16(<6 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB16_4
+; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB16_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB16_2
+; GFX9-NEXT: .LBB16_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1985,16 +2050,27 @@ define <12 x half> @bitcast_v6i32_to_v12f16(<6 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB16_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB16_4
+; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB16_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-NEXT: .LBB16_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2090,6 +2166,8 @@ define inreg <12 x half> @bitcast_v6i32_to_v12f16_scalar(<6 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB17_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2115,6 +2193,8 @@ define inreg <12 x half> @bitcast_v6i32_to_v12f16_scalar(<6 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB17_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2142,6 +2222,8 @@ define inreg <12 x half> @bitcast_v6i32_to_v12f16_scalar(<6 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB17_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -3462,15 +3544,27 @@ define <12 x i16> @bitcast_v6f32_to_v12i16(<6 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB28_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB28_4
+; VI-NEXT: .LBB28_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB28_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB28_2
+; VI-NEXT: .LBB28_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -3480,15 +3574,27 @@ define <12 x i16> @bitcast_v6f32_to_v12i16(<6 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB28_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB28_4
+; GFX9-NEXT: .LBB28_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB28_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB28_2
+; GFX9-NEXT: .LBB28_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -3498,13 +3604,24 @@ define <12 x i16> @bitcast_v6f32_to_v12i16(<6 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB28_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB28_4
+; GFX11-NEXT: .LBB28_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB28_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-NEXT: .LBB28_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -3608,6 +3725,8 @@ define inreg <12 x i16> @bitcast_v6f32_to_v12i16_scalar(<6 x float> inreg %a, i3
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB29_3:
; VI-NEXT: s_branch .LBB29_2
@@ -3636,6 +3755,8 @@ define inreg <12 x i16> @bitcast_v6f32_to_v12i16_scalar(<6 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB29_3:
; GFX9-NEXT: s_branch .LBB29_2
@@ -3668,6 +3789,8 @@ define inreg <12 x i16> @bitcast_v6f32_to_v12i16_scalar(<6 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB29_3:
; GFX11-NEXT: s_branch .LBB29_2
@@ -4125,15 +4248,27 @@ define <12 x half> @bitcast_v6f32_to_v12f16(<6 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB32_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB32_4
+; VI-NEXT: .LBB32_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB32_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB32_2
+; VI-NEXT: .LBB32_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -4143,15 +4278,27 @@ define <12 x half> @bitcast_v6f32_to_v12f16(<6 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB32_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB32_4
+; GFX9-NEXT: .LBB32_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB32_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB32_2
+; GFX9-NEXT: .LBB32_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -4161,13 +4308,24 @@ define <12 x half> @bitcast_v6f32_to_v12f16(<6 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB32_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB32_4
+; GFX11-NEXT: .LBB32_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB32_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-NEXT: .LBB32_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4271,6 +4429,8 @@ define inreg <12 x half> @bitcast_v6f32_to_v12f16_scalar(<6 x float> inreg %a, i
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB33_3:
; VI-NEXT: s_branch .LBB33_2
@@ -4299,6 +4459,8 @@ define inreg <12 x half> @bitcast_v6f32_to_v12f16_scalar(<6 x float> inreg %a, i
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB33_3:
; GFX9-NEXT: s_branch .LBB33_2
@@ -4331,6 +4493,8 @@ define inreg <12 x half> @bitcast_v6f32_to_v12f16_scalar(<6 x float> inreg %a, i
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB33_3:
; GFX11-NEXT: s_branch .LBB33_2
@@ -5233,15 +5397,27 @@ define <12 x i16> @bitcast_v3i64_to_v12i16(<3 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB40_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB40_4
+; VI-NEXT: .LBB40_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB40_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB40_2
+; VI-NEXT: .LBB40_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -5251,15 +5427,27 @@ define <12 x i16> @bitcast_v3i64_to_v12i16(<3 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB40_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB40_4
+; GFX9-NEXT: .LBB40_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB40_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB40_2
+; GFX9-NEXT: .LBB40_4: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -5269,9 +5457,19 @@ define <12 x i16> @bitcast_v3i64_to_v12i16(<3 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB40_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB40_4
+; GFX11-NEXT: .LBB40_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB40_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-NEXT: .LBB40_4: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
@@ -5280,7 +5478,8 @@ define <12 x i16> @bitcast_v3i64_to_v12i16(<3 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -5376,6 +5575,8 @@ define inreg <12 x i16> @bitcast_v3i64_to_v12i16_scalar(<3 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB41_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -5401,6 +5602,8 @@ define inreg <12 x i16> @bitcast_v3i64_to_v12i16_scalar(<3 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB41_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -5428,6 +5631,8 @@ define inreg <12 x i16> @bitcast_v3i64_to_v12i16_scalar(<3 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB41_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -5884,15 +6089,27 @@ define <12 x half> @bitcast_v3i64_to_v12f16(<3 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB44_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB44_4
+; VI-NEXT: .LBB44_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB44_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB44_2
+; VI-NEXT: .LBB44_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -5902,15 +6119,27 @@ define <12 x half> @bitcast_v3i64_to_v12f16(<3 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB44_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB44_4
+; GFX9-NEXT: .LBB44_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB44_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB44_2
+; GFX9-NEXT: .LBB44_4: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -5920,9 +6149,19 @@ define <12 x half> @bitcast_v3i64_to_v12f16(<3 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB44_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB44_4
+; GFX11-NEXT: .LBB44_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB44_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB44_2
+; GFX11-NEXT: .LBB44_4: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
@@ -5931,7 +6170,8 @@ define <12 x half> @bitcast_v3i64_to_v12f16(<3 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6027,6 +6267,8 @@ define inreg <12 x half> @bitcast_v3i64_to_v12f16_scalar(<3 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB45_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -6052,6 +6294,8 @@ define inreg <12 x half> @bitcast_v3i64_to_v12f16_scalar(<3 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB45_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -6079,6 +6323,8 @@ define inreg <12 x half> @bitcast_v3i64_to_v12f16_scalar(<3 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB45_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -6578,13 +6824,24 @@ define <12 x i16> @bitcast_v3f64_to_v12i16(<3 x double> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB48_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB48_4
+; VI-NEXT: .LBB48_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB48_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB48_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB48_4: ; %cmp.true
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; VI-NEXT: .LBB48_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6594,13 +6851,24 @@ define <12 x i16> @bitcast_v3f64_to_v12i16(<3 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB48_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB48_4
+; GFX9-NEXT: .LBB48_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB48_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB48_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB48_4: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX9-NEXT: .LBB48_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6610,14 +6878,24 @@ define <12 x i16> @bitcast_v3f64_to_v12i16(<3 x double> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB48_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB48_4
+; GFX11-NEXT: .LBB48_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB48_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB48_4: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-NEXT: .LBB48_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6715,6 +6993,8 @@ define inreg <12 x i16> @bitcast_v3f64_to_v12i16_scalar(<3 x double> inreg %a, i
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB49_3:
; VI-NEXT: s_branch .LBB49_2
@@ -6740,6 +7020,8 @@ define inreg <12 x i16> @bitcast_v3f64_to_v12i16_scalar(<3 x double> inreg %a, i
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB49_3:
; GFX9-NEXT: s_branch .LBB49_2
@@ -6769,6 +7051,8 @@ define inreg <12 x i16> @bitcast_v3f64_to_v12i16_scalar(<3 x double> inreg %a, i
; GFX11-NEXT: v_add_f64 v[4:5], s[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB49_3:
; GFX11-NEXT: s_branch .LBB49_2
@@ -7223,13 +7507,24 @@ define <12 x half> @bitcast_v3f64_to_v12f16(<3 x double> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB52_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB52_4
+; VI-NEXT: .LBB52_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB52_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB52_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB52_4: ; %cmp.true
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; VI-NEXT: .LBB52_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -7239,13 +7534,24 @@ define <12 x half> @bitcast_v3f64_to_v12f16(<3 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB52_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB52_4
+; GFX9-NEXT: .LBB52_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB52_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB52_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB52_4: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX9-NEXT: .LBB52_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -7255,14 +7561,24 @@ define <12 x half> @bitcast_v3f64_to_v12f16(<3 x double> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB52_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB52_4
+; GFX11-NEXT: .LBB52_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB52_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB52_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB52_4: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-NEXT: .LBB52_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -7360,6 +7676,8 @@ define inreg <12 x half> @bitcast_v3f64_to_v12f16_scalar(<3 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB53_3:
; VI-NEXT: s_branch .LBB53_2
@@ -7385,6 +7703,8 @@ define inreg <12 x half> @bitcast_v3f64_to_v12f16_scalar(<3 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB53_3:
; GFX9-NEXT: s_branch .LBB53_2
@@ -7414,6 +7734,8 @@ define inreg <12 x half> @bitcast_v3f64_to_v12f16_scalar(<3 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB53_3:
; GFX11-NEXT: s_branch .LBB53_2
@@ -7995,6 +8317,8 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v9
; VI-NEXT: v_or_b32_e32 v1, v1, v8
; VI-NEXT: v_or_b32_e32 v0, v0, v7
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: .LBB56_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8013,6 +8337,8 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8032,6 +8358,8 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8200,6 +8528,8 @@ define inreg <12 x half> @bitcast_v12i16_to_v12f16_scalar(<12 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB57_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -8225,6 +8555,8 @@ define inreg <12 x half> @bitcast_v12i16_to_v12f16_scalar(<12 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB57_3:
; GFX9-NEXT: s_branch .LBB57_2
@@ -8257,6 +8589,8 @@ define inreg <12 x half> @bitcast_v12i16_to_v12f16_scalar(<12 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB57_3:
; GFX11-NEXT: s_branch .LBB57_2
@@ -8400,6 +8734,8 @@ define <12 x i16> @bitcast_v12f16_to_v12i16(<12 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v9, v2
; VI-NEXT: v_or_b32_e32 v1, v8, v1
; VI-NEXT: v_or_b32_e32 v0, v6, v0
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: .LBB58_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8419,6 +8755,8 @@ define <12 x i16> @bitcast_v12f16_to_v12i16(<12 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8438,6 +8776,8 @@ define <12 x i16> @bitcast_v12f16_to_v12i16(<12 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8600,6 +8940,8 @@ define inreg <12 x i16> @bitcast_v12f16_to_v12i16_scalar(<12 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v2, v2, v9
; VI-NEXT: v_or_b32_e32 v1, v1, v8
; VI-NEXT: v_or_b32_e32 v0, v6, v7
+; VI-NEXT: ; implicit-def: $vgpr6
+; VI-NEXT: ; implicit-def: $vgpr6
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB59_3:
; VI-NEXT: s_branch .LBB59_2
@@ -8629,6 +8971,8 @@ define inreg <12 x i16> @bitcast_v12f16_to_v12i16_scalar(<12 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: ; implicit-def: $vgpr6
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB59_3:
; GFX9-NEXT: s_branch .LBB59_2
@@ -8661,6 +9005,8 @@ define inreg <12 x i16> @bitcast_v12f16_to_v12i16_scalar(<12 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr6
+; GFX11-NEXT: ; implicit-def: $vgpr6
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB59_3:
; GFX11-NEXT: s_branch .LBB59_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
index c66f5ea8e6c60..ee28578d1c333 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
@@ -519,8 +519,18 @@ define <14 x i16> @bitcast_v7i32_to_v14i16(<7 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB4_4
+; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB4_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr7
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB4_2
+; VI-NEXT: .LBB4_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
@@ -528,7 +538,7 @@ define <14 x i16> @bitcast_v7i32_to_v14i16(<7 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -538,8 +548,18 @@ define <14 x i16> @bitcast_v7i32_to_v14i16(<7 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB4_4
+; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB4_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr7
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB4_2
+; GFX9-NEXT: .LBB4_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
@@ -547,7 +567,7 @@ define <14 x i16> @bitcast_v7i32_to_v14i16(<7 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -557,10 +577,18 @@ define <14 x i16> @bitcast_v7i32_to_v14i16(<7 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB4_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB4_4
+; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB4_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB4_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB4_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
@@ -568,7 +596,7 @@ define <14 x i16> @bitcast_v7i32_to_v14i16(<7 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -673,6 +701,7 @@ define inreg <14 x i16> @bitcast_v7i32_to_v14i16_scalar(<7 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -700,6 +729,7 @@ define inreg <14 x i16> @bitcast_v7i32_to_v14i16_scalar(<7 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -729,6 +759,7 @@ define inreg <14 x i16> @bitcast_v7i32_to_v14i16_scalar(<7 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1231,8 +1262,18 @@ define <14 x half> @bitcast_v7i32_to_v14f16(<7 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB8_4
+; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB8_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr7
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB8_2
+; VI-NEXT: .LBB8_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
@@ -1240,7 +1281,7 @@ define <14 x half> @bitcast_v7i32_to_v14f16(<7 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1250,8 +1291,18 @@ define <14 x half> @bitcast_v7i32_to_v14f16(<7 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB8_4
+; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB8_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr7
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB8_2
+; GFX9-NEXT: .LBB8_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
@@ -1259,7 +1310,7 @@ define <14 x half> @bitcast_v7i32_to_v14f16(<7 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1269,10 +1320,18 @@ define <14 x half> @bitcast_v7i32_to_v14f16(<7 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB8_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB8_4
+; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB8_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB8_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB8_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
@@ -1280,7 +1339,7 @@ define <14 x half> @bitcast_v7i32_to_v14f16(<7 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1385,6 +1444,7 @@ define inreg <14 x half> @bitcast_v7i32_to_v14f16_scalar(<7 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1412,6 +1472,7 @@ define inreg <14 x half> @bitcast_v7i32_to_v14f16_scalar(<7 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1441,6 +1502,7 @@ define inreg <14 x half> @bitcast_v7i32_to_v14f16_scalar(<7 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1996,8 +2058,18 @@ define <14 x i16> @bitcast_v7f32_to_v14i16(<7 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB12_4
+; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB12_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr7
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB12_2
+; VI-NEXT: .LBB12_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
@@ -2005,7 +2077,7 @@ define <14 x i16> @bitcast_v7f32_to_v14i16(<7 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2015,8 +2087,18 @@ define <14 x i16> @bitcast_v7f32_to_v14i16(<7 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB12_4
+; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB12_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr7
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB12_2
+; GFX9-NEXT: .LBB12_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
@@ -2024,7 +2106,7 @@ define <14 x i16> @bitcast_v7f32_to_v14i16(<7 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -2034,14 +2116,23 @@ define <14 x i16> @bitcast_v7f32_to_v14i16(<7 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB12_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB12_4
+; GFX11-NEXT: .LBB12_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB12_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr7
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-NEXT: .LBB12_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2155,6 +2246,7 @@ define inreg <14 x i16> @bitcast_v7f32_to_v14i16_scalar(<7 x float> inreg %a, i3
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB13_3:
; VI-NEXT: s_branch .LBB13_2
@@ -2184,6 +2276,7 @@ define inreg <14 x i16> @bitcast_v7f32_to_v14i16_scalar(<7 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB13_3:
; GFX9-NEXT: s_branch .LBB13_2
@@ -2218,6 +2311,7 @@ define inreg <14 x i16> @bitcast_v7f32_to_v14i16_scalar(<7 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB13_3:
; GFX11-NEXT: s_branch .LBB13_2
@@ -2720,8 +2814,18 @@ define <14 x half> @bitcast_v7f32_to_v14f16(<7 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB16_4
+; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB16_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr7
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB16_2
+; VI-NEXT: .LBB16_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
@@ -2729,7 +2833,7 @@ define <14 x half> @bitcast_v7f32_to_v14f16(<7 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2739,8 +2843,18 @@ define <14 x half> @bitcast_v7f32_to_v14f16(<7 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB16_4
+; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB16_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr7
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB16_2
+; GFX9-NEXT: .LBB16_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
@@ -2748,7 +2862,7 @@ define <14 x half> @bitcast_v7f32_to_v14f16(<7 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -2758,14 +2872,23 @@ define <14 x half> @bitcast_v7f32_to_v14f16(<7 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB16_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB16_4
+; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB16_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr7
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-NEXT: .LBB16_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2879,6 +3002,7 @@ define inreg <14 x half> @bitcast_v7f32_to_v14f16_scalar(<7 x float> inreg %a, i
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB17_3:
; VI-NEXT: s_branch .LBB17_2
@@ -2908,6 +3032,7 @@ define inreg <14 x half> @bitcast_v7f32_to_v14f16_scalar(<7 x float> inreg %a, i
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB17_3:
; GFX9-NEXT: s_branch .LBB17_2
@@ -2942,6 +3067,7 @@ define inreg <14 x half> @bitcast_v7f32_to_v14f16_scalar(<7 x float> inreg %a, i
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB17_3:
; GFX11-NEXT: s_branch .LBB17_2
@@ -3586,6 +3712,7 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v10
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v0, v0, v8
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -3605,6 +3732,7 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3626,6 +3754,7 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3814,6 +3943,7 @@ define inreg <14 x half> @bitcast_v14i16_to_v14f16_scalar(<14 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB21_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -3841,6 +3971,7 @@ define inreg <14 x half> @bitcast_v14i16_to_v14f16_scalar(<14 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -3875,6 +4006,7 @@ define inreg <14 x half> @bitcast_v14i16_to_v14f16_scalar(<14 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -4033,6 +4165,7 @@ define <14 x i16> @bitcast_v14f16_to_v14i16(<14 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v10, v2
; VI-NEXT: v_or_b32_e32 v1, v9, v1
; VI-NEXT: v_or_b32_e32 v0, v7, v0
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4053,6 +4186,7 @@ define <14 x i16> @bitcast_v14f16_to_v14i16(<14 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4074,6 +4208,7 @@ define <14 x i16> @bitcast_v14f16_to_v14i16(<14 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4255,6 +4390,7 @@ define inreg <14 x i16> @bitcast_v14f16_to_v14i16_scalar(<14 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v2, v2, v10
; VI-NEXT: v_or_b32_e32 v1, v1, v9
; VI-NEXT: v_or_b32_e32 v0, v7, v8
+; VI-NEXT: ; implicit-def: $vgpr7
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB23_3:
; VI-NEXT: s_branch .LBB23_2
@@ -4285,6 +4421,7 @@ define inreg <14 x i16> @bitcast_v14f16_to_v14i16_scalar(<14 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB23_3:
; GFX9-NEXT: s_branch .LBB23_2
@@ -4319,6 +4456,7 @@ define inreg <14 x i16> @bitcast_v14f16_to_v14i16_scalar(<14 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr7
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB23_3:
; GFX11-NEXT: s_branch .LBB23_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index 224b73353c3bc..0768a101b7447 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -6583,8 +6583,7 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v5.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v4.l
@@ -6606,24 +6605,56 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB26_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v39, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v35, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v33, v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v32, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v33, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v12, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v30, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
@@ -6638,8 +6669,8 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
@@ -6677,11 +6708,11 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v8.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v10.l, 3
@@ -7496,143 +7527,295 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_branch .LBB27_2
;
-; GFX11-LABEL: bitcast_v32i8_to_v8i32_scalar:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s42, v14
-; GFX11-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-NEXT: v_readfirstlane_b32 s5, v12
-; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_readfirstlane_b32 s7, v10
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v8
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v6
-; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_readfirstlane_b32 s13, v4
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v2
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v0
-; GFX11-NEXT: s_cmp_lg_u32 s42, 0
-; GFX11-NEXT: s_mov_b32 s42, 0
-; GFX11-NEXT: s_cbranch_scc0 .LBB27_4
-; GFX11-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v12, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v11
-; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
-; GFX11-NEXT: s_cbranch_vccnz .LBB27_3
-; GFX11-NEXT: .LBB27_2: ; %cmp.true
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
-; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: s_add_i32 s11, s11, 3
-; GFX11-NEXT: s_add_i32 s9, s9, 3
-; GFX11-NEXT: s_add_i32 s7, s7, 3
-; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
-; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v8, s15, s14, v3
-; GFX11-NEXT: v_perm_b32 v9, s13, s12, v3
-; GFX11-NEXT: v_perm_b32 v10, s11, s10, v3
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v12, s7, s6, v3
-; GFX11-NEXT: v_perm_b32 v3, s5, s4, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v3
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-NEXT: v_or_b32_e32 v4, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v13
-; GFX11-NEXT: .LBB27_3: ; %end
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT: .LBB27_4:
-; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT: s_branch .LBB27_2
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v8i32_scalar:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s42, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB27_4
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s41, s40, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s5, s4, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s13, s12, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v10, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB27_3
+; GFX11-TRUE16-NEXT: .LBB27_2: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s28, s29, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s40, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s5, s4, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v10, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT: .LBB27_3: ; %end
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB27_4:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_branch .LBB27_2
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v8i32_scalar:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s42, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s42, 0
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB27_4
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s41, s40, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s5, s4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s13, s12, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB27_3
+; GFX11-FAKE16-NEXT: .LBB27_2: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s28, s29, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s41, s40, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s5, s4, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v13
+; GFX11-FAKE16-NEXT: .LBB27_3: ; %end
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB27_4:
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT: s_branch .LBB27_2
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
@@ -13851,8 +14034,7 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v5.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v4.l
@@ -13874,24 +14056,56 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v39, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v35, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v33, v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v32, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v33, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v12, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v30, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
@@ -13906,8 +14120,8 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
@@ -13945,11 +14159,11 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v8.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v10.l, 3
@@ -14764,143 +14978,295 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_branch .LBB51_2
;
-; GFX11-LABEL: bitcast_v32i8_to_v8f32_scalar:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s42, v14
-; GFX11-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-NEXT: v_readfirstlane_b32 s5, v12
-; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_readfirstlane_b32 s7, v10
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v8
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v6
-; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_readfirstlane_b32 s13, v4
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v2
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v0
-; GFX11-NEXT: s_cmp_lg_u32 s42, 0
-; GFX11-NEXT: s_mov_b32 s42, 0
-; GFX11-NEXT: s_cbranch_scc0 .LBB51_4
-; GFX11-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v12, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v11
-; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
-; GFX11-NEXT: s_cbranch_vccnz .LBB51_3
-; GFX11-NEXT: .LBB51_2: ; %cmp.true
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
-; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: s_add_i32 s11, s11, 3
-; GFX11-NEXT: s_add_i32 s9, s9, 3
-; GFX11-NEXT: s_add_i32 s7, s7, 3
-; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
-; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v8, s15, s14, v3
-; GFX11-NEXT: v_perm_b32 v9, s13, s12, v3
-; GFX11-NEXT: v_perm_b32 v10, s11, s10, v3
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v12, s7, s6, v3
-; GFX11-NEXT: v_perm_b32 v3, s5, s4, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v3
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-NEXT: v_or_b32_e32 v4, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v13
-; GFX11-NEXT: .LBB51_3: ; %end
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT: .LBB51_4:
-; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT: s_branch .LBB51_2
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v8f32_scalar:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s42, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_4
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s41, s40, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s5, s4, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s13, s12, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v10, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3
+; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s28, s29, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s40, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s5, s4, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v10, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT: .LBB51_3: ; %end
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB51_4:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_branch .LBB51_2
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v8f32_scalar:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s42, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s42, 0
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB51_4
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s41, s40, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s5, s4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s13, s12, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB51_3
+; GFX11-FAKE16-NEXT: .LBB51_2: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s28, s29, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s41, s40, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s5, s4, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v13
+; GFX11-FAKE16-NEXT: .LBB51_3: ; %end
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB51_4:
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT: s_branch .LBB51_2
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
@@ -20580,8 +20946,7 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v5.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v4.l
@@ -20603,24 +20968,56 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB70_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v39, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v35, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v33, v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v32, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v33, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v12, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v30, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
@@ -20635,8 +21032,8 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
@@ -20674,11 +21071,11 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v8.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v10.l, 3
@@ -21493,143 +21890,295 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_branch .LBB71_2
;
-; GFX11-LABEL: bitcast_v32i8_to_v4i64_scalar:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s42, v14
-; GFX11-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-NEXT: v_readfirstlane_b32 s5, v12
-; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_readfirstlane_b32 s7, v10
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v8
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v6
-; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_readfirstlane_b32 s13, v4
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v2
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v0
-; GFX11-NEXT: s_cmp_lg_u32 s42, 0
-; GFX11-NEXT: s_mov_b32 s42, 0
-; GFX11-NEXT: s_cbranch_scc0 .LBB71_4
-; GFX11-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v12, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v11
-; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
-; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
-; GFX11-NEXT: .LBB71_2: ; %cmp.true
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
-; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: s_add_i32 s11, s11, 3
-; GFX11-NEXT: s_add_i32 s9, s9, 3
-; GFX11-NEXT: s_add_i32 s7, s7, 3
-; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
-; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v8, s15, s14, v3
-; GFX11-NEXT: v_perm_b32 v9, s13, s12, v3
-; GFX11-NEXT: v_perm_b32 v10, s11, s10, v3
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v12, s7, s6, v3
-; GFX11-NEXT: v_perm_b32 v3, s5, s4, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v3
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-NEXT: v_or_b32_e32 v4, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v13
-; GFX11-NEXT: .LBB71_3: ; %end
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT: .LBB71_4:
-; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT: s_branch .LBB71_2
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v4i64_scalar:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s42, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB71_4
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s41, s40, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s5, s4, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s13, s12, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v10, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB71_3
+; GFX11-TRUE16-NEXT: .LBB71_2: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s28, s29, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s40, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s5, s4, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v10, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT: .LBB71_3: ; %end
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB71_4:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_branch .LBB71_2
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v4i64_scalar:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s42, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s42, 0
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB71_4
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s41, s40, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s5, s4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s13, s12, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB71_3
+; GFX11-FAKE16-NEXT: .LBB71_2: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s28, s29, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s41, s40, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s5, s4, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v13
+; GFX11-FAKE16-NEXT: .LBB71_3: ; %end
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB71_4:
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT: s_branch .LBB71_2
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
@@ -26842,8 +27391,7 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v5.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v4.l
@@ -26865,24 +27413,56 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB86_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v39, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v35, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v33, v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v32, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v33, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v12, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v30, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
@@ -26897,8 +27477,8 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
@@ -26936,11 +27516,11 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v8.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v10.l, 3
@@ -27755,143 +28335,295 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-NEXT: s_branch .LBB87_2
;
-; GFX11-LABEL: bitcast_v32i8_to_v4f64_scalar:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s42, v14
-; GFX11-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-NEXT: v_readfirstlane_b32 s5, v12
-; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_readfirstlane_b32 s7, v10
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v8
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v6
-; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_readfirstlane_b32 s13, v4
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v2
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v0
-; GFX11-NEXT: s_cmp_lg_u32 s42, 0
-; GFX11-NEXT: s_mov_b32 s42, 0
-; GFX11-NEXT: s_cbranch_scc0 .LBB87_4
-; GFX11-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v12, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v11
-; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
-; GFX11-NEXT: s_cbranch_vccnz .LBB87_3
-; GFX11-NEXT: .LBB87_2: ; %cmp.true
-; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
-; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: s_add_i32 s11, s11, 3
-; GFX11-NEXT: s_add_i32 s9, s9, 3
-; GFX11-NEXT: s_add_i32 s7, s7, 3
-; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
-; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v8, s15, s14, v3
-; GFX11-NEXT: v_perm_b32 v9, s13, s12, v3
-; GFX11-NEXT: v_perm_b32 v10, s11, s10, v3
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v12, s7, s6, v3
-; GFX11-NEXT: v_perm_b32 v3, s5, s4, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v3
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-NEXT: v_or_b32_e32 v4, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v13
-; GFX11-NEXT: .LBB87_3: ; %end
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT: .LBB87_4:
-; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT: s_branch .LBB87_2
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v4f64_scalar:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s42, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB87_4
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s41, s40, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s5, s4, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s13, s12, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v10, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB87_3
+; GFX11-TRUE16-NEXT: .LBB87_2: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s28, s29, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s40, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s5, s4, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v10, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT: .LBB87_3: ; %end
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB87_4:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_branch .LBB87_2
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v4f64_scalar:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s42, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s42, 0
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB87_4
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s41, s40, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s5, s4, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s13, s12, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB87_3
+; GFX11-FAKE16-NEXT: .LBB87_2: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s28, s29, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s41, s40, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s5, s4, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v13
+; GFX11-FAKE16-NEXT: .LBB87_3: ; %end
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB87_4:
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT: s_branch .LBB87_2
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
@@ -32940,27 +33672,25 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v23.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v19.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v17.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v19.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v23.h
@@ -32979,20 +33709,36 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB98_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v23, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v32, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v21, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v20, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v29, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v19, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v32, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v27, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v31, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v25, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v22.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v30.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v15, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v35, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v5.l, v8.h
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v26.l
@@ -33000,38 +33746,42 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v16.l
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v4.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v6.l, v10.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v34, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v33, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.h
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v10.l
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v9.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
@@ -33045,22 +33795,22 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v36.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v30.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v26.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v33.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v10.h, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v22.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v10.l, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v21.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v2.l
@@ -33073,39 +33823,39 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v31.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v25.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v8.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v31.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v27.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v21.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v15.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v19.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v20.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v23.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v15.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v11.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v12.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v8.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v14.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v23.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v8.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.l, v1.h
@@ -33925,20 +34675,34 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s42, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB99_4
@@ -33946,31 +34710,31 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s43, s28, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s29, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s12, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s9, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s15, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s13, 8
; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s44
; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s18, s19, v4
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_and_b32 s44, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s7, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s12, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s2, s3, v4
; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s14, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s8, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s7, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s4, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v4
; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s22, s23, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s5, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s47, s11, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s6, 8
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s45
; GFX11-TRUE16-NEXT: s_or_b32 s45, s47, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
@@ -33978,8 +34742,8 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s15, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s13, s6, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s40, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s8, s5, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, s43
@@ -33988,33 +34752,33 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-TRUE16-NEXT: .LBB99_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s13, s6, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s8, s5, v0
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s8, s4, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s14, s5, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s7, s4, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s11, s6, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s41, s15, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s41, s40, v0
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s12, s9, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s15, s13, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s28, s29, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s20, s21, v0
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s10, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s11, s7, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s10, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s9, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s26, s27, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v1
@@ -38399,27 +39163,25 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v23.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v19.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v17.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v19.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v23.h
@@ -38438,20 +39200,36 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB106_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v23, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v32, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v21, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v20, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v29, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v19, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v32, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v27, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v31, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v25, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v22.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v30.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v15, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v35, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v5.l, v8.h
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v26.l
@@ -38459,38 +39237,42 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v16.l
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v4.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v6.l, v10.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v34, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v33, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.h
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v10.l
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v9.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
@@ -38504,22 +39286,22 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v36.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v30.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v26.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v33.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v10.h, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v22.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v10.l, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v21.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v2.l
@@ -38532,39 +39314,39 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v31.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v25.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v8.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v31.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v27.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v21.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v15.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v19.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v20.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v23.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v15.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v11.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v12.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v8.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v14.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v23.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v8.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.l, v1.h
@@ -39384,20 +40166,34 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s42, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB107_4
@@ -39405,31 +40201,31 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s43, s28, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s29, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s12, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s9, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s15, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s13, 8
; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s44
; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s18, s19, v4
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_and_b32 s44, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s7, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s12, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s2, s3, v4
; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s14, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s8, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s7, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s4, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v4
; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s22, s23, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s5, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s47, s11, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s6, 8
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s45
; GFX11-TRUE16-NEXT: s_or_b32 s45, s47, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
@@ -39437,8 +40233,8 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s15, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s13, s6, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s40, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s8, s5, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, s43
@@ -39447,33 +40243,33 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-TRUE16-NEXT: .LBB107_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s13, s6, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s8, s5, v0
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s8, s4, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s14, s5, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s7, s4, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s11, s6, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s41, s15, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s41, s40, v0
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s12, s9, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s15, s13, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s28, s29, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s20, s21, v0
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s10, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s11, s7, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s10, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s9, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s26, s27, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v1
@@ -42787,27 +43583,25 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v23.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v19.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v17.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v19.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v23.h
@@ -42826,20 +43620,36 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB110_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v23, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v32, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v21, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v20, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v29, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v19, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v32, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v27, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v31, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v25, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v22.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v30.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v15, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v20, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v35, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v5.l, v8.h
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v26.l
@@ -42847,38 +43657,42 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v16.l
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v4.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v6.l, v10.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v34, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v33, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.h
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v10.l
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v9.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v36, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
@@ -42892,22 +43706,22 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v36.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v30.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v24.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v26.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v33.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v10.h, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v22.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v10.l, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v21.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.h, v2.l
@@ -42920,39 +43734,39 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v31.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v25.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v9.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v8.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v13.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v31.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v27.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v21.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v15.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v19.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v20.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v23.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v20.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v15.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v11.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v14.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v12.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v8.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v14.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v23.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v8.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v9.l, v1.h
@@ -43764,20 +44578,34 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s42, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB111_4
@@ -43785,31 +44613,31 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s43, s28, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s29, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s12, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s9, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s15, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s13, 8
; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s44
; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s18, s19, v4
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_and_b32 s44, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s7, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s12, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s2, s3, v4
; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s14, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s8, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s7, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s4, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v4
; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s22, s23, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s5, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s47, s11, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s6, 8
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s45
; GFX11-TRUE16-NEXT: s_or_b32 s45, s47, s46
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
@@ -43817,8 +44645,8 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s15, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s13, s6, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s40, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s8, s5, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, s43
@@ -43827,33 +44655,33 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-TRUE16-NEXT: .LBB111_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s13, s6, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s8, s5, v0
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s8, s4, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s14, s5, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s7, s4, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s11, s6, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s41, s15, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s41, s40, v0
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s12, s9, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s15, s13, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s28, s29, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s20, s21, v0
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s10, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s11, s7, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s10, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s9, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s26, s27, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
index ead5d76b2e572..d54f2c69c95a0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
@@ -579,8 +579,24 @@ define <18 x i16> @bitcast_v9i32_to_v18i16(<9 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB4_4
+; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB4_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB4_2
+; VI-NEXT: .LBB4_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
@@ -590,7 +606,13 @@ define <18 x i16> @bitcast_v9i32_to_v18i16(<9 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -600,8 +622,24 @@ define <18 x i16> @bitcast_v9i32_to_v18i16(<9 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB4_4
+; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB4_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB4_2
+; GFX9-NEXT: .LBB4_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
@@ -611,7 +649,13 @@ define <18 x i16> @bitcast_v9i32_to_v18i16(<9 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -621,10 +665,24 @@ define <18 x i16> @bitcast_v9i32_to_v18i16(<9 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v9
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB4_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB4_4
+; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB4_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB4_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB4_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
@@ -634,7 +692,13 @@ define <18 x i16> @bitcast_v9i32_to_v18i16(<9 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -757,6 +821,13 @@ define inreg <18 x i16> @bitcast_v9i32_to_v18i16_scalar(<9 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -788,6 +859,13 @@ define inreg <18 x i16> @bitcast_v9i32_to_v18i16_scalar(<9 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -821,6 +899,13 @@ define inreg <18 x i16> @bitcast_v9i32_to_v18i16_scalar(<9 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1410,8 +1495,24 @@ define <18 x half> @bitcast_v9i32_to_v18f16(<9 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB8_4
+; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB8_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB8_2
+; VI-NEXT: .LBB8_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
@@ -1421,7 +1522,13 @@ define <18 x half> @bitcast_v9i32_to_v18f16(<9 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1431,8 +1538,24 @@ define <18 x half> @bitcast_v9i32_to_v18f16(<9 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB8_4
+; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB8_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB8_2
+; GFX9-NEXT: .LBB8_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
@@ -1442,7 +1565,13 @@ define <18 x half> @bitcast_v9i32_to_v18f16(<9 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1452,10 +1581,24 @@ define <18 x half> @bitcast_v9i32_to_v18f16(<9 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v9
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB8_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB8_4
+; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB8_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB8_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB8_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
@@ -1465,7 +1608,13 @@ define <18 x half> @bitcast_v9i32_to_v18f16(<9 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1588,6 +1737,13 @@ define inreg <18 x half> @bitcast_v9i32_to_v18f16_scalar(<9 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1619,6 +1775,13 @@ define inreg <18 x half> @bitcast_v9i32_to_v18f16_scalar(<9 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1652,6 +1815,13 @@ define inreg <18 x half> @bitcast_v9i32_to_v18f16_scalar(<9 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2309,8 +2479,24 @@ define <18 x i16> @bitcast_v9f32_to_v18i16(<9 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB12_4
+; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB12_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB12_2
+; VI-NEXT: .LBB12_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
@@ -2320,7 +2506,13 @@ define <18 x i16> @bitcast_v9f32_to_v18i16(<9 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2330,8 +2522,24 @@ define <18 x i16> @bitcast_v9f32_to_v18i16(<9 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB12_4
+; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB12_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB12_2
+; GFX9-NEXT: .LBB12_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
@@ -2341,7 +2549,13 @@ define <18 x i16> @bitcast_v9f32_to_v18i16(<9 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -2351,15 +2565,36 @@ define <18 x i16> @bitcast_v9f32_to_v18i16(<9 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v9
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB12_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB12_4
+; GFX11-NEXT: .LBB12_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB12_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-NEXT: .LBB12_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7
; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2397,20 +2632,20 @@ define inreg <18 x i16> @bitcast_v9f32_to_v18i16_scalar(<9 x float> inreg %a, i3
; SI-NEXT: s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT: s_cbranch_execnz .LBB13_4
; SI-NEXT: .LBB13_2: ; %cmp.true
-; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
-; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
+; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
+; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
; SI-NEXT: v_lshr_b64 v[9:10], v[6:7], 16
-; SI-NEXT: v_lshr_b64 v[12:13], v[4:5], 16
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: v_lshr_b64 v[10:11], v[4:5], 16
; SI-NEXT: v_lshr_b64 v[13:14], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[14:15], v[0:1], 16
-; SI-NEXT: v_lshr_b64 v[10:11], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[11:12], v[8:9], 16
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
@@ -2441,38 +2676,38 @@ define inreg <18 x i16> @bitcast_v9f32_to_v18i16_scalar(<9 x float> inreg %a, i3
; SI-NEXT: v_mov_b32_e32 v18, s26
; SI-NEXT: v_mov_b32_e32 v17, s27
; SI-NEXT: v_mov_b32_e32 v16, s28
-; SI-NEXT: v_mov_b32_e32 v10, s8
+; SI-NEXT: v_mov_b32_e32 v11, s8
; SI-NEXT: v_mov_b32_e32 v14, s12
; SI-NEXT: v_mov_b32_e32 v13, s10
-; SI-NEXT: v_mov_b32_e32 v12, s6
+; SI-NEXT: v_mov_b32_e32 v10, s6
; SI-NEXT: v_mov_b32_e32 v9, s4
; SI-NEXT: .LBB13_5: ; %end
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v14
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v11
+; SI-NEXT: v_or_b32_e32 v0, v0, v12
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v19
-; SI-NEXT: v_or_b32_e32 v1, v1, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v13
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v11
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v19
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v3, v3, v11
+; SI-NEXT: v_or_b32_e32 v1, v1, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v6, v6, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v16
-; SI-NEXT: v_or_b32_e32 v4, v4, v11
+; SI-NEXT: v_or_b32_e32 v2, v2, v12
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v18
+; SI-NEXT: v_or_b32_e32 v4, v4, v10
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
; SI-NEXT: v_or_b32_e32 v7, v7, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
-; SI-NEXT: v_or_b32_e32 v5, v5, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v11
+; SI-NEXT: v_or_b32_e32 v3, v3, v12
+; SI-NEXT: v_or_b32_e32 v5, v5, v10
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2493,6 +2728,13 @@ define inreg <18 x i16> @bitcast_v9f32_to_v18i16_scalar(<9 x float> inreg %a, i3
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB13_3:
; VI-NEXT: s_branch .LBB13_2
@@ -2532,6 +2774,13 @@ define inreg <18 x i16> @bitcast_v9f32_to_v18i16_scalar(<9 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB13_3:
; GFX9-NEXT: s_branch .LBB13_2
@@ -2577,6 +2826,13 @@ define inreg <18 x i16> @bitcast_v9f32_to_v18i16_scalar(<9 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB13_3:
; GFX11-NEXT: s_branch .LBB13_2
@@ -3169,8 +3425,24 @@ define <18 x half> @bitcast_v9f32_to_v18f16(<9 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB16_4
+; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB16_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB16_2
+; VI-NEXT: .LBB16_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
@@ -3180,7 +3452,13 @@ define <18 x half> @bitcast_v9f32_to_v18f16(<9 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -3190,8 +3468,24 @@ define <18 x half> @bitcast_v9f32_to_v18f16(<9 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB16_4
+; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB16_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB16_2
+; GFX9-NEXT: .LBB16_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
@@ -3201,7 +3495,13 @@ define <18 x half> @bitcast_v9f32_to_v18f16(<9 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -3211,15 +3511,36 @@ define <18 x half> @bitcast_v9f32_to_v18f16(<9 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v9
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB16_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB16_4
+; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB16_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-NEXT: .LBB16_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7
; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -3257,20 +3578,20 @@ define inreg <18 x half> @bitcast_v9f32_to_v18f16_scalar(<9 x float> inreg %a, i
; SI-NEXT: s_lshr_b64 s[12:13], s[16:17], 16
; SI-NEXT: s_cbranch_execnz .LBB17_4
; SI-NEXT: .LBB17_2: ; %cmp.true
-; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
-; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
+; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
+; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
; SI-NEXT: v_lshr_b64 v[9:10], v[6:7], 16
-; SI-NEXT: v_lshr_b64 v[12:13], v[4:5], 16
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: v_lshr_b64 v[10:11], v[4:5], 16
; SI-NEXT: v_lshr_b64 v[13:14], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[14:15], v[0:1], 16
-; SI-NEXT: v_lshr_b64 v[10:11], v[8:9], 16
+; SI-NEXT: v_lshr_b64 v[11:12], v[8:9], 16
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
@@ -3301,38 +3622,38 @@ define inreg <18 x half> @bitcast_v9f32_to_v18f16_scalar(<9 x float> inreg %a, i
; SI-NEXT: v_mov_b32_e32 v18, s26
; SI-NEXT: v_mov_b32_e32 v17, s27
; SI-NEXT: v_mov_b32_e32 v16, s28
-; SI-NEXT: v_mov_b32_e32 v10, s8
+; SI-NEXT: v_mov_b32_e32 v11, s8
; SI-NEXT: v_mov_b32_e32 v14, s12
; SI-NEXT: v_mov_b32_e32 v13, s10
-; SI-NEXT: v_mov_b32_e32 v12, s6
+; SI-NEXT: v_mov_b32_e32 v10, s6
; SI-NEXT: v_mov_b32_e32 v9, s4
; SI-NEXT: .LBB17_5: ; %end
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v14
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v11
+; SI-NEXT: v_or_b32_e32 v0, v0, v12
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v19
-; SI-NEXT: v_or_b32_e32 v1, v1, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v13
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v11
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v19
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v3, v3, v11
+; SI-NEXT: v_or_b32_e32 v1, v1, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v6, v6, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v16
-; SI-NEXT: v_or_b32_e32 v4, v4, v11
+; SI-NEXT: v_or_b32_e32 v2, v2, v12
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v18
+; SI-NEXT: v_or_b32_e32 v4, v4, v10
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
; SI-NEXT: v_or_b32_e32 v7, v7, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
-; SI-NEXT: v_or_b32_e32 v5, v5, v11
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v11
+; SI-NEXT: v_or_b32_e32 v3, v3, v12
+; SI-NEXT: v_or_b32_e32 v5, v5, v10
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -3353,6 +3674,13 @@ define inreg <18 x half> @bitcast_v9f32_to_v18f16_scalar(<9 x float> inreg %a, i
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB17_3:
; VI-NEXT: s_branch .LBB17_2
@@ -3392,6 +3720,13 @@ define inreg <18 x half> @bitcast_v9f32_to_v18f16_scalar(<9 x float> inreg %a, i
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB17_3:
; GFX9-NEXT: s_branch .LBB17_2
@@ -3437,6 +3772,13 @@ define inreg <18 x half> @bitcast_v9f32_to_v18f16_scalar(<9 x float> inreg %a, i
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB17_3:
; GFX11-NEXT: s_branch .LBB17_2
@@ -4210,6 +4552,13 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v12
; VI-NEXT: v_or_b32_e32 v1, v1, v11
; VI-NEXT: v_or_b32_e32 v0, v0, v10
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4231,6 +4580,13 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4254,6 +4610,13 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4484,6 +4847,13 @@ define inreg <18 x half> @bitcast_v18i16_to_v18f16_scalar(<18 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB21_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -4515,6 +4885,13 @@ define inreg <18 x half> @bitcast_v18i16_to_v18f16_scalar(<18 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -4560,6 +4937,13 @@ define inreg <18 x half> @bitcast_v18i16_to_v18f16_scalar(<18 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -4753,6 +5137,13 @@ define <18 x i16> @bitcast_v18f16_to_v18i16(<18 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v12, v2
; VI-NEXT: v_or_b32_e32 v1, v11, v1
; VI-NEXT: v_or_b32_e32 v0, v9, v0
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4776,6 +5167,13 @@ define <18 x i16> @bitcast_v18f16_to_v18i16(<18 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4799,6 +5197,13 @@ define <18 x i16> @bitcast_v18f16_to_v18i16(<18 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5019,6 +5424,13 @@ define inreg <18 x i16> @bitcast_v18f16_to_v18i16_scalar(<18 x half> inreg %a, i
; VI-NEXT: v_add_f16_e32 v0, s17, v0
; VI-NEXT: v_or_b32_e32 v1, v0, v1
; VI-NEXT: v_or_b32_e32 v0, v9, v10
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB23_3:
; VI-NEXT: s_branch .LBB23_2
@@ -5059,6 +5471,13 @@ define inreg <18 x i16> @bitcast_v18f16_to_v18i16_scalar(<18 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: ; implicit-def: $vgpr9
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB23_3:
; GFX9-NEXT: s_branch .LBB23_2
@@ -5104,6 +5523,13 @@ define inreg <18 x i16> @bitcast_v18f16_to_v18i16_scalar(<18 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: ; implicit-def: $vgpr9
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB23_3:
; GFX11-NEXT: s_branch .LBB23_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index aba9755a4f357..e7dcc65a07d52 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -614,9 +614,23 @@ define <20 x i16> @bitcast_v10i32_to_v20i16(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_4
+; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB4_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB4_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB4_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
@@ -627,7 +641,12 @@ define <20 x i16> @bitcast_v10i32_to_v20i16(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -637,9 +656,23 @@ define <20 x i16> @bitcast_v10i32_to_v20i16(<10 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_4
+; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB4_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB4_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB4_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
@@ -650,7 +683,12 @@ define <20 x i16> @bitcast_v10i32_to_v20i16(<10 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -660,10 +698,23 @@ define <20 x i16> @bitcast_v10i32_to_v20i16(<10 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB4_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB4_4
+; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB4_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB4_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB4_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
@@ -674,7 +725,12 @@ define <20 x i16> @bitcast_v10i32_to_v20i16(<10 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -806,6 +862,12 @@ define inreg <20 x i16> @bitcast_v10i32_to_v20i16_scalar(<10 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -839,6 +901,12 @@ define inreg <20 x i16> @bitcast_v10i32_to_v20i16_scalar(<10 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -874,6 +942,12 @@ define inreg <20 x i16> @bitcast_v10i32_to_v20i16_scalar(<10 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1507,9 +1581,23 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_4
+; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB8_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB8_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB8_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
@@ -1520,7 +1608,12 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1530,9 +1623,23 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_4
+; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB8_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB8_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB8_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
@@ -1543,7 +1650,12 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1553,10 +1665,23 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB8_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB8_4
+; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB8_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB8_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB8_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
@@ -1567,7 +1692,12 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1699,6 +1829,12 @@ define inreg <20 x half> @bitcast_v10i32_to_v20f16_scalar(<10 x i32> inreg %a, i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1732,6 +1868,12 @@ define inreg <20 x half> @bitcast_v10i32_to_v20f16_scalar(<10 x i32> inreg %a, i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1767,6 +1909,12 @@ define inreg <20 x half> @bitcast_v10i32_to_v20f16_scalar(<10 x i32> inreg %a, i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -3038,39 +3186,69 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
@@ -4774,8 +4952,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x9
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v66, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:16
@@ -4807,32 +4985,72 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v53, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v30, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v37, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v34, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v33, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v34, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
@@ -4875,8 +5093,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
@@ -4941,14 +5159,14 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v5.h, v5.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v26.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v32.l, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v36.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v5.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v35.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v10.h
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.l, v5.h
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v6.h
@@ -5916,177 +6134,371 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: s_branch .LBB15_2
;
-; GFX11-LABEL: bitcast_v40i8_to_v10i32_scalar:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s58, v22
-; GFX11-NEXT: v_readfirstlane_b32 s4, v21
-; GFX11-NEXT: v_readfirstlane_b32 s5, v20
-; GFX11-NEXT: v_readfirstlane_b32 s6, v19
-; GFX11-NEXT: v_readfirstlane_b32 s7, v18
-; GFX11-NEXT: v_readfirstlane_b32 s8, v17
-; GFX11-NEXT: v_readfirstlane_b32 s9, v16
-; GFX11-NEXT: v_readfirstlane_b32 s10, v15
-; GFX11-NEXT: v_readfirstlane_b32 s11, v14
-; GFX11-NEXT: v_readfirstlane_b32 s12, v13
-; GFX11-NEXT: v_readfirstlane_b32 s13, v12
-; GFX11-NEXT: v_readfirstlane_b32 s14, v11
-; GFX11-NEXT: v_readfirstlane_b32 s15, v10
-; GFX11-NEXT: v_readfirstlane_b32 s40, v9
-; GFX11-NEXT: v_readfirstlane_b32 s41, v8
-; GFX11-NEXT: v_readfirstlane_b32 s42, v7
-; GFX11-NEXT: v_readfirstlane_b32 s43, v6
-; GFX11-NEXT: v_readfirstlane_b32 s44, v5
-; GFX11-NEXT: v_readfirstlane_b32 s45, v4
-; GFX11-NEXT: v_readfirstlane_b32 s46, v3
-; GFX11-NEXT: v_readfirstlane_b32 s47, v2
-; GFX11-NEXT: v_readfirstlane_b32 s56, v1
-; GFX11-NEXT: v_readfirstlane_b32 s57, v0
-; GFX11-NEXT: s_cmp_lg_u32 s58, 0
-; GFX11-NEXT: s_mov_b32 s58, 0
-; GFX11-NEXT: s_cbranch_scc0 .LBB15_4
-; GFX11-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
-; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
-; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
-; GFX11-NEXT: s_cbranch_vccnz .LBB15_3
-; GFX11-NEXT: .LBB15_2: ; %cmp.true
-; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
-; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s57, s57, 3
-; GFX11-NEXT: s_add_i32 s47, s47, 3
-; GFX11-NEXT: s_add_i32 s45, s45, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: s_add_i32 s43, s43, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: s_add_i32 s11, s11, 3
-; GFX11-NEXT: s_add_i32 s9, s9, 3
-; GFX11-NEXT: s_add_i32 s7, s7, 3
-; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v6, s47, s46, v5
-; GFX11-NEXT: v_perm_b32 v7, s45, s44, v5
-; GFX11-NEXT: v_perm_b32 v8, s43, s42, v5
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v5
-; GFX11-NEXT: v_perm_b32 v11, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v5
-; GFX11-NEXT: v_perm_b32 v13, s9, s8, v5
-; GFX11-NEXT: v_perm_b32 v14, s7, s6, v5
-; GFX11-NEXT: v_perm_b32 v5, s5, s4, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v8, v12, v13
-; GFX11-NEXT: v_or_b32_e32 v9, v14, v15
-; GFX11-NEXT: .LBB15_3: ; %end
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT: .LBB15_4:
-; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT: s_branch .LBB15_2
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v10i32_scalar:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s58, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s58, 0
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB15_4
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s45, s44, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s43, s42, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s15, s14, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, s7, s6, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB15_3
+; GFX11-TRUE16-NEXT: .LBB15_2: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s57, s57, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s5, s4, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v10, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v15
+; GFX11-TRUE16-NEXT: .LBB15_3: ; %end
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB15_4:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT: s_branch .LBB15_2
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10i32_scalar:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v20
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v19
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v18
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v17
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v15
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s58, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s58, 0
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB15_4
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s45, s44, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s43, s42, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s15, s14, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, s7, s6, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB15_3
+; GFX11-FAKE16-NEXT: .LBB15_2: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s57, s57, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s5, s4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v15
+; GFX11-FAKE16-NEXT: .LBB15_3: ; %end
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB15_4:
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT: s_branch .LBB15_2
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
@@ -6111,9 +6523,23 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB16_3
+; SI-NEXT: ; %bb.1: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB16_4
+; SI-NEXT: .LBB16_2: ; %end
+; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: .LBB16_3: ; %cmp.false
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB16_2
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: .LBB16_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
@@ -6124,7 +6550,12 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: .LBB16_2: ; %end
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6134,9 +6565,23 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_4
+; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB16_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB16_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB16_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
@@ -6147,7 +6592,12 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6157,9 +6607,23 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_4
+; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB16_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB16_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB16_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
@@ -6170,7 +6634,12 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6180,10 +6649,23 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB16_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB16_4
+; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB16_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB16_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
@@ -6194,7 +6676,12 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6233,6 +6720,12 @@ define inreg <5 x double> @bitcast_v10i32_to_v5f64_scalar(<10 x i32> inreg %a, i
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB17_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -6266,6 +6759,12 @@ define inreg <5 x double> @bitcast_v10i32_to_v5f64_scalar(<10 x i32> inreg %a, i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB17_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -6299,6 +6798,12 @@ define inreg <5 x double> @bitcast_v10i32_to_v5f64_scalar(<10 x i32> inreg %a, i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB17_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -6334,6 +6839,12 @@ define inreg <5 x double> @bitcast_v10i32_to_v5f64_scalar(<10 x i32> inreg %a, i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB17_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -6592,9 +7103,23 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB20_3
+; SI-NEXT: ; %bb.1: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB20_4
+; SI-NEXT: .LBB20_2: ; %end
+; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: .LBB20_3: ; %cmp.false
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB20_2
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: .LBB20_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
@@ -6605,7 +7130,12 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: .LBB20_2: ; %end
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6615,9 +7145,23 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB20_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB20_4
+; VI-NEXT: .LBB20_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB20_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB20_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB20_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
@@ -6628,7 +7172,12 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB20_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6638,9 +7187,23 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB20_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB20_4
+; GFX9-NEXT: .LBB20_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB20_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB20_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB20_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
@@ -6651,7 +7214,12 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB20_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6661,10 +7229,23 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB20_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB20_4
+; GFX11-NEXT: .LBB20_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB20_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB20_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB20_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
@@ -6675,7 +7256,12 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB20_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6714,6 +7300,12 @@ define inreg <5 x i64> @bitcast_v10i32_to_v5i64_scalar(<10 x i32> inreg %a, i32
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB21_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -6747,6 +7339,12 @@ define inreg <5 x i64> @bitcast_v10i32_to_v5i64_scalar(<10 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB21_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -6780,6 +7378,12 @@ define inreg <5 x i64> @bitcast_v10i32_to_v5i64_scalar(<10 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB21_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -6815,6 +7419,12 @@ define inreg <5 x i64> @bitcast_v10i32_to_v5i64_scalar(<10 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB21_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -7195,9 +7805,23 @@ define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB24_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB24_4
+; VI-NEXT: .LBB24_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB24_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB24_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB24_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -7208,7 +7832,12 @@ define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB24_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -7218,9 +7847,23 @@ define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB24_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB24_4
+; GFX9-NEXT: .LBB24_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB24_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB24_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB24_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -7231,7 +7874,12 @@ define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB24_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -7241,15 +7889,34 @@ define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB24_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB24_4
+; GFX11-NEXT: .LBB24_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB24_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB24_2
+; GFX11-NEXT: .LBB24_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -7393,6 +8060,12 @@ define inreg <20 x i16> @bitcast_v10f32_to_v20i16_scalar(<10 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -7433,6 +8106,12 @@ define inreg <20 x i16> @bitcast_v10f32_to_v20i16_scalar(<10 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -7479,6 +8158,12 @@ define inreg <20 x i16> @bitcast_v10f32_to_v20i16_scalar(<10 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -8115,9 +8800,23 @@ define <20 x half> @bitcast_v10f32_to_v20f16(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB28_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB28_4
+; VI-NEXT: .LBB28_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB28_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB28_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB28_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -8128,7 +8827,12 @@ define <20 x half> @bitcast_v10f32_to_v20f16(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB28_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -8138,9 +8842,23 @@ define <20 x half> @bitcast_v10f32_to_v20f16(<10 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB28_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB28_4
+; GFX9-NEXT: .LBB28_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB28_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB28_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB28_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -8151,7 +8869,12 @@ define <20 x half> @bitcast_v10f32_to_v20f16(<10 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB28_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -8161,15 +8884,34 @@ define <20 x half> @bitcast_v10f32_to_v20f16(<10 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB28_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB28_4
+; GFX11-NEXT: .LBB28_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB28_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-NEXT: .LBB28_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -8313,6 +9055,12 @@ define inreg <20 x half> @bitcast_v10f32_to_v20f16_scalar(<10 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB29_3:
; VI-NEXT: s_branch .LBB29_2
@@ -8353,6 +9101,12 @@ define inreg <20 x half> @bitcast_v10f32_to_v20f16_scalar(<10 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB29_3:
; GFX9-NEXT: s_branch .LBB29_2
@@ -8399,6 +9153,12 @@ define inreg <20 x half> @bitcast_v10f32_to_v20f16_scalar(<10 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB29_3:
; GFX11-NEXT: s_branch .LBB29_2
@@ -9669,39 +10429,69 @@ define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
@@ -11494,8 +12284,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x9
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v66, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:16
@@ -11527,32 +12317,72 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v53, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v30, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v37, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v34, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v33, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v34, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
@@ -11595,8 +12425,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
@@ -11661,14 +12491,14 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v5.h, v5.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v26.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v32.l, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v36.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v5.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v35.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v10.h
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.l, v5.h
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v6.h
@@ -12636,177 +13466,371 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
; GFX9-NEXT: s_branch .LBB35_2
;
-; GFX11-LABEL: bitcast_v40i8_to_v10f32_scalar:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s58, v22
-; GFX11-NEXT: v_readfirstlane_b32 s4, v21
-; GFX11-NEXT: v_readfirstlane_b32 s5, v20
-; GFX11-NEXT: v_readfirstlane_b32 s6, v19
-; GFX11-NEXT: v_readfirstlane_b32 s7, v18
-; GFX11-NEXT: v_readfirstlane_b32 s8, v17
-; GFX11-NEXT: v_readfirstlane_b32 s9, v16
-; GFX11-NEXT: v_readfirstlane_b32 s10, v15
-; GFX11-NEXT: v_readfirstlane_b32 s11, v14
-; GFX11-NEXT: v_readfirstlane_b32 s12, v13
-; GFX11-NEXT: v_readfirstlane_b32 s13, v12
-; GFX11-NEXT: v_readfirstlane_b32 s14, v11
-; GFX11-NEXT: v_readfirstlane_b32 s15, v10
-; GFX11-NEXT: v_readfirstlane_b32 s40, v9
-; GFX11-NEXT: v_readfirstlane_b32 s41, v8
-; GFX11-NEXT: v_readfirstlane_b32 s42, v7
-; GFX11-NEXT: v_readfirstlane_b32 s43, v6
-; GFX11-NEXT: v_readfirstlane_b32 s44, v5
-; GFX11-NEXT: v_readfirstlane_b32 s45, v4
-; GFX11-NEXT: v_readfirstlane_b32 s46, v3
-; GFX11-NEXT: v_readfirstlane_b32 s47, v2
-; GFX11-NEXT: v_readfirstlane_b32 s56, v1
-; GFX11-NEXT: v_readfirstlane_b32 s57, v0
-; GFX11-NEXT: s_cmp_lg_u32 s58, 0
-; GFX11-NEXT: s_mov_b32 s58, 0
-; GFX11-NEXT: s_cbranch_scc0 .LBB35_4
-; GFX11-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
-; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
-; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
-; GFX11-NEXT: s_cbranch_vccnz .LBB35_3
-; GFX11-NEXT: .LBB35_2: ; %cmp.true
-; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
-; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s57, s57, 3
-; GFX11-NEXT: s_add_i32 s47, s47, 3
-; GFX11-NEXT: s_add_i32 s45, s45, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: s_add_i32 s43, s43, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: s_add_i32 s11, s11, 3
-; GFX11-NEXT: s_add_i32 s9, s9, 3
-; GFX11-NEXT: s_add_i32 s7, s7, 3
-; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v6, s47, s46, v5
-; GFX11-NEXT: v_perm_b32 v7, s45, s44, v5
-; GFX11-NEXT: v_perm_b32 v8, s43, s42, v5
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v5
-; GFX11-NEXT: v_perm_b32 v11, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v5
-; GFX11-NEXT: v_perm_b32 v13, s9, s8, v5
-; GFX11-NEXT: v_perm_b32 v14, s7, s6, v5
-; GFX11-NEXT: v_perm_b32 v5, s5, s4, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v8, v12, v13
-; GFX11-NEXT: v_or_b32_e32 v9, v14, v15
-; GFX11-NEXT: .LBB35_3: ; %end
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT: .LBB35_4:
-; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT: s_branch .LBB35_2
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v10f32_scalar:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s58, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s58, 0
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB35_4
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s45, s44, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s43, s42, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s15, s14, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, s7, s6, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB35_3
+; GFX11-TRUE16-NEXT: .LBB35_2: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s57, s57, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s5, s4, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v10, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v15
+; GFX11-TRUE16-NEXT: .LBB35_3: ; %end
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB35_4:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT: s_branch .LBB35_2
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10f32_scalar:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v20
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v19
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v18
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v17
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v15
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s58, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s58, 0
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB35_4
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s45, s44, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s43, s42, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s15, s14, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, s7, s6, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB35_3
+; GFX11-FAKE16-NEXT: .LBB35_2: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s57, s57, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s5, s4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v15
+; GFX11-FAKE16-NEXT: .LBB35_3: ; %end
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB35_4:
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT: s_branch .LBB35_2
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
@@ -12831,9 +13855,23 @@ define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB36_3
+; SI-NEXT: ; %bb.1: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB36_4
+; SI-NEXT: .LBB36_2: ; %end
+; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: .LBB36_3: ; %cmp.false
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB36_2
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: .LBB36_4: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -12844,7 +13882,12 @@ define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; SI-NEXT: .LBB36_2: ; %end
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -12854,9 +13897,23 @@ define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB36_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB36_4
+; VI-NEXT: .LBB36_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB36_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB36_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB36_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -12867,7 +13924,12 @@ define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB36_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -12877,9 +13939,23 @@ define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB36_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB36_4
+; GFX9-NEXT: .LBB36_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB36_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB36_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB36_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -12890,7 +13966,12 @@ define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB36_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -12900,15 +13981,34 @@ define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB36_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB36_4
+; GFX11-NEXT: .LBB36_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB36_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB36_2
+; GFX11-NEXT: .LBB36_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -12947,6 +14047,12 @@ define inreg <5 x double> @bitcast_v10f32_to_v5f64_scalar(<10 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB37_3:
; SI-NEXT: s_branch .LBB37_2
@@ -12987,6 +14093,12 @@ define inreg <5 x double> @bitcast_v10f32_to_v5f64_scalar(<10 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB37_3:
; VI-NEXT: s_branch .LBB37_2
@@ -13027,6 +14139,12 @@ define inreg <5 x double> @bitcast_v10f32_to_v5f64_scalar(<10 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB37_3:
; GFX9-NEXT: s_branch .LBB37_2
@@ -13073,6 +14191,12 @@ define inreg <5 x double> @bitcast_v10f32_to_v5f64_scalar(<10 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB37_3:
; GFX11-NEXT: s_branch .LBB37_2
@@ -13334,9 +14458,23 @@ define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB40_3
+; SI-NEXT: ; %bb.1: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB40_4
+; SI-NEXT: .LBB40_2: ; %end
+; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: .LBB40_3: ; %cmp.false
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB40_2
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: .LBB40_4: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -13347,7 +14485,12 @@ define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; SI-NEXT: .LBB40_2: ; %end
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -13357,9 +14500,23 @@ define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB40_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB40_4
+; VI-NEXT: .LBB40_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB40_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB40_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB40_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -13370,7 +14527,12 @@ define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB40_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -13380,9 +14542,23 @@ define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB40_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB40_4
+; GFX9-NEXT: .LBB40_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB40_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB40_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB40_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
@@ -13393,7 +14569,12 @@ define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB40_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -13403,15 +14584,34 @@ define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v10
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB40_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB40_4
+; GFX11-NEXT: .LBB40_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB40_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-NEXT: .LBB40_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -13450,6 +14650,12 @@ define inreg <5 x i64> @bitcast_v10f32_to_v5i64_scalar(<10 x float> inreg %a, i3
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB41_3:
; SI-NEXT: s_branch .LBB41_2
@@ -13490,6 +14696,12 @@ define inreg <5 x i64> @bitcast_v10f32_to_v5i64_scalar(<10 x float> inreg %a, i3
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB41_3:
; VI-NEXT: s_branch .LBB41_2
@@ -13530,6 +14742,12 @@ define inreg <5 x i64> @bitcast_v10f32_to_v5i64_scalar(<10 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB41_3:
; GFX9-NEXT: s_branch .LBB41_2
@@ -13576,6 +14794,12 @@ define inreg <5 x i64> @bitcast_v10f32_to_v5i64_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB41_3:
; GFX11-NEXT: s_branch .LBB41_2
@@ -14084,6 +15308,12 @@ define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v13
; VI-NEXT: v_or_b32_e32 v1, v1, v12
; VI-NEXT: v_or_b32_e32 v0, v0, v11
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB44_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -14107,6 +15337,12 @@ define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB44_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -14131,6 +15367,12 @@ define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB44_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -14383,6 +15625,12 @@ define inreg <20 x half> @bitcast_v20i16_to_v20f16_scalar(<20 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB45_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -14416,6 +15664,12 @@ define inreg <20 x half> @bitcast_v20i16_to_v20f16_scalar(<20 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB45_3:
; GFX9-NEXT: s_branch .LBB45_2
@@ -14462,6 +15716,12 @@ define inreg <20 x half> @bitcast_v20i16_to_v20f16_scalar(<20 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB45_3:
; GFX11-NEXT: s_branch .LBB45_2
@@ -14671,6 +15931,12 @@ define <20 x i16> @bitcast_v20f16_to_v20i16(<20 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v13, v2
; VI-NEXT: v_or_b32_e32 v1, v12, v1
; VI-NEXT: v_or_b32_e32 v0, v10, v0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB46_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -14695,6 +15961,12 @@ define <20 x i16> @bitcast_v20f16_to_v20i16(<20 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB46_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -14719,6 +15991,12 @@ define <20 x i16> @bitcast_v20f16_to_v20i16(<20 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB46_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -14959,6 +16237,12 @@ define inreg <20 x i16> @bitcast_v20f16_to_v20i16_scalar(<20 x half> inreg %a, i
; VI-NEXT: v_add_f16_e32 v0, s17, v0
; VI-NEXT: v_or_b32_e32 v1, v0, v1
; VI-NEXT: v_or_b32_e32 v0, v10, v11
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB47_3:
; VI-NEXT: s_branch .LBB47_2
@@ -15000,6 +16284,12 @@ define inreg <20 x i16> @bitcast_v20f16_to_v20i16_scalar(<20 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -15046,6 +16336,12 @@ define inreg <20 x i16> @bitcast_v20f16_to_v20i16_scalar(<20 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -15898,39 +17194,69 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
@@ -17543,6 +18869,12 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr37
@@ -17682,6 +19014,12 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v7, v12, v7
; VI-NEXT: v_or_b32_e32 v8, v11, v8
; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -17778,6 +19116,12 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v9, v41, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v10, v44, v43, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr34
@@ -17911,6 +19255,12 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v7, v12, v7, s6
; GFX9-NEXT: v_perm_b32 v8, v11, v8, s6
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s6
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB50_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -17933,48 +19283,43 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v6.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v32.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v33.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v34.h
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v70
@@ -17985,79 +19330,116 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v24, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v66, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v52, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v53, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v54, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v38, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v39, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v37, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v24, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v55, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v32.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v26, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v38, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v64, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v65, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v51, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v53, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v30, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v8.l, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v34, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v69, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v48, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v54, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v26, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v64, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v28, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v16.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v16.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v68, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
@@ -18065,96 +19447,93 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v68.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v32.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v68.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v50.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v54.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v28.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v16.l, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v16.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v52.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v53.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v30.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v67.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v55.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v33.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v48.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v54.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v26.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v55.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v21.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v36.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v24.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v53.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v28.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v36.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v37.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v67.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v38.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v65.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v35.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v22.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v52.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v22.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v26.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v20.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v18.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v10.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v20.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v49.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v10.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v11.l, v1.h
@@ -18165,6 +19544,12 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v10.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v10.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -18246,6 +19631,12 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v13, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v10, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v14, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
@@ -18399,6 +19790,12 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v12, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v11, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -18877,6 +20274,12 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_perm_b32 v9, s63, v11, v9
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s63, s63, 3
@@ -18980,6 +20383,12 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB51_4:
@@ -19083,6 +20492,12 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s4
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s63, s63, 3
@@ -19186,6 +20601,12 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_lshl_or_b32 v6, v6, 16, v11
; GFX9-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB51_3: ; %end
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB51_4:
@@ -19196,34 +20617,56 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s58, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s58, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_and_b32 s59, s43, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s59, s14, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s60, s8, 8
; GFX11-TRUE16-NEXT: s_lshl_b32 s61, s4, 8
; GFX11-TRUE16-NEXT: s_or_b32 s59, s59, s60
@@ -19236,15 +20679,15 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s45, s14, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s47, s46, v8
; GFX11-TRUE16-NEXT: s_and_b32 s60, s6, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s42, s13, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s10, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s44, s41, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s12, v8
; GFX11-TRUE16-NEXT: s_or_b32 s60, s60, s61
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s9, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s62, s11, 0xff
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s10, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s62, s9, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s61, s7, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
@@ -19253,57 +20696,63 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s57, s56, v8
; GFX11-TRUE16-NEXT: s_or_b32 s60, s62, s61
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s47, s44, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s45, s43, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s41, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s42, s15, v8
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s15, s5, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s11, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s59
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s15, s5, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s11, s5, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s6, s4, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s11, s7, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s9, s7, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s46, s41, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s42, s15, v0
; GFX11-TRUE16-NEXT: s_add_i32 s57, s57, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s12, s9, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s47, s44, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s13, s10, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s45, s43, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s57, s56, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s28, s29, v0
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s43, s8, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s8, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s45, s14, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s47, s46, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s20, s21, v0
; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s10, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s42, s13, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s12, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s41, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s26, s27, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v1
@@ -19335,6 +20784,12 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v11.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: .LBB51_3: ; %end
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB51_4:
@@ -19418,6 +20873,12 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s59
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-FAKE16-NEXT: .LBB51_2: ; %cmp.true
@@ -19502,6 +20963,12 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v11, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v9, 16, v16
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: .LBB51_3: ; %end
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB51_4:
@@ -19590,6 +21057,12 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v7, v7, v28
; SI-NEXT: v_or_b32_e32 v8, v8, v27
; SI-NEXT: v_or_b32_e32 v9, v9, v26
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
@@ -19654,6 +21127,12 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -19697,6 +21176,12 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v10, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v10, v0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB52_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -19720,6 +21205,12 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB52_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -19744,6 +21235,12 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB52_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -19823,6 +21320,12 @@ define inreg <5 x double> @bitcast_v20i16_to_v5f64_scalar(<20 x i16> inreg %a, i
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s45, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB53_3
; SI-NEXT: .LBB53_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -19875,6 +21378,12 @@ define inreg <5 x double> @bitcast_v20i16_to_v5f64_scalar(<20 x i16> inreg %a, i
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s45, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB53_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -19961,6 +21470,12 @@ define inreg <5 x double> @bitcast_v20i16_to_v5f64_scalar(<20 x i16> inreg %a, i
; VI-NEXT: s_and_b32 s5, s5, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB53_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -19994,6 +21509,12 @@ define inreg <5 x double> @bitcast_v20i16_to_v5f64_scalar(<20 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB53_3:
; GFX9-NEXT: s_branch .LBB53_2
@@ -20040,6 +21561,12 @@ define inreg <5 x double> @bitcast_v20i16_to_v5f64_scalar(<20 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB53_3:
; GFX11-NEXT: s_branch .LBB53_2
@@ -20166,6 +21693,12 @@ define <20 x i16> @bitcast_v5f64_to_v20i16(<5 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB54_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -20184,6 +21717,12 @@ define <20 x i16> @bitcast_v5f64_to_v20i16(<5 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB54_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -20203,6 +21742,12 @@ define <20 x i16> @bitcast_v5f64_to_v20i16(<5 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB54_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -20337,6 +21882,12 @@ define inreg <20 x i16> @bitcast_v5f64_to_v20i16_scalar(<5 x double> inreg %a, i
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB55_3:
; VI-NEXT: s_branch .LBB55_2
@@ -20372,6 +21923,12 @@ define inreg <20 x i16> @bitcast_v5f64_to_v20i16_scalar(<5 x double> inreg %a, i
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -20413,6 +21970,12 @@ define inreg <20 x i16> @bitcast_v5f64_to_v20i16_scalar(<5 x double> inreg %a, i
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
@@ -20509,6 +22072,12 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v7, v7, v28
; SI-NEXT: v_or_b32_e32 v8, v8, v27
; SI-NEXT: v_or_b32_e32 v9, v9, v26
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
@@ -20573,6 +22142,12 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -20616,6 +22191,12 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v10, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v10, v0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB56_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -20639,6 +22220,12 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB56_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -20663,6 +22250,12 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB56_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -20742,6 +22335,12 @@ define inreg <5 x i64> @bitcast_v20i16_to_v5i64_scalar(<20 x i16> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s45, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB57_3
; SI-NEXT: .LBB57_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -20794,6 +22393,12 @@ define inreg <5 x i64> @bitcast_v20i16_to_v5i64_scalar(<20 x i16> inreg %a, i32
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s45, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB57_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -20880,6 +22485,12 @@ define inreg <5 x i64> @bitcast_v20i16_to_v5i64_scalar(<20 x i16> inreg %a, i32
; VI-NEXT: s_and_b32 s5, s5, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB57_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -20913,6 +22524,12 @@ define inreg <5 x i64> @bitcast_v20i16_to_v5i64_scalar(<20 x i16> inreg %a, i32
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB57_3:
; GFX9-NEXT: s_branch .LBB57_2
@@ -20959,6 +22576,12 @@ define inreg <5 x i64> @bitcast_v20i16_to_v5i64_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB57_3:
; GFX11-NEXT: s_branch .LBB57_2
@@ -21095,6 +22718,12 @@ define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB58_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -21118,6 +22747,12 @@ define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB58_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -21145,6 +22780,12 @@ define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB58_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -21277,6 +22918,12 @@ define inreg <20 x i16> @bitcast_v5i64_to_v20i16_scalar(<5 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB59_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -21310,6 +22957,12 @@ define inreg <20 x i16> @bitcast_v5i64_to_v20i16_scalar(<5 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB59_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -21345,6 +22998,12 @@ define inreg <20 x i16> @bitcast_v5i64_to_v20i16_scalar(<5 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB59_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -22178,39 +23837,69 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: .LBB60_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
@@ -23885,6 +25574,12 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr37
@@ -24024,6 +25719,12 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v7, v12, v7
; VI-NEXT: v_or_b32_e32 v8, v11, v8
; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB62_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -24120,6 +25821,12 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v9, v41, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_perm_b32 v10, v44, v43, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr34
@@ -24253,6 +25960,12 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v7, v12, v7, s6
; GFX9-NEXT: v_perm_b32 v8, v11, v8, s6
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s6
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB62_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -24275,48 +25988,43 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v6.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v32.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v33.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v34.h
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v70
@@ -24327,79 +26035,116 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB62_4
; GFX11-TRUE16-NEXT: .LBB62_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB62_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v24, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v22, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v66, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v52, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v53, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v54, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v38, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v33, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v39, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v37, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v24, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v55, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v32.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v26, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v38, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v64, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v65, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v51, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v53, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v30, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v8.l, v17.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v34, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v69, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v48, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v54, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v26, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v64, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v28, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v16.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v16.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v68, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v11.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
@@ -24407,96 +26152,93 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB62_2
; GFX11-TRUE16-NEXT: .LBB62_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v68.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v32.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v68.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v50.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v54.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v28.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v16.l, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v16.h, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v52.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v53.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v30.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v67.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v55.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v35.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v33.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v48.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v54.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v26.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v55.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v21.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v37.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v36.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v24.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v53.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v28.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v18.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v36.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v37.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v67.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v38.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v65.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v39.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v35.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v22.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v52.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v22.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v26.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v24.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v21.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v19.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v20.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v18.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v19.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v10.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v20.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v49.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v10.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v11.l, v1.h
@@ -24507,6 +26249,12 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v10.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v10.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -24588,6 +26336,12 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v13, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v10, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v11, v14, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
@@ -24741,6 +26495,12 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v12, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v11, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -25219,6 +26979,12 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_perm_b32 v9, s63, v11, v9
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_cbranch_execnz .LBB63_3
; VI-NEXT: .LBB63_2: ; %cmp.true
; VI-NEXT: s_add_i32 s63, s63, 3
@@ -25322,6 +27088,12 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB63_3: ; %end
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB63_4:
@@ -25425,6 +27197,12 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s4
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_cbranch_execnz .LBB63_3
; GFX9-NEXT: .LBB63_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s63, s63, 3
@@ -25528,6 +27306,12 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_lshl_or_b32 v6, v6, 16, v11
; GFX9-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB63_3: ; %end
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB63_4:
@@ -25538,34 +27322,56 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s58, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s58, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB63_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_and_b32 s59, s43, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s59, s14, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s60, s8, 8
; GFX11-TRUE16-NEXT: s_lshl_b32 s61, s4, 8
; GFX11-TRUE16-NEXT: s_or_b32 s59, s59, s60
@@ -25578,15 +27384,15 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s45, s14, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s47, s46, v8
; GFX11-TRUE16-NEXT: s_and_b32 s60, s6, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s42, s13, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s10, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s44, s41, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s12, v8
; GFX11-TRUE16-NEXT: s_or_b32 s60, s60, s61
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s9, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s62, s11, 0xff
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s10, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s62, s9, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s61, s7, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
@@ -25595,57 +27401,63 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s57, s56, v8
; GFX11-TRUE16-NEXT: s_or_b32 s60, s62, s61
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s47, s44, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s45, s43, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s41, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s42, s15, v8
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s15, s5, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s11, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s59
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB63_3
; GFX11-TRUE16-NEXT: .LBB63_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s15, s5, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s11, s5, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s6, s4, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s11, s7, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s9, s7, v0
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s46, s41, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s42, s15, v0
; GFX11-TRUE16-NEXT: s_add_i32 s57, s57, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s12, s9, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s47, s44, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s13, s10, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s45, s43, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s57, s56, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s28, s29, v0
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s43, s8, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s8, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s45, s14, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s47, s46, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s20, s21, v0
; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s10, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s42, s13, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s12, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s41, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s26, s27, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v1
@@ -25677,6 +27489,12 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v11.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: .LBB63_3: ; %end
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB63_4:
@@ -25760,6 +27578,12 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s59
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB63_3
; GFX11-FAKE16-NEXT: .LBB63_2: ; %cmp.true
@@ -25844,6 +27668,12 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v11, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v9, 16, v16
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: .LBB63_3: ; %end
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB63_4:
@@ -25932,6 +27762,12 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v26
; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
@@ -26035,6 +27871,12 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT: v_or_b32_e32 v9, v11, v9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -26078,6 +27920,12 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v11
; VI-NEXT: v_or_b32_e32 v0, v0, v10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB64_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -26102,6 +27950,12 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB64_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -26126,6 +27980,12 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB64_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -26205,6 +28065,12 @@ define inreg <5 x double> @bitcast_v20f16_to_v5f64_scalar(<20 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s45, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr47
+; SI-NEXT: ; implicit-def: $sgpr48
+; SI-NEXT: ; implicit-def: $sgpr49
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
; SI-NEXT: s_cbranch_execnz .LBB65_4
; SI-NEXT: .LBB65_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s15
@@ -26287,6 +28153,12 @@ define inreg <5 x double> @bitcast_v20f16_to_v5f64_scalar(<20 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT: v_or_b32_e32 v9, v11, v9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_branch .LBB65_5
; SI-NEXT: .LBB65_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
@@ -26382,6 +28254,12 @@ define inreg <5 x double> @bitcast_v20f16_to_v5f64_scalar(<20 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v10, v10, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, s16, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB65_3:
; VI-NEXT: s_branch .LBB65_2
@@ -26423,6 +28301,12 @@ define inreg <5 x double> @bitcast_v20f16_to_v5f64_scalar(<20 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB65_3:
; GFX9-NEXT: s_branch .LBB65_2
@@ -26469,6 +28353,12 @@ define inreg <5 x double> @bitcast_v20f16_to_v5f64_scalar(<20 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB65_3:
; GFX11-NEXT: s_branch .LBB65_2
@@ -26595,6 +28485,12 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB66_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -26613,6 +28509,12 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB66_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -26632,6 +28534,12 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB66_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -26766,6 +28674,12 @@ define inreg <20 x half> @bitcast_v5f64_to_v20f16_scalar(<5 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB67_3:
; VI-NEXT: s_branch .LBB67_2
@@ -26801,6 +28715,12 @@ define inreg <20 x half> @bitcast_v5f64_to_v20f16_scalar(<5 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB67_3:
; GFX9-NEXT: s_branch .LBB67_2
@@ -26842,6 +28762,12 @@ define inreg <20 x half> @bitcast_v5f64_to_v20f16_scalar(<5 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB67_3:
; GFX11-NEXT: s_branch .LBB67_2
@@ -26938,6 +28864,12 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v26
; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr23
@@ -27041,6 +28973,12 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT: v_or_b32_e32 v9, v11, v9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -27084,6 +29022,12 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v11
; VI-NEXT: v_or_b32_e32 v0, v0, v10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB68_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -27108,6 +29052,12 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB68_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -27132,6 +29082,12 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB68_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -27211,6 +29167,12 @@ define inreg <5 x i64> @bitcast_v20f16_to_v5i64_scalar(<20 x half> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s45, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr46
+; SI-NEXT: ; implicit-def: $sgpr47
+; SI-NEXT: ; implicit-def: $sgpr48
+; SI-NEXT: ; implicit-def: $sgpr49
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
; SI-NEXT: s_cbranch_execnz .LBB69_4
; SI-NEXT: .LBB69_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s15
@@ -27293,6 +29255,12 @@ define inreg <5 x i64> @bitcast_v20f16_to_v5i64_scalar(<20 x half> inreg %a, i32
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
; SI-NEXT: v_or_b32_e32 v9, v11, v9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_branch .LBB69_5
; SI-NEXT: .LBB69_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
@@ -27388,6 +29356,12 @@ define inreg <5 x i64> @bitcast_v20f16_to_v5i64_scalar(<20 x half> inreg %a, i32
; VI-NEXT: v_add_f16_sdwa v10, v10, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, s16, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB69_3:
; VI-NEXT: s_branch .LBB69_2
@@ -27429,6 +29403,12 @@ define inreg <5 x i64> @bitcast_v20f16_to_v5i64_scalar(<20 x half> inreg %a, i32
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB69_3:
; GFX9-NEXT: s_branch .LBB69_2
@@ -27475,6 +29455,12 @@ define inreg <5 x i64> @bitcast_v20f16_to_v5i64_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB69_3:
; GFX11-NEXT: s_branch .LBB69_2
@@ -27611,6 +29597,12 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB70_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -27634,6 +29626,12 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB70_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -27661,6 +29659,12 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB70_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -27793,6 +29797,12 @@ define inreg <20 x half> @bitcast_v5i64_to_v20f16_scalar(<5 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB71_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -27826,6 +29836,12 @@ define inreg <20 x half> @bitcast_v5i64_to_v20f16_scalar(<5 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB71_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -27861,6 +29877,12 @@ define inreg <20 x half> @bitcast_v5i64_to_v20f16_scalar(<5 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB71_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -28023,6 +30045,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v10, v17, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr33
@@ -28180,6 +30208,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: .LBB72_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -28281,6 +30315,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v9, v42, v41, s6
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -28417,6 +30457,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v10, 0x300, v10
; VI-NEXT: v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB72_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -28506,6 +30552,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v9, v42, v41, s6
; GFX9-NEXT: v_perm_b32 v10, v40, v55, s6
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
@@ -28642,6 +30694,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB72_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -28660,8 +30718,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x9
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v80, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:16
@@ -28669,12 +30727,11 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v14.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v11.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v10.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v8.l
@@ -28700,37 +30757,83 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB72_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v71, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v67, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v53, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v52, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v49, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v48, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v53, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v30, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v37, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v34, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v33, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v34, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
@@ -28742,12 +30845,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
@@ -28768,8 +30871,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB72_2
@@ -28795,13 +30898,13 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v54.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v16.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v3.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v22.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v23.l
@@ -28809,7 +30912,7 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v3.l, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v4.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v48.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v6.l
@@ -28834,14 +30937,14 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v5.h, v5.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v26.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v32.l, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v36.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v5.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v35.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v10.h
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.l, v5.h
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v6.h
@@ -28878,6 +30981,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v10.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -28949,6 +31058,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
@@ -29124,6 +31239,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -29279,6 +31400,12 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s5, s45, s5
; SI-NEXT: s_or_b32 s45, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB73_3
; SI-NEXT: .LBB73_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -29411,6 +31538,12 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s45, s4, 0x3000000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB73_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -29533,6 +31666,12 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_cbranch_execnz .LBB73_3
; VI-NEXT: .LBB73_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -29636,6 +31775,12 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB73_3: ; %end
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB73_4:
@@ -29736,6 +31881,12 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_cbranch_execnz .LBB73_3
; GFX9-NEXT: .LBB73_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -29830,183 +31981,407 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT: v_add_u32_sdwa v9, v9, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB73_3: ; %end
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB73_4:
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_branch .LBB73_2
;
-; GFX11-LABEL: bitcast_v40i8_to_v5f64_scalar:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s58, v22
-; GFX11-NEXT: v_readfirstlane_b32 s4, v21
-; GFX11-NEXT: v_readfirstlane_b32 s5, v20
-; GFX11-NEXT: v_readfirstlane_b32 s6, v19
-; GFX11-NEXT: v_readfirstlane_b32 s7, v18
-; GFX11-NEXT: v_readfirstlane_b32 s8, v17
-; GFX11-NEXT: v_readfirstlane_b32 s9, v16
-; GFX11-NEXT: v_readfirstlane_b32 s10, v15
-; GFX11-NEXT: v_readfirstlane_b32 s11, v14
-; GFX11-NEXT: v_readfirstlane_b32 s12, v13
-; GFX11-NEXT: v_readfirstlane_b32 s13, v12
-; GFX11-NEXT: v_readfirstlane_b32 s14, v11
-; GFX11-NEXT: v_readfirstlane_b32 s15, v10
-; GFX11-NEXT: v_readfirstlane_b32 s40, v9
-; GFX11-NEXT: v_readfirstlane_b32 s41, v8
-; GFX11-NEXT: v_readfirstlane_b32 s42, v7
-; GFX11-NEXT: v_readfirstlane_b32 s43, v6
-; GFX11-NEXT: v_readfirstlane_b32 s44, v5
-; GFX11-NEXT: v_readfirstlane_b32 s45, v4
-; GFX11-NEXT: v_readfirstlane_b32 s46, v3
-; GFX11-NEXT: v_readfirstlane_b32 s47, v2
-; GFX11-NEXT: v_readfirstlane_b32 s56, v1
-; GFX11-NEXT: v_readfirstlane_b32 s57, v0
-; GFX11-NEXT: s_cmp_lg_u32 s58, 0
-; GFX11-NEXT: s_mov_b32 s58, 0
-; GFX11-NEXT: s_cbranch_scc0 .LBB73_4
-; GFX11-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
-; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
-; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
-; GFX11-NEXT: s_cbranch_vccnz .LBB73_3
-; GFX11-NEXT: .LBB73_2: ; %cmp.true
-; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
-; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s57, s57, 3
-; GFX11-NEXT: s_add_i32 s47, s47, 3
-; GFX11-NEXT: s_add_i32 s45, s45, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: s_add_i32 s43, s43, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: s_add_i32 s11, s11, 3
-; GFX11-NEXT: s_add_i32 s9, s9, 3
-; GFX11-NEXT: s_add_i32 s7, s7, 3
-; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v6, s47, s46, v5
-; GFX11-NEXT: v_perm_b32 v7, s45, s44, v5
-; GFX11-NEXT: v_perm_b32 v8, s43, s42, v5
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v5
-; GFX11-NEXT: v_perm_b32 v11, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v5
-; GFX11-NEXT: v_perm_b32 v13, s9, s8, v5
-; GFX11-NEXT: v_perm_b32 v14, s7, s6, v5
-; GFX11-NEXT: v_perm_b32 v5, s5, s4, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v8, v12, v13
-; GFX11-NEXT: v_or_b32_e32 v9, v14, v15
-; GFX11-NEXT: .LBB73_3: ; %end
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT: .LBB73_4:
-; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT: s_branch .LBB73_2
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v5f64_scalar:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s58, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s58, 0
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB73_4
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s45, s44, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s43, s42, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s15, s14, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, s7, s6, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB73_3
+; GFX11-TRUE16-NEXT: .LBB73_2: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s57, s57, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s5, s4, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v10, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: .LBB73_3: ; %end
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB73_4:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT: s_branch .LBB73_2
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5f64_scalar:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v20
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v19
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v18
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v17
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v15
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s58, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s58, 0
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB73_4
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s45, s44, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s43, s42, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s15, s14, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, s7, s6, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB73_3
+; GFX11-FAKE16-NEXT: .LBB73_2: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s57, s57, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s5, s4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v15
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: .LBB73_3: ; %end
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB73_4:
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT: s_branch .LBB73_2
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
@@ -30661,39 +33036,69 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: .LBB74_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
@@ -31870,6 +34275,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v10, v17, v10
; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr33
@@ -32027,6 +34438,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: .LBB76_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -32128,6 +34545,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v9, v42, v41, s6
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -32264,6 +34687,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v10, 0x300, v10
; VI-NEXT: v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB76_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -32353,6 +34782,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v9, v42, v41, s6
; GFX9-NEXT: v_perm_b32 v10, v40, v55, s6
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
@@ -32489,6 +34924,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB76_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -32507,8 +34948,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x9
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_b32 v80, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:16
@@ -32516,12 +34957,11 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v14.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v11.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v10.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v8.l
@@ -32547,37 +34987,83 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB76_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v71, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v67, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v53, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v52, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v49, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v48, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v53, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v30, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v37, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v34, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v33, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v34, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
@@ -32589,12 +35075,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
@@ -32615,8 +35101,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB76_2
@@ -32642,13 +35128,13 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v3.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v54.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, v52.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v49.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v48.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, v16.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v2.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v51.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v3.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v22.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v23.l
@@ -32656,7 +35142,7 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v3.l, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v4.l, v3.h
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v48.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v17.l
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v6.l
@@ -32681,14 +35167,14 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v5.h, v5.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v26.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v34.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v32.l, 3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v36.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v9.l
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v5.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v35.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v10.h
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.l, v5.h
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v6.h
@@ -32725,6 +35211,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v9.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v10.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -32796,6 +35288,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
@@ -32971,6 +35469,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -33126,6 +35630,12 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_or_b32 s5, s45, s5
; SI-NEXT: s_or_b32 s45, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB77_3
; SI-NEXT: .LBB77_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -33258,6 +35768,12 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; SI-NEXT: s_or_b32 s5, s5, s6
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s45, s4, 0x3000000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB77_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -33380,6 +35896,12 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_cbranch_execnz .LBB77_3
; VI-NEXT: .LBB77_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -33483,6 +36005,12 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB77_3: ; %end
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB77_4:
@@ -33583,6 +36111,12 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_cbranch_execnz .LBB77_3
; GFX9-NEXT: .LBB77_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -33677,183 +36211,407 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT: v_add_u32_sdwa v9, v9, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB77_3: ; %end
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB77_4:
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-NEXT: s_branch .LBB77_2
;
-; GFX11-LABEL: bitcast_v40i8_to_v5i64_scalar:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s58, v22
-; GFX11-NEXT: v_readfirstlane_b32 s4, v21
-; GFX11-NEXT: v_readfirstlane_b32 s5, v20
-; GFX11-NEXT: v_readfirstlane_b32 s6, v19
-; GFX11-NEXT: v_readfirstlane_b32 s7, v18
-; GFX11-NEXT: v_readfirstlane_b32 s8, v17
-; GFX11-NEXT: v_readfirstlane_b32 s9, v16
-; GFX11-NEXT: v_readfirstlane_b32 s10, v15
-; GFX11-NEXT: v_readfirstlane_b32 s11, v14
-; GFX11-NEXT: v_readfirstlane_b32 s12, v13
-; GFX11-NEXT: v_readfirstlane_b32 s13, v12
-; GFX11-NEXT: v_readfirstlane_b32 s14, v11
-; GFX11-NEXT: v_readfirstlane_b32 s15, v10
-; GFX11-NEXT: v_readfirstlane_b32 s40, v9
-; GFX11-NEXT: v_readfirstlane_b32 s41, v8
-; GFX11-NEXT: v_readfirstlane_b32 s42, v7
-; GFX11-NEXT: v_readfirstlane_b32 s43, v6
-; GFX11-NEXT: v_readfirstlane_b32 s44, v5
-; GFX11-NEXT: v_readfirstlane_b32 s45, v4
-; GFX11-NEXT: v_readfirstlane_b32 s46, v3
-; GFX11-NEXT: v_readfirstlane_b32 s47, v2
-; GFX11-NEXT: v_readfirstlane_b32 s56, v1
-; GFX11-NEXT: v_readfirstlane_b32 s57, v0
-; GFX11-NEXT: s_cmp_lg_u32 s58, 0
-; GFX11-NEXT: s_mov_b32 s58, 0
-; GFX11-NEXT: s_cbranch_scc0 .LBB77_4
-; GFX11-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
-; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
-; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
-; GFX11-NEXT: s_cbranch_vccnz .LBB77_3
-; GFX11-NEXT: .LBB77_2: ; %cmp.true
-; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
-; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s57, s57, 3
-; GFX11-NEXT: s_add_i32 s47, s47, 3
-; GFX11-NEXT: s_add_i32 s45, s45, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: s_add_i32 s43, s43, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: s_add_i32 s11, s11, 3
-; GFX11-NEXT: s_add_i32 s9, s9, 3
-; GFX11-NEXT: s_add_i32 s7, s7, 3
-; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v6, s47, s46, v5
-; GFX11-NEXT: v_perm_b32 v7, s45, s44, v5
-; GFX11-NEXT: v_perm_b32 v8, s43, s42, v5
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v5
-; GFX11-NEXT: v_perm_b32 v11, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v5
-; GFX11-NEXT: v_perm_b32 v13, s9, s8, v5
-; GFX11-NEXT: v_perm_b32 v14, s7, s6, v5
-; GFX11-NEXT: v_perm_b32 v5, s5, s4, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v8, v12, v13
-; GFX11-NEXT: v_or_b32_e32 v9, v14, v15
-; GFX11-NEXT: .LBB77_3: ; %end
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-; GFX11-NEXT: .LBB77_4:
-; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT: s_branch .LBB77_2
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v5i64_scalar:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s58, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s58, 0
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB77_4
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s45, s44, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s43, s42, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s15, s14, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, s7, s6, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB77_3
+; GFX11-TRUE16-NEXT: .LBB77_2: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s57, s57, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s5, s4, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v10, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-TRUE16-NEXT: .LBB77_3: ; %end
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB77_4:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT: s_branch .LBB77_2
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5i64_scalar:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v22
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v21
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v20
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v19
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v18
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v17
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v16
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v15
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s58, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s58, 0
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB77_4
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s45, s44, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s43, s42, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s15, s14, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, s7, s6, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB77_3
+; GFX11-FAKE16-NEXT: .LBB77_2: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s57, s57, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s5, s4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v15
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT: .LBB77_3: ; %end
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB77_4:
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT: s_branch .LBB77_2
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
@@ -34531,39 +37289,69 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: .LBB78_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
@@ -35560,6 +38348,12 @@ define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: .LBB80_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -35578,6 +38372,12 @@ define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB80_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -35596,6 +38396,12 @@ define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB80_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -35615,6 +38421,12 @@ define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB80_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -35649,6 +38461,12 @@ define inreg <5 x i64> @bitcast_v5f64_to_v5i64_scalar(<5 x double> inreg %a, i32
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB81_3:
; SI-NEXT: s_branch .LBB81_2
@@ -35684,6 +38502,12 @@ define inreg <5 x i64> @bitcast_v5f64_to_v5i64_scalar(<5 x double> inreg %a, i32
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB81_3:
; VI-NEXT: s_branch .LBB81_2
@@ -35719,6 +38543,12 @@ define inreg <5 x i64> @bitcast_v5f64_to_v5i64_scalar(<5 x double> inreg %a, i32
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB81_3:
; GFX9-NEXT: s_branch .LBB81_2
@@ -35760,6 +38590,12 @@ define inreg <5 x i64> @bitcast_v5f64_to_v5i64_scalar(<5 x double> inreg %a, i32
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB81_3:
; GFX11-NEXT: s_branch .LBB81_2
@@ -35810,6 +38646,12 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: .LBB82_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -35833,6 +38675,12 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: .LBB82_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -35856,6 +38704,12 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: ; implicit-def: $vgpr10
; GFX9-NEXT: .LBB82_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -35883,6 +38737,12 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: ; implicit-def: $vgpr10
; GFX11-NEXT: .LBB82_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -35922,6 +38782,12 @@ define inreg <5 x double> @bitcast_v5i64_to_v5f64_scalar(<5 x i64> inreg %a, i32
; SI-NEXT: s_addc_u32 s23, s23, 0
; SI-NEXT: s_add_u32 s24, s24, 3
; SI-NEXT: s_addc_u32 s25, s25, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB83_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -35955,6 +38821,12 @@ define inreg <5 x double> @bitcast_v5i64_to_v5f64_scalar(<5 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s23, s23, 0
; VI-NEXT: s_add_u32 s24, s24, 3
; VI-NEXT: s_addc_u32 s25, s25, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB83_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -35988,6 +38860,12 @@ define inreg <5 x double> @bitcast_v5i64_to_v5f64_scalar(<5 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s23, s23, 0
; GFX9-NEXT: s_add_u32 s24, s24, 3
; GFX9-NEXT: s_addc_u32 s25, s25, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB83_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -36023,6 +38901,12 @@ define inreg <5 x double> @bitcast_v5i64_to_v5f64_scalar(<5 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s19, s19, 0
; GFX11-NEXT: s_add_u32 s20, s20, 3
; GFX11-NEXT: s_addc_u32 s21, s21, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB83_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index 123d1042e27c9..fdaf2a089ed16 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -2310,7 +2310,11 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB22_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v5, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
@@ -4573,7 +4577,11 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v5, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
@@ -6554,7 +6562,11 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB58_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v5, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
@@ -8213,7 +8225,11 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB70_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v5, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
@@ -9656,7 +9672,11 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB78_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v5, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
@@ -10340,7 +10360,11 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB82_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v5, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
index 79c9fc7faf339..189ddca5830e4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
@@ -645,9 +645,22 @@ define <22 x i16> @bitcast_v11i32_to_v22i16(<11 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_4
+; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB4_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB4_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB4_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
@@ -659,7 +672,11 @@ define <22 x i16> @bitcast_v11i32_to_v22i16(<11 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -669,9 +686,22 @@ define <22 x i16> @bitcast_v11i32_to_v22i16(<11 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_4
+; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB4_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB4_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB4_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
@@ -683,7 +713,11 @@ define <22 x i16> @bitcast_v11i32_to_v22i16(<11 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -693,10 +727,22 @@ define <22 x i16> @bitcast_v11i32_to_v22i16(<11 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v11
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB4_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB4_4
+; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB4_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB4_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB4_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
@@ -708,7 +754,11 @@ define <22 x i16> @bitcast_v11i32_to_v22i16(<11 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -849,6 +899,11 @@ define inreg <22 x i16> @bitcast_v11i32_to_v22i16_scalar(<11 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -884,6 +939,11 @@ define inreg <22 x i16> @bitcast_v11i32_to_v22i16_scalar(<11 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -921,6 +981,11 @@ define inreg <22 x i16> @bitcast_v11i32_to_v22i16_scalar(<11 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1598,9 +1663,22 @@ define <22 x half> @bitcast_v11i32_to_v22f16(<11 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_4
+; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB8_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB8_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB8_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
@@ -1612,7 +1690,11 @@ define <22 x half> @bitcast_v11i32_to_v22f16(<11 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1622,9 +1704,22 @@ define <22 x half> @bitcast_v11i32_to_v22f16(<11 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_4
+; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB8_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB8_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB8_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
@@ -1636,7 +1731,11 @@ define <22 x half> @bitcast_v11i32_to_v22f16(<11 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1646,10 +1745,22 @@ define <22 x half> @bitcast_v11i32_to_v22f16(<11 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v11
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB8_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB8_4
+; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB8_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB8_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB8_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
@@ -1661,7 +1772,11 @@ define <22 x half> @bitcast_v11i32_to_v22f16(<11 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1802,6 +1917,11 @@ define inreg <22 x half> @bitcast_v11i32_to_v22f16_scalar(<11 x i32> inreg %a, i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1837,6 +1957,11 @@ define inreg <22 x half> @bitcast_v11i32_to_v22f16_scalar(<11 x i32> inreg %a, i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1874,6 +1999,11 @@ define inreg <22 x half> @bitcast_v11i32_to_v22f16_scalar(<11 x i32> inreg %a, i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2632,9 +2762,22 @@ define <22 x i16> @bitcast_v11f32_to_v22i16(<11 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_4
+; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB12_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB12_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB12_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
@@ -2646,7 +2789,11 @@ define <22 x i16> @bitcast_v11f32_to_v22i16(<11 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2656,9 +2803,22 @@ define <22 x i16> @bitcast_v11f32_to_v22i16(<11 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_4
+; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB12_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB12_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB12_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
@@ -2670,7 +2830,11 @@ define <22 x i16> @bitcast_v11f32_to_v22i16(<11 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -2680,16 +2844,33 @@ define <22 x i16> @bitcast_v11f32_to_v22i16(<11 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v11
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB12_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB12_4
+; GFX11-NEXT: .LBB12_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB12_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-NEXT: .LBB12_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v9, 1.0, v9
; GFX11-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7
; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2843,6 +3024,11 @@ define inreg <22 x i16> @bitcast_v11f32_to_v22i16_scalar(<11 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB13_3:
; VI-NEXT: s_branch .LBB13_2
@@ -2884,6 +3070,11 @@ define inreg <22 x i16> @bitcast_v11f32_to_v22i16_scalar(<11 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB13_3:
; GFX9-NEXT: s_branch .LBB13_2
@@ -2931,6 +3122,11 @@ define inreg <22 x i16> @bitcast_v11f32_to_v22i16_scalar(<11 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB13_3:
; GFX11-NEXT: s_branch .LBB13_2
@@ -3610,9 +3806,22 @@ define <22 x half> @bitcast_v11f32_to_v22f16(<11 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_4
+; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB16_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB16_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB16_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
@@ -3624,7 +3833,11 @@ define <22 x half> @bitcast_v11f32_to_v22f16(<11 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -3634,9 +3847,22 @@ define <22 x half> @bitcast_v11f32_to_v22f16(<11 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_4
+; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB16_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB16_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB16_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
@@ -3648,7 +3874,11 @@ define <22 x half> @bitcast_v11f32_to_v22f16(<11 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -3658,16 +3888,33 @@ define <22 x half> @bitcast_v11f32_to_v22f16(<11 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v11
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB16_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB16_4
+; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB16_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-NEXT: .LBB16_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v9, 1.0, v9
; GFX11-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7
; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -3821,6 +4068,11 @@ define inreg <22 x half> @bitcast_v11f32_to_v22f16_scalar(<11 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB17_3:
; VI-NEXT: s_branch .LBB17_2
@@ -3862,6 +4114,11 @@ define inreg <22 x half> @bitcast_v11f32_to_v22f16_scalar(<11 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB17_3:
; GFX9-NEXT: s_branch .LBB17_2
@@ -3909,6 +4166,11 @@ define inreg <22 x half> @bitcast_v11f32_to_v22f16_scalar(<11 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB17_3:
; GFX11-NEXT: s_branch .LBB17_2
@@ -4805,6 +5067,11 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v14
; VI-NEXT: v_or_b32_e32 v1, v1, v13
; VI-NEXT: v_or_b32_e32 v0, v0, v12
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4829,6 +5096,11 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4854,6 +5126,11 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5126,6 +5403,11 @@ define inreg <22 x half> @bitcast_v22i16_to_v22f16_scalar(<22 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB21_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -5161,6 +5443,11 @@ define inreg <22 x half> @bitcast_v22i16_to_v22f16_scalar(<22 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -5208,6 +5495,11 @@ define inreg <22 x half> @bitcast_v22i16_to_v22f16_scalar(<22 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -5432,6 +5724,11 @@ define <22 x i16> @bitcast_v22f16_to_v22i16(<22 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v14, v2
; VI-NEXT: v_or_b32_e32 v1, v13, v1
; VI-NEXT: v_or_b32_e32 v0, v11, v0
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -5457,6 +5754,11 @@ define <22 x i16> @bitcast_v22f16_to_v22i16(<22 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -5482,6 +5784,11 @@ define <22 x i16> @bitcast_v22f16_to_v22i16(<22 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5741,6 +6048,11 @@ define inreg <22 x i16> @bitcast_v22f16_to_v22i16_scalar(<22 x half> inreg %a, i
; VI-NEXT: v_add_f16_e32 v0, s17, v0
; VI-NEXT: v_or_b32_e32 v1, v0, v1
; VI-NEXT: v_or_b32_e32 v0, v11, v12
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: ; implicit-def: $vgpr11
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB23_3:
; VI-NEXT: s_branch .LBB23_2
@@ -5783,6 +6095,11 @@ define inreg <22 x i16> @bitcast_v22f16_to_v22i16_scalar(<22 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: ; implicit-def: $vgpr11
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB23_3:
; GFX9-NEXT: s_branch .LBB23_2
@@ -5830,6 +6147,11 @@ define inreg <22 x i16> @bitcast_v22f16_to_v22i16_scalar(<22 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: ; implicit-def: $vgpr11
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB23_3:
; GFX11-NEXT: s_branch .LBB23_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
index 6d91f0ea85573..a4bc8d747b62e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
@@ -573,9 +573,21 @@ define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB4_3
+; SI-NEXT: ; %bb.1: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB4_4
+; SI-NEXT: .LBB4_2: ; %end
+; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: .LBB4_3: ; %cmp.false
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB4_2
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: .LBB4_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
@@ -588,7 +600,10 @@ define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: .LBB4_2: ; %end
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -598,9 +613,21 @@ define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB4_4
+; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB4_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB4_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB4_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
@@ -613,7 +640,10 @@ define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB4_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -623,9 +653,21 @@ define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB4_4
+; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB4_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB4_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB4_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
@@ -638,7 +680,10 @@ define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB4_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -648,10 +693,21 @@ define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB4_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB4_4
+; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB4_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB4_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB4_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
@@ -664,7 +720,10 @@ define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB4_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -705,6 +764,10 @@ define inreg <6 x double> @bitcast_v12i32_to_v6f64_scalar(<12 x i32> inreg %a, i
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -742,6 +805,10 @@ define inreg <6 x double> @bitcast_v12i32_to_v6f64_scalar(<12 x i32> inreg %a, i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -779,6 +846,10 @@ define inreg <6 x double> @bitcast_v12i32_to_v6f64_scalar(<12 x i32> inreg %a, i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -818,6 +889,10 @@ define inreg <6 x double> @bitcast_v12i32_to_v6f64_scalar(<12 x i32> inreg %a, i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1092,9 +1167,21 @@ define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB8_3
+; SI-NEXT: ; %bb.1: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB8_4
+; SI-NEXT: .LBB8_2: ; %end
+; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: .LBB8_3: ; %cmp.false
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB8_2
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: .LBB8_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
@@ -1107,7 +1194,10 @@ define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: .LBB8_2: ; %end
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1117,9 +1207,21 @@ define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_4
+; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB8_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB8_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB8_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
@@ -1132,7 +1234,10 @@ define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1142,9 +1247,21 @@ define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_4
+; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB8_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB8_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB8_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
@@ -1157,7 +1274,10 @@ define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1167,10 +1287,21 @@ define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB8_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB8_4
+; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB8_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB8_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB8_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
@@ -1183,7 +1314,10 @@ define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1224,6 +1358,10 @@ define inreg <6 x i64> @bitcast_v12i32_to_v6i64_scalar(<12 x i32> inreg %a, i32
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1261,6 +1399,10 @@ define inreg <6 x i64> @bitcast_v12i32_to_v6i64_scalar(<12 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1298,6 +1440,10 @@ define inreg <6 x i64> @bitcast_v12i32_to_v6i64_scalar(<12 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1337,6 +1483,10 @@ define inreg <6 x i64> @bitcast_v12i32_to_v6i64_scalar(<12 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1755,9 +1905,21 @@ define <24 x i16> @bitcast_v12i32_to_v24i16(<12 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_4
+; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB12_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB12_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB12_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
@@ -1770,7 +1932,10 @@ define <24 x i16> @bitcast_v12i32_to_v24i16(<12 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1780,9 +1945,21 @@ define <24 x i16> @bitcast_v12i32_to_v24i16(<12 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_4
+; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB12_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB12_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB12_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
@@ -1795,7 +1972,10 @@ define <24 x i16> @bitcast_v12i32_to_v24i16(<12 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1805,10 +1985,21 @@ define <24 x i16> @bitcast_v12i32_to_v24i16(<12 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB12_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB12_4
+; GFX11-NEXT: .LBB12_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB12_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB12_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB12_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
@@ -1821,7 +2012,10 @@ define <24 x i16> @bitcast_v12i32_to_v24i16(<12 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB12_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1971,6 +2165,10 @@ define inreg <24 x i16> @bitcast_v12i32_to_v24i16_scalar(<12 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB13_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2008,6 +2206,10 @@ define inreg <24 x i16> @bitcast_v12i32_to_v24i16_scalar(<12 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB13_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2047,6 +2249,10 @@ define inreg <24 x i16> @bitcast_v12i32_to_v24i16_scalar(<12 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2766,9 +2972,21 @@ define <24 x half> @bitcast_v12i32_to_v24f16(<12 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_4
+; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB16_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB16_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB16_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
@@ -2781,7 +2999,10 @@ define <24 x half> @bitcast_v12i32_to_v24f16(<12 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2791,9 +3012,21 @@ define <24 x half> @bitcast_v12i32_to_v24f16(<12 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_4
+; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB16_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB16_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB16_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
@@ -2806,7 +3039,10 @@ define <24 x half> @bitcast_v12i32_to_v24f16(<12 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -2816,10 +3052,21 @@ define <24 x half> @bitcast_v12i32_to_v24f16(<12 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB16_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB16_4
+; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB16_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: .LBB16_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
@@ -2832,7 +3079,10 @@ define <24 x half> @bitcast_v12i32_to_v24f16(<12 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2982,6 +3232,10 @@ define inreg <24 x half> @bitcast_v12i32_to_v24f16_scalar(<12 x i32> inreg %a, i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB17_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -3019,6 +3273,10 @@ define inreg <24 x half> @bitcast_v12i32_to_v24f16_scalar(<12 x i32> inreg %a, i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB17_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -3058,6 +3316,10 @@ define inreg <24 x half> @bitcast_v12i32_to_v24f16_scalar(<12 x i32> inreg %a, i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB17_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -3765,9 +4027,21 @@ define <6 x double> @bitcast_v12f32_to_v6f64(<12 x float> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB20_3
+; SI-NEXT: ; %bb.1: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB20_4
+; SI-NEXT: .LBB20_2: ; %end
+; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: .LBB20_3: ; %cmp.false
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB20_2
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: .LBB20_4: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -3780,7 +4054,10 @@ define <6 x double> @bitcast_v12f32_to_v6f64(<12 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; SI-NEXT: .LBB20_2: ; %end
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -3790,9 +4067,21 @@ define <6 x double> @bitcast_v12f32_to_v6f64(<12 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB20_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB20_4
+; VI-NEXT: .LBB20_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB20_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB20_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB20_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -3805,7 +4094,10 @@ define <6 x double> @bitcast_v12f32_to_v6f64(<12 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB20_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -3815,9 +4107,21 @@ define <6 x double> @bitcast_v12f32_to_v6f64(<12 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB20_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB20_4
+; GFX9-NEXT: .LBB20_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB20_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB20_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB20_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -3830,7 +4134,10 @@ define <6 x double> @bitcast_v12f32_to_v6f64(<12 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB20_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -3840,16 +4147,31 @@ define <6 x double> @bitcast_v12f32_to_v6f64(<12 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB20_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB20_4
+; GFX11-NEXT: .LBB20_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB20_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB20_2
+; GFX11-NEXT: .LBB20_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -3890,6 +4212,10 @@ define inreg <6 x double> @bitcast_v12f32_to_v6f64_scalar(<12 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -3932,6 +4258,10 @@ define inreg <6 x double> @bitcast_v12f32_to_v6f64_scalar(<12 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -3974,6 +4304,10 @@ define inreg <6 x double> @bitcast_v12f32_to_v6f64_scalar(<12 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -4022,6 +4356,10 @@ define inreg <6 x double> @bitcast_v12f32_to_v6f64_scalar(<12 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -4298,9 +4636,21 @@ define <6 x i64> @bitcast_v12f32_to_v6i64(<12 x float> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB24_3
+; SI-NEXT: ; %bb.1: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execnz .LBB24_4
+; SI-NEXT: .LBB24_2: ; %end
+; SI-NEXT: s_or_b64 exec, exec, s[4:5]
+; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: .LBB24_3: ; %cmp.false
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB24_2
-; SI-NEXT: ; %bb.1: ; %cmp.true
+; SI-NEXT: .LBB24_4: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -4313,7 +4663,10 @@ define <6 x i64> @bitcast_v12f32_to_v6i64(<12 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; SI-NEXT: .LBB24_2: ; %end
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -4323,9 +4676,21 @@ define <6 x i64> @bitcast_v12f32_to_v6i64(<12 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB24_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB24_4
+; VI-NEXT: .LBB24_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB24_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB24_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB24_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -4338,7 +4703,10 @@ define <6 x i64> @bitcast_v12f32_to_v6i64(<12 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB24_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -4348,9 +4716,21 @@ define <6 x i64> @bitcast_v12f32_to_v6i64(<12 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB24_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB24_4
+; GFX9-NEXT: .LBB24_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB24_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB24_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB24_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -4363,7 +4743,10 @@ define <6 x i64> @bitcast_v12f32_to_v6i64(<12 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB24_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -4373,16 +4756,31 @@ define <6 x i64> @bitcast_v12f32_to_v6i64(<12 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB24_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB24_4
+; GFX11-NEXT: .LBB24_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB24_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB24_2
+; GFX11-NEXT: .LBB24_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4423,6 +4821,10 @@ define inreg <6 x i64> @bitcast_v12f32_to_v6i64_scalar(<12 x float> inreg %a, i3
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -4465,6 +4867,10 @@ define inreg <6 x i64> @bitcast_v12f32_to_v6i64_scalar(<12 x float> inreg %a, i3
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -4507,6 +4913,10 @@ define inreg <6 x i64> @bitcast_v12f32_to_v6i64_scalar(<12 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -4555,6 +4965,10 @@ define inreg <6 x i64> @bitcast_v12f32_to_v6i64_scalar(<12 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -4975,9 +5389,21 @@ define <24 x i16> @bitcast_v12f32_to_v24i16(<12 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB28_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB28_4
+; VI-NEXT: .LBB28_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB28_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB28_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB28_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -4990,7 +5416,10 @@ define <24 x i16> @bitcast_v12f32_to_v24i16(<12 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB28_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -5000,9 +5429,21 @@ define <24 x i16> @bitcast_v12f32_to_v24i16(<12 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB28_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB28_4
+; GFX9-NEXT: .LBB28_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB28_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB28_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB28_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -5015,7 +5456,10 @@ define <24 x i16> @bitcast_v12f32_to_v24i16(<12 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB28_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -5025,16 +5469,31 @@ define <24 x i16> @bitcast_v12f32_to_v24i16(<12 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB28_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB28_4
+; GFX11-NEXT: .LBB28_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB28_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-NEXT: .LBB28_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -5198,6 +5657,10 @@ define inreg <24 x i16> @bitcast_v12f32_to_v24i16_scalar(<12 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB29_3:
; VI-NEXT: s_branch .LBB29_2
@@ -5240,6 +5703,10 @@ define inreg <24 x i16> @bitcast_v12f32_to_v24i16_scalar(<12 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB29_3:
; GFX9-NEXT: s_branch .LBB29_2
@@ -5288,6 +5755,10 @@ define inreg <24 x i16> @bitcast_v12f32_to_v24i16_scalar(<12 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB29_3:
; GFX11-NEXT: s_branch .LBB29_2
@@ -6009,9 +6480,21 @@ define <24 x half> @bitcast_v12f32_to_v24f16(<12 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB32_3
+; VI-NEXT: ; %bb.1: ; %Flow
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB32_4
+; VI-NEXT: .LBB32_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB32_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB32_2
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: .LBB32_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -6024,7 +6507,10 @@ define <24 x half> @bitcast_v12f32_to_v24f16(<12 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: .LBB32_2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6034,9 +6520,21 @@ define <24 x half> @bitcast_v12f32_to_v24f16(<12 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB32_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB32_4
+; GFX9-NEXT: .LBB32_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB32_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB32_2
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: .LBB32_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
@@ -6049,7 +6547,10 @@ define <24 x half> @bitcast_v12f32_to_v24f16(<12 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: .LBB32_2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6059,16 +6560,31 @@ define <24 x half> @bitcast_v12f32_to_v24f16(<12 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB32_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB32_4
+; GFX11-NEXT: .LBB32_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB32_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-NEXT: .LBB32_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6232,6 +6748,10 @@ define inreg <24 x half> @bitcast_v12f32_to_v24f16_scalar(<12 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB33_3:
; VI-NEXT: s_branch .LBB33_2
@@ -6274,6 +6794,10 @@ define inreg <24 x half> @bitcast_v12f32_to_v24f16_scalar(<12 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB33_3:
; GFX9-NEXT: s_branch .LBB33_2
@@ -6322,6 +6846,10 @@ define inreg <24 x half> @bitcast_v12f32_to_v24f16_scalar(<12 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB33_3:
; GFX11-NEXT: s_branch .LBB33_2
@@ -7040,6 +7568,10 @@ define <6 x i64> @bitcast_v6f64_to_v6i64(<6 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -7059,6 +7591,10 @@ define <6 x i64> @bitcast_v6f64_to_v6i64(<6 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -7078,6 +7614,10 @@ define <6 x i64> @bitcast_v6f64_to_v6i64(<6 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -7098,6 +7638,10 @@ define <6 x i64> @bitcast_v6f64_to_v6i64(<6 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7133,6 +7677,10 @@ define inreg <6 x i64> @bitcast_v6f64_to_v6i64_scalar(<6 x double> inreg %a, i32
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB37_3:
; SI-NEXT: s_branch .LBB37_2
@@ -7169,6 +7717,10 @@ define inreg <6 x i64> @bitcast_v6f64_to_v6i64_scalar(<6 x double> inreg %a, i32
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB37_3:
; VI-NEXT: s_branch .LBB37_2
@@ -7205,6 +7757,10 @@ define inreg <6 x i64> @bitcast_v6f64_to_v6i64_scalar(<6 x double> inreg %a, i32
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB37_3:
; GFX9-NEXT: s_branch .LBB37_2
@@ -7247,6 +7803,10 @@ define inreg <6 x i64> @bitcast_v6f64_to_v6i64_scalar(<6 x double> inreg %a, i32
; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB37_3:
; GFX11-NEXT: s_branch .LBB37_2
@@ -7299,6 +7859,10 @@ define <6 x double> @bitcast_v6i64_to_v6f64(<6 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -7324,6 +7888,10 @@ define <6 x double> @bitcast_v6i64_to_v6f64(<6 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -7349,6 +7917,10 @@ define <6 x double> @bitcast_v6i64_to_v6f64(<6 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -7378,6 +7950,10 @@ define <6 x double> @bitcast_v6i64_to_v6f64(<6 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7419,6 +7995,10 @@ define inreg <6 x double> @bitcast_v6i64_to_v6f64_scalar(<6 x i64> inreg %a, i32
; SI-NEXT: s_addc_u32 s25, s25, 0
; SI-NEXT: s_add_u32 s26, s26, 3
; SI-NEXT: s_addc_u32 s27, s27, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB39_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -7456,6 +8036,10 @@ define inreg <6 x double> @bitcast_v6i64_to_v6f64_scalar(<6 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s25, s25, 0
; VI-NEXT: s_add_u32 s26, s26, 3
; VI-NEXT: s_addc_u32 s27, s27, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB39_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -7493,6 +8077,10 @@ define inreg <6 x double> @bitcast_v6i64_to_v6f64_scalar(<6 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s25, s25, 0
; GFX9-NEXT: s_add_u32 s26, s26, 3
; GFX9-NEXT: s_addc_u32 s27, s27, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB39_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -7532,6 +8120,10 @@ define inreg <6 x double> @bitcast_v6i64_to_v6f64_scalar(<6 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s21, s21, 0
; GFX11-NEXT: s_add_u32 s22, s22, 3
; GFX11-NEXT: s_addc_u32 s23, s23, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB39_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -7669,6 +8261,10 @@ define <24 x i16> @bitcast_v6f64_to_v24i16(<6 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB40_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -7688,6 +8284,10 @@ define <24 x i16> @bitcast_v6f64_to_v24i16(<6 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB40_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -7708,6 +8308,10 @@ define <24 x i16> @bitcast_v6f64_to_v24i16(<6 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB40_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7860,6 +8464,10 @@ define inreg <24 x i16> @bitcast_v6f64_to_v24i16_scalar(<6 x double> inreg %a, i
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB41_3:
; VI-NEXT: s_branch .LBB41_2
@@ -7896,6 +8504,10 @@ define inreg <24 x i16> @bitcast_v6f64_to_v24i16_scalar(<6 x double> inreg %a, i
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB41_3:
; GFX9-NEXT: s_branch .LBB41_2
@@ -7938,6 +8550,10 @@ define inreg <24 x i16> @bitcast_v6f64_to_v24i16_scalar(<6 x double> inreg %a, i
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB41_3:
; GFX11-NEXT: s_branch .LBB41_2
@@ -8044,6 +8660,10 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v9, v30
; SI-NEXT: v_or_b32_e32 v10, v10, v29
; SI-NEXT: v_or_b32_e32 v11, v11, v28
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
@@ -8120,6 +8740,10 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -8169,6 +8793,10 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v12, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v12, v0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB42_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8194,6 +8822,10 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB42_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8220,6 +8852,10 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB42_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8307,6 +8943,10 @@ define inreg <6 x double> @bitcast_v24i16_to_v6f64_scalar(<24 x i16> inreg %a, i
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s47, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -8369,6 +9009,10 @@ define inreg <6 x double> @bitcast_v24i16_to_v6f64_scalar(<24 x i16> inreg %a, i
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s47, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -8467,6 +9111,10 @@ define inreg <6 x double> @bitcast_v24i16_to_v6f64_scalar(<24 x i16> inreg %a, i
; VI-NEXT: s_and_b32 s5, s5, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -8504,6 +9152,10 @@ define inreg <6 x double> @bitcast_v24i16_to_v6f64_scalar(<24 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -8552,6 +9204,10 @@ define inreg <6 x double> @bitcast_v24i16_to_v6f64_scalar(<24 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -8692,6 +9348,10 @@ define <24 x half> @bitcast_v6f64_to_v24f16(<6 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB44_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8711,6 +9371,10 @@ define <24 x half> @bitcast_v6f64_to_v24f16(<6 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB44_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8731,6 +9395,10 @@ define <24 x half> @bitcast_v6f64_to_v24f16(<6 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB44_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8883,6 +9551,10 @@ define inreg <24 x half> @bitcast_v6f64_to_v24f16_scalar(<6 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB45_3:
; VI-NEXT: s_branch .LBB45_2
@@ -8919,6 +9591,10 @@ define inreg <24 x half> @bitcast_v6f64_to_v24f16_scalar(<6 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB45_3:
; GFX9-NEXT: s_branch .LBB45_2
@@ -8961,6 +9637,10 @@ define inreg <24 x half> @bitcast_v6f64_to_v24f16_scalar(<6 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB45_3:
; GFX11-NEXT: s_branch .LBB45_2
@@ -9067,6 +9747,10 @@ define <6 x double> @bitcast_v24f16_to_v6f64(<24 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
@@ -9190,6 +9874,10 @@ define <6 x double> @bitcast_v24f16_to_v6f64(<24 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -9239,6 +9927,10 @@ define <6 x double> @bitcast_v24f16_to_v6f64(<24 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v13
; VI-NEXT: v_or_b32_e32 v0, v0, v12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB46_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -9265,6 +9957,10 @@ define <6 x double> @bitcast_v24f16_to_v6f64(<24 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB46_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -9291,6 +9987,10 @@ define <6 x double> @bitcast_v24f16_to_v6f64(<24 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB46_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9378,6 +10078,10 @@ define inreg <6 x double> @bitcast_v24f16_to_v6f64_scalar(<24 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s47, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr48
+; SI-NEXT: ; implicit-def: $sgpr49
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s56
@@ -9476,6 +10180,10 @@ define inreg <6 x double> @bitcast_v24f16_to_v6f64_scalar(<24 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
@@ -9581,6 +10289,10 @@ define inreg <6 x double> @bitcast_v24f16_to_v6f64_scalar(<24 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v12, v12, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, s16, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB47_3:
; VI-NEXT: s_branch .LBB47_2
@@ -9624,6 +10336,10 @@ define inreg <6 x double> @bitcast_v24f16_to_v6f64_scalar(<24 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -9672,6 +10388,10 @@ define inreg <6 x double> @bitcast_v24f16_to_v6f64_scalar(<24 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -9824,6 +10544,10 @@ define <24 x i16> @bitcast_v6i64_to_v24i16(<6 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB48_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -9849,6 +10573,10 @@ define <24 x i16> @bitcast_v6i64_to_v24i16(<6 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB48_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -9878,6 +10606,10 @@ define <24 x i16> @bitcast_v6i64_to_v24i16(<6 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB48_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10028,6 +10760,10 @@ define inreg <24 x i16> @bitcast_v6i64_to_v24i16_scalar(<6 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB49_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -10065,6 +10801,10 @@ define inreg <24 x i16> @bitcast_v6i64_to_v24i16_scalar(<6 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB49_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -10104,6 +10844,10 @@ define inreg <24 x i16> @bitcast_v6i64_to_v24i16_scalar(<6 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB49_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -10208,6 +10952,10 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v9, v30
; SI-NEXT: v_or_b32_e32 v10, v10, v29
; SI-NEXT: v_or_b32_e32 v11, v11, v28
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
@@ -10284,6 +11032,10 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -10333,6 +11085,10 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v12, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v12, v0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB50_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -10358,6 +11114,10 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB50_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10384,6 +11144,10 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB50_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10471,6 +11235,10 @@ define inreg <6 x i64> @bitcast_v24i16_to_v6i64_scalar(<24 x i16> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s47, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -10533,6 +11301,10 @@ define inreg <6 x i64> @bitcast_v24i16_to_v6i64_scalar(<24 x i16> inreg %a, i32
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s47, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -10631,6 +11403,10 @@ define inreg <6 x i64> @bitcast_v24i16_to_v6i64_scalar(<24 x i16> inreg %a, i32
; VI-NEXT: s_and_b32 s5, s5, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -10668,6 +11444,10 @@ define inreg <6 x i64> @bitcast_v24i16_to_v6i64_scalar(<24 x i16> inreg %a, i32
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -10716,6 +11496,10 @@ define inreg <6 x i64> @bitcast_v24i16_to_v6i64_scalar(<24 x i16> inreg %a, i32
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -10868,6 +11652,10 @@ define <24 x half> @bitcast_v6i64_to_v24f16(<6 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB52_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -10893,6 +11681,10 @@ define <24 x half> @bitcast_v6i64_to_v24f16(<6 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB52_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10922,6 +11714,10 @@ define <24 x half> @bitcast_v6i64_to_v24f16(<6 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB52_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11072,6 +11868,10 @@ define inreg <24 x half> @bitcast_v6i64_to_v24f16_scalar(<6 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB53_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -11109,6 +11909,10 @@ define inreg <24 x half> @bitcast_v6i64_to_v24f16_scalar(<6 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB53_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -11148,6 +11952,10 @@ define inreg <24 x half> @bitcast_v6i64_to_v24f16_scalar(<6 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB53_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -11252,6 +12060,10 @@ define <6 x i64> @bitcast_v24f16_to_v6i64(<24 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
; SI-NEXT: v_or_b32_e32 v11, v11, v12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr25
@@ -11375,6 +12187,10 @@ define <6 x i64> @bitcast_v24f16_to_v6i64(<24 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -11424,6 +12240,10 @@ define <6 x i64> @bitcast_v24f16_to_v6i64(<24 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v13
; VI-NEXT: v_or_b32_e32 v0, v0, v12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB54_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -11450,6 +12270,10 @@ define <6 x i64> @bitcast_v24f16_to_v6i64(<24 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB54_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -11476,6 +12300,10 @@ define <6 x i64> @bitcast_v24f16_to_v6i64(<24 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB54_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11563,6 +12391,10 @@ define inreg <6 x i64> @bitcast_v24f16_to_v6i64_scalar(<24 x half> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s47, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr48
+; SI-NEXT: ; implicit-def: $sgpr49
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s56
@@ -11661,6 +12493,10 @@ define inreg <6 x i64> @bitcast_v24f16_to_v6i64_scalar(<24 x half> inreg %a, i32
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
@@ -11766,6 +12602,10 @@ define inreg <6 x i64> @bitcast_v24f16_to_v6i64_scalar(<24 x half> inreg %a, i32
; VI-NEXT: v_add_f16_sdwa v12, v12, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, s16, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB55_3:
; VI-NEXT: s_branch .LBB55_2
@@ -11809,6 +12649,10 @@ define inreg <6 x i64> @bitcast_v24f16_to_v6i64_scalar(<24 x half> inreg %a, i32
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -11857,6 +12701,10 @@ define inreg <6 x i64> @bitcast_v24f16_to_v6i64_scalar(<24 x half> inreg %a, i32
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
@@ -12143,6 +12991,10 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v15
; VI-NEXT: v_or_b32_e32 v1, v1, v14
; VI-NEXT: v_or_b32_e32 v0, v0, v13
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB56_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12168,6 +13020,10 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB56_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12194,6 +13050,10 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB56_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -12488,6 +13348,10 @@ define inreg <24 x half> @bitcast_v24i16_to_v24f16_scalar(<24 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB57_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -12525,6 +13389,10 @@ define inreg <24 x half> @bitcast_v24i16_to_v24f16_scalar(<24 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB57_3:
; GFX9-NEXT: s_branch .LBB57_2
@@ -12573,6 +13441,10 @@ define inreg <24 x half> @bitcast_v24i16_to_v24f16_scalar(<24 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB57_3:
; GFX11-NEXT: s_branch .LBB57_2
@@ -12813,6 +13685,10 @@ define <24 x i16> @bitcast_v24f16_to_v24i16(<24 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v15, v2
; VI-NEXT: v_or_b32_e32 v1, v14, v1
; VI-NEXT: v_or_b32_e32 v0, v12, v0
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: .LBB58_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12839,6 +13715,10 @@ define <24 x i16> @bitcast_v24f16_to_v24i16(<24 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: .LBB58_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12865,6 +13745,10 @@ define <24 x i16> @bitcast_v24f16_to_v24i16(<24 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: .LBB58_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13144,6 +14028,10 @@ define inreg <24 x i16> @bitcast_v24f16_to_v24i16_scalar(<24 x half> inreg %a, i
; VI-NEXT: v_add_f16_e32 v0, s17, v0
; VI-NEXT: v_or_b32_e32 v1, v0, v1
; VI-NEXT: v_or_b32_e32 v0, v12, v13
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
+; VI-NEXT: ; implicit-def: $vgpr12
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB59_3:
; VI-NEXT: s_branch .LBB59_2
@@ -13187,6 +14075,10 @@ define inreg <24 x i16> @bitcast_v24f16_to_v24i16_scalar(<24 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
+; GFX9-NEXT: ; implicit-def: $vgpr12
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB59_3:
; GFX9-NEXT: s_branch .LBB59_2
@@ -13235,6 +14127,10 @@ define inreg <24 x i16> @bitcast_v24f16_to_v24i16_scalar(<24 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
+; GFX11-NEXT: ; implicit-def: $vgpr12
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB59_3:
; GFX11-NEXT: s_branch .LBB59_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
index 04ccab7cc4b61..f9da90f90102a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
@@ -30,6 +30,8 @@ define <14 x float> @bitcast_v14i32_to_v14f32(<14 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -57,6 +59,8 @@ define <14 x float> @bitcast_v14i32_to_v14f32(<14 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -84,6 +88,8 @@ define <14 x float> @bitcast_v14i32_to_v14f32(<14 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -112,6 +118,8 @@ define <14 x float> @bitcast_v14i32_to_v14f32(<14 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -156,6 +164,8 @@ define inreg <14 x float> @bitcast_v14i32_to_v14f32_scalar(<14 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB1_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -198,6 +208,8 @@ define inreg <14 x float> @bitcast_v14i32_to_v14f32_scalar(<14 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB1_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -240,6 +252,8 @@ define inreg <14 x float> @bitcast_v14i32_to_v14f32_scalar(<14 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB1_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -283,6 +297,8 @@ define inreg <14 x float> @bitcast_v14i32_to_v14f32_scalar(<14 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB1_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -336,6 +352,8 @@ define <14 x i32> @bitcast_v14f32_to_v14i32(<14 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -363,6 +381,8 @@ define <14 x i32> @bitcast_v14f32_to_v14i32(<14 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -390,6 +410,8 @@ define <14 x i32> @bitcast_v14f32_to_v14i32(<14 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -411,6 +433,8 @@ define <14 x i32> @bitcast_v14f32_to_v14i32(<14 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -455,6 +479,8 @@ define inreg <14 x i32> @bitcast_v14f32_to_v14i32_scalar(<14 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB3_3:
; SI-NEXT: s_branch .LBB3_2
@@ -500,6 +526,8 @@ define inreg <14 x i32> @bitcast_v14f32_to_v14i32_scalar(<14 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB3_3:
; VI-NEXT: s_branch .LBB3_2
@@ -545,6 +573,8 @@ define inreg <14 x i32> @bitcast_v14f32_to_v14i32_scalar(<14 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB3_3:
; GFX9-NEXT: s_branch .LBB3_2
@@ -595,6 +625,8 @@ define inreg <14 x i32> @bitcast_v14f32_to_v14i32_scalar(<14 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB3_3:
; GFX11-NEXT: s_branch .LBB3_2
@@ -649,6 +681,8 @@ define <7 x i64> @bitcast_v14i32_to_v7i64(<14 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -676,6 +710,8 @@ define <7 x i64> @bitcast_v14i32_to_v7i64(<14 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -703,6 +739,8 @@ define <7 x i64> @bitcast_v14i32_to_v7i64(<14 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -731,6 +769,8 @@ define <7 x i64> @bitcast_v14i32_to_v7i64(<14 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -775,6 +815,8 @@ define inreg <7 x i64> @bitcast_v14i32_to_v7i64_scalar(<14 x i32> inreg %a, i32
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -817,6 +859,8 @@ define inreg <7 x i64> @bitcast_v14i32_to_v7i64_scalar(<14 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -859,6 +903,8 @@ define inreg <7 x i64> @bitcast_v14i32_to_v7i64_scalar(<14 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -902,6 +948,8 @@ define inreg <7 x i64> @bitcast_v14i32_to_v7i64_scalar(<14 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -955,6 +1003,8 @@ define <14 x i32> @bitcast_v7i64_to_v14i32(<7 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -982,6 +1032,8 @@ define <14 x i32> @bitcast_v7i64_to_v14i32(<7 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1009,6 +1061,8 @@ define <14 x i32> @bitcast_v7i64_to_v14i32(<7 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1041,6 +1095,8 @@ define <14 x i32> @bitcast_v7i64_to_v14i32(<7 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1085,6 +1141,8 @@ define inreg <14 x i32> @bitcast_v7i64_to_v14i32_scalar(<7 x i64> inreg %a, i32
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB7_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1127,6 +1185,8 @@ define inreg <14 x i32> @bitcast_v7i64_to_v14i32_scalar(<7 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB7_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1169,6 +1229,8 @@ define inreg <14 x i32> @bitcast_v7i64_to_v14i32_scalar(<7 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB7_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1212,6 +1274,8 @@ define inreg <14 x i32> @bitcast_v7i64_to_v14i32_scalar(<7 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1265,6 +1329,8 @@ define <7 x double> @bitcast_v14i32_to_v7f64(<14 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1292,6 +1358,8 @@ define <7 x double> @bitcast_v14i32_to_v7f64(<14 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1319,6 +1387,8 @@ define <7 x double> @bitcast_v14i32_to_v7f64(<14 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1347,6 +1417,8 @@ define <7 x double> @bitcast_v14i32_to_v7f64(<14 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1391,6 +1463,8 @@ define inreg <7 x double> @bitcast_v14i32_to_v7f64_scalar(<14 x i32> inreg %a, i
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1433,6 +1507,8 @@ define inreg <7 x double> @bitcast_v14i32_to_v7f64_scalar(<14 x i32> inreg %a, i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1475,6 +1551,8 @@ define inreg <7 x double> @bitcast_v14i32_to_v7f64_scalar(<14 x i32> inreg %a, i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1518,6 +1596,8 @@ define inreg <7 x double> @bitcast_v14i32_to_v7f64_scalar(<14 x i32> inreg %a, i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1564,6 +1644,8 @@ define <14 x i32> @bitcast_v7f64_to_v14i32(<7 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1584,6 +1666,8 @@ define <14 x i32> @bitcast_v7f64_to_v14i32(<7 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1604,6 +1688,8 @@ define <14 x i32> @bitcast_v7f64_to_v14i32(<7 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1625,6 +1711,8 @@ define <14 x i32> @bitcast_v7f64_to_v14i32(<7 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1662,6 +1750,8 @@ define inreg <14 x i32> @bitcast_v7f64_to_v14i32_scalar(<7 x double> inreg %a, i
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB11_3:
; SI-NEXT: s_branch .LBB11_2
@@ -1700,6 +1790,8 @@ define inreg <14 x i32> @bitcast_v7f64_to_v14i32_scalar(<7 x double> inreg %a, i
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -1738,6 +1830,8 @@ define inreg <14 x i32> @bitcast_v7f64_to_v14i32_scalar(<7 x double> inreg %a, i
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB11_3:
; GFX9-NEXT: s_branch .LBB11_2
@@ -1781,6 +1875,8 @@ define inreg <14 x i32> @bitcast_v7f64_to_v14i32_scalar(<7 x double> inreg %a, i
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB11_3:
; GFX11-NEXT: s_branch .LBB11_2
@@ -1949,6 +2045,8 @@ define <28 x i16> @bitcast_v14i32_to_v28i16(<14 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB12_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1976,6 +2074,8 @@ define <28 x i16> @bitcast_v14i32_to_v28i16(<14 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB12_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2004,6 +2104,8 @@ define <28 x i16> @bitcast_v14i32_to_v28i16(<14 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB12_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2174,6 +2276,8 @@ define inreg <28 x i16> @bitcast_v14i32_to_v28i16_scalar(<14 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB13_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2216,6 +2320,8 @@ define inreg <28 x i16> @bitcast_v14i32_to_v28i16_scalar(<14 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB13_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2259,6 +2365,8 @@ define inreg <28 x i16> @bitcast_v14i32_to_v28i16_scalar(<14 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2374,6 +2482,8 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v11, v11, v32
; SI-NEXT: v_or_b32_e32 v12, v12, v31
; SI-NEXT: v_or_b32_e32 v13, v13, v30
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -2462,6 +2572,8 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2517,6 +2629,8 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v14, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v14, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB14_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2544,6 +2658,8 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB14_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2572,6 +2688,8 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB14_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2668,6 +2786,8 @@ define inreg <14 x i32> @bitcast_v28i16_to_v14i32_scalar(<28 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s49, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -2740,6 +2860,8 @@ define inreg <14 x i32> @bitcast_v28i16_to_v14i32_scalar(<28 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s49, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -2851,6 +2973,8 @@ define inreg <14 x i32> @bitcast_v28i16_to_v14i32_scalar(<28 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s5, s5, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB15_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2893,6 +3017,8 @@ define inreg <14 x i32> @bitcast_v28i16_to_v14i32_scalar(<28 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB15_3:
; GFX9-NEXT: s_branch .LBB15_2
@@ -2943,6 +3069,8 @@ define inreg <14 x i32> @bitcast_v28i16_to_v14i32_scalar(<28 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_3:
; GFX11-NEXT: s_branch .LBB15_2
@@ -3111,6 +3239,8 @@ define <28 x half> @bitcast_v14i32_to_v28f16(<14 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB16_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -3138,6 +3268,8 @@ define <28 x half> @bitcast_v14i32_to_v28f16(<14 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB16_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3166,6 +3298,8 @@ define <28 x half> @bitcast_v14i32_to_v28f16(<14 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB16_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3336,6 +3470,8 @@ define inreg <28 x half> @bitcast_v14i32_to_v28f16_scalar(<14 x i32> inreg %a, i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB17_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -3378,6 +3514,8 @@ define inreg <28 x half> @bitcast_v14i32_to_v28f16_scalar(<14 x i32> inreg %a, i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB17_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -3421,6 +3559,8 @@ define inreg <28 x half> @bitcast_v14i32_to_v28f16_scalar(<14 x i32> inreg %a, i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB17_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -3536,6 +3676,8 @@ define <14 x i32> @bitcast_v28f16_to_v14i32(<28 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -3679,6 +3821,8 @@ define <14 x i32> @bitcast_v28f16_to_v14i32(<28 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -3734,6 +3878,8 @@ define <14 x i32> @bitcast_v28f16_to_v14i32(<28 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: v_or_b32_e32 v0, v0, v14
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB18_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -3762,6 +3908,8 @@ define <14 x i32> @bitcast_v28f16_to_v14i32(<28 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB18_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3790,6 +3938,8 @@ define <14 x i32> @bitcast_v28f16_to_v14i32(<28 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB18_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3886,6 +4036,8 @@ define inreg <14 x i32> @bitcast_v28f16_to_v14i32_scalar(<28 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s49, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
; SI-NEXT: s_cbranch_execnz .LBB19_4
; SI-NEXT: .LBB19_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s59
@@ -4000,6 +4152,8 @@ define inreg <14 x i32> @bitcast_v28f16_to_v14i32_scalar(<28 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_branch .LBB19_5
; SI-NEXT: .LBB19_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
@@ -4116,6 +4270,8 @@ define inreg <14 x i32> @bitcast_v28f16_to_v14i32_scalar(<28 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v14, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, s16, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v14
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB19_3:
; VI-NEXT: s_branch .LBB19_2
@@ -4162,6 +4318,8 @@ define inreg <14 x i32> @bitcast_v28f16_to_v14i32_scalar(<28 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB19_3:
; GFX9-NEXT: s_branch .LBB19_2
@@ -4212,6 +4370,8 @@ define inreg <14 x i32> @bitcast_v28f16_to_v14i32_scalar(<28 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3:
; GFX11-NEXT: s_branch .LBB19_2
@@ -4266,6 +4426,8 @@ define <7 x i64> @bitcast_v14f32_to_v7i64(<14 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -4293,6 +4455,8 @@ define <7 x i64> @bitcast_v14f32_to_v7i64(<14 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4320,6 +4484,8 @@ define <7 x i64> @bitcast_v14f32_to_v7i64(<14 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4341,6 +4507,8 @@ define <7 x i64> @bitcast_v14f32_to_v7i64(<14 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4385,6 +4553,8 @@ define inreg <7 x i64> @bitcast_v14f32_to_v7i64_scalar(<14 x float> inreg %a, i3
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -4430,6 +4600,8 @@ define inreg <7 x i64> @bitcast_v14f32_to_v7i64_scalar(<14 x float> inreg %a, i3
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -4475,6 +4647,8 @@ define inreg <7 x i64> @bitcast_v14f32_to_v7i64_scalar(<14 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -4525,6 +4699,8 @@ define inreg <7 x i64> @bitcast_v14f32_to_v7i64_scalar(<14 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -4579,6 +4755,8 @@ define <14 x float> @bitcast_v7i64_to_v14f32(<7 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -4606,6 +4784,8 @@ define <14 x float> @bitcast_v7i64_to_v14f32(<7 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4633,6 +4813,8 @@ define <14 x float> @bitcast_v7i64_to_v14f32(<7 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4665,6 +4847,8 @@ define <14 x float> @bitcast_v7i64_to_v14f32(<7 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4709,6 +4893,8 @@ define inreg <14 x float> @bitcast_v7i64_to_v14f32_scalar(<7 x i64> inreg %a, i3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -4751,6 +4937,8 @@ define inreg <14 x float> @bitcast_v7i64_to_v14f32_scalar(<7 x i64> inreg %a, i3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB23_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -4793,6 +4981,8 @@ define inreg <14 x float> @bitcast_v7i64_to_v14f32_scalar(<7 x i64> inreg %a, i3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB23_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -4836,6 +5026,8 @@ define inreg <14 x float> @bitcast_v7i64_to_v14f32_scalar(<7 x i64> inreg %a, i3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -4889,6 +5081,8 @@ define <7 x double> @bitcast_v14f32_to_v7f64(<14 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -4916,6 +5110,8 @@ define <7 x double> @bitcast_v14f32_to_v7f64(<14 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4943,6 +5139,8 @@ define <7 x double> @bitcast_v14f32_to_v7f64(<14 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4964,6 +5162,8 @@ define <7 x double> @bitcast_v14f32_to_v7f64(<14 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5008,6 +5208,8 @@ define inreg <7 x double> @bitcast_v14f32_to_v7f64_scalar(<14 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -5053,6 +5255,8 @@ define inreg <7 x double> @bitcast_v14f32_to_v7f64_scalar(<14 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -5098,6 +5302,8 @@ define inreg <7 x double> @bitcast_v14f32_to_v7f64_scalar(<14 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -5148,6 +5354,8 @@ define inreg <7 x double> @bitcast_v14f32_to_v7f64_scalar(<14 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -5195,6 +5403,8 @@ define <14 x float> @bitcast_v7f64_to_v14f32(<7 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -5215,6 +5425,8 @@ define <14 x float> @bitcast_v7f64_to_v14f32(<7 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -5235,6 +5447,8 @@ define <14 x float> @bitcast_v7f64_to_v14f32(<7 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -5256,6 +5470,8 @@ define <14 x float> @bitcast_v7f64_to_v14f32(<7 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5293,6 +5509,8 @@ define inreg <14 x float> @bitcast_v7f64_to_v14f32_scalar(<7 x double> inreg %a,
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB27_3:
; SI-NEXT: s_branch .LBB27_2
@@ -5331,6 +5549,8 @@ define inreg <14 x float> @bitcast_v7f64_to_v14f32_scalar(<7 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -5369,6 +5589,8 @@ define inreg <14 x float> @bitcast_v7f64_to_v14f32_scalar(<7 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB27_3:
; GFX9-NEXT: s_branch .LBB27_2
@@ -5412,6 +5634,8 @@ define inreg <14 x float> @bitcast_v7f64_to_v14f32_scalar(<7 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB27_3:
; GFX11-NEXT: s_branch .LBB27_2
@@ -5580,6 +5804,8 @@ define <28 x i16> @bitcast_v14f32_to_v28i16(<14 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB28_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -5607,6 +5833,8 @@ define <28 x i16> @bitcast_v14f32_to_v28i16(<14 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB28_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -5628,6 +5856,8 @@ define <28 x i16> @bitcast_v14f32_to_v28i16(<14 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB28_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5814,6 +6044,8 @@ define inreg <28 x i16> @bitcast_v14f32_to_v28i16_scalar(<14 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB29_3:
; VI-NEXT: s_branch .LBB29_2
@@ -5859,6 +6091,8 @@ define inreg <28 x i16> @bitcast_v14f32_to_v28i16_scalar(<14 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB29_3:
; GFX9-NEXT: s_branch .LBB29_2
@@ -5909,6 +6143,8 @@ define inreg <28 x i16> @bitcast_v14f32_to_v28i16_scalar(<14 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB29_3:
; GFX11-NEXT: s_branch .LBB29_2
@@ -6025,6 +6261,8 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v11, v11, v32
; SI-NEXT: v_or_b32_e32 v12, v12, v31
; SI-NEXT: v_or_b32_e32 v13, v13, v30
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -6113,6 +6351,8 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6168,6 +6408,8 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v14, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v14, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB30_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -6195,6 +6437,8 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB30_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -6223,6 +6467,8 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB30_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6319,6 +6565,8 @@ define inreg <14 x float> @bitcast_v28i16_to_v14f32_scalar(<28 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s49, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB31_3
; SI-NEXT: .LBB31_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -6391,6 +6639,8 @@ define inreg <14 x float> @bitcast_v28i16_to_v14f32_scalar(<28 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s49, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB31_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -6502,6 +6752,8 @@ define inreg <14 x float> @bitcast_v28i16_to_v14f32_scalar(<28 x i16> inreg %a,
; VI-NEXT: s_and_b32 s5, s5, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB31_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -6544,6 +6796,8 @@ define inreg <14 x float> @bitcast_v28i16_to_v14f32_scalar(<28 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB31_3:
; GFX9-NEXT: s_branch .LBB31_2
@@ -6594,6 +6848,8 @@ define inreg <14 x float> @bitcast_v28i16_to_v14f32_scalar(<28 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_3:
; GFX11-NEXT: s_branch .LBB31_2
@@ -6762,6 +7018,8 @@ define <28 x half> @bitcast_v14f32_to_v28f16(<14 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB32_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -6789,6 +7047,8 @@ define <28 x half> @bitcast_v14f32_to_v28f16(<14 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB32_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -6810,6 +7070,8 @@ define <28 x half> @bitcast_v14f32_to_v28f16(<14 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB32_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6996,6 +7258,8 @@ define inreg <28 x half> @bitcast_v14f32_to_v28f16_scalar(<14 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB33_3:
; VI-NEXT: s_branch .LBB33_2
@@ -7041,6 +7305,8 @@ define inreg <28 x half> @bitcast_v14f32_to_v28f16_scalar(<14 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB33_3:
; GFX9-NEXT: s_branch .LBB33_2
@@ -7091,6 +7357,8 @@ define inreg <28 x half> @bitcast_v14f32_to_v28f16_scalar(<14 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB33_3:
; GFX11-NEXT: s_branch .LBB33_2
@@ -7207,6 +7475,8 @@ define <14 x float> @bitcast_v28f16_to_v14f32(<28 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -7350,6 +7620,8 @@ define <14 x float> @bitcast_v28f16_to_v14f32(<28 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -7405,6 +7677,8 @@ define <14 x float> @bitcast_v28f16_to_v14f32(<28 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: v_or_b32_e32 v0, v0, v14
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB34_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -7433,6 +7707,8 @@ define <14 x float> @bitcast_v28f16_to_v14f32(<28 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB34_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -7461,6 +7737,8 @@ define <14 x float> @bitcast_v28f16_to_v14f32(<28 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB34_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7557,6 +7835,8 @@ define inreg <14 x float> @bitcast_v28f16_to_v14f32_scalar(<28 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s49, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
; SI-NEXT: s_cbranch_execnz .LBB35_4
; SI-NEXT: .LBB35_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s59
@@ -7671,6 +7951,8 @@ define inreg <14 x float> @bitcast_v28f16_to_v14f32_scalar(<28 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_branch .LBB35_5
; SI-NEXT: .LBB35_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
@@ -7787,6 +8069,8 @@ define inreg <14 x float> @bitcast_v28f16_to_v14f32_scalar(<28 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v14, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, s16, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v14
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB35_3:
; VI-NEXT: s_branch .LBB35_2
@@ -7833,6 +8117,8 @@ define inreg <14 x float> @bitcast_v28f16_to_v14f32_scalar(<28 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB35_3:
; GFX9-NEXT: s_branch .LBB35_2
@@ -7883,6 +8169,8 @@ define inreg <14 x float> @bitcast_v28f16_to_v14f32_scalar(<28 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3:
; GFX11-NEXT: s_branch .LBB35_2
@@ -7937,6 +8225,8 @@ define <7 x double> @bitcast_v7i64_to_v7f64(<7 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -7964,6 +8254,8 @@ define <7 x double> @bitcast_v7i64_to_v7f64(<7 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -7991,6 +8283,8 @@ define <7 x double> @bitcast_v7i64_to_v7f64(<7 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8023,6 +8317,8 @@ define <7 x double> @bitcast_v7i64_to_v7f64(<7 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8067,6 +8363,8 @@ define inreg <7 x double> @bitcast_v7i64_to_v7f64_scalar(<7 x i64> inreg %a, i32
; SI-NEXT: s_addc_u32 s27, s27, 0
; SI-NEXT: s_add_u32 s28, s28, 3
; SI-NEXT: s_addc_u32 s29, s29, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB37_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -8109,6 +8407,8 @@ define inreg <7 x double> @bitcast_v7i64_to_v7f64_scalar(<7 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s27, s27, 0
; VI-NEXT: s_add_u32 s28, s28, 3
; VI-NEXT: s_addc_u32 s29, s29, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -8151,6 +8451,8 @@ define inreg <7 x double> @bitcast_v7i64_to_v7f64_scalar(<7 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s27, s27, 0
; GFX9-NEXT: s_add_u32 s28, s28, 3
; GFX9-NEXT: s_addc_u32 s29, s29, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -8194,6 +8496,8 @@ define inreg <7 x double> @bitcast_v7i64_to_v7f64_scalar(<7 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s23, s23, 0
; GFX11-NEXT: s_add_u32 s24, s24, 3
; GFX11-NEXT: s_addc_u32 s25, s25, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -8239,6 +8543,8 @@ define <7 x i64> @bitcast_v7f64_to_v7i64(<7 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -8259,6 +8565,8 @@ define <7 x i64> @bitcast_v7f64_to_v7i64(<7 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8279,6 +8587,8 @@ define <7 x i64> @bitcast_v7f64_to_v7i64(<7 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8300,6 +8610,8 @@ define <7 x i64> @bitcast_v7f64_to_v7i64(<7 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8337,6 +8649,8 @@ define inreg <7 x i64> @bitcast_v7f64_to_v7i64_scalar(<7 x double> inreg %a, i32
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB39_3:
; SI-NEXT: s_branch .LBB39_2
@@ -8375,6 +8689,8 @@ define inreg <7 x i64> @bitcast_v7f64_to_v7i64_scalar(<7 x double> inreg %a, i32
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB39_3:
; VI-NEXT: s_branch .LBB39_2
@@ -8413,6 +8729,8 @@ define inreg <7 x i64> @bitcast_v7f64_to_v7i64_scalar(<7 x double> inreg %a, i32
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB39_3:
; GFX9-NEXT: s_branch .LBB39_2
@@ -8456,6 +8774,8 @@ define inreg <7 x i64> @bitcast_v7f64_to_v7i64_scalar(<7 x double> inreg %a, i32
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB39_3:
; GFX11-NEXT: s_branch .LBB39_2
@@ -8624,6 +8944,8 @@ define <28 x i16> @bitcast_v7i64_to_v28i16(<7 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB40_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8651,6 +8973,8 @@ define <28 x i16> @bitcast_v7i64_to_v28i16(<7 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB40_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8683,6 +9007,8 @@ define <28 x i16> @bitcast_v7i64_to_v28i16(<7 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB40_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8853,6 +9179,8 @@ define inreg <28 x i16> @bitcast_v7i64_to_v28i16_scalar(<7 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB41_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -8895,6 +9223,8 @@ define inreg <28 x i16> @bitcast_v7i64_to_v28i16_scalar(<7 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB41_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -8938,6 +9268,8 @@ define inreg <28 x i16> @bitcast_v7i64_to_v28i16_scalar(<7 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB41_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -9053,6 +9385,8 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v11, v11, v32
; SI-NEXT: v_or_b32_e32 v12, v12, v31
; SI-NEXT: v_or_b32_e32 v13, v13, v30
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -9141,6 +9475,8 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -9196,6 +9532,8 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v14, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v14, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB42_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -9223,6 +9561,8 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB42_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -9251,6 +9591,8 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB42_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9347,6 +9689,8 @@ define inreg <7 x i64> @bitcast_v28i16_to_v7i64_scalar(<28 x i16> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s49, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -9419,6 +9763,8 @@ define inreg <7 x i64> @bitcast_v28i16_to_v7i64_scalar(<28 x i16> inreg %a, i32
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s49, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -9530,6 +9876,8 @@ define inreg <7 x i64> @bitcast_v28i16_to_v7i64_scalar(<28 x i16> inreg %a, i32
; VI-NEXT: s_and_b32 s5, s5, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -9572,6 +9920,8 @@ define inreg <7 x i64> @bitcast_v28i16_to_v7i64_scalar(<28 x i16> inreg %a, i32
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -9622,6 +9972,8 @@ define inreg <7 x i64> @bitcast_v28i16_to_v7i64_scalar(<28 x i16> inreg %a, i32
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -9790,6 +10142,8 @@ define <28 x half> @bitcast_v7i64_to_v28f16(<7 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB44_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -9817,6 +10171,8 @@ define <28 x half> @bitcast_v7i64_to_v28f16(<7 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB44_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -9849,6 +10205,8 @@ define <28 x half> @bitcast_v7i64_to_v28f16(<7 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB44_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10019,6 +10377,8 @@ define inreg <28 x half> @bitcast_v7i64_to_v28f16_scalar(<7 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB45_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -10061,6 +10421,8 @@ define inreg <28 x half> @bitcast_v7i64_to_v28f16_scalar(<7 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB45_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -10104,6 +10466,8 @@ define inreg <28 x half> @bitcast_v7i64_to_v28f16_scalar(<7 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB45_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -10219,6 +10583,8 @@ define <7 x i64> @bitcast_v28f16_to_v7i64(<28 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -10362,6 +10728,8 @@ define <7 x i64> @bitcast_v28f16_to_v7i64(<28 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -10417,6 +10785,8 @@ define <7 x i64> @bitcast_v28f16_to_v7i64(<28 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: v_or_b32_e32 v0, v0, v14
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB46_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -10445,6 +10815,8 @@ define <7 x i64> @bitcast_v28f16_to_v7i64(<28 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB46_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10473,6 +10845,8 @@ define <7 x i64> @bitcast_v28f16_to_v7i64(<28 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB46_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10569,6 +10943,8 @@ define inreg <7 x i64> @bitcast_v28f16_to_v7i64_scalar(<28 x half> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s49, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s59
@@ -10683,6 +11059,8 @@ define inreg <7 x i64> @bitcast_v28f16_to_v7i64_scalar(<28 x half> inreg %a, i32
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
@@ -10799,6 +11177,8 @@ define inreg <7 x i64> @bitcast_v28f16_to_v7i64_scalar(<28 x half> inreg %a, i32
; VI-NEXT: v_add_f16_sdwa v14, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, s16, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v14
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB47_3:
; VI-NEXT: s_branch .LBB47_2
@@ -10845,6 +11225,8 @@ define inreg <7 x i64> @bitcast_v28f16_to_v7i64_scalar(<28 x half> inreg %a, i32
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -10895,6 +11277,8 @@ define inreg <7 x i64> @bitcast_v28f16_to_v7i64_scalar(<28 x half> inreg %a, i32
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -11049,6 +11433,8 @@ define <28 x i16> @bitcast_v7f64_to_v28i16(<7 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB48_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -11069,6 +11455,8 @@ define <28 x i16> @bitcast_v7f64_to_v28i16(<7 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB48_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -11090,6 +11478,8 @@ define <28 x i16> @bitcast_v7f64_to_v28i16(<7 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB48_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11262,6 +11652,8 @@ define inreg <28 x i16> @bitcast_v7f64_to_v28i16_scalar(<7 x double> inreg %a, i
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB49_3:
; VI-NEXT: s_branch .LBB49_2
@@ -11300,6 +11692,8 @@ define inreg <28 x i16> @bitcast_v7f64_to_v28i16_scalar(<7 x double> inreg %a, i
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB49_3:
; GFX9-NEXT: s_branch .LBB49_2
@@ -11343,6 +11737,8 @@ define inreg <28 x i16> @bitcast_v7f64_to_v28i16_scalar(<7 x double> inreg %a, i
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB49_3:
; GFX11-NEXT: s_branch .LBB49_2
@@ -11459,6 +11855,8 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v11, v11, v32
; SI-NEXT: v_or_b32_e32 v12, v12, v31
; SI-NEXT: v_or_b32_e32 v13, v13, v30
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -11547,6 +11945,8 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -11602,6 +12002,8 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v14, 3, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v14, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB50_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -11629,6 +12031,8 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB50_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -11657,6 +12061,8 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB50_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11753,6 +12159,8 @@ define inreg <7 x double> @bitcast_v28i16_to_v7f64_scalar(<28 x i16> inreg %a, i
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s49, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -11825,6 +12233,8 @@ define inreg <7 x double> @bitcast_v28i16_to_v7f64_scalar(<28 x i16> inreg %a, i
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s49, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -11936,6 +12346,8 @@ define inreg <7 x double> @bitcast_v28i16_to_v7f64_scalar(<28 x i16> inreg %a, i
; VI-NEXT: s_and_b32 s5, s5, 0xffff
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -11978,6 +12390,8 @@ define inreg <7 x double> @bitcast_v28i16_to_v7f64_scalar(<28 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -12028,6 +12442,8 @@ define inreg <7 x double> @bitcast_v28i16_to_v7f64_scalar(<28 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -12182,6 +12598,8 @@ define <28 x half> @bitcast_v7f64_to_v28f16(<7 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB52_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12202,6 +12620,8 @@ define <28 x half> @bitcast_v7f64_to_v28f16(<7 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB52_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12223,6 +12643,8 @@ define <28 x half> @bitcast_v7f64_to_v28f16(<7 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB52_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -12395,6 +12817,8 @@ define inreg <28 x half> @bitcast_v7f64_to_v28f16_scalar(<7 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB53_3:
; VI-NEXT: s_branch .LBB53_2
@@ -12433,6 +12857,8 @@ define inreg <28 x half> @bitcast_v7f64_to_v28f16_scalar(<7 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB53_3:
; GFX9-NEXT: s_branch .LBB53_2
@@ -12476,6 +12902,8 @@ define inreg <28 x half> @bitcast_v7f64_to_v28f16_scalar(<7 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB53_3:
; GFX11-NEXT: s_branch .LBB53_2
@@ -12592,6 +13020,8 @@ define <7 x double> @bitcast_v28f16_to_v7f64(<28 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v14
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr27
@@ -12735,6 +13165,8 @@ define <7 x double> @bitcast_v28f16_to_v7f64(<28 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -12790,6 +13222,8 @@ define <7 x double> @bitcast_v28f16_to_v7f64(<28 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: v_or_b32_e32 v0, v0, v14
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB54_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12818,6 +13252,8 @@ define <7 x double> @bitcast_v28f16_to_v7f64(<28 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB54_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12846,6 +13282,8 @@ define <7 x double> @bitcast_v28f16_to_v7f64(<28 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB54_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -12942,6 +13380,8 @@ define inreg <7 x double> @bitcast_v28f16_to_v7f64_scalar(<28 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s49, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr50
+; SI-NEXT: ; implicit-def: $sgpr51
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s59
@@ -13056,6 +13496,8 @@ define inreg <7 x double> @bitcast_v28f16_to_v7f64_scalar(<28 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
@@ -13172,6 +13614,8 @@ define inreg <7 x double> @bitcast_v28f16_to_v7f64_scalar(<28 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v14, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v0, s16, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v14
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB55_3:
; VI-NEXT: s_branch .LBB55_2
@@ -13218,6 +13662,8 @@ define inreg <7 x double> @bitcast_v28f16_to_v7f64_scalar(<28 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -13268,6 +13714,8 @@ define inreg <7 x double> @bitcast_v28f16_to_v7f64_scalar(<28 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
@@ -13613,6 +14061,8 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v17
; VI-NEXT: v_or_b32_e32 v1, v1, v16
; VI-NEXT: v_or_b32_e32 v0, v0, v15
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB56_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -13640,6 +14090,8 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB56_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -13668,6 +14120,8 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB56_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -14006,6 +14460,8 @@ define inreg <28 x half> @bitcast_v28i16_to_v28f16_scalar(<28 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB57_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -14048,6 +14504,8 @@ define inreg <28 x half> @bitcast_v28i16_to_v28f16_scalar(<28 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB57_3:
; GFX9-NEXT: s_branch .LBB57_2
@@ -14098,6 +14556,8 @@ define inreg <28 x half> @bitcast_v28i16_to_v28f16_scalar(<28 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB57_3:
; GFX11-NEXT: s_branch .LBB57_2
@@ -14369,6 +14829,8 @@ define <28 x i16> @bitcast_v28f16_to_v28i16(<28 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v17, v2
; VI-NEXT: v_or_b32_e32 v1, v16, v1
; VI-NEXT: v_or_b32_e32 v0, v14, v0
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: .LBB58_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -14397,6 +14859,8 @@ define <28 x i16> @bitcast_v28f16_to_v28i16(<28 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: .LBB58_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -14425,6 +14889,8 @@ define <28 x i16> @bitcast_v28f16_to_v28i16(<28 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: .LBB58_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -14745,6 +15211,8 @@ define inreg <28 x i16> @bitcast_v28f16_to_v28i16_scalar(<28 x half> inreg %a, i
; VI-NEXT: v_add_f16_e32 v0, s17, v0
; VI-NEXT: v_or_b32_e32 v1, v0, v1
; VI-NEXT: v_or_b32_e32 v0, v14, v15
+; VI-NEXT: ; implicit-def: $vgpr14
+; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB59_3:
; VI-NEXT: s_branch .LBB59_2
@@ -14791,6 +15259,8 @@ define inreg <28 x i16> @bitcast_v28f16_to_v28i16_scalar(<28 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr14
+; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB59_3:
; GFX9-NEXT: s_branch .LBB59_2
@@ -14841,6 +15311,8 @@ define inreg <28 x i16> @bitcast_v28f16_to_v28i16_scalar(<28 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr14
+; GFX11-NEXT: ; implicit-def: $vgpr14
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB59_3:
; GFX11-NEXT: s_branch .LBB59_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 092528a4feb1e..b3b5a9b5cb903 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -9625,18 +9625,45 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB24_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
@@ -9644,10 +9671,13 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
@@ -9658,12 +9688,16 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
@@ -9671,18 +9705,32 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
@@ -12883,8 +12931,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:108
@@ -12893,20 +12941,20 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:20
@@ -12917,14 +12965,13 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v14.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v12.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v6.l
@@ -12948,17 +12995,41 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB26_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v119, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v117, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v113, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v102, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v101, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v99, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v96, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -12966,32 +13037,72 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v30, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v84, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v71, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v70, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v68, v67, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v65, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v64, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v54, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v50, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
@@ -13006,14 +13117,14 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
@@ -13036,20 +13147,20 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
@@ -13058,8 +13169,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB26_2
@@ -13079,13 +13190,13 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v103.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v101.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v100.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v99.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v102.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
@@ -13095,12 +13206,12 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v97.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v16.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v20.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v96.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v26.l, 3
@@ -13128,7 +13239,7 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v80.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v71.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v70.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v68.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v6.l
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v7.l
@@ -13137,7 +13248,7 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v87.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v65.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v64.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v55.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v54.l, 3
@@ -13152,13 +13263,13 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v9.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v83.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v50.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v51.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v49.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v8.h
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v71.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v69.l
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v12.h
@@ -13170,15 +13281,15 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v67.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v36.l
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v11.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v65.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v11.h, v11.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v53.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
@@ -14695,10 +14806,10 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
@@ -14708,38 +14819,84 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -14750,10 +14907,10 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -14924,7 +15081,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
@@ -14936,7 +15093,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
@@ -24385,18 +24542,45 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
@@ -24404,10 +24588,13 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
@@ -24418,12 +24605,16 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
@@ -24431,18 +24622,32 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
@@ -27876,8 +28081,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:108
@@ -27886,20 +28091,20 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:20
@@ -27910,14 +28115,13 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v14.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v12.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v6.l
@@ -27941,17 +28145,41 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v119, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v117, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v113, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v102, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v101, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v99, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v96, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -27959,32 +28187,72 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v30, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v84, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v71, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v70, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v68, v67, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v65, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v64, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v54, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v50, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
@@ -27999,14 +28267,14 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
@@ -28029,20 +28297,20 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
@@ -28051,8 +28319,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
@@ -28072,13 +28340,13 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v103.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v101.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v100.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v99.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v102.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
@@ -28088,12 +28356,12 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v97.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v16.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v20.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v96.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v26.l, 3
@@ -28121,7 +28389,7 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v80.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v71.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v70.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v68.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v6.l
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v7.l
@@ -28130,7 +28398,7 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v87.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v65.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v64.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v55.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v54.l, 3
@@ -28145,13 +28413,13 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v9.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v83.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v50.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v51.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v49.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v8.h
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v71.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v69.l
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v12.h
@@ -28163,15 +28431,15 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v67.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v36.l
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v11.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v65.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v11.h, v11.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v53.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
@@ -29688,10 +29956,10 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
@@ -29701,38 +29969,84 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -29743,10 +30057,10 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -29917,7 +30231,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
@@ -29929,7 +30243,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
@@ -38524,18 +38838,45 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB68_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
@@ -38543,10 +38884,13 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
@@ -38557,12 +38901,16 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
@@ -38570,18 +38918,32 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
@@ -41787,8 +42149,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:108
@@ -41797,20 +42159,20 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:20
@@ -41821,14 +42183,13 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v14.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v12.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v6.l
@@ -41852,17 +42213,41 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB70_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v119, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v117, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v113, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v102, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v101, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v99, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v96, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -41870,32 +42255,72 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v30, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v84, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v71, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v70, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v68, v67, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v65, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v64, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v54, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v50, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
@@ -41910,14 +42335,14 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
@@ -41940,20 +42365,20 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
@@ -41962,8 +42387,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB70_2
@@ -41983,13 +42408,13 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v103.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v101.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v100.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v99.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v102.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
@@ -41999,12 +42424,12 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v97.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v16.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v20.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v96.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v26.l, 3
@@ -42032,7 +42457,7 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v80.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v71.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v70.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v68.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v6.l
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v7.l
@@ -42041,7 +42466,7 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v87.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v65.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v64.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v55.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v54.l, 3
@@ -42056,13 +42481,13 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v9.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v83.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v50.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v51.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v49.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v8.h
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v71.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v69.l
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v12.h
@@ -42074,15 +42499,15 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v67.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v36.l
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v11.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v65.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v11.h, v11.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v53.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
@@ -43599,10 +44024,10 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
@@ -43612,38 +44037,84 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -43654,10 +44125,10 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -43828,7 +44299,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
@@ -43840,7 +44311,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
@@ -51693,18 +52164,45 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB84_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
@@ -51712,10 +52210,13 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
@@ -51726,12 +52227,16 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
@@ -51739,18 +52244,32 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
@@ -55165,8 +55684,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:108
@@ -55175,20 +55694,20 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:96
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:72
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:20
@@ -55199,14 +55718,13 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v15.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v14.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v13.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v12.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v6.l
@@ -55230,17 +55748,41 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB86_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v119, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v117, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v113, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v102, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v101, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v99, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v96, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -55248,32 +55790,72 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v30, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v84, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v71, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v70, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v68, v67, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v65, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v64, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v54, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v50, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
@@ -55288,14 +55870,14 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
@@ -55318,20 +55900,20 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
@@ -55340,8 +55922,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB86_2
@@ -55361,13 +55943,13 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v103.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v102.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v101.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v100.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v99.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v101.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v102.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
@@ -55377,12 +55959,12 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v97.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v16.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v20.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v96.l
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v4.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v22.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v26.l, 3
@@ -55410,7 +55992,7 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v80.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v71.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v70.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v68.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v6.l
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v7.l
@@ -55419,7 +56001,7 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v87.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v65.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v64.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v55.l
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v54.l, 3
@@ -55434,13 +56016,13 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v9.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v83.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v51.l, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v50.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v51.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v49.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v8.h
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.l, v9.h
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v71.l
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v69.l
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v12.h
@@ -55452,15 +56034,15 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v67.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v35.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v36.l
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v11.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v65.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v34.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v32.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v33.l
; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v11.h, v11.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v53.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
@@ -56977,10 +57559,10 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
@@ -56990,38 +57572,84 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -57032,10 +57660,10 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -57206,7 +57834,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
@@ -57218,7 +57846,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
@@ -65073,18 +65701,45 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB96_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
@@ -65092,10 +65747,13 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
@@ -65106,12 +65764,16 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
@@ -65119,18 +65781,32 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
@@ -68864,20 +69540,20 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
@@ -68886,64 +69562,63 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v30.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v24.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v48.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v49.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v50.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v53.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v54.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v55.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -68953,147 +69628,185 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB98_4
; GFX11-TRUE16-NEXT: .LBB98_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB98_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v87, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v81, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v85, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v82, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v86, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v83, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v67, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v71, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v68, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v66, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v98, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v96, v27, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v84, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v51, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.h
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v19.h
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v80, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.h
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v20.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v38, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-TRUE16-NEXT: .LBB98_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v39.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v71.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
@@ -69101,129 +69814,123 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v19.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v97.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v80.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v50.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v84.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v69.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v83.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v64.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v28.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v82.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v22.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v65.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v86.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v68.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v54.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v26.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v81.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v67.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v85.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v30.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v53.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
@@ -71072,54 +71779,100 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -71127,70 +71880,70 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s59, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s42, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s41, 0xff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s62, s58, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s10, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s7, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s61, s47, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s44, v8
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s43, s14, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v49
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s72, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s73, s57, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s60, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s45, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s12, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s79, s9, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s5, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s13, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v38
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s6, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s8, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s15, 0xff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v39
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v34
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v31
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
@@ -71198,92 +71951,92 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-TRUE16-NEXT: .LBB99_2: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v34
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s45, s12, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s40, s8, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s15, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s41, s11, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s46, s13, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s6, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s60, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s74, s72, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s43, s14, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s59, s42, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s56, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, s61, s47, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
@@ -77702,18 +78455,45 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB104_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
@@ -77721,10 +78501,13 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
@@ -77735,12 +78518,16 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
@@ -77748,18 +78535,32 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
@@ -81621,20 +82422,20 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
@@ -81643,64 +82444,63 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v30.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v24.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v48.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v49.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v50.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v53.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v54.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v55.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -81710,147 +82510,185 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB106_4
; GFX11-TRUE16-NEXT: .LBB106_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB106_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v87, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v81, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v85, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v82, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v86, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v83, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v67, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v71, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v68, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v66, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v98, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v96, v27, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v84, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v51, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.h
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v19.h
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v80, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.h
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v20.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v38, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB106_2
; GFX11-TRUE16-NEXT: .LBB106_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v39.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v71.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
@@ -81858,129 +82696,123 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v19.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v97.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v80.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v50.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v84.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v69.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v83.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v64.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v28.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v82.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v22.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v65.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v86.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v68.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v54.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v26.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v81.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v67.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v85.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v30.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v53.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
@@ -83829,54 +84661,100 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -83884,70 +84762,70 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s59, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s42, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s41, 0xff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s62, s58, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s10, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s7, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s61, s47, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s44, v8
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s43, s14, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v49
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s72, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s73, s57, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s60, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s45, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s12, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s79, s9, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s5, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s13, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v38
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s6, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s8, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s15, 0xff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v39
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v34
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v31
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
@@ -83955,92 +84833,92 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-TRUE16-NEXT: .LBB107_2: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v34
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s45, s12, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s40, s8, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s15, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s41, s11, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s46, s13, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s6, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s60, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s74, s72, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s43, s14, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s59, s42, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s56, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, s61, s47, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
@@ -86360,131 +87238,131 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[7:8]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[30:31], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[27:28], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[31:32], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.h, v1.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v1.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.h, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v2.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.h, v4.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v4.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v5.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v6.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.h, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v7.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v8.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.h, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.h, v9.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v9.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.h, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v11.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.h, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v12.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.h, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.h, v13.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.h, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.h, v14.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.h, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.h, v15.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.h, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.h, v16.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.h, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.h, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.h, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.h, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.h, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.h, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.h, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.h, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.h, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.h, v16.h
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
@@ -86497,40 +87375,41 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v20, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v20, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v24, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v52, v18, v23 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v53, v18, v23 :: v_dual_and_b32 v2, 0xffff0000, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v1, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v24, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v23, v25, v1, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v21, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v52.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v23, v26, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v53.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v23, v26, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
@@ -86540,49 +87419,46 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v20 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v54.h
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v17
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v55, v19, v21 :: v_dual_add_f32 v22, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v53.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v19, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v22
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v1, v20, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v55.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v1, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v1, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v54.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v55.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v64, v3, v21 :: v_dual_and_b32 v3, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v65, v3, v21 :: v_dual_lshlrev_b32 v6, 16, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v8
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
@@ -86591,18 +87467,20 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v64.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v64.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v65.h
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v2, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v5, v6, 0x7fff
@@ -86614,14 +87492,13 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v65.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v67, v4, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v7 :: v_dual_lshlrev_b32 v5, 16, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v1, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
@@ -86630,230 +87507,298 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v67.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v66.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v22
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v1, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v21
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v67, v3, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v70, v3, v8 :: v_dual_and_b32 v3, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v68, v1, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v12
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v68, v1, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v66.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v2, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v67.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v70.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v24
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v23
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v68.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v13
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v6, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v81, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v87, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v81.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v71, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v87.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v82, v1, v2, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v25
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v71.h
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v27, v2, v3 :: v_dual_add_f32 v2, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v29, v2, v3 :: v_dual_and_b32 v6, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v4 :: v_dual_add_f32 v3, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v28
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v97, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v82.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v100, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v97.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v99, v6, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v97, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v100.h
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v15
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v99.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v97.h
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v15
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[25:26]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v115, v4, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v5 :: v_dual_add_f32 v6, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[29:30]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v34
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v114, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v15
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v115.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v117, v2, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v114.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v112, v2, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v10, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v34
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[31:32], 24, v[33:34]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v30
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v33
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v29
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v27
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v118, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v115, v7, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v4, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v117.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v2, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v118.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v112.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v115.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v49
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v49
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[48:49]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[30:31], 24, v[32:33]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v48
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v39
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v39
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[27:28], 24, v[38:39]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v38
; GFX11-TRUE16-NEXT: .LBB108_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v53.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v54.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v17.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v18.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v55.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v64.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v19.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v54.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v52.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v65.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v55.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v53.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v66.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v21.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v5, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v6, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v5, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v7, v128, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v20.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v64.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v65.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v22.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v114, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v113, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v25.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v67.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v70.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v23.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v66.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v67.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v24.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v81.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v25.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v87.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v68.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v26.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v97.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v27.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v103, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v102, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v100.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v29.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v34.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v71.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v28.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v82.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v30.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v115.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v32.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v99.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v33.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v118.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v48.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v117.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v49.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v114.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v33.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v97.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v115.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v38.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v112.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v39.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
@@ -92416,20 +93361,20 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:116
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:84
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:68
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
@@ -92438,64 +93383,63 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v30.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v24.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v48.h
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v49.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v50.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v53.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v54.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v55.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -92505,147 +93449,185 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB110_4
; GFX11-TRUE16-NEXT: .LBB110_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB110_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v87, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v81, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v85, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v82, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v86, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v83, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v67, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v71, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v68, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v66, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v98, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v28, v22, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v96, v27, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v84, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v51, v23, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v55, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.h
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
-; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.l
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
-; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.h
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
-; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
-; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v19.h
+; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v32.l
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v80, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
-; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.h
+; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v97, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
-; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
-; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v20.l
+; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v38, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB110_2
; GFX11-TRUE16-NEXT: .LBB110_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v48.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v39.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v32.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v38.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v71.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v33.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
@@ -92653,129 +93635,123 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v19.h, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v97.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.l, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v80.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.l, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v50.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.h, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v66.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v84.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v49.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v69.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v83.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v51.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v52.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v23.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v64.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v28.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v82.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v22.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v65.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v96.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v86.l, 3
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v68.l, 3
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v27.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v54.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v26.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v81.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v98.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v67.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v85.l, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v87.l, 3
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v30.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v53.l
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v25.l
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v24.l
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v70.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
@@ -94530,54 +95506,100 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v14
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v6
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
@@ -94585,70 +95607,70 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s59, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s42, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s41, 0xff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s62, s58, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s10, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s7, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s61, s47, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s44, v8
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s43, s14, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v49
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s72, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s73, s57, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s60, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s45, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s12, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s79, s9, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s5, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s13, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v38
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s6, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s8, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s15, 0xff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v39
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v34
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v31
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
@@ -94656,92 +95678,92 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-TRUE16-NEXT: .LBB111_2: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v34
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s45, s12, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s40, s8, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s15, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s41, s11, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s46, s13, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s6, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s60, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s74, s72, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s43, s14, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s59, s42, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s56, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, s61, s47, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
index 9a74ac7e2b943..02c1d9ccb46cb 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
@@ -34,6 +34,20 @@ define <18 x float> @bitcast_v18i32_to_v18f32(<18 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -65,6 +79,20 @@ define <18 x float> @bitcast_v18i32_to_v18f32(<18 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -96,6 +124,20 @@ define <18 x float> @bitcast_v18i32_to_v18f32(<18 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -128,6 +170,20 @@ define <18 x float> @bitcast_v18i32_to_v18f32(<18 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -180,6 +236,20 @@ define inreg <18 x float> @bitcast_v18i32_to_v18f32_scalar(<18 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB1_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -234,6 +304,20 @@ define inreg <18 x float> @bitcast_v18i32_to_v18f32_scalar(<18 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB1_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -288,6 +372,20 @@ define inreg <18 x float> @bitcast_v18i32_to_v18f32_scalar(<18 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB1_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -340,6 +438,20 @@ define inreg <18 x float> @bitcast_v18i32_to_v18f32_scalar(<18 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB1_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -399,6 +511,20 @@ define <18 x i32> @bitcast_v18f32_to_v18i32(<18 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -430,6 +556,20 @@ define <18 x i32> @bitcast_v18f32_to_v18i32(<18 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -461,6 +601,20 @@ define <18 x i32> @bitcast_v18f32_to_v18i32(<18 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -484,6 +638,20 @@ define <18 x i32> @bitcast_v18f32_to_v18i32(<18 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -564,6 +732,20 @@ define inreg <18 x i32> @bitcast_v18f32_to_v18i32_scalar(<18 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: .LBB3_3:
; SI-NEXT: s_branch .LBB3_2
@@ -675,6 +857,20 @@ define inreg <18 x i32> @bitcast_v18f32_to_v18i32_scalar(<18 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB3_5
; VI-NEXT: .LBB3_3:
; VI-NEXT: s_branch .LBB3_2
@@ -786,6 +982,20 @@ define inreg <18 x i32> @bitcast_v18f32_to_v18i32_scalar(<18 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: .LBB3_3:
; GFX9-NEXT: s_branch .LBB3_2
@@ -899,6 +1109,20 @@ define inreg <18 x i32> @bitcast_v18f32_to_v18i32_scalar(<18 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_branch .LBB3_5
; GFX11-NEXT: .LBB3_3:
; GFX11-NEXT: s_branch .LBB3_2
@@ -980,6 +1204,20 @@ define <9 x i64> @bitcast_v18i32_to_v9i64(<18 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1011,6 +1249,20 @@ define <9 x i64> @bitcast_v18i32_to_v9i64(<18 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1042,6 +1294,20 @@ define <9 x i64> @bitcast_v18i32_to_v9i64(<18 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1074,6 +1340,20 @@ define <9 x i64> @bitcast_v18i32_to_v9i64(<18 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1126,6 +1406,20 @@ define inreg <9 x i64> @bitcast_v18i32_to_v9i64_scalar(<18 x i32> inreg %a, i32
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1180,6 +1474,20 @@ define inreg <9 x i64> @bitcast_v18i32_to_v9i64_scalar(<18 x i32> inreg %a, i32
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1234,6 +1542,20 @@ define inreg <9 x i64> @bitcast_v18i32_to_v9i64_scalar(<18 x i32> inreg %a, i32
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1286,6 +1608,20 @@ define inreg <9 x i64> @bitcast_v18i32_to_v9i64_scalar(<18 x i32> inreg %a, i32
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1345,6 +1681,20 @@ define <18 x i32> @bitcast_v9i64_to_v18i32(<9 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1376,6 +1726,20 @@ define <18 x i32> @bitcast_v9i64_to_v18i32(<9 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1407,6 +1771,20 @@ define <18 x i32> @bitcast_v9i64_to_v18i32(<9 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1444,6 +1822,20 @@ define <18 x i32> @bitcast_v9i64_to_v18i32(<9 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1496,6 +1888,20 @@ define inreg <18 x i32> @bitcast_v9i64_to_v18i32_scalar(<9 x i64> inreg %a, i32
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB7_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1550,6 +1956,20 @@ define inreg <18 x i32> @bitcast_v9i64_to_v18i32_scalar(<9 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB7_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1604,6 +2024,20 @@ define inreg <18 x i32> @bitcast_v9i64_to_v18i32_scalar(<9 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB7_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1656,6 +2090,20 @@ define inreg <18 x i32> @bitcast_v9i64_to_v18i32_scalar(<9 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1715,6 +2163,20 @@ define <9 x double> @bitcast_v18i32_to_v9f64(<18 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1746,6 +2208,20 @@ define <9 x double> @bitcast_v18i32_to_v9f64(<18 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1777,6 +2253,20 @@ define <9 x double> @bitcast_v18i32_to_v9f64(<18 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1809,6 +2299,20 @@ define <9 x double> @bitcast_v18i32_to_v9f64(<18 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1861,6 +2365,20 @@ define inreg <9 x double> @bitcast_v18i32_to_v9f64_scalar(<18 x i32> inreg %a, i
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1915,6 +2433,20 @@ define inreg <9 x double> @bitcast_v18i32_to_v9f64_scalar(<18 x i32> inreg %a, i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1969,6 +2501,20 @@ define inreg <9 x double> @bitcast_v18i32_to_v9f64_scalar(<18 x i32> inreg %a, i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2021,6 +2567,20 @@ define inreg <9 x double> @bitcast_v18i32_to_v9f64_scalar(<18 x i32> inreg %a, i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2071,6 +2631,20 @@ define <18 x i32> @bitcast_v9f64_to_v18i32(<9 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2093,6 +2667,20 @@ define <18 x i32> @bitcast_v9f64_to_v18i32(<9 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2115,6 +2703,20 @@ define <18 x i32> @bitcast_v9f64_to_v18i32(<9 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2138,6 +2740,20 @@ define <18 x i32> @bitcast_v9f64_to_v18i32(<9 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2209,6 +2825,20 @@ define inreg <18 x i32> @bitcast_v9f64_to_v18i32_scalar(<9 x double> inreg %a, i
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB11_5
; SI-NEXT: .LBB11_3:
; SI-NEXT: s_branch .LBB11_2
@@ -2311,6 +2941,20 @@ define inreg <18 x i32> @bitcast_v9f64_to_v18i32_scalar(<9 x double> inreg %a, i
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB11_5
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -2413,6 +3057,20 @@ define inreg <18 x i32> @bitcast_v9f64_to_v18i32_scalar(<9 x double> inreg %a, i
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB11_5
; GFX9-NEXT: .LBB11_3:
; GFX9-NEXT: s_branch .LBB11_2
@@ -2517,6 +3175,20 @@ define inreg <18 x i32> @bitcast_v9f64_to_v18i32_scalar(<9 x double> inreg %a, i
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_branch .LBB11_5
; GFX11-NEXT: .LBB11_3:
; GFX11-NEXT: s_branch .LBB11_2
@@ -3843,6 +4515,20 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -3939,6 +4625,20 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -4026,6 +4726,20 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
@@ -4103,6 +4817,20 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v18, 3, v32
; VI-NEXT: v_add_u16_sdwa v17, v32, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB14_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -4176,10 +4904,24 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB14_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr18
-; GFX9-NEXT: ; kill: killed $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; kill: killed $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
@@ -4275,6 +5017,20 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v14, v14, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -4314,10 +5070,31 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -4336,7 +5113,20 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4382,10 +5172,31 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -4404,7 +5215,20 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4528,6 +5352,20 @@ define inreg <18 x i32> @bitcast_v36i16_to_v18i32_scalar(<36 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s53, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -4620,6 +5458,20 @@ define inreg <18 x i32> @bitcast_v36i16_to_v18i32_scalar(<36 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -4766,6 +5618,20 @@ define inreg <18 x i32> @bitcast_v36i16_to_v18i32_scalar(<36 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s53, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -4858,6 +5724,20 @@ define inreg <18 x i32> @bitcast_v36i16_to_v18i32_scalar(<36 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s53, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB15_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
@@ -4982,6 +5862,20 @@ define inreg <18 x i32> @bitcast_v36i16_to_v18i32_scalar(<36 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v15, s51, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, s52, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB15_5
; GFX9-NEXT: .LBB15_3:
; GFX9-NEXT: s_branch .LBB15_2
@@ -5100,6 +5994,20 @@ define inreg <18 x i32> @bitcast_v36i16_to_v18i32_scalar(<36 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_3:
; GFX11-NEXT: s_branch .LBB15_2
@@ -6413,6 +7321,20 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -6580,6 +7502,20 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v19, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB18_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -6667,6 +7603,20 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
@@ -6744,6 +7694,20 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v17, v32, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, 0x200, v32
; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB18_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -6817,10 +7781,24 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB18_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr18
-; GFX9-NEXT: ; kill: killed $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; kill: killed $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
@@ -6917,6 +7895,20 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v14, v14, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -6956,10 +7948,31 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -6978,7 +7991,20 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7024,10 +8050,31 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -7046,7 +8093,20 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -7170,6 +8230,20 @@ define inreg <18 x i32> @bitcast_v36f16_to_v18i32_scalar(<36 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s53, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB19_4
; SI-NEXT: .LBB19_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s91
@@ -7316,6 +8390,20 @@ define inreg <18 x i32> @bitcast_v36f16_to_v18i32_scalar(<36 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB19_5
; SI-NEXT: .LBB19_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -7478,6 +8566,20 @@ define inreg <18 x i32> @bitcast_v36f16_to_v18i32_scalar(<36 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s53, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr54
+; VI-NEXT: ; implicit-def: $sgpr55
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 0x200
@@ -7553,6 +8655,20 @@ define inreg <18 x i32> @bitcast_v36f16_to_v18i32_scalar(<36 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v18, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s6, v17
; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -7694,6 +8810,20 @@ define inreg <18 x i32> @bitcast_v36f16_to_v18i32_scalar(<36 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v15, s51, v17 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, s52, v17 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, s53, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB19_5
; GFX9-NEXT: .LBB19_3:
; GFX9-NEXT: s_branch .LBB19_2
@@ -7812,6 +8942,20 @@ define inreg <18 x i32> @bitcast_v36f16_to_v18i32_scalar(<36 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3:
; GFX11-NEXT: s_branch .LBB19_2
@@ -7878,6 +9022,20 @@ define <9 x i64> @bitcast_v18f32_to_v9i64(<18 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -7909,6 +9067,20 @@ define <9 x i64> @bitcast_v18f32_to_v9i64(<18 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -7940,6 +9112,20 @@ define <9 x i64> @bitcast_v18f32_to_v9i64(<18 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -7963,6 +9149,20 @@ define <9 x i64> @bitcast_v18f32_to_v9i64(<18 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8043,6 +9243,20 @@ define inreg <9 x i64> @bitcast_v18f32_to_v9i64_scalar(<18 x float> inreg %a, i3
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB21_5
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -8154,6 +9368,20 @@ define inreg <9 x i64> @bitcast_v18f32_to_v9i64_scalar(<18 x float> inreg %a, i3
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB21_5
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -8265,6 +9493,20 @@ define inreg <9 x i64> @bitcast_v18f32_to_v9i64_scalar(<18 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB21_5
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -8378,6 +9620,20 @@ define inreg <9 x i64> @bitcast_v18f32_to_v9i64_scalar(<18 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_branch .LBB21_5
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -8459,6 +9715,20 @@ define <18 x float> @bitcast_v9i64_to_v18f32(<9 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -8490,6 +9760,20 @@ define <18 x float> @bitcast_v9i64_to_v18f32(<9 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8521,6 +9805,20 @@ define <18 x float> @bitcast_v9i64_to_v18f32(<9 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8558,6 +9856,20 @@ define <18 x float> @bitcast_v9i64_to_v18f32(<9 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8610,6 +9922,20 @@ define inreg <18 x float> @bitcast_v9i64_to_v18f32_scalar(<9 x i64> inreg %a, i3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -8664,6 +9990,20 @@ define inreg <18 x float> @bitcast_v9i64_to_v18f32_scalar(<9 x i64> inreg %a, i3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB23_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -8718,6 +10058,20 @@ define inreg <18 x float> @bitcast_v9i64_to_v18f32_scalar(<9 x i64> inreg %a, i3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB23_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -8770,6 +10124,20 @@ define inreg <18 x float> @bitcast_v9i64_to_v18f32_scalar(<9 x i64> inreg %a, i3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -8829,6 +10197,20 @@ define <9 x double> @bitcast_v18f32_to_v9f64(<18 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -8860,6 +10242,20 @@ define <9 x double> @bitcast_v18f32_to_v9f64(<18 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8891,6 +10287,20 @@ define <9 x double> @bitcast_v18f32_to_v9f64(<18 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8914,6 +10324,20 @@ define <9 x double> @bitcast_v18f32_to_v9f64(<18 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8994,6 +10418,20 @@ define inreg <9 x double> @bitcast_v18f32_to_v9f64_scalar(<18 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB25_5
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -9105,6 +10543,20 @@ define inreg <9 x double> @bitcast_v18f32_to_v9f64_scalar(<18 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB25_5
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -9216,6 +10668,20 @@ define inreg <9 x double> @bitcast_v18f32_to_v9f64_scalar(<18 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB25_5
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -9329,6 +10795,20 @@ define inreg <9 x double> @bitcast_v18f32_to_v9f64_scalar(<18 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_branch .LBB25_5
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -9401,6 +10881,20 @@ define <18 x float> @bitcast_v9f64_to_v18f32(<9 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -9423,6 +10917,20 @@ define <18 x float> @bitcast_v9f64_to_v18f32(<9 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -9445,6 +10953,20 @@ define <18 x float> @bitcast_v9f64_to_v18f32(<9 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -9468,6 +10990,20 @@ define <18 x float> @bitcast_v9f64_to_v18f32(<9 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9539,6 +11075,20 @@ define inreg <18 x float> @bitcast_v9f64_to_v18f32_scalar(<9 x double> inreg %a,
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB27_5
; SI-NEXT: .LBB27_3:
; SI-NEXT: s_branch .LBB27_2
@@ -9641,6 +11191,20 @@ define inreg <18 x float> @bitcast_v9f64_to_v18f32_scalar(<9 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB27_5
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -9743,6 +11307,20 @@ define inreg <18 x float> @bitcast_v9f64_to_v18f32_scalar(<9 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB27_5
; GFX9-NEXT: .LBB27_3:
; GFX9-NEXT: s_branch .LBB27_2
@@ -9847,6 +11425,20 @@ define inreg <18 x float> @bitcast_v9f64_to_v18f32_scalar(<9 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_branch .LBB27_5
; GFX11-NEXT: .LBB27_3:
; GFX11-NEXT: s_branch .LBB27_2
@@ -11370,6 +12962,20 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -11466,6 +13072,20 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -11553,6 +13173,20 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
@@ -11630,6 +13264,20 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v18, 3, v32
; VI-NEXT: v_add_u16_sdwa v17, v32, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB30_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -11703,10 +13351,24 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB30_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr18
-; GFX9-NEXT: ; kill: killed $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; kill: killed $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
@@ -11802,6 +13464,20 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v14, v14, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -11841,10 +13517,31 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -11863,7 +13560,20 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -11909,10 +13619,31 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -11931,7 +13662,20 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -12055,6 +13799,20 @@ define inreg <18 x float> @bitcast_v36i16_to_v18f32_scalar(<36 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s53, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB31_3
; SI-NEXT: .LBB31_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -12147,6 +13905,20 @@ define inreg <18 x float> @bitcast_v36i16_to_v18f32_scalar(<36 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB31_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -12293,6 +14065,20 @@ define inreg <18 x float> @bitcast_v36i16_to_v18f32_scalar(<36 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s53, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB31_3
; VI-NEXT: .LBB31_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -12385,6 +14171,20 @@ define inreg <18 x float> @bitcast_v36i16_to_v18f32_scalar(<36 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s53, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB31_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
@@ -12509,6 +14309,20 @@ define inreg <18 x float> @bitcast_v36i16_to_v18f32_scalar(<36 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v15, s51, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, s52, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB31_5
; GFX9-NEXT: .LBB31_3:
; GFX9-NEXT: s_branch .LBB31_2
@@ -12627,6 +14441,20 @@ define inreg <18 x float> @bitcast_v36i16_to_v18f32_scalar(<36 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_3:
; GFX11-NEXT: s_branch .LBB31_2
@@ -14137,6 +15965,20 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -14304,6 +16146,20 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v19, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -14391,6 +16247,20 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
@@ -14468,6 +16338,20 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v17, v32, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, 0x200, v32
; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -14541,10 +16425,24 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB34_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr18
-; GFX9-NEXT: ; kill: killed $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; kill: killed $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
@@ -14641,6 +16539,20 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v14, v14, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -14680,10 +16592,31 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -14702,7 +16635,20 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -14748,10 +16694,31 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -14770,7 +16737,20 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -14894,6 +16874,20 @@ define inreg <18 x float> @bitcast_v36f16_to_v18f32_scalar(<36 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s53, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB35_4
; SI-NEXT: .LBB35_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s91
@@ -15040,6 +17034,20 @@ define inreg <18 x float> @bitcast_v36f16_to_v18f32_scalar(<36 x half> inreg %a,
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB35_5
; SI-NEXT: .LBB35_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -15202,6 +17210,20 @@ define inreg <18 x float> @bitcast_v36f16_to_v18f32_scalar(<36 x half> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s53, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr54
+; VI-NEXT: ; implicit-def: $sgpr55
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 0x200
@@ -15277,6 +17299,20 @@ define inreg <18 x float> @bitcast_v36f16_to_v18f32_scalar(<36 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v18, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s6, v17
; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -15418,6 +17454,20 @@ define inreg <18 x float> @bitcast_v36f16_to_v18f32_scalar(<36 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v15, s51, v17 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, s52, v17 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, s53, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB35_5
; GFX9-NEXT: .LBB35_3:
; GFX9-NEXT: s_branch .LBB35_2
@@ -15536,6 +17586,20 @@ define inreg <18 x float> @bitcast_v36f16_to_v18f32_scalar(<36 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3:
; GFX11-NEXT: s_branch .LBB35_2
@@ -15602,6 +17666,20 @@ define <9 x double> @bitcast_v9i64_to_v9f64(<9 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -15633,6 +17711,20 @@ define <9 x double> @bitcast_v9i64_to_v9f64(<9 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -15664,6 +17756,20 @@ define <9 x double> @bitcast_v9i64_to_v9f64(<9 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, 3, v16
; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v17, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -15701,6 +17807,20 @@ define <9 x double> @bitcast_v9i64_to_v9f64(<9 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -15753,6 +17873,20 @@ define inreg <9 x double> @bitcast_v9i64_to_v9f64_scalar(<9 x i64> inreg %a, i32
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB37_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -15807,6 +17941,20 @@ define inreg <9 x double> @bitcast_v9i64_to_v9f64_scalar(<9 x i64> inreg %a, i32
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -15861,6 +18009,20 @@ define inreg <9 x double> @bitcast_v9i64_to_v9f64_scalar(<9 x i64> inreg %a, i32
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -15913,6 +18075,20 @@ define inreg <9 x double> @bitcast_v9i64_to_v9f64_scalar(<9 x i64> inreg %a, i32
; GFX11-NEXT: s_addc_u32 s27, s27, 0
; GFX11-NEXT: s_add_u32 s28, s28, 3
; GFX11-NEXT: s_addc_u32 s29, s29, 0
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
+; GFX11-NEXT: ; implicit-def: $sgpr4
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -15962,6 +18138,20 @@ define <9 x i64> @bitcast_v9f64_to_v9i64(<9 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -15984,6 +18174,20 @@ define <9 x i64> @bitcast_v9f64_to_v9i64(<9 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; VI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -16006,6 +18210,20 @@ define <9 x i64> @bitcast_v9f64_to_v9i64(<9 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -16029,6 +18247,20 @@ define <9 x i64> @bitcast_v9f64_to_v9i64(<9 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -16100,6 +18332,20 @@ define inreg <9 x i64> @bitcast_v9f64_to_v9i64_scalar(<9 x double> inreg %a, i32
; SI-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; SI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; SI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB39_5
; SI-NEXT: .LBB39_3:
; SI-NEXT: s_branch .LBB39_2
@@ -16202,6 +18448,20 @@ define inreg <9 x i64> @bitcast_v9f64_to_v9i64_scalar(<9 x double> inreg %a, i32
; VI-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; VI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; VI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB39_5
; VI-NEXT: .LBB39_3:
; VI-NEXT: s_branch .LBB39_2
@@ -16304,6 +18564,20 @@ define inreg <9 x i64> @bitcast_v9f64_to_v9i64_scalar(<9 x double> inreg %a, i32
; GFX9-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB39_5
; GFX9-NEXT: .LBB39_3:
; GFX9-NEXT: s_branch .LBB39_2
@@ -16408,6 +18682,20 @@ define inreg <9 x i64> @bitcast_v9f64_to_v9i64_scalar(<9 x double> inreg %a, i32
; GFX11-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; GFX11-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_branch .LBB39_5
; GFX11-NEXT: .LBB39_3:
; GFX11-NEXT: s_branch .LBB39_2
@@ -17744,6 +20032,20 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -17840,6 +20142,20 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -17927,6 +20243,20 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
@@ -18004,6 +20334,20 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v18, 3, v32
; VI-NEXT: v_add_u16_sdwa v17, v32, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -18077,10 +20421,24 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB42_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr18
-; GFX9-NEXT: ; kill: killed $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; kill: killed $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
@@ -18176,6 +20534,20 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v14, v14, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -18215,10 +20587,31 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -18237,7 +20630,20 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -18283,10 +20689,31 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -18305,7 +20732,20 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -18429,6 +20869,20 @@ define inreg <9 x i64> @bitcast_v36i16_to_v9i64_scalar(<36 x i16> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s53, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -18521,6 +20975,20 @@ define inreg <9 x i64> @bitcast_v36i16_to_v9i64_scalar(<36 x i16> inreg %a, i32
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -18667,6 +21135,20 @@ define inreg <9 x i64> @bitcast_v36i16_to_v9i64_scalar(<36 x i16> inreg %a, i32
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s53, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -18759,6 +21241,20 @@ define inreg <9 x i64> @bitcast_v36i16_to_v9i64_scalar(<36 x i16> inreg %a, i32
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s53, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
@@ -18883,6 +21379,20 @@ define inreg <9 x i64> @bitcast_v36i16_to_v9i64_scalar(<36 x i16> inreg %a, i32
; GFX9-NEXT: v_pk_add_u16 v15, s51, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, s52, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB43_5
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -19001,6 +21511,20 @@ define inreg <9 x i64> @bitcast_v36i16_to_v9i64_scalar(<36 x i16> inreg %a, i32
; GFX11-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -20324,6 +22848,20 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -20491,6 +23029,20 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v19, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -20578,6 +23130,20 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
@@ -20655,6 +23221,20 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v17, v32, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, 0x200, v32
; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -20728,10 +23308,24 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB46_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr18
-; GFX9-NEXT: ; kill: killed $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; kill: killed $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
@@ -20828,6 +23422,20 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v14, v14, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -20867,10 +23475,31 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -20889,7 +23518,20 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -20935,10 +23577,31 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -20957,7 +23620,20 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -21081,6 +23757,20 @@ define inreg <9 x i64> @bitcast_v36f16_to_v9i64_scalar(<36 x half> inreg %a, i32
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s53, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s91
@@ -21227,6 +23917,20 @@ define inreg <9 x i64> @bitcast_v36f16_to_v9i64_scalar(<36 x half> inreg %a, i32
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -21389,6 +24093,20 @@ define inreg <9 x i64> @bitcast_v36f16_to_v9i64_scalar(<36 x half> inreg %a, i32
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s53, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr54
+; VI-NEXT: ; implicit-def: $sgpr55
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 0x200
@@ -21464,6 +24182,20 @@ define inreg <9 x i64> @bitcast_v36f16_to_v9i64_scalar(<36 x half> inreg %a, i32
; VI-NEXT: v_add_f16_sdwa v18, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s6, v17
; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -21605,6 +24337,20 @@ define inreg <9 x i64> @bitcast_v36f16_to_v9i64_scalar(<36 x half> inreg %a, i32
; GFX9-NEXT: v_pk_add_f16 v15, s51, v17 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, s52, v17 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, s53, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB47_5
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -21723,6 +24469,20 @@ define inreg <9 x i64> @bitcast_v36f16_to_v9i64_scalar(<36 x half> inreg %a, i32
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -23159,6 +25919,20 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -23255,6 +26029,20 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -23342,6 +26130,20 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
@@ -23419,6 +26221,20 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v18, 3, v32
; VI-NEXT: v_add_u16_sdwa v17, v32, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -23492,10 +26308,24 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB50_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr18
-; GFX9-NEXT: ; kill: killed $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; kill: killed $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
@@ -23591,6 +26421,20 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v14, v14, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -23630,10 +26474,31 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -23652,7 +26517,20 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -23698,10 +26576,31 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -23720,7 +26619,20 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -23844,6 +26756,20 @@ define inreg <9 x double> @bitcast_v36i16_to_v9f64_scalar(<36 x i16> inreg %a, i
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s53, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -23936,6 +26862,20 @@ define inreg <9 x double> @bitcast_v36i16_to_v9f64_scalar(<36 x i16> inreg %a, i
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -24082,6 +27022,20 @@ define inreg <9 x double> @bitcast_v36i16_to_v9f64_scalar(<36 x i16> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s53, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -24174,6 +27128,20 @@ define inreg <9 x double> @bitcast_v36i16_to_v9f64_scalar(<36 x i16> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s53, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
@@ -24298,6 +27266,20 @@ define inreg <9 x double> @bitcast_v36i16_to_v9f64_scalar(<36 x i16> inreg %a, i
; GFX9-NEXT: v_pk_add_u16 v15, s51, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, s52, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB51_5
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -24416,6 +27398,20 @@ define inreg <9 x double> @bitcast_v36i16_to_v9f64_scalar(<36 x i16> inreg %a, i
; GFX11-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -25854,6 +28850,20 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; kill: killed $vgpr18
@@ -26021,6 +29031,20 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v19, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -26108,6 +29132,20 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
@@ -26185,6 +29223,20 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v17, v32, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, 0x200, v32
; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -26258,10 +29310,24 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB54_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr18
-; GFX9-NEXT: ; kill: killed $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; kill: killed $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
@@ -26358,6 +29424,20 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v14, v14, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -26397,10 +29477,31 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -26419,7 +29520,20 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -26465,10 +29579,31 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -26487,7 +29622,20 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -26611,6 +29759,20 @@ define inreg <9 x double> @bitcast_v36f16_to_v9f64_scalar(<36 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s53, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr54
+; SI-NEXT: ; implicit-def: $sgpr55
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s91
@@ -26757,6 +29919,20 @@ define inreg <9 x double> @bitcast_v36f16_to_v9f64_scalar(<36 x half> inreg %a,
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -26919,6 +30095,20 @@ define inreg <9 x double> @bitcast_v36f16_to_v9f64_scalar(<36 x half> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s53, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr54
+; VI-NEXT: ; implicit-def: $sgpr55
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 0x200
@@ -26994,6 +30184,20 @@ define inreg <9 x double> @bitcast_v36f16_to_v9f64_scalar(<36 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v18, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s6, v17
; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
+; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -27135,6 +30339,20 @@ define inreg <9 x double> @bitcast_v36f16_to_v9f64_scalar(<36 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v15, s51, v17 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, s52, v17 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, s53, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
+; GFX9-NEXT: ; implicit-def: $vgpr18
; GFX9-NEXT: s_branch .LBB55_5
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -27253,6 +30471,20 @@ define inreg <9 x double> @bitcast_v36f16_to_v9f64_scalar(<36 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
+; GFX11-NEXT: ; implicit-def: $vgpr18
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
index 69562f9d0a70d..55240e844499a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
@@ -36,6 +36,18 @@ define <20 x float> @bitcast_v20i32_to_v20f32(<20 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -69,6 +81,18 @@ define <20 x float> @bitcast_v20i32_to_v20f32(<20 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -102,6 +126,18 @@ define <20 x float> @bitcast_v20i32_to_v20f32(<20 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -136,6 +172,18 @@ define <20 x float> @bitcast_v20i32_to_v20f32(<20 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -192,6 +240,18 @@ define inreg <20 x float> @bitcast_v20i32_to_v20f32_scalar(<20 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB1_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -252,6 +312,18 @@ define inreg <20 x float> @bitcast_v20i32_to_v20f32_scalar(<20 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB1_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -312,6 +384,18 @@ define inreg <20 x float> @bitcast_v20i32_to_v20f32_scalar(<20 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB1_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -370,6 +454,18 @@ define inreg <20 x float> @bitcast_v20i32_to_v20f32_scalar(<20 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
; GFX11-NEXT: .LBB1_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -432,6 +528,18 @@ define <20 x i32> @bitcast_v20f32_to_v20i32(<20 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -465,6 +573,18 @@ define <20 x i32> @bitcast_v20f32_to_v20i32(<20 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -498,6 +618,18 @@ define <20 x i32> @bitcast_v20f32_to_v20i32(<20 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -522,6 +654,18 @@ define <20 x i32> @bitcast_v20f32_to_v20i32(<20 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -608,6 +752,18 @@ define inreg <20 x i32> @bitcast_v20f32_to_v20i32_scalar(<20 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: .LBB3_3:
; SI-NEXT: s_branch .LBB3_2
@@ -727,6 +883,18 @@ define inreg <20 x i32> @bitcast_v20f32_to_v20i32_scalar(<20 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB3_5
; VI-NEXT: .LBB3_3:
; VI-NEXT: s_branch .LBB3_2
@@ -846,6 +1014,18 @@ define inreg <20 x i32> @bitcast_v20f32_to_v20i32_scalar(<20 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: .LBB3_3:
; GFX9-NEXT: s_branch .LBB3_2
@@ -967,6 +1147,18 @@ define inreg <20 x i32> @bitcast_v20f32_to_v20i32_scalar(<20 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_branch .LBB3_5
; GFX11-NEXT: .LBB3_3:
; GFX11-NEXT: s_branch .LBB3_2
@@ -1052,6 +1244,18 @@ define <10 x i64> @bitcast_v20i32_to_v10i64(<20 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1085,6 +1289,18 @@ define <10 x i64> @bitcast_v20i32_to_v10i64(<20 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1118,6 +1334,18 @@ define <10 x i64> @bitcast_v20i32_to_v10i64(<20 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1152,6 +1380,18 @@ define <10 x i64> @bitcast_v20i32_to_v10i64(<20 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1208,6 +1448,18 @@ define inreg <10 x i64> @bitcast_v20i32_to_v10i64_scalar(<20 x i32> inreg %a, i3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1268,6 +1520,18 @@ define inreg <10 x i64> @bitcast_v20i32_to_v10i64_scalar(<20 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1328,6 +1592,18 @@ define inreg <10 x i64> @bitcast_v20i32_to_v10i64_scalar(<20 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1386,6 +1662,18 @@ define inreg <10 x i64> @bitcast_v20i32_to_v10i64_scalar(<20 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1448,6 +1736,18 @@ define <20 x i32> @bitcast_v10i64_to_v20i32(<10 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1481,6 +1781,18 @@ define <20 x i32> @bitcast_v10i64_to_v20i32(<10 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1514,6 +1826,18 @@ define <20 x i32> @bitcast_v10i64_to_v20i32(<10 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1553,6 +1877,18 @@ define <20 x i32> @bitcast_v10i64_to_v20i32(<10 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1609,6 +1945,18 @@ define inreg <20 x i32> @bitcast_v10i64_to_v20i32_scalar(<10 x i64> inreg %a, i3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB7_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1669,6 +2017,18 @@ define inreg <20 x i32> @bitcast_v10i64_to_v20i32_scalar(<10 x i64> inreg %a, i3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB7_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1729,6 +2089,18 @@ define inreg <20 x i32> @bitcast_v10i64_to_v20i32_scalar(<10 x i64> inreg %a, i3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB7_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1787,6 +2159,18 @@ define inreg <20 x i32> @bitcast_v10i64_to_v20i32_scalar(<10 x i64> inreg %a, i3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1849,6 +2233,18 @@ define <10 x double> @bitcast_v20i32_to_v10f64(<20 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1882,6 +2278,18 @@ define <10 x double> @bitcast_v20i32_to_v10f64(<20 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1915,6 +2323,18 @@ define <10 x double> @bitcast_v20i32_to_v10f64(<20 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1949,6 +2369,18 @@ define <10 x double> @bitcast_v20i32_to_v10f64(<20 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2005,6 +2437,18 @@ define inreg <10 x double> @bitcast_v20i32_to_v10f64_scalar(<20 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -2065,6 +2509,18 @@ define inreg <10 x double> @bitcast_v20i32_to_v10f64_scalar(<20 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2125,6 +2581,18 @@ define inreg <10 x double> @bitcast_v20i32_to_v10f64_scalar(<20 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2183,6 +2651,18 @@ define inreg <10 x double> @bitcast_v20i32_to_v10f64_scalar(<20 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2235,6 +2715,18 @@ define <20 x i32> @bitcast_v10f64_to_v20i32(<10 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2258,6 +2750,18 @@ define <20 x i32> @bitcast_v10f64_to_v20i32(<10 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2281,6 +2785,18 @@ define <20 x i32> @bitcast_v10f64_to_v20i32(<10 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2305,6 +2821,18 @@ define <20 x i32> @bitcast_v10f64_to_v20i32(<10 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2381,6 +2909,18 @@ define inreg <20 x i32> @bitcast_v10f64_to_v20i32_scalar(<10 x double> inreg %a,
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB11_5
; SI-NEXT: .LBB11_3:
; SI-NEXT: s_branch .LBB11_2
@@ -2490,6 +3030,18 @@ define inreg <20 x i32> @bitcast_v10f64_to_v20i32_scalar(<10 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB11_5
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -2599,6 +3151,18 @@ define inreg <20 x i32> @bitcast_v10f64_to_v20i32_scalar(<10 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB11_5
; GFX9-NEXT: .LBB11_3:
; GFX9-NEXT: s_branch .LBB11_2
@@ -2710,6 +3274,18 @@ define inreg <20 x i32> @bitcast_v10f64_to_v20i32_scalar(<10 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_branch .LBB11_5
; GFX11-NEXT: .LBB11_3:
; GFX11-NEXT: s_branch .LBB11_2
@@ -4168,6 +4744,18 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -4292,6 +4880,18 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -4387,6 +4987,18 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v17, v34, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v33, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v32, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -4472,6 +5084,18 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v20, 3, v32
; VI-NEXT: v_add_u16_sdwa v19, v32, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB14_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -4555,7 +5179,17 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB14_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr20
-; GFX9-NEXT: ; kill: killed $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; kill: killed $vgpr20
@@ -4570,7 +5204,9 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
@@ -4668,6 +5304,18 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v12, v12, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
@@ -4719,10 +5367,29 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -4743,7 +5410,18 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4792,11 +5470,31 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -4817,7 +5515,18 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4951,6 +5660,18 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s55, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -5053,6 +5774,18 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s55, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -5215,6 +5948,18 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s55, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -5317,6 +6062,18 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s55, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB15_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v20, 18
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -5457,6 +6214,18 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, s54, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB15_5
; GFX9-NEXT: .LBB15_3:
; GFX9-NEXT: s_branch .LBB15_2
@@ -5585,6 +6354,18 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_3:
; GFX11-NEXT: s_branch .LBB15_2
@@ -7031,6 +7812,18 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -7234,6 +8027,18 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v21, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB18_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -7329,6 +8134,18 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v17, v34, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v33, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v32, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -7414,6 +8231,18 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v19, v32, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, 0x200, v32
; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB18_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -7497,7 +8326,17 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB18_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr20
-; GFX9-NEXT: ; kill: killed $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; kill: killed $vgpr20
@@ -7512,7 +8351,9 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
@@ -7611,6 +8452,18 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v12, v12, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
@@ -7662,10 +8515,29 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -7686,7 +8558,18 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7735,11 +8618,31 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -7760,7 +8663,18 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -7894,6 +8808,18 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s55, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB19_4
; SI-NEXT: .LBB19_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s95
@@ -8056,6 +8982,18 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v21, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB19_5
; SI-NEXT: .LBB19_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -8232,6 +9170,18 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s55, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v19, 0x200
@@ -8315,6 +9265,18 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v20, v20, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s6, v19
; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -8470,6 +9432,18 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v17, s53, v19 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, s54, v19 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, s55, v19 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB19_5
; GFX9-NEXT: .LBB19_3:
; GFX9-NEXT: s_branch .LBB19_2
@@ -8598,6 +9572,18 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3:
; GFX11-NEXT: s_branch .LBB19_2
@@ -8666,6 +9652,18 @@ define <10 x i64> @bitcast_v20f32_to_v10i64(<20 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -8699,6 +9697,18 @@ define <10 x i64> @bitcast_v20f32_to_v10i64(<20 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8732,6 +9742,18 @@ define <10 x i64> @bitcast_v20f32_to_v10i64(<20 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -8756,6 +9778,18 @@ define <10 x i64> @bitcast_v20f32_to_v10i64(<20 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8842,6 +9876,18 @@ define inreg <10 x i64> @bitcast_v20f32_to_v10i64_scalar(<20 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB21_5
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -8961,6 +10007,18 @@ define inreg <10 x i64> @bitcast_v20f32_to_v10i64_scalar(<20 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB21_5
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -9080,6 +10138,18 @@ define inreg <10 x i64> @bitcast_v20f32_to_v10i64_scalar(<20 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB21_5
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -9201,6 +10271,18 @@ define inreg <10 x i64> @bitcast_v20f32_to_v10i64_scalar(<20 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_branch .LBB21_5
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -9286,6 +10368,18 @@ define <20 x float> @bitcast_v10i64_to_v20f32(<10 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -9319,6 +10413,18 @@ define <20 x float> @bitcast_v10i64_to_v20f32(<10 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -9352,6 +10458,18 @@ define <20 x float> @bitcast_v10i64_to_v20f32(<10 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -9391,6 +10509,18 @@ define <20 x float> @bitcast_v10i64_to_v20f32(<10 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9447,6 +10577,18 @@ define inreg <20 x float> @bitcast_v10i64_to_v20f32_scalar(<10 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -9507,6 +10649,18 @@ define inreg <20 x float> @bitcast_v10i64_to_v20f32_scalar(<10 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB23_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -9567,6 +10721,18 @@ define inreg <20 x float> @bitcast_v10i64_to_v20f32_scalar(<10 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB23_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -9625,6 +10791,18 @@ define inreg <20 x float> @bitcast_v10i64_to_v20f32_scalar(<10 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -9687,6 +10865,18 @@ define <10 x double> @bitcast_v20f32_to_v10f64(<20 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -9720,6 +10910,18 @@ define <10 x double> @bitcast_v20f32_to_v10f64(<20 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -9753,6 +10955,18 @@ define <10 x double> @bitcast_v20f32_to_v10f64(<20 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -9777,6 +10991,18 @@ define <10 x double> @bitcast_v20f32_to_v10f64(<20 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9863,6 +11089,18 @@ define inreg <10 x double> @bitcast_v20f32_to_v10f64_scalar(<20 x float> inreg %
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB25_5
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -9982,6 +11220,18 @@ define inreg <10 x double> @bitcast_v20f32_to_v10f64_scalar(<20 x float> inreg %
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB25_5
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -10101,6 +11351,18 @@ define inreg <10 x double> @bitcast_v20f32_to_v10f64_scalar(<20 x float> inreg %
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB25_5
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -10222,6 +11484,18 @@ define inreg <10 x double> @bitcast_v20f32_to_v10f64_scalar(<20 x float> inreg %
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_branch .LBB25_5
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -10297,6 +11571,18 @@ define <20 x float> @bitcast_v10f64_to_v20f32(<10 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -10320,6 +11606,18 @@ define <20 x float> @bitcast_v10f64_to_v20f32(<10 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -10343,6 +11641,18 @@ define <20 x float> @bitcast_v10f64_to_v20f32(<10 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10367,6 +11677,18 @@ define <20 x float> @bitcast_v10f64_to_v20f32(<10 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10443,6 +11765,18 @@ define inreg <20 x float> @bitcast_v10f64_to_v20f32_scalar(<10 x double> inreg %
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB27_5
; SI-NEXT: .LBB27_3:
; SI-NEXT: s_branch .LBB27_2
@@ -10552,6 +11886,18 @@ define inreg <20 x float> @bitcast_v10f64_to_v20f32_scalar(<10 x double> inreg %
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB27_5
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -10661,6 +12007,18 @@ define inreg <20 x float> @bitcast_v10f64_to_v20f32_scalar(<10 x double> inreg %
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB27_5
; GFX9-NEXT: .LBB27_3:
; GFX9-NEXT: s_branch .LBB27_2
@@ -10772,6 +12130,18 @@ define inreg <20 x float> @bitcast_v10f64_to_v20f32_scalar(<10 x double> inreg %
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_branch .LBB27_5
; GFX11-NEXT: .LBB27_3:
; GFX11-NEXT: s_branch .LBB27_2
@@ -12448,6 +13818,18 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -12572,6 +13954,18 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -12667,6 +14061,18 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v17, v34, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v33, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v32, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -12752,6 +14158,18 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v20, 3, v32
; VI-NEXT: v_add_u16_sdwa v19, v32, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB30_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -12835,7 +14253,17 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB30_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr20
-; GFX9-NEXT: ; kill: killed $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; kill: killed $vgpr20
@@ -12850,7 +14278,9 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
@@ -12948,6 +14378,18 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v12, v12, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
@@ -12999,10 +14441,29 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -13023,7 +14484,18 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13072,11 +14544,31 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -13097,7 +14589,18 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -13231,6 +14734,18 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s55, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB31_3
; SI-NEXT: .LBB31_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -13333,6 +14848,18 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s55, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB31_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -13495,6 +15022,18 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s55, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB31_3
; VI-NEXT: .LBB31_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -13597,6 +15136,18 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s55, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB31_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v20, 18
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -13737,6 +15288,18 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, s54, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB31_5
; GFX9-NEXT: .LBB31_3:
; GFX9-NEXT: s_branch .LBB31_2
@@ -13865,6 +15428,18 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_3:
; GFX11-NEXT: s_branch .LBB31_2
@@ -15529,6 +17104,18 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -15732,6 +17319,18 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v21, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -15827,6 +17426,18 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v17, v34, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v33, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v32, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -15912,6 +17523,18 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v19, v32, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, 0x200, v32
; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -15995,7 +17618,17 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB34_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr20
-; GFX9-NEXT: ; kill: killed $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; kill: killed $vgpr20
@@ -16010,7 +17643,9 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
@@ -16109,6 +17744,18 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v12, v12, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
@@ -16160,10 +17807,29 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -16184,7 +17850,18 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16233,11 +17910,31 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -16258,7 +17955,18 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -16392,6 +18100,18 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s55, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB35_4
; SI-NEXT: .LBB35_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s95
@@ -16554,6 +18274,18 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v21, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB35_5
; SI-NEXT: .LBB35_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -16730,6 +18462,18 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s55, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v19, 0x200
@@ -16813,6 +18557,18 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v20, v20, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s6, v19
; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -16968,6 +18724,18 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v17, s53, v19 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, s54, v19 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, s55, v19 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB35_5
; GFX9-NEXT: .LBB35_3:
; GFX9-NEXT: s_branch .LBB35_2
@@ -17096,6 +18864,18 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3:
; GFX11-NEXT: s_branch .LBB35_2
@@ -17164,6 +18944,18 @@ define <10 x double> @bitcast_v10i64_to_v10f64(<10 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -17197,6 +18989,18 @@ define <10 x double> @bitcast_v10i64_to_v10f64(<10 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -17230,6 +19034,18 @@ define <10 x double> @bitcast_v10i64_to_v10f64(<10 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v17, vcc
; GFX9-NEXT: v_add_co_u32_e32 v18, vcc, 3, v18
; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v19, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -17269,6 +19085,18 @@ define <10 x double> @bitcast_v10i64_to_v10f64(<10 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -17325,6 +19153,18 @@ define inreg <10 x double> @bitcast_v10i64_to_v10f64_scalar(<10 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB37_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -17385,6 +19225,18 @@ define inreg <10 x double> @bitcast_v10i64_to_v10f64_scalar(<10 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -17445,6 +19297,18 @@ define inreg <10 x double> @bitcast_v10i64_to_v10f64_scalar(<10 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -17503,6 +19367,18 @@ define inreg <10 x double> @bitcast_v10i64_to_v10f64_scalar(<10 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s29, s29, 0
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
+; GFX11-NEXT: ; implicit-def: $sgpr6
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -17554,6 +19430,18 @@ define <10 x i64> @bitcast_v10f64_to_v10i64(<10 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -17577,6 +19465,18 @@ define <10 x i64> @bitcast_v10f64_to_v10i64(<10 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; VI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; VI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -17600,6 +19500,18 @@ define <10 x i64> @bitcast_v10f64_to_v10i64(<10 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -17624,6 +19536,18 @@ define <10 x i64> @bitcast_v10f64_to_v10i64(<10 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -17700,6 +19624,18 @@ define inreg <10 x i64> @bitcast_v10f64_to_v10i64_scalar(<10 x double> inreg %a,
; SI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; SI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; SI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB39_5
; SI-NEXT: .LBB39_3:
; SI-NEXT: s_branch .LBB39_2
@@ -17809,6 +19745,18 @@ define inreg <10 x i64> @bitcast_v10f64_to_v10i64_scalar(<10 x double> inreg %a,
; VI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; VI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; VI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB39_5
; VI-NEXT: .LBB39_3:
; VI-NEXT: s_branch .LBB39_2
@@ -17918,6 +19866,18 @@ define inreg <10 x i64> @bitcast_v10f64_to_v10i64_scalar(<10 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB39_5
; GFX9-NEXT: .LBB39_3:
; GFX9-NEXT: s_branch .LBB39_2
@@ -18029,6 +19989,18 @@ define inreg <10 x i64> @bitcast_v10f64_to_v10i64_scalar(<10 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_branch .LBB39_5
; GFX11-NEXT: .LBB39_3:
; GFX11-NEXT: s_branch .LBB39_2
@@ -19497,6 +21469,18 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -19621,6 +21605,18 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -19716,6 +21712,18 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v17, v34, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v33, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v32, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -19801,6 +21809,18 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v20, 3, v32
; VI-NEXT: v_add_u16_sdwa v19, v32, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -19884,7 +21904,17 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB42_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr20
-; GFX9-NEXT: ; kill: killed $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; kill: killed $vgpr20
@@ -19899,7 +21929,9 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
@@ -19997,6 +22029,18 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v12, v12, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
@@ -20048,10 +22092,29 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -20072,7 +22135,18 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -20121,11 +22195,31 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -20146,7 +22240,18 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -20280,6 +22385,18 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s55, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -20382,6 +22499,18 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s55, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -20544,6 +22673,18 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s55, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -20646,6 +22787,18 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s55, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v20, 18
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -20786,6 +22939,18 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, s54, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB43_5
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -20914,6 +23079,18 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -22370,6 +24547,18 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -22573,6 +24762,18 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v21, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -22668,6 +24869,18 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v17, v34, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v33, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v32, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -22753,6 +24966,18 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v19, v32, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, 0x200, v32
; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -22836,7 +25061,17 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB46_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr20
-; GFX9-NEXT: ; kill: killed $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; kill: killed $vgpr20
@@ -22851,7 +25086,9 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
@@ -22950,6 +25187,18 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v12, v12, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
@@ -23001,10 +25250,29 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -23025,7 +25293,18 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -23074,11 +25353,31 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -23099,7 +25398,18 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -23233,6 +25543,18 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s55, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s95
@@ -23395,6 +25717,18 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v21, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -23571,6 +25905,18 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s55, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v19, 0x200
@@ -23654,6 +26000,18 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v20, v20, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s6, v19
; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -23809,6 +26167,18 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v17, s53, v19 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, s54, v19 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, s55, v19 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB47_5
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -23937,6 +26307,18 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -25516,6 +27898,18 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -25640,6 +28034,18 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -25735,6 +28141,18 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v17, v34, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v33, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v32, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -25820,6 +28238,18 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v20, 3, v32
; VI-NEXT: v_add_u16_sdwa v19, v32, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -25903,7 +28333,17 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB50_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr20
-; GFX9-NEXT: ; kill: killed $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; kill: killed $vgpr20
@@ -25918,7 +28358,9 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
@@ -26016,6 +28458,18 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v12, v12, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
@@ -26067,10 +28521,29 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -26091,7 +28564,18 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -26140,11 +28624,31 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -26165,7 +28669,18 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -26299,6 +28814,18 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s55, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -26401,6 +28928,18 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s55, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
@@ -26563,6 +29102,18 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s55, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -26665,6 +29216,18 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s55, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v20, 18
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -26805,6 +29368,18 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, s54, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB51_5
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -26933,6 +29508,18 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -28517,6 +31104,18 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; kill: killed $vgpr20
@@ -28720,6 +31319,18 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v21, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -28815,6 +31426,18 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v17, v34, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v33, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v32, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -28900,6 +31523,18 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v19, v32, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, 0x200, v32
; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -28983,7 +31618,17 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB54_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr20
-; GFX9-NEXT: ; kill: killed $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: ; kill: killed $vgpr20
@@ -28998,7 +31643,9 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; kill: killed $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v32
@@ -29097,6 +31744,18 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v12, v12, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
@@ -29148,10 +31807,29 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -29172,7 +31850,18 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -29221,11 +31910,31 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v22, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v21, v19, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -29246,7 +31955,18 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -29380,6 +32100,18 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s55, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr56
+; SI-NEXT: ; implicit-def: $sgpr57
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s95
@@ -29542,6 +32274,18 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v21, v19
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -29718,6 +32462,18 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s55, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr56
+; VI-NEXT: ; implicit-def: $sgpr57
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v19, 0x200
@@ -29801,6 +32557,18 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v20, v20, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s6, v19
; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
+; VI-NEXT: ; implicit-def: $vgpr20
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -29956,6 +32724,18 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a
; GFX9-NEXT: v_pk_add_f16 v17, s53, v19 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, s54, v19 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, s55, v19 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
+; GFX9-NEXT: ; implicit-def: $vgpr20
; GFX9-NEXT: s_branch .LBB55_5
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -30084,6 +32864,18 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
+; GFX11-NEXT: ; implicit-def: $vgpr20
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 77c047f492cac..be338186eb1c9 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -3158,9 +3158,17 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB26_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v10, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
@@ -6336,9 +6344,17 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v10, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
@@ -9193,9 +9209,17 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB70_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v10, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
@@ -11759,9 +11783,17 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB86_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v10, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
@@ -14021,9 +14053,17 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB98_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v10, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
@@ -15890,9 +15930,17 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB106_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v10, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
@@ -17251,9 +17299,17 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB110_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v10, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
index df100725d890c..273dddaed360f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
@@ -38,6 +38,16 @@ define <22 x float> @bitcast_v22i32_to_v22f32(<22 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -73,6 +83,16 @@ define <22 x float> @bitcast_v22i32_to_v22f32(<22 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -108,6 +128,16 @@ define <22 x float> @bitcast_v22i32_to_v22f32(<22 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -144,6 +174,16 @@ define <22 x float> @bitcast_v22i32_to_v22f32(<22 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -204,6 +244,16 @@ define inreg <22 x float> @bitcast_v22i32_to_v22f32_scalar(<22 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB1_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -270,6 +320,16 @@ define inreg <22 x float> @bitcast_v22i32_to_v22f32_scalar(<22 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB1_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -336,6 +396,16 @@ define inreg <22 x float> @bitcast_v22i32_to_v22f32_scalar(<22 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB1_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -400,6 +470,16 @@ define inreg <22 x float> @bitcast_v22i32_to_v22f32_scalar(<22 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
; GFX11-NEXT: .LBB1_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -465,6 +545,16 @@ define <22 x i32> @bitcast_v22f32_to_v22i32(<22 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -500,6 +590,16 @@ define <22 x i32> @bitcast_v22f32_to_v22i32(<22 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -535,6 +635,16 @@ define <22 x i32> @bitcast_v22f32_to_v22i32(<22 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -560,6 +670,16 @@ define <22 x i32> @bitcast_v22f32_to_v22i32(<22 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -650,6 +770,16 @@ define inreg <22 x i32> @bitcast_v22f32_to_v22i32_scalar(<22 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: .LBB3_3:
; SI-NEXT: s_branch .LBB3_2
@@ -773,6 +903,16 @@ define inreg <22 x i32> @bitcast_v22f32_to_v22i32_scalar(<22 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB3_5
; VI-NEXT: .LBB3_3:
; VI-NEXT: s_branch .LBB3_2
@@ -896,6 +1036,16 @@ define inreg <22 x i32> @bitcast_v22f32_to_v22i32_scalar(<22 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: .LBB3_3:
; GFX9-NEXT: s_branch .LBB3_2
@@ -1021,6 +1171,16 @@ define inreg <22 x i32> @bitcast_v22f32_to_v22i32_scalar(<22 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_branch .LBB3_5
; GFX11-NEXT: .LBB3_3:
; GFX11-NEXT: s_branch .LBB3_2
@@ -1108,6 +1268,16 @@ define <11 x i64> @bitcast_v22i32_to_v11i64(<22 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1143,6 +1313,16 @@ define <11 x i64> @bitcast_v22i32_to_v11i64(<22 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1178,6 +1358,16 @@ define <11 x i64> @bitcast_v22i32_to_v11i64(<22 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1214,6 +1404,16 @@ define <11 x i64> @bitcast_v22i32_to_v11i64(<22 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1274,6 +1474,16 @@ define inreg <11 x i64> @bitcast_v22i32_to_v11i64_scalar(<22 x i32> inreg %a, i3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1340,6 +1550,16 @@ define inreg <11 x i64> @bitcast_v22i32_to_v11i64_scalar(<22 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1406,6 +1626,16 @@ define inreg <11 x i64> @bitcast_v22i32_to_v11i64_scalar(<22 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1470,6 +1700,16 @@ define inreg <11 x i64> @bitcast_v22i32_to_v11i64_scalar(<22 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1535,6 +1775,16 @@ define <22 x i32> @bitcast_v11i64_to_v22i32(<11 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1570,6 +1820,16 @@ define <22 x i32> @bitcast_v11i64_to_v22i32(<11 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1605,6 +1865,16 @@ define <22 x i32> @bitcast_v11i64_to_v22i32(<11 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1647,6 +1917,16 @@ define <22 x i32> @bitcast_v11i64_to_v22i32(<11 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1707,6 +1987,16 @@ define inreg <22 x i32> @bitcast_v11i64_to_v22i32_scalar(<11 x i64> inreg %a, i3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB7_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1773,6 +2063,16 @@ define inreg <22 x i32> @bitcast_v11i64_to_v22i32_scalar(<11 x i64> inreg %a, i3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB7_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1839,6 +2139,16 @@ define inreg <22 x i32> @bitcast_v11i64_to_v22i32_scalar(<11 x i64> inreg %a, i3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB7_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1903,6 +2213,16 @@ define inreg <22 x i32> @bitcast_v11i64_to_v22i32_scalar(<11 x i64> inreg %a, i3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1968,6 +2288,16 @@ define <11 x double> @bitcast_v22i32_to_v11f64(<22 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2003,6 +2333,16 @@ define <11 x double> @bitcast_v22i32_to_v11f64(<22 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2038,6 +2378,16 @@ define <11 x double> @bitcast_v22i32_to_v11f64(<22 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2074,6 +2424,16 @@ define <11 x double> @bitcast_v22i32_to_v11f64(<22 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2134,6 +2494,16 @@ define inreg <11 x double> @bitcast_v22i32_to_v11f64_scalar(<22 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -2200,6 +2570,16 @@ define inreg <11 x double> @bitcast_v22i32_to_v11f64_scalar(<22 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2266,6 +2646,16 @@ define inreg <11 x double> @bitcast_v22i32_to_v11f64_scalar(<22 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2330,6 +2720,16 @@ define inreg <11 x double> @bitcast_v22i32_to_v11f64_scalar(<22 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2384,6 +2784,16 @@ define <22 x i32> @bitcast_v11f64_to_v22i32(<11 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2408,6 +2818,16 @@ define <22 x i32> @bitcast_v11f64_to_v22i32(<11 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2432,6 +2852,16 @@ define <22 x i32> @bitcast_v11f64_to_v22i32(<11 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2457,6 +2887,16 @@ define <22 x i32> @bitcast_v11f64_to_v22i32(<11 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2536,6 +2976,16 @@ define inreg <22 x i32> @bitcast_v11f64_to_v22i32_scalar(<11 x double> inreg %a,
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB11_5
; SI-NEXT: .LBB11_3:
; SI-NEXT: s_branch .LBB11_2
@@ -2648,6 +3098,16 @@ define inreg <22 x i32> @bitcast_v11f64_to_v22i32_scalar(<11 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB11_5
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -2760,6 +3220,16 @@ define inreg <22 x i32> @bitcast_v11f64_to_v22i32_scalar(<11 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB11_5
; GFX9-NEXT: .LBB11_3:
; GFX9-NEXT: s_branch .LBB11_2
@@ -2874,6 +3344,16 @@ define inreg <22 x i32> @bitcast_v11f64_to_v22i32_scalar(<11 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_branch .LBB11_5
; GFX11-NEXT: .LBB11_3:
; GFX11-NEXT: s_branch .LBB11_2
@@ -4467,6 +4947,16 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
@@ -4607,6 +5097,16 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -4710,6 +5210,16 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v19, v34, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v32, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
@@ -4803,6 +5313,16 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v22, 3, v32
; VI-NEXT: v_add_u16_sdwa v21, v32, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB14_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -4896,7 +5416,15 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB14_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr22
-; GFX9-NEXT: ; kill: killed $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; kill: killed $vgpr22
@@ -4923,7 +5451,9 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
@@ -5023,6 +5553,16 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v10, v10, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
@@ -5086,10 +5626,27 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5112,7 +5669,16 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5165,11 +5731,29 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5192,7 +5776,16 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -5340,6 +5933,16 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s57, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -5452,6 +6055,16 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v22, 18
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -5634,6 +6247,16 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s57, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -5746,6 +6369,16 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s57, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB15_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v22, 22
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -5900,6 +6533,16 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, s56, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB15_5
; GFX9-NEXT: .LBB15_3:
; GFX9-NEXT: s_branch .LBB15_2
@@ -6036,6 +6679,16 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_3:
; GFX11-NEXT: s_branch .LBB15_2
@@ -7622,6 +8275,16 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
@@ -7850,6 +8513,16 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB18_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -7953,6 +8626,16 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v19, v34, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v32, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
@@ -8046,6 +8729,16 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v21, v32, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v32
; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB18_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -8139,7 +8832,15 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB18_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr22
-; GFX9-NEXT: ; kill: killed $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; kill: killed $vgpr22
@@ -8166,7 +8867,9 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
@@ -8267,6 +8970,16 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v10, v10, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
@@ -8330,10 +9043,27 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -8356,7 +9086,16 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -8409,11 +9148,29 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -8436,7 +9193,16 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -8584,6 +9350,16 @@ define inreg <22 x i32> @bitcast_v44f16_to_v22i32_scalar(<44 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s57, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB19_4
; SI-NEXT: .LBB19_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s35
@@ -8762,6 +9538,16 @@ define inreg <22 x i32> @bitcast_v44f16_to_v22i32_scalar(<44 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB19_5
; SI-NEXT: .LBB19_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -8956,6 +9742,16 @@ define inreg <22 x i32> @bitcast_v44f16_to_v22i32_scalar(<44 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s57, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v21, 0x200
@@ -9047,6 +9843,16 @@ define inreg <22 x i32> @bitcast_v44f16_to_v22i32_scalar(<44 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v22, v22, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s6, v21
; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -9214,6 +10020,16 @@ define inreg <22 x i32> @bitcast_v44f16_to_v22i32_scalar(<44 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v19, s55, v21 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, s56, v21 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, s57, v21 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB19_5
; GFX9-NEXT: .LBB19_3:
; GFX9-NEXT: s_branch .LBB19_2
@@ -9350,6 +10166,16 @@ define inreg <22 x i32> @bitcast_v44f16_to_v22i32_scalar(<44 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s20 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3:
; GFX11-NEXT: s_branch .LBB19_2
@@ -9420,6 +10246,16 @@ define <11 x i64> @bitcast_v22f32_to_v11i64(<22 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -9455,6 +10291,16 @@ define <11 x i64> @bitcast_v22f32_to_v11i64(<22 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -9490,6 +10336,16 @@ define <11 x i64> @bitcast_v22f32_to_v11i64(<22 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -9515,6 +10371,16 @@ define <11 x i64> @bitcast_v22f32_to_v11i64(<22 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9605,6 +10471,16 @@ define inreg <11 x i64> @bitcast_v22f32_to_v11i64_scalar(<22 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB21_5
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -9728,6 +10604,16 @@ define inreg <11 x i64> @bitcast_v22f32_to_v11i64_scalar(<22 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB21_5
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -9851,6 +10737,16 @@ define inreg <11 x i64> @bitcast_v22f32_to_v11i64_scalar(<22 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB21_5
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -9976,6 +10872,16 @@ define inreg <11 x i64> @bitcast_v22f32_to_v11i64_scalar(<22 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_branch .LBB21_5
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -10063,6 +10969,16 @@ define <22 x float> @bitcast_v11i64_to_v22f32(<11 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -10098,6 +11014,16 @@ define <22 x float> @bitcast_v11i64_to_v22f32(<11 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -10133,6 +11059,16 @@ define <22 x float> @bitcast_v11i64_to_v22f32(<11 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10175,6 +11111,16 @@ define <22 x float> @bitcast_v11i64_to_v22f32(<11 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10235,6 +11181,16 @@ define inreg <22 x float> @bitcast_v11i64_to_v22f32_scalar(<11 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -10301,6 +11257,16 @@ define inreg <22 x float> @bitcast_v11i64_to_v22f32_scalar(<11 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB23_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -10367,6 +11333,16 @@ define inreg <22 x float> @bitcast_v11i64_to_v22f32_scalar(<11 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB23_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -10431,6 +11407,16 @@ define inreg <22 x float> @bitcast_v11i64_to_v22f32_scalar(<11 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -10496,6 +11482,16 @@ define <11 x double> @bitcast_v22f32_to_v11f64(<22 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -10531,6 +11527,16 @@ define <11 x double> @bitcast_v22f32_to_v11f64(<22 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -10566,6 +11572,16 @@ define <11 x double> @bitcast_v22f32_to_v11f64(<22 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10591,6 +11607,16 @@ define <11 x double> @bitcast_v22f32_to_v11f64(<22 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10681,6 +11707,16 @@ define inreg <11 x double> @bitcast_v22f32_to_v11f64_scalar(<22 x float> inreg %
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB25_5
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -10804,6 +11840,16 @@ define inreg <11 x double> @bitcast_v22f32_to_v11f64_scalar(<22 x float> inreg %
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB25_5
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -10927,6 +11973,16 @@ define inreg <11 x double> @bitcast_v22f32_to_v11f64_scalar(<22 x float> inreg %
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB25_5
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -11052,6 +12108,16 @@ define inreg <11 x double> @bitcast_v22f32_to_v11f64_scalar(<22 x float> inreg %
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_branch .LBB25_5
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -11128,6 +12194,16 @@ define <22 x float> @bitcast_v11f64_to_v22f32(<11 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -11152,6 +12228,16 @@ define <22 x float> @bitcast_v11f64_to_v22f32(<11 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -11176,6 +12262,16 @@ define <22 x float> @bitcast_v11f64_to_v22f32(<11 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -11201,6 +12297,16 @@ define <22 x float> @bitcast_v11f64_to_v22f32(<11 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11280,6 +12386,16 @@ define inreg <22 x float> @bitcast_v11f64_to_v22f32_scalar(<11 x double> inreg %
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB27_5
; SI-NEXT: .LBB27_3:
; SI-NEXT: s_branch .LBB27_2
@@ -11392,6 +12508,16 @@ define inreg <22 x float> @bitcast_v11f64_to_v22f32_scalar(<11 x double> inreg %
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB27_5
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -11504,6 +12630,16 @@ define inreg <22 x float> @bitcast_v11f64_to_v22f32_scalar(<11 x double> inreg %
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB27_5
; GFX9-NEXT: .LBB27_3:
; GFX9-NEXT: s_branch .LBB27_2
@@ -11618,6 +12754,16 @@ define inreg <22 x float> @bitcast_v11f64_to_v22f32_scalar(<11 x double> inreg %
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_branch .LBB27_5
; GFX11-NEXT: .LBB27_3:
; GFX11-NEXT: s_branch .LBB27_2
@@ -13450,6 +14596,16 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
@@ -13590,6 +14746,16 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -13693,6 +14859,16 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v19, v34, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v32, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
@@ -13786,6 +14962,16 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v22, 3, v32
; VI-NEXT: v_add_u16_sdwa v21, v32, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB30_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -13879,7 +15065,15 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB30_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr22
-; GFX9-NEXT: ; kill: killed $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; kill: killed $vgpr22
@@ -13906,7 +15100,9 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
@@ -14006,6 +15202,16 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v10, v10, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
@@ -14069,10 +15275,27 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -14095,7 +15318,16 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -14148,11 +15380,29 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -14175,7 +15425,16 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -14323,6 +15582,16 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s57, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB31_3
; SI-NEXT: .LBB31_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -14435,6 +15704,16 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB31_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v22, 18
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -14617,6 +15896,16 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s57, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB31_3
; VI-NEXT: .LBB31_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -14729,6 +16018,16 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s57, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB31_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v22, 22
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -14883,6 +16182,16 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, s56, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB31_5
; GFX9-NEXT: .LBB31_3:
; GFX9-NEXT: s_branch .LBB31_2
@@ -15019,6 +16328,16 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_3:
; GFX11-NEXT: s_branch .LBB31_2
@@ -16844,6 +18163,16 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
@@ -17072,6 +18401,16 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -17175,6 +18514,16 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v19, v34, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v32, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
@@ -17268,6 +18617,16 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v21, v32, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v32
; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -17361,7 +18720,15 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB34_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr22
-; GFX9-NEXT: ; kill: killed $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; kill: killed $vgpr22
@@ -17388,7 +18755,9 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
@@ -17489,6 +18858,16 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v10, v10, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
@@ -17552,10 +18931,27 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -17578,7 +18974,16 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17631,11 +19036,29 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -17658,7 +19081,16 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -17806,6 +19238,16 @@ define inreg <22 x float> @bitcast_v44f16_to_v22f32_scalar(<44 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s57, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB35_4
; SI-NEXT: .LBB35_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s35
@@ -17984,6 +19426,16 @@ define inreg <22 x float> @bitcast_v44f16_to_v22f32_scalar(<44 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB35_5
; SI-NEXT: .LBB35_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -18178,6 +19630,16 @@ define inreg <22 x float> @bitcast_v44f16_to_v22f32_scalar(<44 x half> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s57, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v21, 0x200
@@ -18269,6 +19731,16 @@ define inreg <22 x float> @bitcast_v44f16_to_v22f32_scalar(<44 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v22, v22, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s6, v21
; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -18436,6 +19908,16 @@ define inreg <22 x float> @bitcast_v44f16_to_v22f32_scalar(<44 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v19, s55, v21 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, s56, v21 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, s57, v21 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB35_5
; GFX9-NEXT: .LBB35_3:
; GFX9-NEXT: s_branch .LBB35_2
@@ -18572,6 +20054,16 @@ define inreg <22 x float> @bitcast_v44f16_to_v22f32_scalar(<44 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s20 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3:
; GFX11-NEXT: s_branch .LBB35_2
@@ -18642,6 +20134,16 @@ define <11 x double> @bitcast_v11i64_to_v11f64(<11 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -18677,6 +20179,16 @@ define <11 x double> @bitcast_v11i64_to_v11f64(<11 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -18712,6 +20224,16 @@ define <11 x double> @bitcast_v11i64_to_v11f64(<11 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v19, vcc
; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, 3, v20
; GFX9-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -18754,6 +20276,16 @@ define <11 x double> @bitcast_v11i64_to_v11f64(<11 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -18814,6 +20346,16 @@ define inreg <11 x double> @bitcast_v11i64_to_v11f64_scalar(<11 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB37_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -18880,6 +20422,16 @@ define inreg <11 x double> @bitcast_v11i64_to_v11f64_scalar(<11 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -18946,6 +20498,16 @@ define inreg <11 x double> @bitcast_v11i64_to_v11f64_scalar(<11 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -19010,6 +20572,16 @@ define inreg <11 x double> @bitcast_v11i64_to_v11f64_scalar(<11 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
+; GFX11-NEXT: ; implicit-def: $sgpr8
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -19063,6 +20635,16 @@ define <11 x i64> @bitcast_v11f64_to_v11i64(<11 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -19087,6 +20669,16 @@ define <11 x i64> @bitcast_v11f64_to_v11i64(<11 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; VI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; VI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -19111,6 +20703,16 @@ define <11 x i64> @bitcast_v11f64_to_v11i64(<11 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -19136,6 +20738,16 @@ define <11 x i64> @bitcast_v11f64_to_v11i64(<11 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -19215,6 +20827,16 @@ define inreg <11 x i64> @bitcast_v11f64_to_v11i64_scalar(<11 x double> inreg %a,
; SI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; SI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; SI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB39_5
; SI-NEXT: .LBB39_3:
; SI-NEXT: s_branch .LBB39_2
@@ -19327,6 +20949,16 @@ define inreg <11 x i64> @bitcast_v11f64_to_v11i64_scalar(<11 x double> inreg %a,
; VI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; VI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; VI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB39_5
; VI-NEXT: .LBB39_3:
; VI-NEXT: s_branch .LBB39_2
@@ -19439,6 +21071,16 @@ define inreg <11 x i64> @bitcast_v11f64_to_v11i64_scalar(<11 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB39_5
; GFX9-NEXT: .LBB39_3:
; GFX9-NEXT: s_branch .LBB39_2
@@ -19553,6 +21195,16 @@ define inreg <11 x i64> @bitcast_v11f64_to_v11i64_scalar(<11 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_branch .LBB39_5
; GFX11-NEXT: .LBB39_3:
; GFX11-NEXT: s_branch .LBB39_2
@@ -21158,6 +22810,16 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
@@ -21298,6 +22960,16 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -21401,6 +23073,16 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v19, v34, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v32, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
@@ -21494,6 +23176,16 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v22, 3, v32
; VI-NEXT: v_add_u16_sdwa v21, v32, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -21587,7 +23279,15 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB42_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr22
-; GFX9-NEXT: ; kill: killed $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; kill: killed $vgpr22
@@ -21614,7 +23314,9 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
@@ -21714,6 +23416,16 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v10, v10, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
@@ -21777,10 +23489,27 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -21803,7 +23532,16 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -21856,11 +23594,29 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -21883,7 +23639,16 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -22031,6 +23796,16 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s57, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -22143,6 +23918,16 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v22, 18
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -22325,6 +24110,16 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s57, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -22437,6 +24232,16 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s57, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v22, 22
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -22591,6 +24396,16 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, s56, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB43_5
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -22727,6 +24542,16 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -24325,6 +26150,16 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
@@ -24553,6 +26388,16 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -24656,6 +26501,16 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v19, v34, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v32, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
@@ -24749,6 +26604,16 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v21, v32, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v32
; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -24842,7 +26707,15 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB46_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr22
-; GFX9-NEXT: ; kill: killed $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; kill: killed $vgpr22
@@ -24869,7 +26742,9 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
@@ -24970,6 +26845,16 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v10, v10, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
@@ -25033,10 +26918,27 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -25059,7 +26961,16 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -25112,11 +27023,29 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -25139,7 +27068,16 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -25287,6 +27225,16 @@ define inreg <11 x i64> @bitcast_v44f16_to_v11i64_scalar(<44 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s57, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s35
@@ -25465,6 +27413,16 @@ define inreg <11 x i64> @bitcast_v44f16_to_v11i64_scalar(<44 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -25659,6 +27617,16 @@ define inreg <11 x i64> @bitcast_v44f16_to_v11i64_scalar(<44 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s57, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v21, 0x200
@@ -25750,6 +27718,16 @@ define inreg <11 x i64> @bitcast_v44f16_to_v11i64_scalar(<44 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v22, v22, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s6, v21
; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -25917,6 +27895,16 @@ define inreg <11 x i64> @bitcast_v44f16_to_v11i64_scalar(<44 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v19, s55, v21 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, s56, v21 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, s57, v21 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB47_5
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -26053,6 +28041,16 @@ define inreg <11 x i64> @bitcast_v44f16_to_v11i64_scalar(<44 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s20 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -27780,6 +29778,16 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
@@ -27920,6 +29928,16 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -28023,6 +30041,16 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v19, v34, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v32, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
@@ -28116,6 +30144,16 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v22, 3, v32
; VI-NEXT: v_add_u16_sdwa v21, v32, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -28209,7 +30247,15 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB50_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr22
-; GFX9-NEXT: ; kill: killed $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; kill: killed $vgpr22
@@ -28236,7 +30282,9 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
@@ -28336,6 +30384,16 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v10, v10, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
@@ -28399,10 +30457,27 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -28425,7 +30500,16 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -28478,11 +30562,29 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -28505,7 +30607,16 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -28653,6 +30764,16 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s57, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -28765,6 +30886,16 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v22, 18
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -28947,6 +31078,16 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s57, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -29059,6 +31200,16 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s57, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v22, 22
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -29213,6 +31364,16 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, s56, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB51_5
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -29349,6 +31510,16 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -31086,6 +33257,16 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
@@ -31314,6 +33495,16 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -31417,6 +33608,16 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v19, v34, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v33, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v32, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
@@ -31510,6 +33711,16 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v21, v32, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v32
; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -31603,7 +33814,15 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_cbranch_execz .LBB54_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: ; implicit-def: $vgpr22
-; GFX9-NEXT: ; kill: killed $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: ; kill: killed $vgpr22
@@ -31630,7 +33849,9 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; kill: killed $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v32
@@ -31731,6 +33952,16 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v10, v10, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
@@ -31794,10 +34025,27 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -31820,7 +34068,16 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -31873,11 +34130,29 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v24, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v23, v21, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -31900,7 +34175,16 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -32048,6 +34332,16 @@ define inreg <11 x double> @bitcast_v44f16_to_v11f64_scalar(<44 x half> inreg %a
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s57, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr58
+; SI-NEXT: ; implicit-def: $sgpr59
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s35
@@ -32226,6 +34520,16 @@ define inreg <11 x double> @bitcast_v44f16_to_v11f64_scalar(<44 x half> inreg %a
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v23, v21
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -32420,6 +34724,16 @@ define inreg <11 x double> @bitcast_v44f16_to_v11f64_scalar(<44 x half> inreg %a
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s57, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr58
+; VI-NEXT: ; implicit-def: $sgpr59
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v21, 0x200
@@ -32511,6 +34825,16 @@ define inreg <11 x double> @bitcast_v44f16_to_v11f64_scalar(<44 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v22, v22, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s6, v21
; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
+; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -32678,6 +35002,16 @@ define inreg <11 x double> @bitcast_v44f16_to_v11f64_scalar(<44 x half> inreg %a
; GFX9-NEXT: v_pk_add_f16 v19, s55, v21 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, s56, v21 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, s57, v21 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
+; GFX9-NEXT: ; implicit-def: $vgpr22
; GFX9-NEXT: s_branch .LBB55_5
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -32814,6 +35148,16 @@ define inreg <11 x double> @bitcast_v44f16_to_v11f64_scalar(<44 x half> inreg %a
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s20 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
+; GFX11-NEXT: ; implicit-def: $vgpr22
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
index 332c550eaaccf..3c637e5b3f592 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
@@ -40,6 +40,14 @@ define <24 x float> @bitcast_v24i32_to_v24f32(<24 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -77,6 +85,14 @@ define <24 x float> @bitcast_v24i32_to_v24f32(<24 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -114,6 +130,14 @@ define <24 x float> @bitcast_v24i32_to_v24f32(<24 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -152,6 +176,14 @@ define <24 x float> @bitcast_v24i32_to_v24f32(<24 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -216,6 +248,14 @@ define inreg <24 x float> @bitcast_v24i32_to_v24f32_scalar(<24 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB1_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -288,6 +328,14 @@ define inreg <24 x float> @bitcast_v24i32_to_v24f32_scalar(<24 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB1_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -360,6 +408,14 @@ define inreg <24 x float> @bitcast_v24i32_to_v24f32_scalar(<24 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB1_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -430,6 +486,14 @@ define inreg <24 x float> @bitcast_v24i32_to_v24f32_scalar(<24 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB1_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -498,6 +562,14 @@ define <24 x i32> @bitcast_v24f32_to_v24i32(<24 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -535,6 +607,14 @@ define <24 x i32> @bitcast_v24f32_to_v24i32(<24 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -572,6 +652,14 @@ define <24 x i32> @bitcast_v24f32_to_v24i32(<24 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -598,6 +686,14 @@ define <24 x i32> @bitcast_v24f32_to_v24i32(<24 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -692,6 +788,14 @@ define inreg <24 x i32> @bitcast_v24f32_to_v24i32_scalar(<24 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: .LBB3_3:
; SI-NEXT: s_branch .LBB3_2
@@ -819,6 +923,14 @@ define inreg <24 x i32> @bitcast_v24f32_to_v24i32_scalar(<24 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB3_5
; VI-NEXT: .LBB3_3:
; VI-NEXT: s_branch .LBB3_2
@@ -946,6 +1058,14 @@ define inreg <24 x i32> @bitcast_v24f32_to_v24i32_scalar(<24 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: .LBB3_3:
; GFX9-NEXT: s_branch .LBB3_2
@@ -1075,6 +1195,14 @@ define inreg <24 x i32> @bitcast_v24f32_to_v24i32_scalar(<24 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_branch .LBB3_5
; GFX11-NEXT: .LBB3_3:
; GFX11-NEXT: s_branch .LBB3_2
@@ -1164,6 +1292,14 @@ define <12 x i64> @bitcast_v24i32_to_v12i64(<24 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1201,6 +1337,14 @@ define <12 x i64> @bitcast_v24i32_to_v12i64(<24 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1238,6 +1382,14 @@ define <12 x i64> @bitcast_v24i32_to_v12i64(<24 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1276,6 +1428,14 @@ define <12 x i64> @bitcast_v24i32_to_v12i64(<24 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1340,6 +1500,14 @@ define inreg <12 x i64> @bitcast_v24i32_to_v12i64_scalar(<24 x i32> inreg %a, i3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1412,6 +1580,14 @@ define inreg <12 x i64> @bitcast_v24i32_to_v12i64_scalar(<24 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1484,6 +1660,14 @@ define inreg <12 x i64> @bitcast_v24i32_to_v12i64_scalar(<24 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1554,6 +1738,14 @@ define inreg <12 x i64> @bitcast_v24i32_to_v12i64_scalar(<24 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1622,6 +1814,14 @@ define <24 x i32> @bitcast_v12i64_to_v24i32(<12 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1659,6 +1859,14 @@ define <24 x i32> @bitcast_v12i64_to_v24i32(<12 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1696,6 +1904,14 @@ define <24 x i32> @bitcast_v12i64_to_v24i32(<12 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1740,6 +1956,14 @@ define <24 x i32> @bitcast_v12i64_to_v24i32(<12 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1804,6 +2028,14 @@ define inreg <24 x i32> @bitcast_v12i64_to_v24i32_scalar(<12 x i64> inreg %a, i3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB7_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1876,6 +2108,14 @@ define inreg <24 x i32> @bitcast_v12i64_to_v24i32_scalar(<12 x i64> inreg %a, i3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB7_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1948,6 +2188,14 @@ define inreg <24 x i32> @bitcast_v12i64_to_v24i32_scalar(<12 x i64> inreg %a, i3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB7_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2018,6 +2266,14 @@ define inreg <24 x i32> @bitcast_v12i64_to_v24i32_scalar(<12 x i64> inreg %a, i3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2086,6 +2342,14 @@ define <12 x double> @bitcast_v24i32_to_v12f64(<24 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2123,6 +2387,14 @@ define <12 x double> @bitcast_v24i32_to_v12f64(<24 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2160,6 +2432,14 @@ define <12 x double> @bitcast_v24i32_to_v12f64(<24 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2198,6 +2478,14 @@ define <12 x double> @bitcast_v24i32_to_v12f64(<24 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2262,6 +2550,14 @@ define inreg <12 x double> @bitcast_v24i32_to_v12f64_scalar(<24 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -2334,6 +2630,14 @@ define inreg <12 x double> @bitcast_v24i32_to_v12f64_scalar(<24 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2406,6 +2710,14 @@ define inreg <12 x double> @bitcast_v24i32_to_v12f64_scalar(<24 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2476,6 +2788,14 @@ define inreg <12 x double> @bitcast_v24i32_to_v12f64_scalar(<24 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2532,6 +2852,14 @@ define <24 x i32> @bitcast_v12f64_to_v24i32(<12 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2557,6 +2885,14 @@ define <24 x i32> @bitcast_v12f64_to_v24i32(<12 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2582,6 +2918,14 @@ define <24 x i32> @bitcast_v12f64_to_v24i32(<12 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2608,6 +2952,14 @@ define <24 x i32> @bitcast_v12f64_to_v24i32(<12 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2690,6 +3042,14 @@ define inreg <24 x i32> @bitcast_v12f64_to_v24i32_scalar(<12 x double> inreg %a,
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB11_5
; SI-NEXT: .LBB11_3:
; SI-NEXT: s_branch .LBB11_2
@@ -2805,6 +3165,14 @@ define inreg <24 x i32> @bitcast_v12f64_to_v24i32_scalar(<12 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB11_5
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -2920,6 +3288,14 @@ define inreg <24 x i32> @bitcast_v12f64_to_v24i32_scalar(<12 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB11_5
; GFX9-NEXT: .LBB11_3:
; GFX9-NEXT: s_branch .LBB11_2
@@ -3037,6 +3413,14 @@ define inreg <24 x i32> @bitcast_v12f64_to_v24i32_scalar(<12 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_branch .LBB11_5
; GFX11-NEXT: .LBB11_3:
; GFX11-NEXT: s_branch .LBB11_2
@@ -4775,6 +5159,14 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
@@ -4937,6 +5329,14 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -5048,6 +5448,14 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -5149,6 +5557,14 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v24, 3, v32
; VI-NEXT: v_add_u16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB14_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -5325,6 +5741,14 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
@@ -5440,6 +5864,14 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB14_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -5467,10 +5899,25 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5495,7 +5942,14 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5552,11 +6006,27 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5581,7 +6051,14 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -5743,6 +6220,14 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -5865,6 +6350,14 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v24, 22
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -6067,6 +6560,14 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s59, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -6189,6 +6690,14 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s59, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB15_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v24, 26
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -6357,6 +6866,14 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, s58, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB15_5
; GFX9-NEXT: .LBB15_3:
; GFX9-NEXT: s_branch .LBB15_2
@@ -6501,6 +7018,14 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v22, s22, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_3:
; GFX11-NEXT: s_branch .LBB15_2
@@ -8236,6 +8761,14 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
@@ -8495,6 +9028,14 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB18_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -8606,6 +9147,14 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -8707,6 +9256,14 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v32
; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB18_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -8883,6 +9440,14 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
@@ -8999,6 +9564,14 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB18_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -9026,10 +9599,25 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -9054,7 +9642,14 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -9111,11 +9706,27 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -9140,7 +9751,14 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9302,6 +9920,14 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB19_4
; SI-NEXT: .LBB19_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s71
@@ -9496,6 +10122,14 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB19_5
; SI-NEXT: .LBB19_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -9708,6 +10342,14 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s59, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
@@ -9807,6 +10449,14 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v24, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s6, v23
; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -9986,6 +10636,14 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v21, s57, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, s58, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, s59, v23 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB19_5
; GFX9-NEXT: .LBB19_3:
; GFX9-NEXT: s_branch .LBB19_2
@@ -10130,6 +10788,14 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s22 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3:
; GFX11-NEXT: s_branch .LBB19_2
@@ -10202,6 +10868,14 @@ define <12 x i64> @bitcast_v24f32_to_v12i64(<24 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -10239,6 +10913,14 @@ define <12 x i64> @bitcast_v24f32_to_v12i64(<24 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -10276,6 +10958,14 @@ define <12 x i64> @bitcast_v24f32_to_v12i64(<24 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10302,6 +10992,14 @@ define <12 x i64> @bitcast_v24f32_to_v12i64(<24 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10396,6 +11094,14 @@ define inreg <12 x i64> @bitcast_v24f32_to_v12i64_scalar(<24 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB21_5
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -10523,6 +11229,14 @@ define inreg <12 x i64> @bitcast_v24f32_to_v12i64_scalar(<24 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB21_5
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -10650,6 +11364,14 @@ define inreg <12 x i64> @bitcast_v24f32_to_v12i64_scalar(<24 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB21_5
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -10779,6 +11501,14 @@ define inreg <12 x i64> @bitcast_v24f32_to_v12i64_scalar(<24 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_branch .LBB21_5
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -10868,6 +11598,14 @@ define <24 x float> @bitcast_v12i64_to_v24f32(<12 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -10905,6 +11643,14 @@ define <24 x float> @bitcast_v12i64_to_v24f32(<12 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -10942,6 +11688,14 @@ define <24 x float> @bitcast_v12i64_to_v24f32(<12 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10986,6 +11740,14 @@ define <24 x float> @bitcast_v12i64_to_v24f32(<12 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11050,6 +11812,14 @@ define inreg <24 x float> @bitcast_v12i64_to_v24f32_scalar(<12 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -11122,6 +11892,14 @@ define inreg <24 x float> @bitcast_v12i64_to_v24f32_scalar(<12 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB23_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -11194,6 +11972,14 @@ define inreg <24 x float> @bitcast_v12i64_to_v24f32_scalar(<12 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB23_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -11264,6 +12050,14 @@ define inreg <24 x float> @bitcast_v12i64_to_v24f32_scalar(<12 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -11332,6 +12126,14 @@ define <12 x double> @bitcast_v24f32_to_v12f64(<24 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -11369,6 +12171,14 @@ define <12 x double> @bitcast_v24f32_to_v12f64(<24 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -11406,6 +12216,14 @@ define <12 x double> @bitcast_v24f32_to_v12f64(<24 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -11432,6 +12250,14 @@ define <12 x double> @bitcast_v24f32_to_v12f64(<24 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11526,6 +12352,14 @@ define inreg <12 x double> @bitcast_v24f32_to_v12f64_scalar(<24 x float> inreg %
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB25_5
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -11653,6 +12487,14 @@ define inreg <12 x double> @bitcast_v24f32_to_v12f64_scalar(<24 x float> inreg %
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB25_5
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -11780,6 +12622,14 @@ define inreg <12 x double> @bitcast_v24f32_to_v12f64_scalar(<24 x float> inreg %
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB25_5
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -11909,6 +12759,14 @@ define inreg <12 x double> @bitcast_v24f32_to_v12f64_scalar(<24 x float> inreg %
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_branch .LBB25_5
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -11986,6 +12844,14 @@ define <24 x float> @bitcast_v12f64_to_v24f32(<12 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -12011,6 +12877,14 @@ define <24 x float> @bitcast_v12f64_to_v24f32(<12 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12036,6 +12910,14 @@ define <24 x float> @bitcast_v12f64_to_v24f32(<12 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12062,6 +12944,14 @@ define <24 x float> @bitcast_v12f64_to_v24f32(<12 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -12144,6 +13034,14 @@ define inreg <24 x float> @bitcast_v12f64_to_v24f32_scalar(<12 x double> inreg %
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB27_5
; SI-NEXT: .LBB27_3:
; SI-NEXT: s_branch .LBB27_2
@@ -12259,6 +13157,14 @@ define inreg <24 x float> @bitcast_v12f64_to_v24f32_scalar(<12 x double> inreg %
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB27_5
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -12374,6 +13280,14 @@ define inreg <24 x float> @bitcast_v12f64_to_v24f32_scalar(<12 x double> inreg %
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB27_5
; GFX9-NEXT: .LBB27_3:
; GFX9-NEXT: s_branch .LBB27_2
@@ -12491,6 +13405,14 @@ define inreg <24 x float> @bitcast_v12f64_to_v24f32_scalar(<12 x double> inreg %
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_branch .LBB27_5
; GFX11-NEXT: .LBB27_3:
; GFX11-NEXT: s_branch .LBB27_2
@@ -14489,6 +15411,14 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
@@ -14651,6 +15581,14 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -14762,6 +15700,14 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -14863,6 +15809,14 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v24, 3, v32
; VI-NEXT: v_add_u16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB30_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -15039,6 +15993,14 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
@@ -15154,6 +16116,14 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB30_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -15181,10 +16151,25 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -15209,7 +16194,14 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -15266,11 +16258,27 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -15295,7 +16303,14 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -15457,6 +16472,14 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB31_3
; SI-NEXT: .LBB31_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -15579,6 +16602,14 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB31_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v24, 22
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -15781,6 +16812,14 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s59, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB31_3
; VI-NEXT: .LBB31_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -15903,6 +16942,14 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s59, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB31_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v24, 26
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -16071,6 +17118,14 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, s58, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB31_5
; GFX9-NEXT: .LBB31_3:
; GFX9-NEXT: s_branch .LBB31_2
@@ -16215,6 +17270,14 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v22, s22, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_3:
; GFX11-NEXT: s_branch .LBB31_2
@@ -18210,6 +19273,14 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
@@ -18469,6 +19540,14 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -18580,6 +19659,14 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -18681,6 +19768,14 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v32
; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -18857,6 +19952,14 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
@@ -18973,6 +20076,14 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB34_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -19000,10 +20111,25 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -19028,7 +20154,14 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -19085,11 +20218,27 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -19114,7 +20263,14 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -19276,6 +20432,14 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB35_4
; SI-NEXT: .LBB35_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s71
@@ -19470,6 +20634,14 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB35_5
; SI-NEXT: .LBB35_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -19682,6 +20854,14 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s59, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
@@ -19781,6 +20961,14 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v24, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s6, v23
; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -19960,6 +21148,14 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v21, s57, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, s58, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, s59, v23 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB35_5
; GFX9-NEXT: .LBB35_3:
; GFX9-NEXT: s_branch .LBB35_2
@@ -20104,6 +21300,14 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s22 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3:
; GFX11-NEXT: s_branch .LBB35_2
@@ -20176,6 +21380,14 @@ define <12 x double> @bitcast_v12i64_to_v12f64(<12 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -20213,6 +21425,14 @@ define <12 x double> @bitcast_v12i64_to_v12f64(<12 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -20250,6 +21470,14 @@ define <12 x double> @bitcast_v12i64_to_v12f64(<12 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, 3, v22
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v23, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -20294,6 +21522,14 @@ define <12 x double> @bitcast_v12i64_to_v12f64(<12 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -20358,6 +21594,14 @@ define inreg <12 x double> @bitcast_v12i64_to_v12f64_scalar(<12 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB37_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -20430,6 +21674,14 @@ define inreg <12 x double> @bitcast_v12i64_to_v12f64_scalar(<12 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -20502,6 +21754,14 @@ define inreg <12 x double> @bitcast_v12i64_to_v12f64_scalar(<12 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -20572,6 +21832,14 @@ define inreg <12 x double> @bitcast_v12i64_to_v12f64_scalar(<12 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
+; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -20627,6 +21895,14 @@ define <12 x i64> @bitcast_v12f64_to_v12i64(<12 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; SI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -20652,6 +21928,14 @@ define <12 x i64> @bitcast_v12f64_to_v12i64(<12 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; VI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; VI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -20677,6 +21961,14 @@ define <12 x i64> @bitcast_v12f64_to_v12i64(<12 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -20703,6 +21995,14 @@ define <12 x i64> @bitcast_v12f64_to_v12i64(<12 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -20785,6 +22085,14 @@ define inreg <12 x i64> @bitcast_v12f64_to_v12i64_scalar(<12 x double> inreg %a,
; SI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; SI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; SI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB39_5
; SI-NEXT: .LBB39_3:
; SI-NEXT: s_branch .LBB39_2
@@ -20900,6 +22208,14 @@ define inreg <12 x i64> @bitcast_v12f64_to_v12i64_scalar(<12 x double> inreg %a,
; VI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; VI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; VI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB39_5
; VI-NEXT: .LBB39_3:
; VI-NEXT: s_branch .LBB39_2
@@ -21015,6 +22331,14 @@ define inreg <12 x i64> @bitcast_v12f64_to_v12i64_scalar(<12 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX9-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB39_5
; GFX9-NEXT: .LBB39_3:
; GFX9-NEXT: s_branch .LBB39_2
@@ -21132,6 +22456,14 @@ define inreg <12 x i64> @bitcast_v12f64_to_v12i64_scalar(<12 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX11-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_branch .LBB39_5
; GFX11-NEXT: .LBB39_3:
; GFX11-NEXT: s_branch .LBB39_2
@@ -22882,6 +24214,14 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
@@ -23044,6 +24384,14 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -23155,6 +24503,14 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -23256,6 +24612,14 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v24, 3, v32
; VI-NEXT: v_add_u16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -23432,6 +24796,14 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
@@ -23547,6 +24919,14 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB42_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -23574,10 +24954,25 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -23602,7 +24997,14 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -23659,11 +25061,27 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -23688,7 +25106,14 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -23850,6 +25275,14 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -23972,6 +25405,14 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v24, 22
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -24174,6 +25615,14 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s59, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -24296,6 +25745,14 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s59, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v24, 26
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -24464,6 +25921,14 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, s58, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB43_5
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -24608,6 +26073,14 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v22, s22, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -26355,6 +27828,14 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
@@ -26614,6 +28095,14 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -26725,6 +28214,14 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -26826,6 +28323,14 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v32
; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -27002,6 +28507,14 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
@@ -27118,6 +28631,14 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB46_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -27145,10 +28666,25 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -27173,7 +28709,14 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -27230,11 +28773,27 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -27259,7 +28818,14 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -27421,6 +28987,14 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s71
@@ -27615,6 +29189,14 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -27827,6 +29409,14 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s59, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
@@ -27926,6 +29516,14 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v24, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s6, v23
; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -28105,6 +29703,14 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v21, s57, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, s58, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, s59, v23 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB47_5
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -28249,6 +29855,14 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s22 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -30134,6 +31748,14 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
@@ -30296,6 +31918,14 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -30407,6 +32037,14 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -30508,6 +32146,14 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v24, 3, v32
; VI-NEXT: v_add_u16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -30684,6 +32330,14 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
@@ -30799,6 +32453,14 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB50_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -30826,10 +32488,25 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -30854,7 +32531,14 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -30911,11 +32595,27 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -30940,7 +32640,14 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -31102,6 +32809,14 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -31224,6 +32939,14 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v24, 22
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -31426,6 +33149,14 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s59, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -31548,6 +33279,14 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s59, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v24, 26
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -31716,6 +33455,14 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, s58, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB51_5
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -31860,6 +33607,14 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v22, s22, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -33759,6 +35514,14 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
@@ -34018,6 +35781,14 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -34129,6 +35900,14 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -34230,6 +36009,14 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v32
; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -34406,6 +36193,14 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
@@ -34522,6 +36317,14 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: .LBB54_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -34549,10 +36352,25 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -34577,7 +36395,14 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -34634,11 +36459,27 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -34663,7 +36504,14 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -34825,6 +36673,14 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s59, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr60
+; SI-NEXT: ; implicit-def: $sgpr61
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s71
@@ -35019,6 +36875,14 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -35231,6 +37095,14 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s59, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr60
+; VI-NEXT: ; implicit-def: $sgpr61
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
@@ -35330,6 +37202,14 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v24, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s6, v23
; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
+; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -35509,6 +37389,14 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; GFX9-NEXT: v_pk_add_f16 v21, s57, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, s58, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, s59, v23 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
+; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_branch .LBB55_5
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -35653,6 +37541,14 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s22 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
+; GFX11-NEXT: ; implicit-def: $vgpr24
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
index bae36084f83f9..b4ccc9e18a7f7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
@@ -42,6 +42,12 @@ define <26 x float> @bitcast_v26i32_to_v26f32(<26 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -81,6 +87,12 @@ define <26 x float> @bitcast_v26i32_to_v26f32(<26 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -120,6 +132,12 @@ define <26 x float> @bitcast_v26i32_to_v26f32(<26 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -160,6 +178,12 @@ define <26 x float> @bitcast_v26i32_to_v26f32(<26 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -228,6 +252,12 @@ define inreg <26 x float> @bitcast_v26i32_to_v26f32_scalar(<26 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB1_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -306,6 +336,12 @@ define inreg <26 x float> @bitcast_v26i32_to_v26f32_scalar(<26 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB1_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -384,6 +420,12 @@ define inreg <26 x float> @bitcast_v26i32_to_v26f32_scalar(<26 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB1_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -460,6 +502,12 @@ define inreg <26 x float> @bitcast_v26i32_to_v26f32_scalar(<26 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: .LBB1_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -531,6 +579,12 @@ define <26 x i32> @bitcast_v26f32_to_v26i32(<26 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -570,6 +624,12 @@ define <26 x i32> @bitcast_v26f32_to_v26i32(<26 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -609,6 +669,12 @@ define <26 x i32> @bitcast_v26f32_to_v26i32(<26 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -636,6 +702,12 @@ define <26 x i32> @bitcast_v26f32_to_v26i32(<26 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -734,6 +806,12 @@ define inreg <26 x i32> @bitcast_v26f32_to_v26i32_scalar(<26 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: .LBB3_3:
; SI-NEXT: s_branch .LBB3_2
@@ -865,6 +943,12 @@ define inreg <26 x i32> @bitcast_v26f32_to_v26i32_scalar(<26 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB3_5
; VI-NEXT: .LBB3_3:
; VI-NEXT: s_branch .LBB3_2
@@ -996,6 +1080,12 @@ define inreg <26 x i32> @bitcast_v26f32_to_v26i32_scalar(<26 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: .LBB3_3:
; GFX9-NEXT: s_branch .LBB3_2
@@ -1129,6 +1219,12 @@ define inreg <26 x i32> @bitcast_v26f32_to_v26i32_scalar(<26 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_branch .LBB3_5
; GFX11-NEXT: .LBB3_3:
; GFX11-NEXT: s_branch .LBB3_2
@@ -1220,6 +1316,12 @@ define <13 x i64> @bitcast_v26i32_to_v13i64(<26 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1259,6 +1361,12 @@ define <13 x i64> @bitcast_v26i32_to_v13i64(<26 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1298,6 +1406,12 @@ define <13 x i64> @bitcast_v26i32_to_v13i64(<26 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1338,6 +1452,12 @@ define <13 x i64> @bitcast_v26i32_to_v13i64(<26 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1406,6 +1526,12 @@ define inreg <13 x i64> @bitcast_v26i32_to_v13i64_scalar(<26 x i32> inreg %a, i3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1484,6 +1610,12 @@ define inreg <13 x i64> @bitcast_v26i32_to_v13i64_scalar(<26 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1562,6 +1694,12 @@ define inreg <13 x i64> @bitcast_v26i32_to_v13i64_scalar(<26 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1638,6 +1776,12 @@ define inreg <13 x i64> @bitcast_v26i32_to_v13i64_scalar(<26 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1709,6 +1853,12 @@ define <26 x i32> @bitcast_v13i64_to_v26i32(<13 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1748,6 +1898,12 @@ define <26 x i32> @bitcast_v13i64_to_v26i32(<13 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1787,6 +1943,12 @@ define <26 x i32> @bitcast_v13i64_to_v26i32(<13 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1834,6 +1996,12 @@ define <26 x i32> @bitcast_v13i64_to_v26i32(<13 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1902,6 +2070,12 @@ define inreg <26 x i32> @bitcast_v13i64_to_v26i32_scalar(<13 x i64> inreg %a, i3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB7_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1980,6 +2154,12 @@ define inreg <26 x i32> @bitcast_v13i64_to_v26i32_scalar(<13 x i64> inreg %a, i3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB7_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2058,6 +2238,12 @@ define inreg <26 x i32> @bitcast_v13i64_to_v26i32_scalar(<13 x i64> inreg %a, i3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB7_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2134,6 +2320,12 @@ define inreg <26 x i32> @bitcast_v13i64_to_v26i32_scalar(<13 x i64> inreg %a, i3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2205,6 +2397,12 @@ define <13 x double> @bitcast_v26i32_to_v13f64(<26 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2244,6 +2442,12 @@ define <13 x double> @bitcast_v26i32_to_v13f64(<26 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2283,6 +2487,12 @@ define <13 x double> @bitcast_v26i32_to_v13f64(<26 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2323,6 +2533,12 @@ define <13 x double> @bitcast_v26i32_to_v13f64(<26 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2391,6 +2607,12 @@ define inreg <13 x double> @bitcast_v26i32_to_v13f64_scalar(<26 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -2469,6 +2691,12 @@ define inreg <13 x double> @bitcast_v26i32_to_v13f64_scalar(<26 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2547,6 +2775,12 @@ define inreg <13 x double> @bitcast_v26i32_to_v13f64_scalar(<26 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2623,6 +2857,12 @@ define inreg <13 x double> @bitcast_v26i32_to_v13f64_scalar(<26 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2681,6 +2921,12 @@ define <26 x i32> @bitcast_v13f64_to_v26i32(<13 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2707,6 +2953,12 @@ define <26 x i32> @bitcast_v13f64_to_v26i32(<13 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2733,6 +2985,12 @@ define <26 x i32> @bitcast_v13f64_to_v26i32(<13 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2760,6 +3018,12 @@ define <26 x i32> @bitcast_v13f64_to_v26i32(<13 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2845,6 +3109,12 @@ define inreg <26 x i32> @bitcast_v13f64_to_v26i32_scalar(<13 x double> inreg %a,
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB11_5
; SI-NEXT: .LBB11_3:
; SI-NEXT: s_branch .LBB11_2
@@ -2963,6 +3233,12 @@ define inreg <26 x i32> @bitcast_v13f64_to_v26i32_scalar(<13 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB11_5
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -3081,6 +3357,12 @@ define inreg <26 x i32> @bitcast_v13f64_to_v26i32_scalar(<13 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB11_5
; GFX9-NEXT: .LBB11_3:
; GFX9-NEXT: s_branch .LBB11_2
@@ -3201,6 +3483,12 @@ define inreg <26 x i32> @bitcast_v13f64_to_v26i32_scalar(<13 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_branch .LBB11_5
; GFX11-NEXT: .LBB11_3:
; GFX11-NEXT: s_branch .LBB11_2
@@ -5117,6 +5405,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
@@ -5302,6 +5596,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -5421,6 +5721,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v23, v34, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v24, v33, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v25, v32, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr47
@@ -5530,6 +5836,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v26, 3, v32
; VI-NEXT: v_add_u16_sdwa v25, v32, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB14_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -5722,6 +6034,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
@@ -5855,6 +6173,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB14_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -5882,10 +6206,23 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5912,7 +6249,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5973,11 +6315,25 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6004,7 +6360,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6180,6 +6541,12 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s61, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -6312,6 +6679,12 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s61, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v26, 26
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -6534,6 +6907,12 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s61, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -6666,6 +7045,12 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s61, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB15_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v26, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -6848,6 +7233,12 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v24, s60, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v25, s61, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB15_5
; GFX9-NEXT: .LBB15_3:
; GFX9-NEXT: s_branch .LBB15_2
@@ -7000,6 +7391,12 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v24, s24, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v25, s25, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_3:
; GFX11-NEXT: s_branch .LBB15_2
@@ -8915,6 +9312,12 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
@@ -9204,6 +9607,12 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB18_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -9323,6 +9732,12 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v23, v34, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v24, v33, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v25, v32, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr47
@@ -9432,6 +9847,12 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v25, v32, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, 0x200, v32
; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB18_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -9624,6 +10045,12 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
@@ -9758,6 +10185,12 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: v_pk_add_f16 v25, v25, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB18_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -9785,10 +10218,23 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -9815,7 +10261,12 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -9876,11 +10327,25 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -9907,7 +10372,12 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10083,6 +10553,12 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s61, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB19_4
; SI-NEXT: .LBB19_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s83
@@ -10293,6 +10769,12 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB19_5
; SI-NEXT: .LBB19_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -10523,6 +11005,12 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s61, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v25, 0x200
@@ -10630,6 +11118,12 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v26, v26, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s6, v25
; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -10821,6 +11315,12 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v23, s59, v25 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v24, s60, v25 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v25, s61, v25 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB19_5
; GFX9-NEXT: .LBB19_3:
; GFX9-NEXT: s_branch .LBB19_2
@@ -10973,6 +11473,12 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v24, 0x200, s24 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s25 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3:
; GFX11-NEXT: s_branch .LBB19_2
@@ -11047,6 +11553,12 @@ define <13 x i64> @bitcast_v26f32_to_v13i64(<26 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -11086,6 +11598,12 @@ define <13 x i64> @bitcast_v26f32_to_v13i64(<26 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -11125,6 +11643,12 @@ define <13 x i64> @bitcast_v26f32_to_v13i64(<26 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -11152,6 +11676,12 @@ define <13 x i64> @bitcast_v26f32_to_v13i64(<26 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11250,6 +11780,12 @@ define inreg <13 x i64> @bitcast_v26f32_to_v13i64_scalar(<26 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB21_5
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -11381,6 +11917,12 @@ define inreg <13 x i64> @bitcast_v26f32_to_v13i64_scalar(<26 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB21_5
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -11512,6 +12054,12 @@ define inreg <13 x i64> @bitcast_v26f32_to_v13i64_scalar(<26 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB21_5
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -11645,6 +12193,12 @@ define inreg <13 x i64> @bitcast_v26f32_to_v13i64_scalar(<26 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_branch .LBB21_5
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -11736,6 +12290,12 @@ define <26 x float> @bitcast_v13i64_to_v26f32(<13 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -11775,6 +12335,12 @@ define <26 x float> @bitcast_v13i64_to_v26f32(<13 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -11814,6 +12380,12 @@ define <26 x float> @bitcast_v13i64_to_v26f32(<13 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -11861,6 +12433,12 @@ define <26 x float> @bitcast_v13i64_to_v26f32(<13 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11929,6 +12507,12 @@ define inreg <26 x float> @bitcast_v13i64_to_v26f32_scalar(<13 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -12007,6 +12591,12 @@ define inreg <26 x float> @bitcast_v13i64_to_v26f32_scalar(<13 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB23_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -12085,6 +12675,12 @@ define inreg <26 x float> @bitcast_v13i64_to_v26f32_scalar(<13 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB23_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -12161,6 +12757,12 @@ define inreg <26 x float> @bitcast_v13i64_to_v26f32_scalar(<13 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -12232,6 +12834,12 @@ define <13 x double> @bitcast_v26f32_to_v13f64(<26 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -12271,6 +12879,12 @@ define <13 x double> @bitcast_v26f32_to_v13f64(<26 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12310,6 +12924,12 @@ define <13 x double> @bitcast_v26f32_to_v13f64(<26 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12337,6 +12957,12 @@ define <13 x double> @bitcast_v26f32_to_v13f64(<26 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -12435,6 +13061,12 @@ define inreg <13 x double> @bitcast_v26f32_to_v13f64_scalar(<26 x float> inreg %
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB25_5
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -12566,6 +13198,12 @@ define inreg <13 x double> @bitcast_v26f32_to_v13f64_scalar(<26 x float> inreg %
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB25_5
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -12697,6 +13335,12 @@ define inreg <13 x double> @bitcast_v26f32_to_v13f64_scalar(<26 x float> inreg %
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB25_5
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -12830,6 +13474,12 @@ define inreg <13 x double> @bitcast_v26f32_to_v13f64_scalar(<26 x float> inreg %
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_branch .LBB25_5
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -12908,6 +13558,12 @@ define <26 x float> @bitcast_v13f64_to_v26f32(<13 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -12934,6 +13590,12 @@ define <26 x float> @bitcast_v13f64_to_v26f32(<13 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12960,6 +13622,12 @@ define <26 x float> @bitcast_v13f64_to_v26f32(<13 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12987,6 +13655,12 @@ define <26 x float> @bitcast_v13f64_to_v26f32(<13 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13072,6 +13746,12 @@ define inreg <26 x float> @bitcast_v13f64_to_v26f32_scalar(<13 x double> inreg %
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB27_5
; SI-NEXT: .LBB27_3:
; SI-NEXT: s_branch .LBB27_2
@@ -13190,6 +13870,12 @@ define inreg <26 x float> @bitcast_v13f64_to_v26f32_scalar(<13 x double> inreg %
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB27_5
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -13308,6 +13994,12 @@ define inreg <26 x float> @bitcast_v13f64_to_v26f32_scalar(<13 x double> inreg %
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB27_5
; GFX9-NEXT: .LBB27_3:
; GFX9-NEXT: s_branch .LBB27_2
@@ -13428,6 +14120,12 @@ define inreg <26 x float> @bitcast_v13f64_to_v26f32_scalar(<13 x double> inreg %
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_branch .LBB27_5
; GFX11-NEXT: .LBB27_3:
; GFX11-NEXT: s_branch .LBB27_2
@@ -15659,6 +16357,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
@@ -15844,6 +16548,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -15963,6 +16673,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v23, v34, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v24, v33, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v25, v32, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr47
@@ -16072,6 +16788,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v26, 3, v32
; VI-NEXT: v_add_u16_sdwa v25, v32, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB30_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -16264,6 +16986,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
@@ -16397,6 +17125,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB30_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -16424,10 +17158,23 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -16454,7 +17201,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16515,11 +17267,25 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -16546,7 +17312,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -16722,6 +17493,12 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s61, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB31_3
; SI-NEXT: .LBB31_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -16854,6 +17631,12 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s61, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB31_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v26, 26
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -17076,6 +17859,12 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s61, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB31_3
; VI-NEXT: .LBB31_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -17208,6 +17997,12 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s61, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB31_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v26, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -17390,6 +18185,12 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v24, s60, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v25, s61, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB31_5
; GFX9-NEXT: .LBB31_3:
; GFX9-NEXT: s_branch .LBB31_2
@@ -17542,6 +18343,12 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v24, s24, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v25, s25, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_3:
; GFX11-NEXT: s_branch .LBB31_2
@@ -19772,6 +20579,12 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
@@ -20061,6 +20874,12 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -20180,6 +20999,12 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v23, v34, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v24, v33, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v25, v32, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr47
@@ -20289,6 +21114,12 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v25, v32, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, 0x200, v32
; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -20481,6 +21312,12 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
@@ -20615,6 +21452,12 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: v_pk_add_f16 v25, v25, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB34_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -20642,10 +21485,23 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -20672,7 +21528,12 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -20733,11 +21594,25 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -20764,7 +21639,12 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -20940,6 +21820,12 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s61, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB35_4
; SI-NEXT: .LBB35_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s83
@@ -21150,6 +22036,12 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB35_5
; SI-NEXT: .LBB35_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -21380,6 +22272,12 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s61, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v25, 0x200
@@ -21487,6 +22385,12 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v26, v26, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s6, v25
; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -21678,6 +22582,12 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v23, s59, v25 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v24, s60, v25 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v25, s61, v25 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB35_5
; GFX9-NEXT: .LBB35_3:
; GFX9-NEXT: s_branch .LBB35_2
@@ -21830,6 +22740,12 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v24, 0x200, s24 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s25 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3:
; GFX11-NEXT: s_branch .LBB35_2
@@ -21904,6 +22820,12 @@ define <13 x double> @bitcast_v13i64_to_v13f64(<13 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_addc_u32_e32 v25, vcc, 0, v25, vcc
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -21943,6 +22865,12 @@ define <13 x double> @bitcast_v13i64_to_v13f64(<13 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; VI-NEXT: v_add_u32_e32 v24, vcc, 3, v24
; VI-NEXT: v_addc_u32_e32 v25, vcc, 0, v25, vcc
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -21982,6 +22910,12 @@ define <13 x double> @bitcast_v13i64_to_v13f64(<13 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v23, vcc
; GFX9-NEXT: v_add_co_u32_e32 v24, vcc, 3, v24
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v25, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -22029,6 +22963,12 @@ define <13 x double> @bitcast_v13i64_to_v13f64(<13 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v24, vcc_lo, v24, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v25, null, 0, v25, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -22097,6 +23037,12 @@ define inreg <13 x double> @bitcast_v13i64_to_v13f64_scalar(<13 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB37_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -22175,6 +23121,12 @@ define inreg <13 x double> @bitcast_v13i64_to_v13f64_scalar(<13 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -22253,6 +23205,12 @@ define inreg <13 x double> @bitcast_v13i64_to_v13f64_scalar(<13 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -22329,6 +23287,12 @@ define inreg <13 x double> @bitcast_v13i64_to_v13f64_scalar(<13 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
+; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -22386,6 +23350,12 @@ define <13 x i64> @bitcast_v13f64_to_v13i64(<13 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; SI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; SI-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -22412,6 +23382,12 @@ define <13 x i64> @bitcast_v13f64_to_v13i64(<13 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; VI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; VI-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -22438,6 +23414,12 @@ define <13 x i64> @bitcast_v13f64_to_v13i64(<13 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -22465,6 +23447,12 @@ define <13 x i64> @bitcast_v13f64_to_v13i64(<13 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -22550,6 +23538,12 @@ define inreg <13 x i64> @bitcast_v13f64_to_v13i64_scalar(<13 x double> inreg %a,
; SI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; SI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; SI-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB39_5
; SI-NEXT: .LBB39_3:
; SI-NEXT: s_branch .LBB39_2
@@ -22668,6 +23662,12 @@ define inreg <13 x i64> @bitcast_v13f64_to_v13i64_scalar(<13 x double> inreg %a,
; VI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; VI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; VI-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB39_5
; VI-NEXT: .LBB39_3:
; VI-NEXT: s_branch .LBB39_2
@@ -22786,6 +23786,12 @@ define inreg <13 x i64> @bitcast_v13f64_to_v13i64_scalar(<13 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX9-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX9-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB39_5
; GFX9-NEXT: .LBB39_3:
; GFX9-NEXT: s_branch .LBB39_2
@@ -22906,6 +23912,12 @@ define inreg <13 x i64> @bitcast_v13f64_to_v13i64_scalar(<13 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX11-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX11-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_branch .LBB39_5
; GFX11-NEXT: .LBB39_3:
; GFX11-NEXT: s_branch .LBB39_2
@@ -24836,6 +25848,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
@@ -25021,6 +26039,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -25140,6 +26164,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v23, v34, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v24, v33, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v25, v32, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr47
@@ -25249,6 +26279,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v26, 3, v32
; VI-NEXT: v_add_u16_sdwa v25, v32, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -25441,6 +26477,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
@@ -25574,6 +26616,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB42_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -25601,10 +26649,23 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -25631,7 +26692,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -25692,11 +26758,25 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -25723,7 +26803,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -25899,6 +26984,12 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s61, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -26031,6 +27122,12 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s61, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v26, 26
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -26253,6 +27350,12 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s61, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -26385,6 +27488,12 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s61, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v26, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -26567,6 +27676,12 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v24, s60, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v25, s61, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB43_5
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -26719,6 +27834,12 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v24, s24, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v25, s25, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -28648,6 +29769,12 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
@@ -28937,6 +30064,12 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -29056,6 +30189,12 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v23, v34, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v24, v33, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v25, v32, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr47
@@ -29165,6 +30304,12 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v25, v32, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, 0x200, v32
; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -29357,6 +30502,12 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
@@ -29491,6 +30642,12 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: v_pk_add_f16 v25, v25, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB46_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -29518,10 +30675,23 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -29548,7 +30718,12 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -29609,11 +30784,25 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -29640,7 +30829,12 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -29816,6 +31010,12 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s61, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s83
@@ -30026,6 +31226,12 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -30256,6 +31462,12 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s61, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v25, 0x200
@@ -30363,6 +31575,12 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v26, v26, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s6, v25
; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -30554,6 +31772,12 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v23, s59, v25 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v24, s60, v25 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v25, s61, v25 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB47_5
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -30706,6 +31930,12 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v24, 0x200, s24 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s25 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -32820,6 +34050,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
@@ -33005,6 +34241,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -33124,6 +34366,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v23, v34, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v24, v33, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v25, v32, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr47
@@ -33233,6 +34481,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v26, 3, v32
; VI-NEXT: v_add_u16_sdwa v25, v32, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -33425,6 +34679,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
@@ -33558,6 +34818,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB50_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -33585,10 +34851,23 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -33615,7 +34894,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -33676,11 +34960,25 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -33707,7 +35005,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -33883,6 +35186,12 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s61, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -34015,6 +35324,12 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s61, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v26, 26
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -34237,6 +35552,12 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s61, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -34369,6 +35690,12 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s61, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v26, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -34551,6 +35878,12 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v24, s60, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v25, s61, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB51_5
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -34703,6 +36036,12 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v24, s24, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v25, s25, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -36833,6 +38172,12 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v25, v26
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; kill: killed $vgpr26
@@ -37122,6 +38467,12 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -37241,6 +38592,12 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v23, v34, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v24, v33, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v25, v32, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr57
; VI-NEXT: ; implicit-def: $vgpr56
; VI-NEXT: ; implicit-def: $vgpr47
@@ -37350,6 +38707,12 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v25, v32, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v26, 0x200, v32
; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -37542,6 +38905,12 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; kill: killed $vgpr26
@@ -37676,6 +39045,12 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s6
; GFX9-NEXT: v_pk_add_f16 v25, v25, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: .LBB54_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -37703,10 +39078,23 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -37733,7 +39121,12 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -37794,11 +39187,25 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v28, v24, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v27, v25, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -37825,7 +39232,12 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -38001,6 +39413,12 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s61, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr62
+; SI-NEXT: ; implicit-def: $sgpr63
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s83
@@ -38211,6 +39629,12 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v26
; SI-NEXT: v_or_b32_e32 v25, v27, v25
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -38441,6 +39865,12 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s7, 16
; VI-NEXT: s_or_b32 s61, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr62
+; VI-NEXT: ; implicit-def: $sgpr63
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v25, 0x200
@@ -38548,6 +39978,12 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v26, v26, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, s6, v25
; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
+; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -38739,6 +40175,12 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; GFX9-NEXT: v_pk_add_f16 v23, s59, v25 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v24, s60, v25 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v25, s61, v25 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
+; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: s_branch .LBB55_5
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -38891,6 +40333,12 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v24, 0x200, s24 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s25 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
+; GFX11-NEXT: ; implicit-def: $vgpr26
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
index 22b1bc3ed9468..71dd90f842fb1 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
@@ -44,6 +44,10 @@ define <28 x float> @bitcast_v28i32_to_v28f32(<28 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -85,6 +89,10 @@ define <28 x float> @bitcast_v28i32_to_v28f32(<28 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -126,6 +134,10 @@ define <28 x float> @bitcast_v28i32_to_v28f32(<28 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -168,6 +180,10 @@ define <28 x float> @bitcast_v28i32_to_v28f32(<28 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -240,6 +256,10 @@ define inreg <28 x float> @bitcast_v28i32_to_v28f32_scalar(<28 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB1_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -324,6 +344,10 @@ define inreg <28 x float> @bitcast_v28i32_to_v28f32_scalar(<28 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB1_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -408,6 +432,10 @@ define inreg <28 x float> @bitcast_v28i32_to_v28f32_scalar(<28 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB1_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -490,6 +518,10 @@ define inreg <28 x float> @bitcast_v28i32_to_v28f32_scalar(<28 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: .LBB1_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -564,6 +596,10 @@ define <28 x i32> @bitcast_v28f32_to_v28i32(<28 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -605,6 +641,10 @@ define <28 x i32> @bitcast_v28f32_to_v28i32(<28 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -646,6 +686,10 @@ define <28 x i32> @bitcast_v28f32_to_v28i32(<28 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -674,6 +718,10 @@ define <28 x i32> @bitcast_v28f32_to_v28i32(<28 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -776,6 +824,10 @@ define inreg <28 x i32> @bitcast_v28f32_to_v28i32_scalar(<28 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: .LBB3_3:
; SI-NEXT: s_branch .LBB3_2
@@ -911,6 +963,10 @@ define inreg <28 x i32> @bitcast_v28f32_to_v28i32_scalar(<28 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB3_5
; VI-NEXT: .LBB3_3:
; VI-NEXT: s_branch .LBB3_2
@@ -1046,6 +1102,10 @@ define inreg <28 x i32> @bitcast_v28f32_to_v28i32_scalar(<28 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: .LBB3_3:
; GFX9-NEXT: s_branch .LBB3_2
@@ -1183,6 +1243,10 @@ define inreg <28 x i32> @bitcast_v28f32_to_v28i32_scalar(<28 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_branch .LBB3_5
; GFX11-NEXT: .LBB3_3:
; GFX11-NEXT: s_branch .LBB3_2
@@ -1276,6 +1340,10 @@ define <14 x i64> @bitcast_v28i32_to_v14i64(<28 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1317,6 +1385,10 @@ define <14 x i64> @bitcast_v28i32_to_v14i64(<28 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1358,6 +1430,10 @@ define <14 x i64> @bitcast_v28i32_to_v14i64(<28 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1400,6 +1476,10 @@ define <14 x i64> @bitcast_v28i32_to_v14i64(<28 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1472,6 +1552,10 @@ define inreg <14 x i64> @bitcast_v28i32_to_v14i64_scalar(<28 x i32> inreg %a, i3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1556,6 +1640,10 @@ define inreg <14 x i64> @bitcast_v28i32_to_v14i64_scalar(<28 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1640,6 +1728,10 @@ define inreg <14 x i64> @bitcast_v28i32_to_v14i64_scalar(<28 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1722,6 +1814,10 @@ define inreg <14 x i64> @bitcast_v28i32_to_v14i64_scalar(<28 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1796,6 +1892,10 @@ define <28 x i32> @bitcast_v14i64_to_v28i32(<14 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1837,6 +1937,10 @@ define <28 x i32> @bitcast_v14i64_to_v28i32(<14 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1878,6 +1982,10 @@ define <28 x i32> @bitcast_v14i64_to_v28i32(<14 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1927,6 +2035,10 @@ define <28 x i32> @bitcast_v14i64_to_v28i32(<14 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1999,6 +2111,10 @@ define inreg <28 x i32> @bitcast_v14i64_to_v28i32_scalar(<14 x i64> inreg %a, i3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB7_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -2083,6 +2199,10 @@ define inreg <28 x i32> @bitcast_v14i64_to_v28i32_scalar(<14 x i64> inreg %a, i3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB7_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2167,6 +2287,10 @@ define inreg <28 x i32> @bitcast_v14i64_to_v28i32_scalar(<14 x i64> inreg %a, i3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB7_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2249,6 +2373,10 @@ define inreg <28 x i32> @bitcast_v14i64_to_v28i32_scalar(<14 x i64> inreg %a, i3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2323,6 +2451,10 @@ define <14 x double> @bitcast_v28i32_to_v14f64(<28 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2364,6 +2496,10 @@ define <14 x double> @bitcast_v28i32_to_v14f64(<28 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2405,6 +2541,10 @@ define <14 x double> @bitcast_v28i32_to_v14f64(<28 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2447,6 +2587,10 @@ define <14 x double> @bitcast_v28i32_to_v14f64(<28 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2519,6 +2663,10 @@ define inreg <14 x double> @bitcast_v28i32_to_v14f64_scalar(<28 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -2603,6 +2751,10 @@ define inreg <14 x double> @bitcast_v28i32_to_v14f64_scalar(<28 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2687,6 +2839,10 @@ define inreg <14 x double> @bitcast_v28i32_to_v14f64_scalar(<28 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2769,6 +2925,10 @@ define inreg <14 x double> @bitcast_v28i32_to_v14f64_scalar(<28 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2829,6 +2989,10 @@ define <28 x i32> @bitcast_v14f64_to_v28i32(<14 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2856,6 +3020,10 @@ define <28 x i32> @bitcast_v14f64_to_v28i32(<14 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2883,6 +3051,10 @@ define <28 x i32> @bitcast_v14f64_to_v28i32(<14 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2911,6 +3083,10 @@ define <28 x i32> @bitcast_v14f64_to_v28i32(<14 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2999,6 +3175,10 @@ define inreg <28 x i32> @bitcast_v14f64_to_v28i32_scalar(<14 x double> inreg %a,
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB11_5
; SI-NEXT: .LBB11_3:
; SI-NEXT: s_branch .LBB11_2
@@ -3120,6 +3300,10 @@ define inreg <28 x i32> @bitcast_v14f64_to_v28i32_scalar(<14 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB11_5
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -3241,6 +3425,10 @@ define inreg <28 x i32> @bitcast_v14f64_to_v28i32_scalar(<14 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB11_5
; GFX9-NEXT: .LBB11_3:
; GFX9-NEXT: s_branch .LBB11_2
@@ -3364,6 +3552,10 @@ define inreg <28 x i32> @bitcast_v14f64_to_v28i32_scalar(<14 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_branch .LBB11_5
; GFX11-NEXT: .LBB11_3:
; GFX11-NEXT: s_branch .LBB11_2
@@ -5463,6 +5655,10 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
@@ -5669,6 +5865,10 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -5796,6 +5996,10 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v25, v34, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v26, v33, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v27, v32, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -5913,6 +6117,10 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v28, 3, v32
; VI-NEXT: v_add_u16_sdwa v27, v32, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB14_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -6121,6 +6329,10 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
@@ -6272,6 +6484,10 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB14_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -6299,10 +6515,21 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6331,7 +6558,10 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6396,11 +6626,23 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6429,7 +6671,10 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6619,6 +6864,10 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -6761,6 +7010,10 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s63, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v28, 30
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -6872,11 +7125,11 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: v_writelane_b32 v28, s31, 31
; VI-NEXT: v_readfirstlane_b32 s86, v13
; VI-NEXT: v_readfirstlane_b32 s6, v12
-; VI-NEXT: v_readfirstlane_b32 s9, v11
-; VI-NEXT: v_readfirstlane_b32 s8, v10
+; VI-NEXT: v_readfirstlane_b32 s8, v11
+; VI-NEXT: v_readfirstlane_b32 s11, v10
; VI-NEXT: v_readfirstlane_b32 s87, v9
; VI-NEXT: v_readfirstlane_b32 s12, v8
-; VI-NEXT: v_readfirstlane_b32 s73, v7
+; VI-NEXT: v_readfirstlane_b32 s75, v7
; VI-NEXT: v_readfirstlane_b32 s77, v6
; VI-NEXT: v_readfirstlane_b32 s88, v5
; VI-NEXT: v_readfirstlane_b32 s91, v4
@@ -6893,18 +7146,18 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_lshr_b32 s85, s22, 16
; VI-NEXT: s_lshr_b32 s7, s21, 16
-; VI-NEXT: s_lshr_b32 s11, s20, 16
+; VI-NEXT: s_lshr_b32 s9, s20, 16
; VI-NEXT: s_lshr_b32 s13, s19, 16
; VI-NEXT: s_lshr_b32 s15, s18, 16
; VI-NEXT: s_lshr_b32 s10, s17, 16
-; VI-NEXT: s_lshr_b32 s75, s16, 16
+; VI-NEXT: s_lshr_b32 s73, s16, 16
; VI-NEXT: s_lshr_b32 s64, s86, 16
; VI-NEXT: s_lshr_b32 s65, s6, 16
-; VI-NEXT: s_lshr_b32 s66, s9, 16
-; VI-NEXT: s_lshr_b32 s14, s8, 16
+; VI-NEXT: s_lshr_b32 s66, s8, 16
+; VI-NEXT: s_lshr_b32 s14, s11, 16
; VI-NEXT: s_lshr_b32 s72, s87, 16
; VI-NEXT: s_lshr_b32 s74, s12, 16
-; VI-NEXT: s_lshr_b32 s76, s73, 16
+; VI-NEXT: s_lshr_b32 s76, s75, 16
; VI-NEXT: s_lshr_b32 s78, s77, 16
; VI-NEXT: s_lshr_b32 s89, s88, 16
; VI-NEXT: s_lshr_b32 s30, s91, 16
@@ -6917,7 +7170,7 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_cbranch_scc0 .LBB15_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s15, 16
@@ -6928,7 +7181,7 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s41, s10, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
@@ -6979,7 +7232,7 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s56, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s73
+; VI-NEXT: s_and_b32 s4, 0xffff, s75
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s12
@@ -6988,10 +7241,10 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s87
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s59, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s8
+; VI-NEXT: s_and_b32 s4, 0xffff, s11
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s60, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s9
+; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
@@ -7000,11 +7253,15 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s86
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s63, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s17, 0xffff
@@ -7024,7 +7281,7 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
@@ -7106,7 +7363,7 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, s77, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s75, s73, 3
+; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s75, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
@@ -7121,12 +7378,12 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, s15, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s13, s8, 3
+; VI-NEXT: s_add_i32 s13, s11, 3
; VI-NEXT: s_add_i32 s59, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s13, 0xffff
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s11, s9, 3
+; VI-NEXT: s_add_i32 s11, s8, 3
; VI-NEXT: s_add_i32 s60, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s11, 0xffff
; VI-NEXT: s_lshl_b32 s5, s66, 16
@@ -7142,6 +7399,10 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s63, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB15_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v28, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -7212,19 +7473,18 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: .LBB15_4:
; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b32 vcc_lo, s64
-; VI-NEXT: v_writelane_b32 v29, s75, 0
+; VI-NEXT: v_writelane_b32 v29, s73, 0
; VI-NEXT: s_mov_b32 vcc_hi, s65
-; VI-NEXT: s_mov_b32 s75, s73
; VI-NEXT: s_mov_b32 s73, s12
-; VI-NEXT: v_writelane_b32 v29, s25, 1
-; VI-NEXT: s_mov_b32 s25, s91
+; VI-NEXT: v_writelane_b32 v29, s91, 1
; VI-NEXT: s_mov_b32 s91, s26
; VI-NEXT: s_mov_b32 s26, s27
; VI-NEXT: s_mov_b32 s27, s88
; VI-NEXT: s_mov_b32 s88, s28
; VI-NEXT: s_mov_b32 s28, s77
; VI-NEXT: s_mov_b32 s77, s29
-; VI-NEXT: s_mov_b32 s29, s15
+; VI-NEXT: s_mov_b32 s29, s75
+; VI-NEXT: s_mov_b32 s75, s15
; VI-NEXT: s_mov_b32 s15, s87
; VI-NEXT: s_mov_b32 s87, s85
; VI-NEXT: s_mov_b32 s85, s82
@@ -7244,9 +7504,9 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s14, s66
; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s13
-; VI-NEXT: s_mov_b32 s13, s8
-; VI-NEXT: s_mov_b32 s8, s11
-; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s13, s11
+; VI-NEXT: s_mov_b32 s11, s8
+; VI-NEXT: s_mov_b32 s8, s9
; VI-NEXT: s_mov_b32 s9, s6
; VI-NEXT: s_mov_b32 s6, s7
; VI-NEXT: s_mov_b32 s7, s86
@@ -7262,9 +7522,9 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s86, s7
; VI-NEXT: s_mov_b32 s7, s6
; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_mov_b32 s9, s11
-; VI-NEXT: s_mov_b32 s11, s8
-; VI-NEXT: s_mov_b32 s8, s13
+; VI-NEXT: s_mov_b32 s9, s8
+; VI-NEXT: s_mov_b32 s8, s11
+; VI-NEXT: s_mov_b32 s11, s13
; VI-NEXT: s_mov_b32 s13, s10
; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s66, s14
@@ -7284,18 +7544,17 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s82, s85
; VI-NEXT: s_mov_b32 s85, s87
; VI-NEXT: s_mov_b32 s87, s15
-; VI-NEXT: s_mov_b32 s15, s29
+; VI-NEXT: s_mov_b32 s15, s75
+; VI-NEXT: s_mov_b32 s75, s29
; VI-NEXT: s_mov_b32 s29, s77
; VI-NEXT: s_mov_b32 s77, s28
; VI-NEXT: s_mov_b32 s28, s88
; VI-NEXT: s_mov_b32 s88, s27
; VI-NEXT: s_mov_b32 s27, s26
; VI-NEXT: s_mov_b32 s26, s91
-; VI-NEXT: s_mov_b32 s91, s25
-; VI-NEXT: v_readlane_b32 s25, v29, 1
+; VI-NEXT: v_readlane_b32 s91, v29, 1
; VI-NEXT: s_mov_b32 s12, s73
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: v_readlane_b32 s75, v29, 0
+; VI-NEXT: v_readlane_b32 s73, v29, 0
; VI-NEXT: s_mov_b32 s65, vcc_hi
; VI-NEXT: s_mov_b32 s64, vcc_lo
; VI-NEXT: s_branch .LBB15_2
@@ -7422,6 +7681,10 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v25, s61, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v26, s62, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v27, s63, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB15_5
; GFX9-NEXT: .LBB15_3:
; GFX9-NEXT: s_branch .LBB15_2
@@ -7582,6 +7845,10 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v25, s25, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v26, s26, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v27, s27, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_3:
; GFX11-NEXT: s_branch .LBB15_2
@@ -9684,6 +9951,10 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
@@ -10006,6 +10277,10 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB18_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -10133,6 +10408,10 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v25, v34, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v26, v33, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v27, v32, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -10250,6 +10529,10 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v27, v32, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v28, 0x200, v32
; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB18_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -10458,6 +10741,10 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
@@ -10610,6 +10897,10 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: v_pk_add_f16 v27, v27, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB18_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -10637,10 +10928,21 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -10669,7 +10971,10 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10734,11 +11039,23 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -10767,7 +11084,10 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10957,6 +11277,10 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB19_4
; SI-NEXT: .LBB19_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s87
@@ -11183,6 +11507,10 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB19_5
; SI-NEXT: .LBB19_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -11317,7 +11645,7 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s83, v0
; VI-NEXT: v_writelane_b32 v33, s15, 0
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s75, s28, 16
+; VI-NEXT: s_lshr_b32 s88, s28, 16
; VI-NEXT: s_lshr_b32 s90, s27, 16
; VI-NEXT: s_lshr_b32 s31, s26, 16
; VI-NEXT: s_lshr_b32 s68, s25, 16
@@ -11386,7 +11714,7 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s88, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
@@ -11411,11 +11739,10 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s62, 16
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s73, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s73, s75
; VI-NEXT: s_mov_b32 s75, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s72
@@ -11433,12 +11760,16 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s15, 16
-; VI-NEXT: s_mov_b32 s88, s62
+; VI-NEXT: s_mov_b32 s77, s62
; VI-NEXT: s_or_b32 s62, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: s_or_b32 s63, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v27, 0x200
@@ -11490,11 +11821,11 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v11, v11, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v27
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s73
+; VI-NEXT: v_mov_b32_e32 v12, s88
; VI-NEXT: v_add_f16_sdwa v12, v12, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v27
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s77
+; VI-NEXT: v_mov_b32_e32 v13, s73
; VI-NEXT: v_add_f16_sdwa v13, v13, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v27
; VI-NEXT: v_or_b32_e32 v13, v14, v13
@@ -11522,7 +11853,7 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v19, v19, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s79, v27
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v20, s77
; VI-NEXT: v_add_f16_sdwa v20, v20, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s76, v27
; VI-NEXT: v_or_b32_e32 v20, v21, v20
@@ -11558,11 +11889,14 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v28, v28, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, s6, v27
; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s88, s62
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s77, s62
+; VI-NEXT: s_mov_b32 s73, s56
; VI-NEXT: s_mov_b32 s75, s57
; VI-NEXT: s_mov_b32 s78, s58
; VI-NEXT: s_mov_b32 s15, s63
@@ -11764,6 +12098,10 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v25, s61, v27 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v26, s62, v27 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v27, s63, v27 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB19_5
; GFX9-NEXT: .LBB19_3:
; GFX9-NEXT: s_branch .LBB19_2
@@ -11924,6 +12262,10 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s25 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v26, 0x200, s26 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s27 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3:
; GFX11-NEXT: s_branch .LBB19_2
@@ -12000,6 +12342,10 @@ define <14 x i64> @bitcast_v28f32_to_v14i64(<28 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -12041,6 +12387,10 @@ define <14 x i64> @bitcast_v28f32_to_v14i64(<28 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12082,6 +12432,10 @@ define <14 x i64> @bitcast_v28f32_to_v14i64(<28 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12110,6 +12464,10 @@ define <14 x i64> @bitcast_v28f32_to_v14i64(<28 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -12212,6 +12570,10 @@ define inreg <14 x i64> @bitcast_v28f32_to_v14i64_scalar(<28 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB21_5
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -12347,6 +12709,10 @@ define inreg <14 x i64> @bitcast_v28f32_to_v14i64_scalar(<28 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB21_5
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -12482,6 +12848,10 @@ define inreg <14 x i64> @bitcast_v28f32_to_v14i64_scalar(<28 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB21_5
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -12619,6 +12989,10 @@ define inreg <14 x i64> @bitcast_v28f32_to_v14i64_scalar(<28 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_branch .LBB21_5
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -12712,6 +13086,10 @@ define <28 x float> @bitcast_v14i64_to_v28f32(<14 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -12753,6 +13131,10 @@ define <28 x float> @bitcast_v14i64_to_v28f32(<14 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12794,6 +13176,10 @@ define <28 x float> @bitcast_v14i64_to_v28f32(<14 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12843,6 +13229,10 @@ define <28 x float> @bitcast_v14i64_to_v28f32(<14 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -12915,6 +13305,10 @@ define inreg <28 x float> @bitcast_v14i64_to_v28f32_scalar(<14 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -12999,6 +13393,10 @@ define inreg <28 x float> @bitcast_v14i64_to_v28f32_scalar(<14 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB23_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -13083,6 +13481,10 @@ define inreg <28 x float> @bitcast_v14i64_to_v28f32_scalar(<14 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB23_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -13165,6 +13567,10 @@ define inreg <28 x float> @bitcast_v14i64_to_v28f32_scalar(<14 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -13239,6 +13645,10 @@ define <14 x double> @bitcast_v28f32_to_v14f64(<28 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -13280,6 +13690,10 @@ define <14 x double> @bitcast_v28f32_to_v14f64(<28 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -13321,6 +13735,10 @@ define <14 x double> @bitcast_v28f32_to_v14f64(<28 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -13349,6 +13767,10 @@ define <14 x double> @bitcast_v28f32_to_v14f64(<28 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13451,6 +13873,10 @@ define inreg <14 x double> @bitcast_v28f32_to_v14f64_scalar(<28 x float> inreg %
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB25_5
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -13586,6 +14012,10 @@ define inreg <14 x double> @bitcast_v28f32_to_v14f64_scalar(<28 x float> inreg %
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB25_5
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -13721,6 +14151,10 @@ define inreg <14 x double> @bitcast_v28f32_to_v14f64_scalar(<28 x float> inreg %
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB25_5
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -13858,6 +14292,10 @@ define inreg <14 x double> @bitcast_v28f32_to_v14f64_scalar(<28 x float> inreg %
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_branch .LBB25_5
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -13937,6 +14375,10 @@ define <28 x float> @bitcast_v14f64_to_v28f32(<14 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -13964,6 +14406,10 @@ define <28 x float> @bitcast_v14f64_to_v28f32(<14 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -13991,6 +14437,10 @@ define <28 x float> @bitcast_v14f64_to_v28f32(<14 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -14019,6 +14469,10 @@ define <28 x float> @bitcast_v14f64_to_v28f32(<14 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -14107,6 +14561,10 @@ define inreg <28 x float> @bitcast_v14f64_to_v28f32_scalar(<14 x double> inreg %
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB27_5
; SI-NEXT: .LBB27_3:
; SI-NEXT: s_branch .LBB27_2
@@ -14228,6 +14686,10 @@ define inreg <28 x float> @bitcast_v14f64_to_v28f32_scalar(<14 x double> inreg %
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB27_5
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -14349,6 +14811,10 @@ define inreg <28 x float> @bitcast_v14f64_to_v28f32_scalar(<14 x double> inreg %
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB27_5
; GFX9-NEXT: .LBB27_3:
; GFX9-NEXT: s_branch .LBB27_2
@@ -14472,6 +14938,10 @@ define inreg <28 x float> @bitcast_v14f64_to_v28f32_scalar(<14 x double> inreg %
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_branch .LBB27_5
; GFX11-NEXT: .LBB27_3:
; GFX11-NEXT: s_branch .LBB27_2
@@ -16933,6 +17403,10 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
@@ -17139,6 +17613,10 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -17266,6 +17744,10 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v25, v34, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v26, v33, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v27, v32, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -17383,6 +17865,10 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v28, 3, v32
; VI-NEXT: v_add_u16_sdwa v27, v32, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB30_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -17591,6 +18077,10 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
@@ -17742,6 +18232,10 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB30_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -17769,10 +18263,21 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -17801,7 +18306,10 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17866,11 +18374,23 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -17899,7 +18419,10 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -18089,6 +18612,10 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB31_3
; SI-NEXT: .LBB31_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -18231,6 +18758,10 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s63, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB31_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v28, 30
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -18342,11 +18873,11 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: v_writelane_b32 v28, s31, 31
; VI-NEXT: v_readfirstlane_b32 s86, v13
; VI-NEXT: v_readfirstlane_b32 s6, v12
-; VI-NEXT: v_readfirstlane_b32 s9, v11
-; VI-NEXT: v_readfirstlane_b32 s8, v10
+; VI-NEXT: v_readfirstlane_b32 s8, v11
+; VI-NEXT: v_readfirstlane_b32 s11, v10
; VI-NEXT: v_readfirstlane_b32 s87, v9
; VI-NEXT: v_readfirstlane_b32 s12, v8
-; VI-NEXT: v_readfirstlane_b32 s73, v7
+; VI-NEXT: v_readfirstlane_b32 s75, v7
; VI-NEXT: v_readfirstlane_b32 s77, v6
; VI-NEXT: v_readfirstlane_b32 s88, v5
; VI-NEXT: v_readfirstlane_b32 s91, v4
@@ -18363,18 +18894,18 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_lshr_b32 s85, s22, 16
; VI-NEXT: s_lshr_b32 s7, s21, 16
-; VI-NEXT: s_lshr_b32 s11, s20, 16
+; VI-NEXT: s_lshr_b32 s9, s20, 16
; VI-NEXT: s_lshr_b32 s13, s19, 16
; VI-NEXT: s_lshr_b32 s15, s18, 16
; VI-NEXT: s_lshr_b32 s10, s17, 16
-; VI-NEXT: s_lshr_b32 s75, s16, 16
+; VI-NEXT: s_lshr_b32 s73, s16, 16
; VI-NEXT: s_lshr_b32 s64, s86, 16
; VI-NEXT: s_lshr_b32 s65, s6, 16
-; VI-NEXT: s_lshr_b32 s66, s9, 16
-; VI-NEXT: s_lshr_b32 s14, s8, 16
+; VI-NEXT: s_lshr_b32 s66, s8, 16
+; VI-NEXT: s_lshr_b32 s14, s11, 16
; VI-NEXT: s_lshr_b32 s72, s87, 16
; VI-NEXT: s_lshr_b32 s74, s12, 16
-; VI-NEXT: s_lshr_b32 s76, s73, 16
+; VI-NEXT: s_lshr_b32 s76, s75, 16
; VI-NEXT: s_lshr_b32 s78, s77, 16
; VI-NEXT: s_lshr_b32 s89, s88, 16
; VI-NEXT: s_lshr_b32 s30, s91, 16
@@ -18387,7 +18918,7 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_cbranch_scc0 .LBB31_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s15, 16
@@ -18398,7 +18929,7 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s41, s10, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
@@ -18449,7 +18980,7 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s56, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s73
+; VI-NEXT: s_and_b32 s4, 0xffff, s75
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s12
@@ -18458,10 +18989,10 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s87
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s59, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s8
+; VI-NEXT: s_and_b32 s4, 0xffff, s11
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s60, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s9
+; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
@@ -18470,11 +19001,15 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s86
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s63, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB31_3
; VI-NEXT: .LBB31_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s17, 0xffff
@@ -18494,7 +19029,7 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
@@ -18576,7 +19111,7 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, s77, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s75, s73, 3
+; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s75, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
@@ -18591,12 +19126,12 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, s15, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s13, s8, 3
+; VI-NEXT: s_add_i32 s13, s11, 3
; VI-NEXT: s_add_i32 s59, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s13, 0xffff
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s11, s9, 3
+; VI-NEXT: s_add_i32 s11, s8, 3
; VI-NEXT: s_add_i32 s60, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s11, 0xffff
; VI-NEXT: s_lshl_b32 s5, s66, 16
@@ -18612,6 +19147,10 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s63, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB31_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v28, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -18682,19 +19221,18 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: .LBB31_4:
; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b32 vcc_lo, s64
-; VI-NEXT: v_writelane_b32 v29, s75, 0
+; VI-NEXT: v_writelane_b32 v29, s73, 0
; VI-NEXT: s_mov_b32 vcc_hi, s65
-; VI-NEXT: s_mov_b32 s75, s73
; VI-NEXT: s_mov_b32 s73, s12
-; VI-NEXT: v_writelane_b32 v29, s25, 1
-; VI-NEXT: s_mov_b32 s25, s91
+; VI-NEXT: v_writelane_b32 v29, s91, 1
; VI-NEXT: s_mov_b32 s91, s26
; VI-NEXT: s_mov_b32 s26, s27
; VI-NEXT: s_mov_b32 s27, s88
; VI-NEXT: s_mov_b32 s88, s28
; VI-NEXT: s_mov_b32 s28, s77
; VI-NEXT: s_mov_b32 s77, s29
-; VI-NEXT: s_mov_b32 s29, s15
+; VI-NEXT: s_mov_b32 s29, s75
+; VI-NEXT: s_mov_b32 s75, s15
; VI-NEXT: s_mov_b32 s15, s87
; VI-NEXT: s_mov_b32 s87, s85
; VI-NEXT: s_mov_b32 s85, s82
@@ -18714,9 +19252,9 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s14, s66
; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s13
-; VI-NEXT: s_mov_b32 s13, s8
-; VI-NEXT: s_mov_b32 s8, s11
-; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s13, s11
+; VI-NEXT: s_mov_b32 s11, s8
+; VI-NEXT: s_mov_b32 s8, s9
; VI-NEXT: s_mov_b32 s9, s6
; VI-NEXT: s_mov_b32 s6, s7
; VI-NEXT: s_mov_b32 s7, s86
@@ -18732,9 +19270,9 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s86, s7
; VI-NEXT: s_mov_b32 s7, s6
; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_mov_b32 s9, s11
-; VI-NEXT: s_mov_b32 s11, s8
-; VI-NEXT: s_mov_b32 s8, s13
+; VI-NEXT: s_mov_b32 s9, s8
+; VI-NEXT: s_mov_b32 s8, s11
+; VI-NEXT: s_mov_b32 s11, s13
; VI-NEXT: s_mov_b32 s13, s10
; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s66, s14
@@ -18754,18 +19292,17 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s82, s85
; VI-NEXT: s_mov_b32 s85, s87
; VI-NEXT: s_mov_b32 s87, s15
-; VI-NEXT: s_mov_b32 s15, s29
+; VI-NEXT: s_mov_b32 s15, s75
+; VI-NEXT: s_mov_b32 s75, s29
; VI-NEXT: s_mov_b32 s29, s77
; VI-NEXT: s_mov_b32 s77, s28
; VI-NEXT: s_mov_b32 s28, s88
; VI-NEXT: s_mov_b32 s88, s27
; VI-NEXT: s_mov_b32 s27, s26
; VI-NEXT: s_mov_b32 s26, s91
-; VI-NEXT: s_mov_b32 s91, s25
-; VI-NEXT: v_readlane_b32 s25, v29, 1
+; VI-NEXT: v_readlane_b32 s91, v29, 1
; VI-NEXT: s_mov_b32 s12, s73
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: v_readlane_b32 s75, v29, 0
+; VI-NEXT: v_readlane_b32 s73, v29, 0
; VI-NEXT: s_mov_b32 s65, vcc_hi
; VI-NEXT: s_mov_b32 s64, vcc_lo
; VI-NEXT: s_branch .LBB31_2
@@ -18892,6 +19429,10 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v25, s61, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v26, s62, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v27, s63, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB31_5
; GFX9-NEXT: .LBB31_3:
; GFX9-NEXT: s_branch .LBB31_2
@@ -19052,6 +19593,10 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v25, s25, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v26, s26, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v27, s27, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_3:
; GFX11-NEXT: s_branch .LBB31_2
@@ -21516,6 +22061,10 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
@@ -21838,6 +22387,10 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -21965,6 +22518,10 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v25, v34, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v26, v33, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v27, v32, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -22082,6 +22639,10 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v27, v32, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v28, 0x200, v32
; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -22290,6 +22851,10 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
@@ -22442,6 +23007,10 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: v_pk_add_f16 v27, v27, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB34_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -22469,10 +23038,21 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -22501,7 +23081,10 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -22566,11 +23149,23 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -22599,7 +23194,10 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -22789,6 +23387,10 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB35_4
; SI-NEXT: .LBB35_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s87
@@ -23015,6 +23617,10 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB35_5
; SI-NEXT: .LBB35_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -23149,7 +23755,7 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s83, v0
; VI-NEXT: v_writelane_b32 v33, s15, 0
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s75, s28, 16
+; VI-NEXT: s_lshr_b32 s88, s28, 16
; VI-NEXT: s_lshr_b32 s90, s27, 16
; VI-NEXT: s_lshr_b32 s31, s26, 16
; VI-NEXT: s_lshr_b32 s68, s25, 16
@@ -23218,7 +23824,7 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s88, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
@@ -23243,11 +23849,10 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s62, 16
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s73, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s73, s75
; VI-NEXT: s_mov_b32 s75, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s72
@@ -23265,12 +23870,16 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s15, 16
-; VI-NEXT: s_mov_b32 s88, s62
+; VI-NEXT: s_mov_b32 s77, s62
; VI-NEXT: s_or_b32 s62, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: s_or_b32 s63, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v27, 0x200
@@ -23322,11 +23931,11 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v11, v11, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v27
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s73
+; VI-NEXT: v_mov_b32_e32 v12, s88
; VI-NEXT: v_add_f16_sdwa v12, v12, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v27
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s77
+; VI-NEXT: v_mov_b32_e32 v13, s73
; VI-NEXT: v_add_f16_sdwa v13, v13, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v27
; VI-NEXT: v_or_b32_e32 v13, v14, v13
@@ -23354,7 +23963,7 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v19, v19, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s79, v27
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v20, s77
; VI-NEXT: v_add_f16_sdwa v20, v20, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s76, v27
; VI-NEXT: v_or_b32_e32 v20, v21, v20
@@ -23390,11 +23999,14 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v28, v28, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, s6, v27
; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s88, s62
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s77, s62
+; VI-NEXT: s_mov_b32 s73, s56
; VI-NEXT: s_mov_b32 s75, s57
; VI-NEXT: s_mov_b32 s78, s58
; VI-NEXT: s_mov_b32 s15, s63
@@ -23596,6 +24208,10 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v25, s61, v27 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v26, s62, v27 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v27, s63, v27 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB35_5
; GFX9-NEXT: .LBB35_3:
; GFX9-NEXT: s_branch .LBB35_2
@@ -23756,6 +24372,10 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s25 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v26, 0x200, s26 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s27 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3:
; GFX11-NEXT: s_branch .LBB35_2
@@ -23832,6 +24452,10 @@ define <14 x double> @bitcast_v14i64_to_v14f64(<14 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v25, vcc, 0, v25, vcc
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_addc_u32_e32 v27, vcc, 0, v27, vcc
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -23873,6 +24497,10 @@ define <14 x double> @bitcast_v14i64_to_v14f64(<14 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v25, vcc, 0, v25, vcc
; VI-NEXT: v_add_u32_e32 v26, vcc, 3, v26
; VI-NEXT: v_addc_u32_e32 v27, vcc, 0, v27, vcc
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -23914,6 +24542,10 @@ define <14 x double> @bitcast_v14i64_to_v14f64(<14 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v25, vcc
; GFX9-NEXT: v_add_co_u32_e32 v26, vcc, 3, v26
; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, 0, v27, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -23963,6 +24595,10 @@ define <14 x double> @bitcast_v14i64_to_v14f64(<14 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_ci_u32_e64 v25, null, 0, v25, vcc_lo
; GFX11-NEXT: v_add_co_u32 v26, vcc_lo, v26, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v27, null, 0, v27, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -24035,6 +24671,10 @@ define inreg <14 x double> @bitcast_v14i64_to_v14f64_scalar(<14 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB37_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -24119,6 +24759,10 @@ define inreg <14 x double> @bitcast_v14i64_to_v14f64_scalar(<14 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -24203,6 +24847,10 @@ define inreg <14 x double> @bitcast_v14i64_to_v14f64_scalar(<14 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -24285,6 +24933,10 @@ define inreg <14 x double> @bitcast_v14i64_to_v14f64_scalar(<14 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
+; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -24344,6 +24996,10 @@ define <14 x i64> @bitcast_v14f64_to_v14i64(<14 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; SI-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; SI-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -24371,6 +25027,10 @@ define <14 x i64> @bitcast_v14f64_to_v14i64(<14 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; VI-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; VI-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -24398,6 +25058,10 @@ define <14 x i64> @bitcast_v14f64_to_v14i64(<14 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; GFX9-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -24426,6 +25090,10 @@ define <14 x i64> @bitcast_v14f64_to_v14i64(<14 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; GFX11-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -24514,6 +25182,10 @@ define inreg <14 x i64> @bitcast_v14f64_to_v14i64_scalar(<14 x double> inreg %a,
; SI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; SI-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
; SI-NEXT: v_add_f64 v[26:27], s[62:63], 1.0
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB39_5
; SI-NEXT: .LBB39_3:
; SI-NEXT: s_branch .LBB39_2
@@ -24635,6 +25307,10 @@ define inreg <14 x i64> @bitcast_v14f64_to_v14i64_scalar(<14 x double> inreg %a,
; VI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; VI-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
; VI-NEXT: v_add_f64 v[26:27], s[62:63], 1.0
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB39_5
; VI-NEXT: .LBB39_3:
; VI-NEXT: s_branch .LBB39_2
@@ -24756,6 +25432,10 @@ define inreg <14 x i64> @bitcast_v14f64_to_v14i64_scalar(<14 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX9-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
; GFX9-NEXT: v_add_f64 v[26:27], s[62:63], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB39_5
; GFX9-NEXT: .LBB39_3:
; GFX9-NEXT: s_branch .LBB39_2
@@ -24879,6 +25559,10 @@ define inreg <14 x i64> @bitcast_v14f64_to_v14i64_scalar(<14 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX11-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
; GFX11-NEXT: v_add_f64 v[26:27], s[62:63], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_branch .LBB39_5
; GFX11-NEXT: .LBB39_3:
; GFX11-NEXT: s_branch .LBB39_2
@@ -26992,6 +27676,10 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
@@ -27198,6 +27886,10 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -27325,6 +28017,10 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v25, v34, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v26, v33, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v27, v32, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -27442,6 +28138,10 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v28, 3, v32
; VI-NEXT: v_add_u16_sdwa v27, v32, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -27650,6 +28350,10 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
@@ -27801,6 +28505,10 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB42_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -27828,10 +28536,21 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -27860,7 +28579,10 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -27925,11 +28647,23 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -27958,7 +28692,10 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -28148,6 +28885,10 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -28290,6 +29031,10 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s63, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v28, 30
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -28401,11 +29146,11 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: v_writelane_b32 v28, s31, 31
; VI-NEXT: v_readfirstlane_b32 s86, v13
; VI-NEXT: v_readfirstlane_b32 s6, v12
-; VI-NEXT: v_readfirstlane_b32 s9, v11
-; VI-NEXT: v_readfirstlane_b32 s8, v10
+; VI-NEXT: v_readfirstlane_b32 s8, v11
+; VI-NEXT: v_readfirstlane_b32 s11, v10
; VI-NEXT: v_readfirstlane_b32 s87, v9
; VI-NEXT: v_readfirstlane_b32 s12, v8
-; VI-NEXT: v_readfirstlane_b32 s73, v7
+; VI-NEXT: v_readfirstlane_b32 s75, v7
; VI-NEXT: v_readfirstlane_b32 s77, v6
; VI-NEXT: v_readfirstlane_b32 s88, v5
; VI-NEXT: v_readfirstlane_b32 s91, v4
@@ -28422,18 +29167,18 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_lshr_b32 s85, s22, 16
; VI-NEXT: s_lshr_b32 s7, s21, 16
-; VI-NEXT: s_lshr_b32 s11, s20, 16
+; VI-NEXT: s_lshr_b32 s9, s20, 16
; VI-NEXT: s_lshr_b32 s13, s19, 16
; VI-NEXT: s_lshr_b32 s15, s18, 16
; VI-NEXT: s_lshr_b32 s10, s17, 16
-; VI-NEXT: s_lshr_b32 s75, s16, 16
+; VI-NEXT: s_lshr_b32 s73, s16, 16
; VI-NEXT: s_lshr_b32 s64, s86, 16
; VI-NEXT: s_lshr_b32 s65, s6, 16
-; VI-NEXT: s_lshr_b32 s66, s9, 16
-; VI-NEXT: s_lshr_b32 s14, s8, 16
+; VI-NEXT: s_lshr_b32 s66, s8, 16
+; VI-NEXT: s_lshr_b32 s14, s11, 16
; VI-NEXT: s_lshr_b32 s72, s87, 16
; VI-NEXT: s_lshr_b32 s74, s12, 16
-; VI-NEXT: s_lshr_b32 s76, s73, 16
+; VI-NEXT: s_lshr_b32 s76, s75, 16
; VI-NEXT: s_lshr_b32 s78, s77, 16
; VI-NEXT: s_lshr_b32 s89, s88, 16
; VI-NEXT: s_lshr_b32 s30, s91, 16
@@ -28446,7 +29191,7 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_cbranch_scc0 .LBB43_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s15, 16
@@ -28457,7 +29202,7 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s41, s10, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
@@ -28508,7 +29253,7 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s56, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s73
+; VI-NEXT: s_and_b32 s4, 0xffff, s75
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s12
@@ -28517,10 +29262,10 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s87
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s59, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s8
+; VI-NEXT: s_and_b32 s4, 0xffff, s11
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s60, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s9
+; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
@@ -28529,11 +29274,15 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s86
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s63, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s17, 0xffff
@@ -28553,7 +29302,7 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
@@ -28635,7 +29384,7 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, s77, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s75, s73, 3
+; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s75, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
@@ -28650,12 +29399,12 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, s15, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s13, s8, 3
+; VI-NEXT: s_add_i32 s13, s11, 3
; VI-NEXT: s_add_i32 s59, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s13, 0xffff
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s11, s9, 3
+; VI-NEXT: s_add_i32 s11, s8, 3
; VI-NEXT: s_add_i32 s60, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s11, 0xffff
; VI-NEXT: s_lshl_b32 s5, s66, 16
@@ -28671,6 +29420,10 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s63, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v28, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -28741,19 +29494,18 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: .LBB43_4:
; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b32 vcc_lo, s64
-; VI-NEXT: v_writelane_b32 v29, s75, 0
+; VI-NEXT: v_writelane_b32 v29, s73, 0
; VI-NEXT: s_mov_b32 vcc_hi, s65
-; VI-NEXT: s_mov_b32 s75, s73
; VI-NEXT: s_mov_b32 s73, s12
-; VI-NEXT: v_writelane_b32 v29, s25, 1
-; VI-NEXT: s_mov_b32 s25, s91
+; VI-NEXT: v_writelane_b32 v29, s91, 1
; VI-NEXT: s_mov_b32 s91, s26
; VI-NEXT: s_mov_b32 s26, s27
; VI-NEXT: s_mov_b32 s27, s88
; VI-NEXT: s_mov_b32 s88, s28
; VI-NEXT: s_mov_b32 s28, s77
; VI-NEXT: s_mov_b32 s77, s29
-; VI-NEXT: s_mov_b32 s29, s15
+; VI-NEXT: s_mov_b32 s29, s75
+; VI-NEXT: s_mov_b32 s75, s15
; VI-NEXT: s_mov_b32 s15, s87
; VI-NEXT: s_mov_b32 s87, s85
; VI-NEXT: s_mov_b32 s85, s82
@@ -28773,9 +29525,9 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s14, s66
; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s13
-; VI-NEXT: s_mov_b32 s13, s8
-; VI-NEXT: s_mov_b32 s8, s11
-; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s13, s11
+; VI-NEXT: s_mov_b32 s11, s8
+; VI-NEXT: s_mov_b32 s8, s9
; VI-NEXT: s_mov_b32 s9, s6
; VI-NEXT: s_mov_b32 s6, s7
; VI-NEXT: s_mov_b32 s7, s86
@@ -28791,9 +29543,9 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s86, s7
; VI-NEXT: s_mov_b32 s7, s6
; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_mov_b32 s9, s11
-; VI-NEXT: s_mov_b32 s11, s8
-; VI-NEXT: s_mov_b32 s8, s13
+; VI-NEXT: s_mov_b32 s9, s8
+; VI-NEXT: s_mov_b32 s8, s11
+; VI-NEXT: s_mov_b32 s11, s13
; VI-NEXT: s_mov_b32 s13, s10
; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s66, s14
@@ -28813,18 +29565,17 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; VI-NEXT: s_mov_b32 s82, s85
; VI-NEXT: s_mov_b32 s85, s87
; VI-NEXT: s_mov_b32 s87, s15
-; VI-NEXT: s_mov_b32 s15, s29
+; VI-NEXT: s_mov_b32 s15, s75
+; VI-NEXT: s_mov_b32 s75, s29
; VI-NEXT: s_mov_b32 s29, s77
; VI-NEXT: s_mov_b32 s77, s28
; VI-NEXT: s_mov_b32 s28, s88
; VI-NEXT: s_mov_b32 s88, s27
; VI-NEXT: s_mov_b32 s27, s26
; VI-NEXT: s_mov_b32 s26, s91
-; VI-NEXT: s_mov_b32 s91, s25
-; VI-NEXT: v_readlane_b32 s25, v29, 1
+; VI-NEXT: v_readlane_b32 s91, v29, 1
; VI-NEXT: s_mov_b32 s12, s73
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: v_readlane_b32 s75, v29, 0
+; VI-NEXT: v_readlane_b32 s73, v29, 0
; VI-NEXT: s_mov_b32 s65, vcc_hi
; VI-NEXT: s_mov_b32 s64, vcc_lo
; VI-NEXT: s_branch .LBB43_2
@@ -28951,6 +29702,10 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v25, s61, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v26, s62, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v27, s63, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB43_5
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -29111,6 +29866,10 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v25, s25, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v26, s26, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v27, s27, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -31227,6 +31986,10 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
@@ -31549,6 +32312,10 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -31676,6 +32443,10 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v25, v34, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v26, v33, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v27, v32, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -31793,6 +32564,10 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v27, v32, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v28, 0x200, v32
; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -32001,6 +32776,10 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
@@ -32153,6 +32932,10 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: v_pk_add_f16 v27, v27, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB46_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -32180,10 +32963,21 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -32212,7 +33006,10 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -32277,11 +33074,23 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -32310,7 +33119,10 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -32500,6 +33312,10 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s87
@@ -32726,6 +33542,10 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -32860,7 +33680,7 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s83, v0
; VI-NEXT: v_writelane_b32 v33, s15, 0
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s75, s28, 16
+; VI-NEXT: s_lshr_b32 s88, s28, 16
; VI-NEXT: s_lshr_b32 s90, s27, 16
; VI-NEXT: s_lshr_b32 s31, s26, 16
; VI-NEXT: s_lshr_b32 s68, s25, 16
@@ -32929,7 +33749,7 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s88, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
@@ -32954,11 +33774,10 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s62, 16
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s73, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s73, s75
; VI-NEXT: s_mov_b32 s75, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s72
@@ -32976,12 +33795,16 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s15, 16
-; VI-NEXT: s_mov_b32 s88, s62
+; VI-NEXT: s_mov_b32 s77, s62
; VI-NEXT: s_or_b32 s62, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: s_or_b32 s63, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v27, 0x200
@@ -33033,11 +33856,11 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v11, v11, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v27
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s73
+; VI-NEXT: v_mov_b32_e32 v12, s88
; VI-NEXT: v_add_f16_sdwa v12, v12, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v27
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s77
+; VI-NEXT: v_mov_b32_e32 v13, s73
; VI-NEXT: v_add_f16_sdwa v13, v13, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v27
; VI-NEXT: v_or_b32_e32 v13, v14, v13
@@ -33065,7 +33888,7 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v19, v19, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s79, v27
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v20, s77
; VI-NEXT: v_add_f16_sdwa v20, v20, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s76, v27
; VI-NEXT: v_or_b32_e32 v20, v21, v20
@@ -33101,11 +33924,14 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v28, v28, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, s6, v27
; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s88, s62
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s77, s62
+; VI-NEXT: s_mov_b32 s73, s56
; VI-NEXT: s_mov_b32 s75, s57
; VI-NEXT: s_mov_b32 s78, s58
; VI-NEXT: s_mov_b32 s15, s63
@@ -33307,6 +34133,10 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v25, s61, v27 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v26, s62, v27 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v27, s63, v27 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB47_5
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -33467,6 +34297,10 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s25 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v26, 0x200, s26 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s27 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -35806,6 +36640,10 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
@@ -36012,6 +36850,10 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -36139,6 +36981,10 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v25, v34, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v26, v33, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v27, v32, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -36256,6 +37102,10 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v28, 3, v32
; VI-NEXT: v_add_u16_sdwa v27, v32, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -36464,6 +37314,10 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
@@ -36615,6 +37469,10 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB50_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -36642,10 +37500,21 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -36674,7 +37543,10 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -36739,11 +37611,23 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -36772,7 +37656,10 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -36962,6 +37849,10 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -37104,6 +37995,10 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s63, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v28, 30
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -37215,11 +38110,11 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: v_writelane_b32 v28, s31, 31
; VI-NEXT: v_readfirstlane_b32 s86, v13
; VI-NEXT: v_readfirstlane_b32 s6, v12
-; VI-NEXT: v_readfirstlane_b32 s9, v11
-; VI-NEXT: v_readfirstlane_b32 s8, v10
+; VI-NEXT: v_readfirstlane_b32 s8, v11
+; VI-NEXT: v_readfirstlane_b32 s11, v10
; VI-NEXT: v_readfirstlane_b32 s87, v9
; VI-NEXT: v_readfirstlane_b32 s12, v8
-; VI-NEXT: v_readfirstlane_b32 s73, v7
+; VI-NEXT: v_readfirstlane_b32 s75, v7
; VI-NEXT: v_readfirstlane_b32 s77, v6
; VI-NEXT: v_readfirstlane_b32 s88, v5
; VI-NEXT: v_readfirstlane_b32 s91, v4
@@ -37236,18 +38131,18 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshr_b32 s82, s23, 16
; VI-NEXT: s_lshr_b32 s85, s22, 16
; VI-NEXT: s_lshr_b32 s7, s21, 16
-; VI-NEXT: s_lshr_b32 s11, s20, 16
+; VI-NEXT: s_lshr_b32 s9, s20, 16
; VI-NEXT: s_lshr_b32 s13, s19, 16
; VI-NEXT: s_lshr_b32 s15, s18, 16
; VI-NEXT: s_lshr_b32 s10, s17, 16
-; VI-NEXT: s_lshr_b32 s75, s16, 16
+; VI-NEXT: s_lshr_b32 s73, s16, 16
; VI-NEXT: s_lshr_b32 s64, s86, 16
; VI-NEXT: s_lshr_b32 s65, s6, 16
-; VI-NEXT: s_lshr_b32 s66, s9, 16
-; VI-NEXT: s_lshr_b32 s14, s8, 16
+; VI-NEXT: s_lshr_b32 s66, s8, 16
+; VI-NEXT: s_lshr_b32 s14, s11, 16
; VI-NEXT: s_lshr_b32 s72, s87, 16
; VI-NEXT: s_lshr_b32 s74, s12, 16
-; VI-NEXT: s_lshr_b32 s76, s73, 16
+; VI-NEXT: s_lshr_b32 s76, s75, 16
; VI-NEXT: s_lshr_b32 s78, s77, 16
; VI-NEXT: s_lshr_b32 s89, s88, 16
; VI-NEXT: s_lshr_b32 s30, s91, 16
@@ -37260,7 +38155,7 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s15, 16
@@ -37271,7 +38166,7 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s41, s10, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s37, s40, s41
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
@@ -37322,7 +38217,7 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s56, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s73
+; VI-NEXT: s_and_b32 s4, 0xffff, s75
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s12
@@ -37331,10 +38226,10 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s87
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s59, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s8
+; VI-NEXT: s_and_b32 s4, 0xffff, s11
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s60, s4, s5
-; VI-NEXT: s_and_b32 s4, 0xffff, s9
+; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
@@ -37343,11 +38238,15 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s86
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s63, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_and_b32 s5, s17, 0xffff
@@ -37367,7 +38266,7 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
-; VI-NEXT: s_lshl_b32 s5, s11, 16
+; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
@@ -37449,7 +38348,7 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, s77, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s75, s73, 3
+; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s75, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
@@ -37464,12 +38363,12 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, s15, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s13, s8, 3
+; VI-NEXT: s_add_i32 s13, s11, 3
; VI-NEXT: s_add_i32 s59, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s13, 0xffff
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s4, s5, s4
-; VI-NEXT: s_add_i32 s11, s9, 3
+; VI-NEXT: s_add_i32 s11, s8, 3
; VI-NEXT: s_add_i32 s60, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s11, 0xffff
; VI-NEXT: s_lshl_b32 s5, s66, 16
@@ -37485,6 +38384,10 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s63, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v28, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -37555,19 +38458,18 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: .LBB51_4:
; VI-NEXT: ; implicit-def: $vgpr29 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b32 vcc_lo, s64
-; VI-NEXT: v_writelane_b32 v29, s75, 0
+; VI-NEXT: v_writelane_b32 v29, s73, 0
; VI-NEXT: s_mov_b32 vcc_hi, s65
-; VI-NEXT: s_mov_b32 s75, s73
; VI-NEXT: s_mov_b32 s73, s12
-; VI-NEXT: v_writelane_b32 v29, s25, 1
-; VI-NEXT: s_mov_b32 s25, s91
+; VI-NEXT: v_writelane_b32 v29, s91, 1
; VI-NEXT: s_mov_b32 s91, s26
; VI-NEXT: s_mov_b32 s26, s27
; VI-NEXT: s_mov_b32 s27, s88
; VI-NEXT: s_mov_b32 s88, s28
; VI-NEXT: s_mov_b32 s28, s77
; VI-NEXT: s_mov_b32 s77, s29
-; VI-NEXT: s_mov_b32 s29, s15
+; VI-NEXT: s_mov_b32 s29, s75
+; VI-NEXT: s_mov_b32 s75, s15
; VI-NEXT: s_mov_b32 s15, s87
; VI-NEXT: s_mov_b32 s87, s85
; VI-NEXT: s_mov_b32 s85, s82
@@ -37587,9 +38489,9 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s14, s66
; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s13
-; VI-NEXT: s_mov_b32 s13, s8
-; VI-NEXT: s_mov_b32 s8, s11
-; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_mov_b32 s13, s11
+; VI-NEXT: s_mov_b32 s11, s8
+; VI-NEXT: s_mov_b32 s8, s9
; VI-NEXT: s_mov_b32 s9, s6
; VI-NEXT: s_mov_b32 s6, s7
; VI-NEXT: s_mov_b32 s7, s86
@@ -37605,9 +38507,9 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s86, s7
; VI-NEXT: s_mov_b32 s7, s6
; VI-NEXT: s_mov_b32 s6, s9
-; VI-NEXT: s_mov_b32 s9, s11
-; VI-NEXT: s_mov_b32 s11, s8
-; VI-NEXT: s_mov_b32 s8, s13
+; VI-NEXT: s_mov_b32 s9, s8
+; VI-NEXT: s_mov_b32 s8, s11
+; VI-NEXT: s_mov_b32 s11, s13
; VI-NEXT: s_mov_b32 s13, s10
; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s66, s14
@@ -37627,18 +38529,17 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; VI-NEXT: s_mov_b32 s82, s85
; VI-NEXT: s_mov_b32 s85, s87
; VI-NEXT: s_mov_b32 s87, s15
-; VI-NEXT: s_mov_b32 s15, s29
+; VI-NEXT: s_mov_b32 s15, s75
+; VI-NEXT: s_mov_b32 s75, s29
; VI-NEXT: s_mov_b32 s29, s77
; VI-NEXT: s_mov_b32 s77, s28
; VI-NEXT: s_mov_b32 s28, s88
; VI-NEXT: s_mov_b32 s88, s27
; VI-NEXT: s_mov_b32 s27, s26
; VI-NEXT: s_mov_b32 s26, s91
-; VI-NEXT: s_mov_b32 s91, s25
-; VI-NEXT: v_readlane_b32 s25, v29, 1
+; VI-NEXT: v_readlane_b32 s91, v29, 1
; VI-NEXT: s_mov_b32 s12, s73
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: v_readlane_b32 s75, v29, 0
+; VI-NEXT: v_readlane_b32 s73, v29, 0
; VI-NEXT: s_mov_b32 s65, vcc_hi
; VI-NEXT: s_mov_b32 s64, vcc_lo
; VI-NEXT: s_branch .LBB51_2
@@ -37765,6 +38666,10 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v25, s61, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v26, s62, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v27, s63, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB51_5
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -37925,6 +38830,10 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v25, s25, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v26, s26, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v27, s27, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -40284,6 +41193,10 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
@@ -40606,6 +41519,10 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -40733,6 +41650,10 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v25, v34, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v26, v33, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v27, v32, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -40850,6 +41771,10 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v27, v32, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v28, 0x200, v32
; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -41058,6 +41983,10 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; kill: killed $vgpr28
@@ -41210,6 +42139,10 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s6
; GFX9-NEXT: v_pk_add_f16 v27, v27, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: .LBB54_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -41237,10 +42170,21 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -41269,7 +42213,10 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -41334,11 +42281,23 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v30, v26, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v29, v27, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -41367,7 +42326,10 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -41557,6 +42519,10 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s63, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr64
+; SI-NEXT: ; implicit-def: $sgpr65
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s87
@@ -41783,6 +42749,10 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; SI-NEXT: v_or_b32_e32 v27, v29, v27
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -41917,7 +42887,7 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: v_readfirstlane_b32 s83, v0
; VI-NEXT: v_writelane_b32 v33, s15, 0
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s75, s28, 16
+; VI-NEXT: s_lshr_b32 s88, s28, 16
; VI-NEXT: s_lshr_b32 s90, s27, 16
; VI-NEXT: s_lshr_b32 s31, s26, 16
; VI-NEXT: s_lshr_b32 s68, s25, 16
@@ -41986,7 +42956,7 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s75, 16
+; VI-NEXT: s_lshl_b32 s5, s88, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
@@ -42011,11 +42981,10 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s62, 16
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s73, s56
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s73, s75
; VI-NEXT: s_mov_b32 s75, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s72
@@ -42033,12 +43002,16 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: s_or_b32 s61, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s15, 16
-; VI-NEXT: s_mov_b32 s88, s62
+; VI-NEXT: s_mov_b32 s77, s62
; VI-NEXT: s_or_b32 s62, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_mov_b32 s15, s63
; VI-NEXT: s_or_b32 s63, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr64
+; VI-NEXT: ; implicit-def: $sgpr65
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v27, 0x200
@@ -42090,11 +43063,11 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v11, v11, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v27
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s73
+; VI-NEXT: v_mov_b32_e32 v12, s88
; VI-NEXT: v_add_f16_sdwa v12, v12, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v27
; VI-NEXT: v_or_b32_e32 v12, v13, v12
-; VI-NEXT: v_mov_b32_e32 v13, s77
+; VI-NEXT: v_mov_b32_e32 v13, s73
; VI-NEXT: v_add_f16_sdwa v13, v13, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v27
; VI-NEXT: v_or_b32_e32 v13, v14, v13
@@ -42122,7 +43095,7 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v19, v19, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s79, v27
; VI-NEXT: v_or_b32_e32 v19, v20, v19
-; VI-NEXT: v_mov_b32_e32 v20, s88
+; VI-NEXT: v_mov_b32_e32 v20, s77
; VI-NEXT: v_add_f16_sdwa v20, v20, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s76, v27
; VI-NEXT: v_or_b32_e32 v20, v21, v20
@@ -42158,11 +43131,14 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v28, v28, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, s6, v27
; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
+; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
-; VI-NEXT: s_mov_b32 s73, s75
-; VI-NEXT: s_mov_b32 s88, s62
-; VI-NEXT: s_mov_b32 s77, s56
+; VI-NEXT: s_mov_b32 s77, s62
+; VI-NEXT: s_mov_b32 s73, s56
; VI-NEXT: s_mov_b32 s75, s57
; VI-NEXT: s_mov_b32 s78, s58
; VI-NEXT: s_mov_b32 s15, s63
@@ -42364,6 +43340,10 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; GFX9-NEXT: v_pk_add_f16 v25, s61, v27 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v26, s62, v27 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v27, s63, v27 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
+; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: s_branch .LBB55_5
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -42524,6 +43504,10 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s25 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v26, 0x200, s26 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s27 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
+; GFX11-NEXT: ; implicit-def: $vgpr28
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
index 47a80c7161aae..3943d7be61256 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
@@ -46,6 +46,8 @@ define <30 x float> @bitcast_v30i32_to_v30f32(<30 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -89,6 +91,8 @@ define <30 x float> @bitcast_v30i32_to_v30f32(<30 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -132,6 +136,8 @@ define <30 x float> @bitcast_v30i32_to_v30f32(<30 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -176,6 +182,8 @@ define <30 x float> @bitcast_v30i32_to_v30f32(<30 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -252,6 +260,8 @@ define inreg <30 x float> @bitcast_v30i32_to_v30f32_scalar(<30 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB1_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -342,6 +352,8 @@ define inreg <30 x float> @bitcast_v30i32_to_v30f32_scalar(<30 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB1_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -432,6 +444,8 @@ define inreg <30 x float> @bitcast_v30i32_to_v30f32_scalar(<30 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB1_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -520,6 +534,8 @@ define inreg <30 x float> @bitcast_v30i32_to_v30f32_scalar(<30 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr40
+; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: .LBB1_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -597,6 +613,8 @@ define <30 x i32> @bitcast_v30f32_to_v30i32(<30 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -640,6 +658,8 @@ define <30 x i32> @bitcast_v30f32_to_v30i32(<30 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -683,6 +703,8 @@ define <30 x i32> @bitcast_v30f32_to_v30i32(<30 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -712,6 +734,8 @@ define <30 x i32> @bitcast_v30f32_to_v30i32(<30 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -820,6 +844,8 @@ define inreg <30 x i32> @bitcast_v30f32_to_v30i32_scalar(<30 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB3_5
; SI-NEXT: .LBB3_3:
; SI-NEXT: s_branch .LBB3_2
@@ -963,6 +989,8 @@ define inreg <30 x i32> @bitcast_v30f32_to_v30i32_scalar(<30 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB3_5
; VI-NEXT: .LBB3_3:
; VI-NEXT: s_branch .LBB3_2
@@ -1106,6 +1134,8 @@ define inreg <30 x i32> @bitcast_v30f32_to_v30i32_scalar(<30 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB3_5
; GFX9-NEXT: .LBB3_3:
; GFX9-NEXT: s_branch .LBB3_2
@@ -1251,6 +1281,8 @@ define inreg <30 x i32> @bitcast_v30f32_to_v30i32_scalar(<30 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_branch .LBB3_5
; GFX11-NEXT: .LBB3_3:
; GFX11-NEXT: s_branch .LBB3_2
@@ -1348,6 +1380,8 @@ define <15 x i64> @bitcast_v30i32_to_v15i64(<30 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1391,6 +1425,8 @@ define <15 x i64> @bitcast_v30i32_to_v15i64(<30 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1434,6 +1470,8 @@ define <15 x i64> @bitcast_v30i32_to_v15i64(<30 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1478,6 +1516,8 @@ define <15 x i64> @bitcast_v30i32_to_v15i64(<30 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -1554,6 +1594,8 @@ define inreg <15 x i64> @bitcast_v30i32_to_v15i64_scalar(<30 x i32> inreg %a, i3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB5_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -1644,6 +1686,8 @@ define inreg <15 x i64> @bitcast_v30i32_to_v15i64_scalar(<30 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB5_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1734,6 +1778,8 @@ define inreg <15 x i64> @bitcast_v30i32_to_v15i64_scalar(<30 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB5_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1822,6 +1868,8 @@ define inreg <15 x i64> @bitcast_v30i32_to_v15i64_scalar(<30 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr40
+; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: .LBB5_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -1899,6 +1947,8 @@ define <30 x i32> @bitcast_v15i64_to_v30i32(<15 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -1942,6 +1992,8 @@ define <30 x i32> @bitcast_v15i64_to_v30i32(<15 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -1985,6 +2037,8 @@ define <30 x i32> @bitcast_v15i64_to_v30i32(<15 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2037,6 +2091,8 @@ define <30 x i32> @bitcast_v15i64_to_v30i32(<15 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2113,6 +2169,8 @@ define inreg <30 x i32> @bitcast_v15i64_to_v30i32_scalar(<15 x i64> inreg %a, i3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB7_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -2203,6 +2261,8 @@ define inreg <30 x i32> @bitcast_v15i64_to_v30i32_scalar(<15 x i64> inreg %a, i3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB7_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2293,6 +2353,8 @@ define inreg <30 x i32> @bitcast_v15i64_to_v30i32_scalar(<15 x i64> inreg %a, i3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB7_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2381,6 +2443,8 @@ define inreg <30 x i32> @bitcast_v15i64_to_v30i32_scalar(<15 x i64> inreg %a, i3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr40
+; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2458,6 +2522,8 @@ define <15 x double> @bitcast_v30i32_to_v15f64(<30 x i32> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -2501,6 +2567,8 @@ define <15 x double> @bitcast_v30i32_to_v15f64(<30 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -2544,6 +2612,8 @@ define <15 x double> @bitcast_v30i32_to_v15f64(<30 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -2588,6 +2658,8 @@ define <15 x double> @bitcast_v30i32_to_v15f64(<30 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2664,6 +2736,8 @@ define inreg <15 x double> @bitcast_v30i32_to_v15f64_scalar(<30 x i32> inreg %a,
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB9_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -2754,6 +2828,8 @@ define inreg <15 x double> @bitcast_v30i32_to_v15f64_scalar(<30 x i32> inreg %a,
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2844,6 +2920,8 @@ define inreg <15 x double> @bitcast_v30i32_to_v15f64_scalar(<30 x i32> inreg %a,
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2932,6 +3010,8 @@ define inreg <15 x double> @bitcast_v30i32_to_v15f64_scalar(<30 x i32> inreg %a,
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr40
+; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2994,6 +3074,8 @@ define <30 x i32> @bitcast_v15f64_to_v30i32(<15 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -3022,6 +3104,8 @@ define <30 x i32> @bitcast_v15f64_to_v30i32(<15 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -3050,6 +3134,8 @@ define <30 x i32> @bitcast_v15f64_to_v30i32(<15 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3079,6 +3165,8 @@ define <30 x i32> @bitcast_v15f64_to_v30i32(<15 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3172,6 +3260,8 @@ define inreg <30 x i32> @bitcast_v15f64_to_v30i32_scalar(<15 x double> inreg %a,
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB11_5
; SI-NEXT: .LBB11_3:
; SI-NEXT: s_branch .LBB11_2
@@ -3300,6 +3390,8 @@ define inreg <30 x i32> @bitcast_v15f64_to_v30i32_scalar(<15 x double> inreg %a,
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB11_5
; VI-NEXT: .LBB11_3:
; VI-NEXT: s_branch .LBB11_2
@@ -3428,6 +3520,8 @@ define inreg <30 x i32> @bitcast_v15f64_to_v30i32_scalar(<15 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB11_5
; GFX9-NEXT: .LBB11_3:
; GFX9-NEXT: s_branch .LBB11_2
@@ -3558,6 +3652,8 @@ define inreg <30 x i32> @bitcast_v15f64_to_v30i32_scalar(<15 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_branch .LBB11_5
; GFX11-NEXT: .LBB11_3:
; GFX11-NEXT: s_branch .LBB11_2
@@ -5842,6 +5938,8 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
@@ -6071,6 +6169,8 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -6206,6 +6306,8 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v27, v34, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v28, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v29, v32, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr61
; VI-NEXT: ; implicit-def: $vgpr60
; VI-NEXT: ; implicit-def: $vgpr59
@@ -6331,6 +6433,8 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v30, 3, v32
; VI-NEXT: v_add_u16_sdwa v29, v32, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB14_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -6555,6 +6659,8 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
@@ -6724,6 +6830,8 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB14_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -6751,10 +6859,19 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6785,7 +6902,8 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6854,11 +6972,21 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB14_4
+; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6889,7 +7017,8 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -7093,6 +7222,8 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s65, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB15_3
; SI-NEXT: .LBB15_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -7245,6 +7376,8 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s65, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB15_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v30, 34
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -7507,6 +7640,8 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s65, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -7665,6 +7800,8 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s65, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB15_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v30, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -7874,6 +8011,8 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v27, s63, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v28, s64, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v29, s65, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB15_5
; GFX9-NEXT: .LBB15_3:
; GFX9-NEXT: s_branch .LBB15_2
@@ -8044,6 +8183,8 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v27, s27, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v28, s28, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v29, s29, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_3:
; GFX11-NEXT: s_branch .LBB15_2
@@ -10330,6 +10471,8 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
@@ -10681,6 +10824,8 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; SI-NEXT: v_or_b32_e32 v29, v31, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB18_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -10816,6 +10961,8 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v27, v34, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v28, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v29, v32, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr61
; VI-NEXT: ; implicit-def: $vgpr60
; VI-NEXT: ; implicit-def: $vgpr59
@@ -10941,6 +11088,8 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v29, v32, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v30, 0x200, v32
; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB18_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -11165,6 +11314,8 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
@@ -11335,6 +11486,8 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: v_pk_add_f16 v29, v29, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB18_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -11362,10 +11515,19 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -11396,7 +11558,8 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -11465,11 +11628,21 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB18_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -11500,7 +11673,8 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -11704,6 +11878,8 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s65, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB19_4
; SI-NEXT: .LBB19_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s99
@@ -11946,6 +12122,8 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; SI-NEXT: v_or_b32_e32 v29, v31, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB19_5
; SI-NEXT: .LBB19_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -12094,7 +12272,7 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: v_writelane_b32 v33, s61, 4
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s88, s28, 16
+; VI-NEXT: s_lshr_b32 s79, s28, 16
; VI-NEXT: s_lshr_b32 s31, s27, 16
; VI-NEXT: s_lshr_b32 s68, s26, 16
; VI-NEXT: s_lshr_b32 s70, s25, 16
@@ -12161,7 +12339,7 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s88, 16
+; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
@@ -12190,8 +12368,8 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s78
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s88, s79
+; VI-NEXT: s_mov_b32 s79, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s58, 16
@@ -12218,6 +12396,8 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s65, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB19_4
; VI-NEXT: .LBB19_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v29, 0x200
@@ -12269,7 +12449,7 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v11, v11, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v29
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s79
+; VI-NEXT: v_mov_b32_e32 v12, s88
; VI-NEXT: v_add_f16_sdwa v12, v12, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v29
; VI-NEXT: v_or_b32_e32 v12, v13, v12
@@ -12305,7 +12485,7 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v20, v20, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s89, v29
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s88
+; VI-NEXT: v_mov_b32_e32 v21, s79
; VI-NEXT: v_add_f16_sdwa v21, v21, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s78, v29
; VI-NEXT: v_readlane_b32 s4, v33, 7
@@ -12349,12 +12529,14 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v30, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v29, s6, v29
; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB19_5
; VI-NEXT: .LBB19_3:
; VI-NEXT: s_mov_b32 s90, s64
-; VI-NEXT: s_mov_b32 s79, s88
+; VI-NEXT: s_mov_b32 s88, s79
; VI-NEXT: s_mov_b32 s91, s56
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s79, s57
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB19_2
; VI-NEXT: .LBB19_4:
@@ -12563,6 +12745,8 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v27, s63, v29 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v28, s64, v29 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v29, s65, v29 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB19_5
; GFX9-NEXT: .LBB19_3:
; GFX9-NEXT: s_branch .LBB19_2
@@ -12733,6 +12917,8 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s27 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v28, 0x200, s28 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v29, 0x200, s29 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_3:
; GFX11-NEXT: s_branch .LBB19_2
@@ -12811,6 +12997,8 @@ define <15 x i64> @bitcast_v30f32_to_v15i64(<30 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -12854,6 +13042,8 @@ define <15 x i64> @bitcast_v30f32_to_v15i64(<30 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12897,6 +13087,8 @@ define <15 x i64> @bitcast_v30f32_to_v15i64(<30 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12926,6 +13118,8 @@ define <15 x i64> @bitcast_v30f32_to_v15i64(<30 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13034,6 +13228,8 @@ define inreg <15 x i64> @bitcast_v30f32_to_v15i64_scalar(<30 x float> inreg %a,
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB21_5
; SI-NEXT: .LBB21_3:
; SI-NEXT: s_branch .LBB21_2
@@ -13177,6 +13373,8 @@ define inreg <15 x i64> @bitcast_v30f32_to_v15i64_scalar(<30 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB21_5
; VI-NEXT: .LBB21_3:
; VI-NEXT: s_branch .LBB21_2
@@ -13320,6 +13518,8 @@ define inreg <15 x i64> @bitcast_v30f32_to_v15i64_scalar(<30 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB21_5
; GFX9-NEXT: .LBB21_3:
; GFX9-NEXT: s_branch .LBB21_2
@@ -13465,6 +13665,8 @@ define inreg <15 x i64> @bitcast_v30f32_to_v15i64_scalar(<30 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_branch .LBB21_5
; GFX11-NEXT: .LBB21_3:
; GFX11-NEXT: s_branch .LBB21_2
@@ -13562,6 +13764,8 @@ define <30 x float> @bitcast_v15i64_to_v30f32(<15 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -13605,6 +13809,8 @@ define <30 x float> @bitcast_v15i64_to_v30f32(<15 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -13648,6 +13854,8 @@ define <30 x float> @bitcast_v15i64_to_v30f32(<15 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -13700,6 +13908,8 @@ define <30 x float> @bitcast_v15i64_to_v30f32(<15 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13776,6 +13986,8 @@ define inreg <30 x float> @bitcast_v15i64_to_v30f32_scalar(<15 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB23_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -13866,6 +14078,8 @@ define inreg <30 x float> @bitcast_v15i64_to_v30f32_scalar(<15 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB23_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -13956,6 +14170,8 @@ define inreg <30 x float> @bitcast_v15i64_to_v30f32_scalar(<15 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB23_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -14044,6 +14260,8 @@ define inreg <30 x float> @bitcast_v15i64_to_v30f32_scalar(<15 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
+; GFX11-NEXT: ; implicit-def: $sgpr40
+; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -14121,6 +14339,8 @@ define <15 x double> @bitcast_v30f32_to_v15f64(<30 x float> %a, i32 %b) #0 {
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -14164,6 +14384,8 @@ define <15 x double> @bitcast_v30f32_to_v15f64(<30 x float> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -14207,6 +14429,8 @@ define <15 x double> @bitcast_v30f32_to_v15f64(<30 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -14236,6 +14460,8 @@ define <15 x double> @bitcast_v30f32_to_v15f64(<30 x float> %a, i32 %b) #0 {
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -14344,6 +14570,8 @@ define inreg <15 x double> @bitcast_v30f32_to_v15f64_scalar(<30 x float> inreg %
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB25_5
; SI-NEXT: .LBB25_3:
; SI-NEXT: s_branch .LBB25_2
@@ -14487,6 +14715,8 @@ define inreg <15 x double> @bitcast_v30f32_to_v15f64_scalar(<30 x float> inreg %
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB25_5
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -14630,6 +14860,8 @@ define inreg <15 x double> @bitcast_v30f32_to_v15f64_scalar(<30 x float> inreg %
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB25_5
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -14775,6 +15007,8 @@ define inreg <15 x double> @bitcast_v30f32_to_v15f64_scalar(<30 x float> inreg %
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_branch .LBB25_5
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -14857,6 +15091,8 @@ define <30 x float> @bitcast_v15f64_to_v30f32(<15 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -14885,6 +15121,8 @@ define <30 x float> @bitcast_v15f64_to_v30f32(<15 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -14913,6 +15151,8 @@ define <30 x float> @bitcast_v15f64_to_v30f32(<15 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -14942,6 +15182,8 @@ define <30 x float> @bitcast_v15f64_to_v30f32(<15 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -15035,6 +15277,8 @@ define inreg <30 x float> @bitcast_v15f64_to_v30f32_scalar(<15 x double> inreg %
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB27_5
; SI-NEXT: .LBB27_3:
; SI-NEXT: s_branch .LBB27_2
@@ -15163,6 +15407,8 @@ define inreg <30 x float> @bitcast_v15f64_to_v30f32_scalar(<15 x double> inreg %
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB27_5
; VI-NEXT: .LBB27_3:
; VI-NEXT: s_branch .LBB27_2
@@ -15291,6 +15537,8 @@ define inreg <30 x float> @bitcast_v15f64_to_v30f32_scalar(<15 x double> inreg %
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB27_5
; GFX9-NEXT: .LBB27_3:
; GFX9-NEXT: s_branch .LBB27_2
@@ -15421,6 +15669,8 @@ define inreg <30 x float> @bitcast_v15f64_to_v30f32_scalar(<15 x double> inreg %
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_branch .LBB27_5
; GFX11-NEXT: .LBB27_3:
; GFX11-NEXT: s_branch .LBB27_2
@@ -18111,6 +18361,8 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
@@ -18340,6 +18592,8 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -18475,6 +18729,8 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v27, v34, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v28, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v29, v32, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr61
; VI-NEXT: ; implicit-def: $vgpr60
; VI-NEXT: ; implicit-def: $vgpr59
@@ -18600,6 +18856,8 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v30, 3, v32
; VI-NEXT: v_add_u16_sdwa v29, v32, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB30_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -18824,6 +19082,8 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
@@ -18993,6 +19253,8 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB30_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -19020,10 +19282,19 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -19054,7 +19325,8 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -19123,11 +19395,21 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB30_4
+; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB30_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB30_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -19158,7 +19440,8 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -19362,6 +19645,8 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s65, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB31_3
; SI-NEXT: .LBB31_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -19514,6 +19799,8 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s65, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB31_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v30, 34
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -19776,6 +20063,8 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s65, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB31_3
; VI-NEXT: .LBB31_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -19934,6 +20223,8 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s65, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB31_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v30, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -20143,6 +20434,8 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v27, s63, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v28, s64, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v29, s65, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB31_5
; GFX9-NEXT: .LBB31_3:
; GFX9-NEXT: s_branch .LBB31_2
@@ -20313,6 +20606,8 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v27, s27, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v28, s28, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v29, s29, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_3:
; GFX11-NEXT: s_branch .LBB31_2
@@ -23005,6 +23300,8 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
@@ -23356,6 +23653,8 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; SI-NEXT: v_or_b32_e32 v29, v31, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -23491,6 +23790,8 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v27, v34, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v28, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v29, v32, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr61
; VI-NEXT: ; implicit-def: $vgpr60
; VI-NEXT: ; implicit-def: $vgpr59
@@ -23616,6 +23917,8 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v29, v32, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v30, 0x200, v32
; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -23840,6 +24143,8 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
@@ -24010,6 +24315,8 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: v_pk_add_f16 v29, v29, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB34_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -24037,10 +24344,19 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -24071,7 +24387,8 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -24140,11 +24457,21 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -24175,7 +24502,8 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -24379,6 +24707,8 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s65, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB35_4
; SI-NEXT: .LBB35_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s99
@@ -24621,6 +24951,8 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; SI-NEXT: v_or_b32_e32 v29, v31, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB35_5
; SI-NEXT: .LBB35_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -24769,7 +25101,7 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: v_writelane_b32 v33, s61, 4
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s88, s28, 16
+; VI-NEXT: s_lshr_b32 s79, s28, 16
; VI-NEXT: s_lshr_b32 s31, s27, 16
; VI-NEXT: s_lshr_b32 s68, s26, 16
; VI-NEXT: s_lshr_b32 s70, s25, 16
@@ -24836,7 +25168,7 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s88, 16
+; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
@@ -24865,8 +25197,8 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s78
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s88, s79
+; VI-NEXT: s_mov_b32 s79, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s58, 16
@@ -24893,6 +25225,8 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s65, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB35_4
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v29, 0x200
@@ -24944,7 +25278,7 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v11, v11, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v29
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s79
+; VI-NEXT: v_mov_b32_e32 v12, s88
; VI-NEXT: v_add_f16_sdwa v12, v12, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v29
; VI-NEXT: v_or_b32_e32 v12, v13, v12
@@ -24980,7 +25314,7 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v20, v20, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s89, v29
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s88
+; VI-NEXT: v_mov_b32_e32 v21, s79
; VI-NEXT: v_add_f16_sdwa v21, v21, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s78, v29
; VI-NEXT: v_readlane_b32 s4, v33, 7
@@ -25024,12 +25358,14 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; VI-NEXT: v_add_f16_sdwa v30, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v29, s6, v29
; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB35_5
; VI-NEXT: .LBB35_3:
; VI-NEXT: s_mov_b32 s90, s64
-; VI-NEXT: s_mov_b32 s79, s88
+; VI-NEXT: s_mov_b32 s88, s79
; VI-NEXT: s_mov_b32 s91, s56
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s79, s57
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB35_2
; VI-NEXT: .LBB35_4:
@@ -25238,6 +25574,8 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; GFX9-NEXT: v_pk_add_f16 v27, s63, v29 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v28, s64, v29 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v29, s65, v29 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB35_5
; GFX9-NEXT: .LBB35_3:
; GFX9-NEXT: s_branch .LBB35_2
@@ -25408,6 +25746,8 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s27 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v28, 0x200, s28 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v29, 0x200, s29 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_3:
; GFX11-NEXT: s_branch .LBB35_2
@@ -25486,6 +25826,8 @@ define <15 x double> @bitcast_v15i64_to_v15f64(<15 x i64> %a, i32 %b) #0 {
; SI-NEXT: v_addc_u32_e32 v27, vcc, 0, v27, vcc
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_addc_u32_e32 v29, vcc, 0, v29, vcc
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -25529,6 +25871,8 @@ define <15 x double> @bitcast_v15i64_to_v15f64(<15 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_addc_u32_e32 v27, vcc, 0, v27, vcc
; VI-NEXT: v_add_u32_e32 v28, vcc, 3, v28
; VI-NEXT: v_addc_u32_e32 v29, vcc, 0, v29, vcc
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -25572,6 +25916,8 @@ define <15 x double> @bitcast_v15i64_to_v15f64(<15 x i64> %a, i32 %b) #0 {
; GFX9-NEXT: v_addc_co_u32_e32 v27, vcc, 0, v27, vcc
; GFX9-NEXT: v_add_co_u32_e32 v28, vcc, 3, v28
; GFX9-NEXT: v_addc_co_u32_e32 v29, vcc, 0, v29, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -25624,6 +25970,8 @@ define <15 x double> @bitcast_v15i64_to_v15f64(<15 x i64> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_co_u32 v28, vcc_lo, v28, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v29, null, 0, v29, vcc_lo
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -25700,6 +26048,8 @@ define inreg <15 x double> @bitcast_v15i64_to_v15f64_scalar(<15 x i64> inreg %a,
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB37_3: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
@@ -25790,6 +26140,8 @@ define inreg <15 x double> @bitcast_v15i64_to_v15f64_scalar(<15 x i64> inreg %a,
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -25880,6 +26232,8 @@ define inreg <15 x double> @bitcast_v15i64_to_v15f64_scalar(<15 x i64> inreg %a,
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
+; GFX9-NEXT: ; implicit-def: $sgpr4
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -25968,6 +26322,8 @@ define inreg <15 x double> @bitcast_v15i64_to_v15f64_scalar(<15 x i64> inreg %a,
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
+; GFX11-NEXT: ; implicit-def: $sgpr40
+; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
@@ -26029,6 +26385,8 @@ define <15 x i64> @bitcast_v15f64_to_v15i64(<15 x double> %a, i32 %b) #0 {
; SI-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; SI-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
; SI-NEXT: v_add_f64 v[28:29], v[28:29], 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
@@ -26057,6 +26415,8 @@ define <15 x i64> @bitcast_v15f64_to_v15i64(<15 x double> %a, i32 %b) #0 {
; VI-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; VI-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
; VI-NEXT: v_add_f64 v[28:29], v[28:29], 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -26085,6 +26445,8 @@ define <15 x i64> @bitcast_v15f64_to_v15i64(<15 x double> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; GFX9-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
; GFX9-NEXT: v_add_f64 v[28:29], v[28:29], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -26114,6 +26476,8 @@ define <15 x i64> @bitcast_v15f64_to_v15i64(<15 x double> %a, i32 %b) #0 {
; GFX11-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; GFX11-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
; GFX11-NEXT: v_add_f64 v[28:29], v[28:29], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -26207,6 +26571,8 @@ define inreg <15 x i64> @bitcast_v15f64_to_v15i64_scalar(<15 x double> inreg %a,
; SI-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
; SI-NEXT: v_add_f64 v[26:27], s[62:63], 1.0
; SI-NEXT: v_add_f64 v[28:29], s[64:65], 1.0
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB39_5
; SI-NEXT: .LBB39_3:
; SI-NEXT: s_branch .LBB39_2
@@ -26335,6 +26701,8 @@ define inreg <15 x i64> @bitcast_v15f64_to_v15i64_scalar(<15 x double> inreg %a,
; VI-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
; VI-NEXT: v_add_f64 v[26:27], s[62:63], 1.0
; VI-NEXT: v_add_f64 v[28:29], s[64:65], 1.0
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB39_5
; VI-NEXT: .LBB39_3:
; VI-NEXT: s_branch .LBB39_2
@@ -26463,6 +26831,8 @@ define inreg <15 x i64> @bitcast_v15f64_to_v15i64_scalar(<15 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
; GFX9-NEXT: v_add_f64 v[26:27], s[62:63], 1.0
; GFX9-NEXT: v_add_f64 v[28:29], s[64:65], 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB39_5
; GFX9-NEXT: .LBB39_3:
; GFX9-NEXT: s_branch .LBB39_2
@@ -26593,6 +26963,8 @@ define inreg <15 x i64> @bitcast_v15f64_to_v15i64_scalar(<15 x double> inreg %a,
; GFX11-NEXT: v_add_f64 v[24:25], s[60:61], 1.0
; GFX11-NEXT: v_add_f64 v[26:27], s[62:63], 1.0
; GFX11-NEXT: v_add_f64 v[28:29], s[64:65], 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_branch .LBB39_5
; GFX11-NEXT: .LBB39_3:
; GFX11-NEXT: s_branch .LBB39_2
@@ -28893,6 +29265,8 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
@@ -29122,6 +29496,8 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -29257,6 +29633,8 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v27, v34, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v28, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v29, v32, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr61
; VI-NEXT: ; implicit-def: $vgpr60
; VI-NEXT: ; implicit-def: $vgpr59
@@ -29382,6 +29760,8 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v30, 3, v32
; VI-NEXT: v_add_u16_sdwa v29, v32, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -29606,6 +29986,8 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
@@ -29775,6 +30157,8 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB42_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -29802,10 +30186,19 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -29836,7 +30229,8 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -29905,11 +30299,21 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB42_4
+; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB42_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -29940,7 +30344,8 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -30144,6 +30549,8 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s65, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB43_3
; SI-NEXT: .LBB43_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -30296,6 +30703,8 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s65, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB43_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v30, 34
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -30558,6 +30967,8 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s65, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -30716,6 +31127,8 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s65, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB43_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v30, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -30925,6 +31338,8 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v27, s63, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v28, s64, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v29, s65, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB43_5
; GFX9-NEXT: .LBB43_3:
; GFX9-NEXT: s_branch .LBB43_2
@@ -31095,6 +31510,8 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v27, s27, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v28, s28, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v29, s29, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_3:
; GFX11-NEXT: s_branch .LBB43_2
@@ -33397,6 +33814,8 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
@@ -33748,6 +34167,8 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; SI-NEXT: v_or_b32_e32 v29, v31, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -33883,6 +34304,8 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v27, v34, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v28, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v29, v32, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr61
; VI-NEXT: ; implicit-def: $vgpr60
; VI-NEXT: ; implicit-def: $vgpr59
@@ -34008,6 +34431,8 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v29, v32, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v30, 0x200, v32
; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -34232,6 +34657,8 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
@@ -34402,6 +34829,8 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: v_pk_add_f16 v29, v29, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB46_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -34429,10 +34858,19 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -34463,7 +34901,8 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -34532,11 +34971,21 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB46_4
+; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB46_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB46_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -34567,7 +35016,8 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -34771,6 +35221,8 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s65, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB47_4
; SI-NEXT: .LBB47_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s99
@@ -35013,6 +35465,8 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; SI-NEXT: v_or_b32_e32 v29, v31, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB47_5
; SI-NEXT: .LBB47_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -35161,7 +35615,7 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: v_writelane_b32 v33, s61, 4
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s88, s28, 16
+; VI-NEXT: s_lshr_b32 s79, s28, 16
; VI-NEXT: s_lshr_b32 s31, s27, 16
; VI-NEXT: s_lshr_b32 s68, s26, 16
; VI-NEXT: s_lshr_b32 s70, s25, 16
@@ -35228,7 +35682,7 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s88, 16
+; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
@@ -35257,8 +35711,8 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s78
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s88, s79
+; VI-NEXT: s_mov_b32 s79, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s58, 16
@@ -35285,6 +35739,8 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s65, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB47_4
; VI-NEXT: .LBB47_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v29, 0x200
@@ -35336,7 +35792,7 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v11, v11, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v29
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s79
+; VI-NEXT: v_mov_b32_e32 v12, s88
; VI-NEXT: v_add_f16_sdwa v12, v12, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v29
; VI-NEXT: v_or_b32_e32 v12, v13, v12
@@ -35372,7 +35828,7 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v20, v20, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s89, v29
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s88
+; VI-NEXT: v_mov_b32_e32 v21, s79
; VI-NEXT: v_add_f16_sdwa v21, v21, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s78, v29
; VI-NEXT: v_readlane_b32 s4, v33, 7
@@ -35416,12 +35872,14 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_add_f16_sdwa v30, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v29, s6, v29
; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB47_5
; VI-NEXT: .LBB47_3:
; VI-NEXT: s_mov_b32 s90, s64
-; VI-NEXT: s_mov_b32 s79, s88
+; VI-NEXT: s_mov_b32 s88, s79
; VI-NEXT: s_mov_b32 s91, s56
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s79, s57
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB47_2
; VI-NEXT: .LBB47_4:
@@ -35630,6 +36088,8 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v27, s63, v29 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v28, s64, v29 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v29, s65, v29 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB47_5
; GFX9-NEXT: .LBB47_3:
; GFX9-NEXT: s_branch .LBB47_2
@@ -35800,6 +36260,8 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s27 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v28, 0x200, s28 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v29, 0x200, s29 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_3:
; GFX11-NEXT: s_branch .LBB47_2
@@ -38358,6 +38820,8 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
@@ -38587,6 +39051,8 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -38722,6 +39188,8 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v27, v34, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v28, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v29, v32, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr61
; VI-NEXT: ; implicit-def: $vgpr60
; VI-NEXT: ; implicit-def: $vgpr59
@@ -38847,6 +39315,8 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v30, 3, v32
; VI-NEXT: v_add_u16_sdwa v29, v32, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -39071,6 +39541,8 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
@@ -39240,6 +39712,8 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB50_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -39267,10 +39741,19 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -39301,7 +39784,8 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -39370,11 +39854,21 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
+; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -39405,7 +39899,8 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -39609,6 +40104,8 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s65, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: s_cbranch_execnz .LBB51_3
; SI-NEXT: .LBB51_2: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
@@ -39761,6 +40258,8 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s65, s4, 0x30000
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: .LBB51_3: ; %end
; SI-NEXT: v_readlane_b32 s30, v30, 34
; SI-NEXT: v_mov_b32_e32 v0, s36
@@ -40023,6 +40522,8 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s65, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -40181,6 +40682,8 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; VI-NEXT: s_lshl_b32 s5, s66, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s65, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB51_3: ; %end
; VI-NEXT: v_readlane_b32 s30, v30, 30
; VI-NEXT: v_mov_b32_e32 v0, s36
@@ -40390,6 +40893,8 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; GFX9-NEXT: v_pk_add_u16 v27, s63, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v28, s64, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v29, s65, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB51_5
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -40560,6 +41065,8 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; GFX11-NEXT: v_pk_add_u16 v27, s27, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v28, s28, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v29, s29, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -43139,6 +43646,8 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; kill: killed $vgpr30
@@ -43490,6 +43999,8 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; SI-NEXT: v_or_b32_e32 v29, v31, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -43625,6 +44136,8 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_sdwa v27, v34, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v28, v33, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v29, v32, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr61
; VI-NEXT: ; implicit-def: $vgpr60
; VI-NEXT: ; implicit-def: $vgpr59
@@ -43750,6 +44263,8 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; VI-NEXT: v_add_f16_sdwa v29, v32, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v30, 0x200, v32
; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -43974,6 +44489,8 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; kill: killed $vgpr30
@@ -44144,6 +44661,8 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s6
; GFX9-NEXT: v_pk_add_f16 v29, v29, s7 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: .LBB54_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -44171,10 +44690,19 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -44205,7 +44733,8 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -44274,11 +44803,21 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v32, v28, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v31, v29, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_3
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB54_4
+; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT: .LBB54_3: ; %cmp.false
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT: .LBB54_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -44309,7 +44848,8 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -44513,6 +45053,8 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s7, 16
; SI-NEXT: s_or_b32 s65, s4, s5
+; SI-NEXT: ; implicit-def: $sgpr66
+; SI-NEXT: ; implicit-def: $sgpr67
; SI-NEXT: s_cbranch_execnz .LBB55_4
; SI-NEXT: .LBB55_2: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s99
@@ -44755,6 +45297,8 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v30
; SI-NEXT: v_or_b32_e32 v29, v31, v29
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_branch .LBB55_5
; SI-NEXT: .LBB55_3:
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
@@ -44903,7 +45447,7 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: v_writelane_b32 v33, s61, 4
; VI-NEXT: s_lshr_b32 s56, s29, 16
-; VI-NEXT: s_lshr_b32 s88, s28, 16
+; VI-NEXT: s_lshr_b32 s79, s28, 16
; VI-NEXT: s_lshr_b32 s31, s27, 16
; VI-NEXT: s_lshr_b32 s68, s26, 16
; VI-NEXT: s_lshr_b32 s70, s25, 16
@@ -44970,7 +45514,7 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
-; VI-NEXT: s_lshl_b32 s5, s88, 16
+; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s56, 16
@@ -44999,8 +45543,8 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s78
; VI-NEXT: s_lshl_b32 s5, s57, 16
-; VI-NEXT: s_mov_b32 s79, s88
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s88, s79
+; VI-NEXT: s_mov_b32 s79, s57
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s58, 16
@@ -45027,6 +45571,8 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s65, s4, s5
+; VI-NEXT: ; implicit-def: $sgpr66
+; VI-NEXT: ; implicit-def: $sgpr67
; VI-NEXT: s_cbranch_execnz .LBB55_4
; VI-NEXT: .LBB55_2: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v29, 0x200
@@ -45078,7 +45624,7 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v11, v11, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v29
; VI-NEXT: v_or_b32_e32 v11, v12, v11
-; VI-NEXT: v_mov_b32_e32 v12, s79
+; VI-NEXT: v_mov_b32_e32 v12, s88
; VI-NEXT: v_add_f16_sdwa v12, v12, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v29
; VI-NEXT: v_or_b32_e32 v12, v13, v12
@@ -45114,7 +45660,7 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v20, v20, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s89, v29
; VI-NEXT: v_or_b32_e32 v20, v21, v20
-; VI-NEXT: v_mov_b32_e32 v21, s88
+; VI-NEXT: v_mov_b32_e32 v21, s79
; VI-NEXT: v_add_f16_sdwa v21, v21, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s78, v29
; VI-NEXT: v_readlane_b32 s4, v33, 7
@@ -45158,12 +45704,14 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; VI-NEXT: v_add_f16_sdwa v30, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v29, s6, v29
; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: ; implicit-def: $vgpr30
+; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: s_branch .LBB55_5
; VI-NEXT: .LBB55_3:
; VI-NEXT: s_mov_b32 s90, s64
-; VI-NEXT: s_mov_b32 s79, s88
+; VI-NEXT: s_mov_b32 s88, s79
; VI-NEXT: s_mov_b32 s91, s56
-; VI-NEXT: s_mov_b32 s88, s57
+; VI-NEXT: s_mov_b32 s79, s57
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_branch .LBB55_2
; VI-NEXT: .LBB55_4:
@@ -45372,6 +45920,8 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; GFX9-NEXT: v_pk_add_f16 v27, s63, v29 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v28, s64, v29 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v29, s65, v29 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr30
+; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: s_branch .LBB55_5
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -45542,6 +46092,8 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s27 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v28, 0x200, s28 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v29, 0x200, s29 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr30
+; GFX11-NEXT: ; implicit-def: $vgpr30
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index a1c0db086bf3c..702b8a8f6529e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -1125,11 +1125,23 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB6_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v15, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v13, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
@@ -1628,12 +1640,22 @@ define <6 x bfloat> @bitcast_v3i32_to_v6bf16(<3 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB8_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB8_4
+; VI-NEXT: .LBB8_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB8_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr3
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB8_2
+; VI-NEXT: .LBB8_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -1643,12 +1665,22 @@ define <6 x bfloat> @bitcast_v3i32_to_v6bf16(<3 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB8_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB8_4
+; GFX9-NEXT: .LBB8_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB8_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB8_2
+; GFX9-NEXT: .LBB8_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1658,13 +1690,22 @@ define <6 x bfloat> @bitcast_v3i32_to_v6bf16(<3 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB8_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB8_4
+; GFX11-NEXT: .LBB8_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB8_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr3
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB8_2
+; GFX11-NEXT: .LBB8_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1742,6 +1783,7 @@ define inreg <6 x bfloat> @bitcast_v3i32_to_v6bf16_scalar(<3 x i32> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB9_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -1761,6 +1803,7 @@ define inreg <6 x bfloat> @bitcast_v3i32_to_v6bf16_scalar(<3 x i32> inreg %a, i3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB9_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -1782,6 +1825,7 @@ define inreg <6 x bfloat> @bitcast_v3i32_to_v6bf16_scalar(<3 x i32> inreg %a, i3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr3
; GFX11-NEXT: .LBB9_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -2577,12 +2621,22 @@ define <6 x half> @bitcast_v3i32_to_v6f16(<3 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB12_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB12_4
+; VI-NEXT: .LBB12_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB12_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr3
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB12_2
+; VI-NEXT: .LBB12_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2592,12 +2646,22 @@ define <6 x half> @bitcast_v3i32_to_v6f16(<3 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB12_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB12_4
+; GFX9-NEXT: .LBB12_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB12_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB12_2
+; GFX9-NEXT: .LBB12_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -2607,13 +2671,22 @@ define <6 x half> @bitcast_v3i32_to_v6f16(<3 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB12_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB12_4
+; GFX11-NEXT: .LBB12_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB12_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr3
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-NEXT: .LBB12_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2682,6 +2755,7 @@ define inreg <6 x half> @bitcast_v3i32_to_v6f16_scalar(<3 x i32> inreg %a, i32 i
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB13_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -2701,6 +2775,7 @@ define inreg <6 x half> @bitcast_v3i32_to_v6f16_scalar(<3 x i32> inreg %a, i32 i
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB13_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -2722,6 +2797,7 @@ define inreg <6 x half> @bitcast_v3i32_to_v6f16_scalar(<3 x i32> inreg %a, i32 i
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr3
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -3072,12 +3148,22 @@ define <6 x i16> @bitcast_v3i32_to_v6i16(<3 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB16_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB16_4
+; VI-NEXT: .LBB16_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB16_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr3
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB16_2
+; VI-NEXT: .LBB16_4: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -3087,12 +3173,22 @@ define <6 x i16> @bitcast_v3i32_to_v6i16(<3 x i32> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB16_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB16_4
+; GFX9-NEXT: .LBB16_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB16_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB16_2
+; GFX9-NEXT: .LBB16_4: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -3102,13 +3198,22 @@ define <6 x i16> @bitcast_v3i32_to_v6i16(<3 x i32> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB16_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB16_4
+; GFX11-NEXT: .LBB16_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB16_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr3
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-NEXT: .LBB16_4: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -3177,6 +3282,7 @@ define inreg <6 x i16> @bitcast_v3i32_to_v6i16_scalar(<3 x i32> inreg %a, i32 in
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB17_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -3196,6 +3302,7 @@ define inreg <6 x i16> @bitcast_v3i32_to_v6i16_scalar(<3 x i32> inreg %a, i32 in
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
+; GFX9-NEXT: ; implicit-def: $sgpr4
; GFX9-NEXT: .LBB17_3: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
@@ -3217,6 +3324,7 @@ define inreg <6 x i16> @bitcast_v3i32_to_v6i16_scalar(<3 x i32> inreg %a, i32 in
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: ; implicit-def: $sgpr3
; GFX11-NEXT: .LBB17_3: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
@@ -4288,11 +4396,23 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB22_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v15, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v13, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
@@ -4791,12 +4911,22 @@ define <6 x bfloat> @bitcast_v3f32_to_v6bf16(<3 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB24_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB24_4
+; VI-NEXT: .LBB24_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB24_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr3
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB24_2
+; VI-NEXT: .LBB24_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -4806,12 +4936,22 @@ define <6 x bfloat> @bitcast_v3f32_to_v6bf16(<3 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB24_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB24_4
+; GFX9-NEXT: .LBB24_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB24_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB24_2
+; GFX9-NEXT: .LBB24_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -4821,12 +4961,21 @@ define <6 x bfloat> @bitcast_v3f32_to_v6bf16(<3 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB24_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB24_4
+; GFX11-NEXT: .LBB24_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB24_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr3
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB24_2
+; GFX11-NEXT: .LBB24_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4912,6 +5061,7 @@ define inreg <6 x bfloat> @bitcast_v3f32_to_v6bf16_scalar(<3 x float> inreg %a,
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB25_3:
; VI-NEXT: s_branch .LBB25_2
@@ -4933,6 +5083,7 @@ define inreg <6 x bfloat> @bitcast_v3f32_to_v6bf16_scalar(<3 x float> inreg %a,
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB25_3:
; GFX9-NEXT: s_branch .LBB25_2
@@ -4956,6 +5107,7 @@ define inreg <6 x bfloat> @bitcast_v3f32_to_v6bf16_scalar(<3 x float> inreg %a,
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB25_3:
; GFX11-NEXT: s_branch .LBB25_2
@@ -5751,12 +5903,22 @@ define <6 x half> @bitcast_v3f32_to_v6f16(<3 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB28_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB28_4
+; VI-NEXT: .LBB28_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB28_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr3
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB28_2
+; VI-NEXT: .LBB28_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -5766,12 +5928,22 @@ define <6 x half> @bitcast_v3f32_to_v6f16(<3 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB28_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB28_4
+; GFX9-NEXT: .LBB28_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB28_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB28_2
+; GFX9-NEXT: .LBB28_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -5781,12 +5953,21 @@ define <6 x half> @bitcast_v3f32_to_v6f16(<3 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB28_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB28_4
+; GFX11-NEXT: .LBB28_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB28_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr3
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-NEXT: .LBB28_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -5860,6 +6041,7 @@ define inreg <6 x half> @bitcast_v3f32_to_v6f16_scalar(<3 x float> inreg %a, i32
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB29_3:
; VI-NEXT: s_branch .LBB29_2
@@ -5881,6 +6063,7 @@ define inreg <6 x half> @bitcast_v3f32_to_v6f16_scalar(<3 x float> inreg %a, i32
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB29_3:
; GFX9-NEXT: s_branch .LBB29_2
@@ -5904,6 +6087,7 @@ define inreg <6 x half> @bitcast_v3f32_to_v6f16_scalar(<3 x float> inreg %a, i32
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB29_3:
; GFX11-NEXT: s_branch .LBB29_2
@@ -6254,12 +6438,22 @@ define <6 x i16> @bitcast_v3f32_to_v6i16(<3 x float> %a, i32 %b) #0 {
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; VI-NEXT: s_cbranch_execnz .LBB32_3
+; VI-NEXT: ; %bb.1: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT: ; %bb.1: ; %cmp.true
+; VI-NEXT: s_cbranch_execnz .LBB32_4
+; VI-NEXT: .LBB32_2: ; %end
+; VI-NEXT: s_or_b64 exec, exec, s[4:5]
+; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: .LBB32_3: ; %cmp.false
+; VI-NEXT: ; implicit-def: $vgpr3
+; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; VI-NEXT: s_cbranch_execz .LBB32_2
+; VI-NEXT: .LBB32_4: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT: ; %bb.2: ; %end
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6269,12 +6463,22 @@ define <6 x i16> @bitcast_v3f32_to_v6i16(<3 x float> %a, i32 %b) #0 {
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execnz .LBB32_3
+; GFX9-NEXT: ; %bb.1: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT: ; %bb.1: ; %cmp.true
+; GFX9-NEXT: s_cbranch_execnz .LBB32_4
+; GFX9-NEXT: .LBB32_2: ; %end
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: .LBB32_3: ; %cmp.false
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB32_2
+; GFX9-NEXT: .LBB32_4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT: ; %bb.2: ; %end
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6284,12 +6488,21 @@ define <6 x i16> @bitcast_v3f32_to_v6i16(<3 x float> %a, i32 %b) #0 {
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v3
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_cbranch_execnz .LBB32_3
+; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-NEXT: s_cbranch_execnz .LBB32_4
+; GFX11-NEXT: .LBB32_2: ; %end
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-NEXT: .LBB32_3: ; %cmp.false
+; GFX11-NEXT: ; implicit-def: $vgpr3
+; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-NEXT: .LBB32_4: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: ; %bb.2: ; %end
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6363,6 +6576,7 @@ define inreg <6 x i16> @bitcast_v3f32_to_v6i16_scalar(<3 x float> inreg %a, i32
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB33_3:
; VI-NEXT: s_branch .LBB33_2
@@ -6384,6 +6598,7 @@ define inreg <6 x i16> @bitcast_v3f32_to_v6i16_scalar(<3 x float> inreg %a, i32
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB33_3:
; GFX9-NEXT: s_branch .LBB33_2
@@ -6407,6 +6622,7 @@ define inreg <6 x i16> @bitcast_v3f32_to_v6i16_scalar(<3 x float> inreg %a, i32
; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB33_3:
; GFX11-NEXT: s_branch .LBB33_2
@@ -6835,6 +7051,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -6878,6 +7095,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
; VI-NEXT: v_add_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -6910,6 +7128,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v2, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v3, v10, v11, s6
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr13
@@ -6953,6 +7172,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6975,11 +7195,23 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB36_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v16, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v14, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
@@ -6994,6 +7226,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
@@ -7030,6 +7263,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7069,6 +7303,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
@@ -7114,6 +7349,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -7260,6 +7496,7 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_cbranch_execnz .LBB37_3
; VI-NEXT: .LBB37_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -7293,6 +7530,7 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB37_3: ; %end
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB37_4:
@@ -7324,6 +7562,7 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_cbranch_execnz .LBB37_3
; GFX9-NEXT: .LBB37_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -7355,6 +7594,7 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
; GFX9-NEXT: v_add_u32_sdwa v2, v2, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: .LBB37_3: ; %end
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB37_4:
@@ -7384,6 +7624,7 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX11-NEXT: v_or_b32_e32 v1, v5, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v2, v6, v3
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB37_3
; GFX11-NEXT: .LBB37_2: ; %cmp.true
@@ -7415,6 +7656,7 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8659,6 +8901,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -8702,6 +8945,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
; VI-NEXT: v_add_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -8734,6 +8978,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v2, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v3, v10, v11, s6
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr13
@@ -8777,6 +9022,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -8799,11 +9045,23 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB40_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v16, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v14, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
@@ -8818,6 +9076,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
@@ -8854,6 +9113,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -8893,6 +9153,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
@@ -8938,6 +9199,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -9087,6 +9349,7 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_cbranch_execnz .LBB41_3
; VI-NEXT: .LBB41_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9120,6 +9383,7 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB41_3: ; %end
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB41_4:
@@ -9151,6 +9415,7 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_cbranch_execnz .LBB41_3
; GFX9-NEXT: .LBB41_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9182,6 +9447,7 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
; GFX9-NEXT: v_add_u32_sdwa v2, v2, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: .LBB41_3: ; %end
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB41_4:
@@ -9211,6 +9477,7 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX11-NEXT: v_or_b32_e32 v1, v5, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v2, v6, v3
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB41_3
; GFX11-NEXT: .LBB41_2: ; %cmp.true
@@ -9242,6 +9509,7 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB41_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10022,6 +10290,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -10065,6 +10334,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
; VI-NEXT: v_add_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -10097,6 +10367,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v2, v8, v9, s6
; GFX9-NEXT: v_perm_b32 v3, v10, v11, s6
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; implicit-def: $vgpr15
; GFX9-NEXT: ; implicit-def: $vgpr14
; GFX9-NEXT: ; implicit-def: $vgpr13
@@ -10140,6 +10411,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -10162,11 +10434,23 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB44_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v16, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v14, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v10, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
@@ -10181,6 +10465,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
@@ -10217,6 +10502,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v2.h
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10256,6 +10542,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
@@ -10301,6 +10588,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -10450,6 +10738,7 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_cbranch_execnz .LBB45_3
; VI-NEXT: .LBB45_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -10483,6 +10772,7 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB45_3: ; %end
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB45_4:
@@ -10514,6 +10804,7 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_cbranch_execnz .LBB45_3
; GFX9-NEXT: .LBB45_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -10545,6 +10836,7 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
; GFX9-NEXT: v_add_u32_sdwa v2, v2, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: .LBB45_3: ; %end
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB45_4:
@@ -10574,6 +10866,7 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: v_or_b32_e32 v1, v5, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v2, v6, v3
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB45_3
; GFX11-NEXT: .LBB45_2: ; %cmp.true
@@ -10605,6 +10898,7 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB45_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11356,6 +11650,7 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_alignbit_b32 v2, v2, v5, 16
; VI-NEXT: v_alignbit_b32 v1, v1, v4, 16
; VI-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB48_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -11416,6 +11711,7 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v2, v5, v2, s6
; GFX9-NEXT: v_perm_b32 v1, v4, v1, s6
; GFX9-NEXT: v_perm_b32 v0, v3, v0, s6
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: .LBB48_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -11467,6 +11763,7 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -11557,6 +11854,7 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v3, v0, 0x7060302
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: .LBB48_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -11708,6 +12006,7 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; VI-NEXT: v_lshrrev_b64 v[3:4], 16, v[4:5]
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, v3
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB49_3:
; VI-NEXT: s_branch .LBB49_2
@@ -11785,6 +12084,7 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v0
; GFX9-NEXT: v_and_b32_sdwa v0, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB49_3:
; GFX9-NEXT: s_branch .LBB49_2
@@ -11864,6 +12164,7 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
@@ -11950,6 +12251,7 @@ define inreg <6 x half> @bitcast_v6bf16_to_v6f16_scalar(<6 x bfloat> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB49_3:
@@ -12067,6 +12369,7 @@ define <6 x bfloat> @bitcast_v6f16_to_v6bf16(<6 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v6, v2
; VI-NEXT: v_or_b32_e32 v1, v5, v1
; VI-NEXT: v_or_b32_e32 v0, v3, v0
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB50_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12083,6 +12386,7 @@ define <6 x bfloat> @bitcast_v6f16_to_v6bf16(<6 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12099,6 +12403,7 @@ define <6 x bfloat> @bitcast_v6f16_to_v6bf16(<6 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -12216,6 +12521,7 @@ define inreg <6 x bfloat> @bitcast_v6f16_to_v6bf16_scalar(<6 x half> inreg %a, i
; VI-NEXT: v_or_b32_e32 v2, v2, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_or_b32_e32 v0, v3, v4
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB51_3:
; VI-NEXT: s_branch .LBB51_2
@@ -12238,6 +12544,7 @@ define inreg <6 x bfloat> @bitcast_v6f16_to_v6bf16_scalar(<6 x half> inreg %a, i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB51_3:
; GFX9-NEXT: s_branch .LBB51_2
@@ -12261,6 +12568,7 @@ define inreg <6 x bfloat> @bitcast_v6f16_to_v6bf16_scalar(<6 x half> inreg %a, i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_3:
; GFX11-NEXT: s_branch .LBB51_2
@@ -12424,6 +12732,7 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_alignbit_b32 v2, v2, v5, 16
; VI-NEXT: v_alignbit_b32 v1, v1, v4, 16
; VI-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB52_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -12484,6 +12793,7 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; GFX9-NEXT: v_perm_b32 v2, v5, v2, s6
; GFX9-NEXT: v_perm_b32 v1, v4, v1, s6
; GFX9-NEXT: v_perm_b32 v0, v3, v0, s6
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: .LBB52_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -12532,6 +12842,7 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
@@ -12620,6 +12931,7 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x7060302
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v3, v0, 0x7060302
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: .LBB52_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -12771,6 +13083,7 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; VI-NEXT: v_lshrrev_b64 v[3:4], 16, v[4:5]
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; VI-NEXT: v_mov_b32_e32 v1, v3
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB53_3:
; VI-NEXT: s_branch .LBB53_2
@@ -12845,6 +13158,7 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; GFX9-NEXT: v_and_or_b32 v1, v1, v6, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v4
; GFX9-NEXT: v_and_or_b32 v0, v3, v6, v0
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB53_3:
; GFX9-NEXT: s_branch .LBB53_2
@@ -12913,6 +13227,7 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.h
@@ -12993,6 +13308,7 @@ define inreg <6 x i16> @bitcast_v6bf16_to_v6i16_scalar(<6 x bfloat> inreg %a, i3
; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0xffff0000, v3, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffff0000, v0, v7
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB53_3:
; GFX11-FAKE16-NEXT: s_branch .LBB53_2
@@ -13097,6 +13413,7 @@ define <6 x bfloat> @bitcast_v6i16_to_v6bf16(<6 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_or_b32_e32 v0, v0, v4
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB54_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -13112,6 +13429,7 @@ define <6 x bfloat> @bitcast_v6i16_to_v6bf16(<6 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -13128,6 +13446,7 @@ define <6 x bfloat> @bitcast_v6i16_to_v6bf16(<6 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13233,6 +13552,7 @@ define inreg <6 x bfloat> @bitcast_v6i16_to_v6bf16_scalar(<6 x i16> inreg %a, i3
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB55_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -13252,6 +13572,7 @@ define inreg <6 x bfloat> @bitcast_v6i16_to_v6bf16_scalar(<6 x i16> inreg %a, i3
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB55_3:
; GFX9-NEXT: s_branch .LBB55_2
@@ -13275,6 +13596,7 @@ define inreg <6 x bfloat> @bitcast_v6i16_to_v6bf16_scalar(<6 x i16> inreg %a, i3
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_3:
; GFX11-NEXT: s_branch .LBB55_2
@@ -13369,6 +13691,7 @@ define <6 x i16> @bitcast_v6f16_to_v6i16(<6 x half> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v6, v2
; VI-NEXT: v_or_b32_e32 v1, v5, v1
; VI-NEXT: v_or_b32_e32 v0, v3, v0
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB56_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -13385,6 +13708,7 @@ define <6 x i16> @bitcast_v6f16_to_v6i16(<6 x half> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -13401,6 +13725,7 @@ define <6 x i16> @bitcast_v6f16_to_v6i16(<6 x half> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13504,6 +13829,7 @@ define inreg <6 x i16> @bitcast_v6f16_to_v6i16_scalar(<6 x half> inreg %a, i32 i
; VI-NEXT: v_or_b32_e32 v2, v2, v0
; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_or_b32_e32 v0, v3, v4
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB57_3:
; VI-NEXT: s_branch .LBB57_2
@@ -13526,6 +13852,7 @@ define inreg <6 x i16> @bitcast_v6f16_to_v6i16_scalar(<6 x half> inreg %a, i32 i
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB57_3:
; GFX9-NEXT: s_branch .LBB57_2
@@ -13549,6 +13876,7 @@ define inreg <6 x i16> @bitcast_v6f16_to_v6i16_scalar(<6 x half> inreg %a, i32 i
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB57_3:
; GFX11-NEXT: s_branch .LBB57_2
@@ -13655,6 +13983,7 @@ define <6 x half> @bitcast_v6i16_to_v6f16(<6 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_or_b32_e32 v0, v0, v4
+; VI-NEXT: ; implicit-def: $vgpr3
; VI-NEXT: .LBB58_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -13670,6 +13999,7 @@ define <6 x half> @bitcast_v6i16_to_v6f16(<6 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -13686,6 +14016,7 @@ define <6 x half> @bitcast_v6i16_to_v6f16(<6 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13790,6 +14121,7 @@ define inreg <6 x half> @bitcast_v6i16_to_v6f16_scalar(<6 x i16> inreg %a, i32 i
; VI-NEXT: s_add_i32 s18, s8, 0x30000
; VI-NEXT: s_add_i32 s17, s6, 0x30000
; VI-NEXT: s_add_i32 s16, s4, 0x30000
+; VI-NEXT: ; implicit-def: $sgpr4
; VI-NEXT: .LBB59_3: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
@@ -13809,6 +14141,7 @@ define inreg <6 x half> @bitcast_v6i16_to_v6f16_scalar(<6 x i16> inreg %a, i32 i
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB59_3:
; GFX9-NEXT: s_branch .LBB59_2
@@ -13832,6 +14165,7 @@ define inreg <6 x half> @bitcast_v6i16_to_v6f16_scalar(<6 x i16> inreg %a, i32 i
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: ; implicit-def: $vgpr3
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB59_3:
; GFX11-NEXT: s_branch .LBB59_2
diff --git a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
index aa161a8093532..df58e68e331ff 100644
--- a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
@@ -6,47 +6,47 @@
define amdgpu_kernel void @any_extend_vector_inreg_v16i8_to_v4i32(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) %arg1) local_unnamed_addr #0 {
; GFX6-LABEL: any_extend_vector_inreg_v16i8_to_v4i32:
; GFX6: ; %bb.0: ; %bb
-; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
-; GFX6-NEXT: s_mov_b32 s15, 0xf000
-; GFX6-NEXT: s_mov_b32 s14, -1
+; GFX6-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: ; implicit-def: $sgpr17
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0
+; GFX6-NEXT: s_load_dwordx8 s[4:11], s[12:13], 0x0
+; GFX6-NEXT: s_load_dword s16, s[12:13], 0x8
+; GFX6-NEXT: s_mov_b32 s0, s14
+; GFX6-NEXT: s_mov_b32 s1, s15
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:13
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_load_dword s0, s[8:9], 0x8
-; GFX6-NEXT: s_mov_b32 s12, s10
-; GFX6-NEXT: s_mov_b32 s13, s11
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:13
-; GFX6-NEXT: s_lshr_b32 s3, s5, 16
-; GFX6-NEXT: v_mov_b32_e32 v1, s7
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshl_b64 s[4:5], s[0:1], 8
-; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], 16
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:15
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:14
-; GFX6-NEXT: buffer_store_byte v1, off, s[12:15], 0 offset:9
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:8
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:11
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:10
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:4
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:6
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:1
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:3
-; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s1
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:2
+; GFX6-NEXT: s_lshr_b32 s7, s9, 16
+; GFX6-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NEXT: s_lshl_b64 s[8:9], s[16:17], 8
+; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], 16
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:15
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:14
+; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:9
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:8
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:11
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:10
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:4
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:6
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:1
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:3
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s5
-; GFX6-NEXT: s_lshr_b32 s0, s2, 8
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:12
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:2
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: s_lshr_b32 s0, s2, 24
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:5
+; GFX6-NEXT: v_mov_b32_e32 v0, s9
+; GFX6-NEXT: s_lshr_b32 s4, s6, 8
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:12
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: buffer_store_byte v0, off, s[12:15], 0 offset:7
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: s_lshr_b32 s4, s6, 24
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:5
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:7
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: any_extend_vector_inreg_v16i8_to_v4i32:
@@ -55,12 +55,12 @@ define amdgpu_kernel void @any_extend_vector_inreg_v16i8_to_v4i32(ptr addrspace(
; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0
+; GFX8-NEXT: s_load_dword s8, s[8:9], 0x20
+; GFX8-NEXT: ; implicit-def: $sgpr9
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_load_dword s0, s[8:9], 0x20
; GFX8-NEXT: s_lshr_b32 s6, s5, 24
-; GFX8-NEXT: s_lshr_b32 s8, s2, 24
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], 8
+; GFX8-NEXT: s_lshr_b32 s12, s2, 24
+; GFX8-NEXT: s_lshl_b64 s[2:3], s[8:9], 8
; GFX8-NEXT: s_add_u32 s4, s10, 13
; GFX8-NEXT: s_addc_u32 s5, s11, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s4
@@ -130,7 +130,7 @@ define amdgpu_kernel void @any_extend_vector_inreg_v16i8_to_v4i32(ptr addrspace(
; GFX8-NEXT: s_addc_u32 s1, s11, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_mov_b32_e32 v2, s8
+; GFX8-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NEXT: s_add_u32 s0, s10, 12
; GFX8-NEXT: flat_store_byte v[0:1], v2
; GFX8-NEXT: s_addc_u32 s1, s11, 0
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
index 45fd64b45a98d..2016fc3d67c4d 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
@@ -455,6 +455,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
; GFX10W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX10W64-NEXT: ; implicit-def: $sgpr3
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s6, v0, s[2:3]
; GFX10W64-NEXT: v_mov_b32_e32 v1, 0
@@ -484,6 +485,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
; GFX10W32-NEXT: s_mov_b32 null, 0
; GFX10W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX10W32-NEXT: ; implicit-def: $sgpr5
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: v_mad_u64_u32 v[0:1], s0, s0, v0, s[4:5]
; GFX10W32-NEXT: v_mov_b32_e32 v1, 0
@@ -514,6 +516,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11W64-NEXT: s_waitcnt vmcnt(0)
; GFX11W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX11W64-NEXT: ; implicit-def: $sgpr3
; GFX11W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11W64-NEXT: v_mad_u64_u32 v[1:2], null, s6, v0, s[2:3]
@@ -544,6 +547,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11W32-NEXT: s_waitcnt vmcnt(0)
; GFX11W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11W32-NEXT: ; implicit-def: $sgpr5
; GFX11W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11W32-NEXT: v_mad_u64_u32 v[1:2], null, s0, v0, s[4:5]
@@ -576,6 +580,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12W64-NEXT: ; implicit-def: $sgpr3
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -608,6 +613,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX12W32-NEXT: ; implicit-def: $sgpr5
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
@@ -639,6 +645,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX13W64-NEXT: s_wait_loadcnt 0x0
; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: ; implicit-def: $sgpr3
; GFX13W64-NEXT: s_wait_kmcnt 0x0
; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX13W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
@@ -669,6 +676,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
; GFX13W32-NEXT: s_wait_loadcnt 0x0
; GFX13W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX13W32-NEXT: ; implicit-def: $sgpr5
; GFX13W32-NEXT: s_wait_kmcnt 0x0
; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX13W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index 12548e219125e..40d7436016337 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -541,6 +541,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1064-NEXT: ; implicit-def: $sgpr3
; GFX1064-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s8, v0, s[2:3]
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
; GFX1064-NEXT: s_mov_b32 s2, -1
@@ -576,6 +577,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1032-NEXT: ; implicit-def: $sgpr3
; GFX1032-NEXT: v_mad_u64_u32 v[0:1], s2, s6, v0, s[2:3]
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
; GFX1032-NEXT: s_mov_b32 s2, -1
@@ -612,6 +614,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1164-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1164-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1164-NEXT: ; implicit-def: $sgpr3
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_mad_u64_u32 v[1:2], null, s8, v0, s[2:3]
; GFX1164-NEXT: s_mov_b32 s3, 0x31016000
@@ -648,6 +651,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1132-NEXT: s_or_b32 exec_lo, exec_lo, s5
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1132-NEXT: ; implicit-def: $sgpr3
; GFX1132-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132-NEXT: v_mad_u64_u32 v[1:2], null, s4, v0, s[2:3]
; GFX1132-NEXT: s_mov_b32 s3, 0x31016000
@@ -686,6 +690,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1264-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1264-NEXT: s_wait_kmcnt 0x0
; GFX1264-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1264-NEXT: ; implicit-def: $sgpr3
; GFX1264-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-NEXT: v_mad_co_u64_u32 v[0:1], null, s8, v0, s[2:3]
; GFX1264-NEXT: s_mov_b32 s3, 0x31016000
@@ -723,6 +728,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: s_or_b32 exec_lo, exec_lo, s5
; GFX1232-NEXT: s_wait_kmcnt 0x0
; GFX1232-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1232-NEXT: ; implicit-def: $sgpr3
; GFX1232-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-NEXT: v_mad_co_u64_u32 v[0:1], null, s4, v0, s[2:3]
; GFX1232-NEXT: s_mov_b32 s3, 0x31016000
@@ -762,6 +768,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1364-NEXT: s_wait_kmcnt 0x0
; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: ; implicit-def: $sgpr3
; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1364-NEXT: v_mad_co_u64_u32 v[0:1], null, s8, v0, s[2:3]
; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
@@ -800,6 +807,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s5
; GFX1332-NEXT: s_wait_kmcnt 0x0
; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: ; implicit-def: $sgpr3
; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1332-NEXT: v_mad_co_u64_u32 v[0:1], null, s4, v0, s[2:3]
; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
@@ -9682,6 +9690,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1164-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
; GFX1164-TRUE16-NEXT: .LBB12_4: ; %Flow
; GFX1164-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1164-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1164-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -9790,6 +9799,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1132-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
; GFX1132-TRUE16-NEXT: .LBB12_4: ; %Flow
; GFX1132-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1132-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1132-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1132-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -9898,6 +9908,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1264-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
; GFX1264-TRUE16-NEXT: .LBB12_4: ; %Flow
; GFX1264-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1264-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -10010,6 +10021,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1232-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
; GFX1232-TRUE16-NEXT: .LBB12_4: ; %Flow
; GFX1232-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1232-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1232-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -10121,6 +10133,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
; GFX1364-TRUE16-NEXT: .LBB12_4: ; %Flow
; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1364-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -10227,6 +10240,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
; GFX1332-TRUE16-NEXT: .LBB12_4: ; %Flow
; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1332-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1332-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -10636,6 +10650,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1164-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
; GFX1164-TRUE16-NEXT: .LBB13_4: ; %Flow
; GFX1164-TRUE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1164-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1164-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -10759,6 +10774,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1132-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
; GFX1132-TRUE16-NEXT: .LBB13_4: ; %Flow
; GFX1132-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1132-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1132-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -10882,6 +10898,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1264-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
; GFX1264-TRUE16-NEXT: .LBB13_4: ; %Flow
; GFX1264-TRUE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1264-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1264-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -11010,6 +11027,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1232-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
; GFX1232-TRUE16-NEXT: .LBB13_4: ; %Flow
; GFX1232-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1232-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1232-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -11136,6 +11154,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
; GFX1364-TRUE16-NEXT: .LBB13_4: ; %Flow
; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1364-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -11256,6 +11275,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
; GFX1332-TRUE16-NEXT: .LBB13_4: ; %Flow
; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1332-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -12082,6 +12102,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1164-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
; GFX1164-TRUE16-NEXT: .LBB15_4: ; %Flow
; GFX1164-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1164-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1164-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -12190,6 +12211,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1132-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
; GFX1132-TRUE16-NEXT: .LBB15_4: ; %Flow
; GFX1132-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1132-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1132-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1132-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -12298,6 +12320,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1264-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
; GFX1264-TRUE16-NEXT: .LBB15_4: ; %Flow
; GFX1264-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1264-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -12410,6 +12433,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1232-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
; GFX1232-TRUE16-NEXT: .LBB15_4: ; %Flow
; GFX1232-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1232-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1232-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -12521,6 +12545,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
; GFX1364-TRUE16-NEXT: .LBB15_4: ; %Flow
; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1364-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -12627,6 +12652,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
; GFX1332-TRUE16-NEXT: .LBB15_4: ; %Flow
; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1332-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1332-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -13036,6 +13062,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1164-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
; GFX1164-TRUE16-NEXT: .LBB16_4: ; %Flow
; GFX1164-TRUE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1164-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1164-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -13159,6 +13186,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1132-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
; GFX1132-TRUE16-NEXT: .LBB16_4: ; %Flow
; GFX1132-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1132-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1132-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -13282,6 +13310,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1264-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
; GFX1264-TRUE16-NEXT: .LBB16_4: ; %Flow
; GFX1264-TRUE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1264-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1264-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -13410,6 +13439,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1232-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
; GFX1232-TRUE16-NEXT: .LBB16_4: ; %Flow
; GFX1232-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1232-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1232-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -13536,6 +13566,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
; GFX1364-TRUE16-NEXT: .LBB16_4: ; %Flow
; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1364-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
@@ -13656,6 +13687,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
; GFX1332-TRUE16-NEXT: .LBB16_4: ; %Flow
; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1332-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 2c6d1ee4d24b2..c4198c79747bc 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -402,6 +402,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1064-NEXT: ; implicit-def: $sgpr3
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s6, v0, s[2:3]
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
@@ -432,6 +433,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1032-NEXT: ; implicit-def: $sgpr3
; GFX1032-NEXT: s_mov_b32 s11, 0x31016000
; GFX1032-NEXT: s_mov_b32 s10, -1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
@@ -464,6 +466,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1164-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1164-NEXT: ; implicit-def: $sgpr3
; GFX1164-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_mad_u64_u32 v[1:2], null, s6, v0, s[2:3]
@@ -495,6 +498,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1132-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1132-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX1132-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1132-NEXT: ; implicit-def: $sgpr3
; GFX1132-NEXT: s_mov_b32 s7, 0x31016000
; GFX1132-NEXT: s_mov_b32 s6, -1
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
@@ -527,6 +531,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: ; implicit-def: $sgpr3
; GFX1364-NEXT: s_wait_kmcnt 0x0
; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1364-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
@@ -558,6 +563,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1332-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: ; implicit-def: $sgpr3
; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
; GFX1332-NEXT: s_mov_b32 s6, -1
; GFX1332-NEXT: s_wait_kmcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
index e78a4f4fc7474..600abe1e7697d 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
@@ -454,6 +454,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
; GFX10W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX10W64-NEXT: ; implicit-def: $sgpr3
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s6, v0, s[2:3]
; GFX10W64-NEXT: v_mov_b32_e32 v1, 0
@@ -483,6 +484,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
; GFX10W32-NEXT: s_mov_b32 null, 0
; GFX10W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX10W32-NEXT: ; implicit-def: $sgpr5
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: v_mad_u64_u32 v[0:1], s0, s0, v0, s[4:5]
; GFX10W32-NEXT: v_mov_b32_e32 v1, 0
@@ -513,6 +515,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11W64-NEXT: s_waitcnt vmcnt(0)
; GFX11W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX11W64-NEXT: ; implicit-def: $sgpr3
; GFX11W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11W64-NEXT: v_mad_u64_u32 v[1:2], null, s6, v0, s[2:3]
@@ -543,6 +546,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11W32-NEXT: s_waitcnt vmcnt(0)
; GFX11W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11W32-NEXT: ; implicit-def: $sgpr5
; GFX11W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11W32-NEXT: v_mad_u64_u32 v[1:2], null, s0, v0, s[4:5]
@@ -575,6 +579,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12W64-NEXT: ; implicit-def: $sgpr3
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -607,6 +612,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX12W32-NEXT: ; implicit-def: $sgpr5
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
@@ -638,6 +644,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX13W64-NEXT: s_wait_loadcnt 0x0
; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: ; implicit-def: $sgpr3
; GFX13W64-NEXT: s_wait_kmcnt 0x0
; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX13W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
@@ -668,6 +675,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
; GFX13W32-NEXT: s_wait_loadcnt 0x0
; GFX13W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX13W32-NEXT: ; implicit-def: $sgpr5
; GFX13W32-NEXT: s_wait_kmcnt 0x0
; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX13W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
index 4ae6f053f3c96..a7714620a9141 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
@@ -467,6 +467,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
; GFX10W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX10W64-NEXT: ; implicit-def: $sgpr3
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s6, v0, s[2:3]
; GFX10W64-NEXT: v_mov_b32_e32 v1, 0
@@ -497,6 +498,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
; GFX10W32-NEXT: s_mov_b32 null, 0
; GFX10W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX10W32-NEXT: ; implicit-def: $sgpr5
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: v_mad_u64_u32 v[0:1], s0, s0, v0, s[4:5]
; GFX10W32-NEXT: v_mov_b32_e32 v1, 0
@@ -528,6 +530,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11W64-NEXT: s_waitcnt vmcnt(0)
; GFX11W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX11W64-NEXT: ; implicit-def: $sgpr3
; GFX11W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11W64-NEXT: v_mad_u64_u32 v[1:2], null, s6, v0, s[2:3]
@@ -559,6 +562,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11W32-NEXT: s_waitcnt vmcnt(0)
; GFX11W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11W32-NEXT: ; implicit-def: $sgpr5
; GFX11W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11W32-NEXT: v_mad_u64_u32 v[1:2], null, s0, v0, s[4:5]
@@ -592,6 +596,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12W64-NEXT: ; implicit-def: $sgpr3
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -624,6 +629,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX12W32-NEXT: ; implicit-def: $sgpr5
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
@@ -656,6 +662,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX13W64-NEXT: s_wait_loadcnt 0x0
; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: ; implicit-def: $sgpr3
; GFX13W64-NEXT: s_wait_kmcnt 0x0
; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX13W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
@@ -686,6 +693,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
; GFX13W32-NEXT: s_wait_loadcnt 0x0
; GFX13W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX13W32-NEXT: ; implicit-def: $sgpr5
; GFX13W32-NEXT: s_wait_kmcnt 0x0
; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX13W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll b/llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
index b0fae21a88484..c6d1f84f380a6 100644
--- a/llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
@@ -2242,6 +2242,7 @@ define i8 @global_atomic_usub_sat_8(ptr addrspace(1) %ptr, i8 %data) {
; GFX11-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, v3
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_lshlrev_b16 v2.h, 8, v4.l
; GFX11-GISEL-NEXT: v_sub_nc_u16 v2.h, v2.h, v2.l clamp
@@ -2279,6 +2280,7 @@ define i8 @global_atomic_usub_sat_8(ptr addrspace(1) %ptr, i8 %data) {
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, v3
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_lshlrev_b16 v2.h, 8, v4.l
; GFX12-GISEL-NEXT: v_sub_nc_u16 v2.h, v2.h, v2.l clamp
@@ -2492,6 +2494,7 @@ define i8 @global_atomic_usub_sat_offset_8(ptr addrspace(1) %ptr, i8 %data) {
; GFX11-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, v3
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_lshlrev_b16 v2.h, 8, v4.l
; GFX11-GISEL-NEXT: v_sub_nc_u16 v2.h, v2.h, v2.l clamp
@@ -2529,6 +2532,7 @@ define i8 @global_atomic_usub_sat_offset_8(ptr addrspace(1) %ptr, i8 %data) {
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, v3
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_lshlrev_b16 v2.h, 8, v4.l
; GFX12-GISEL-NEXT: v_sub_nc_u16 v2.h, v2.h, v2.l clamp
@@ -2741,6 +2745,7 @@ define void @global_atomic_usub_sat_nortn_8(ptr addrspace(1) %ptr, i8 %data) {
; GFX11-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_lshlrev_b16 v2.h, 8, v4.l
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_sub_nc_u16 v2.h, v2.h, v2.l clamp
; GFX11-GISEL-NEXT: v_lshrrev_b16 v3.l, 8, v2.h
@@ -2776,6 +2781,7 @@ define void @global_atomic_usub_sat_nortn_8(ptr addrspace(1) %ptr, i8 %data) {
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_lshlrev_b16 v2.h, 8, v4.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_sub_nc_u16 v2.h, v2.h, v2.l clamp
; GFX12-GISEL-NEXT: v_lshrrev_b16 v3.l, 8, v2.h
@@ -2979,6 +2985,7 @@ define void @global_atomic_usub_sat_offset_nortn_8(ptr addrspace(1) %ptr, i8 %da
; GFX11-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_lshlrev_b16 v2.h, 8, v4.l
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_sub_nc_u16 v2.h, v2.h, v2.l clamp
; GFX11-GISEL-NEXT: v_lshrrev_b16 v3.l, 8, v2.h
@@ -3014,6 +3021,7 @@ define void @global_atomic_usub_sat_offset_nortn_8(ptr addrspace(1) %ptr, i8 %da
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_lshlrev_b16 v2.h, 8, v4.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_sub_nc_u16 v2.h, v2.h, v2.l clamp
; GFX12-GISEL-NEXT: v_lshrrev_b16 v3.l, 8, v2.h
@@ -3240,6 +3248,7 @@ define amdgpu_kernel void @global_atomic_usub_sat_sgpr_base_offset_8(ptr addrspa
; GFX11-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, v1
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-NEXT: v_lshlrev_b16 v1.l, 8, v2.l
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_sub_nc_u16 v1.l, v1.l, s3 clamp
@@ -3278,6 +3287,7 @@ define amdgpu_kernel void @global_atomic_usub_sat_sgpr_base_offset_8(ptr addrspa
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, v1
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-NEXT: v_lshlrev_b16 v1.l, 8, v2.l
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_sub_nc_u16 v1.l, v1.l, s2 clamp
@@ -3527,6 +3537,7 @@ define amdgpu_kernel void @global_atomic_usub_sat_sgpr_base_offset_nortn_8(ptr a
; GFX11-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_lshlrev_b16 v0.l, 8, v1.l
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: v_sub_nc_u16 v0.l, v0.l, s3 clamp
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
@@ -3560,6 +3571,7 @@ define amdgpu_kernel void @global_atomic_usub_sat_sgpr_base_offset_nortn_8(ptr a
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_lshlrev_b16 v0.l, 8, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-NEXT: v_sub_nc_u16 v0.l, v0.l, s2 clamp
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-math.ll b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
index fd1db62371aa9..6a8dd933055db 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-math.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
@@ -371,6 +371,7 @@ define amdgpu_ps bfloat @test_clamp_bf16(bfloat %src) {
; TRUE16-LABEL: test_clamp_bf16:
; TRUE16: ; %bb.0:
; TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; TRUE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
; TRUE16-NEXT: ; return to shader part epilog
;
@@ -389,6 +390,7 @@ define amdgpu_ps bfloat @test_clamp_bf16_s(bfloat inreg %src) {
; TRUE16: ; %bb.0:
; TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; TRUE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
; TRUE16-NEXT: ; return to shader part epilog
@@ -408,6 +410,7 @@ define amdgpu_ps float @test_clamp_bf16_hi16(<2 x bfloat> %src) {
; TRUE16: ; %bb.0:
; TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; TRUE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
; TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
@@ -433,6 +436,7 @@ define amdgpu_ps float @test_clamp_bf16_hi16_s(<2 x bfloat> inreg %src) {
; TRUE16: ; %bb.0:
; TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; TRUE16-NEXT: s_lshr_b32 s0, s0, 16
+; TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
; TRUE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
@@ -484,6 +488,7 @@ define amdgpu_ps bfloat @test_clamp_bf16_folding(bfloat %src) {
; TRUE16: ; %bb.0:
; TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; TRUE16-NEXT: v_exp_bf16_e32 v0.l, v0.l
+; TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; TRUE16-NEXT: v_nop
; TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; TRUE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index aa165abe785d6..300f3f437c75d 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -9592,14 +9592,25 @@ define bfloat @v_fadd_bf16(bfloat %a, bfloat %b) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_fadd_bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_fadd_bf16:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_fadd_bf16:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%op = fadd bfloat %a, %b
ret bfloat %op
}
@@ -9960,6 +9971,7 @@ define <3 x bfloat> @v_fadd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fadd_v3bf16:
@@ -13738,15 +13750,26 @@ define bfloat @v_fadd_bf16_fpimm_0(bfloat %arg0) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_fadd_bf16_fpimm_0:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s0, 1.0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_fadd_bf16_fpimm_0:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: s_mov_b32 s0, 1.0
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_fadd_bf16_fpimm_0:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: s_mov_b32 s0, 1.0
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%add = fadd bfloat %arg0, 1.0
ret bfloat %add
}
@@ -13849,15 +13872,26 @@ define bfloat @v_fadd_bf16_fpimm_1(bfloat %arg0) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_fadd_bf16_fpimm_1:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s0, 0x42280000
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_fadd_bf16_fpimm_1:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x42280000
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_fadd_bf16_fpimm_1:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x42280000
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%add = fadd bfloat %arg0, 42.0
ret bfloat %add
}
@@ -13968,14 +14002,25 @@ define bfloat @v_fsub_bf16(bfloat %a, bfloat %b) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_fsub_bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_fsub_bf16:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_fsub_bf16:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%op = fsub bfloat %a, %b
ret bfloat %op
}
@@ -14336,6 +14381,7 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fsub_v3bf16:
@@ -14770,12 +14816,21 @@ define bfloat @v_fmul_bf16(bfloat %a, bfloat %b) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_fmul_bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, 0 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_fmul_bf16:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, 0 op_sel_hi:[1,1,0]
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_fmul_bf16:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, 0 op_sel_hi:[1,1,0]
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%op = fmul bfloat %a, %b
ret bfloat %op
}
@@ -15136,6 +15191,7 @@ define <3 x bfloat> @v_fmul_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmul_v3bf16:
@@ -19890,6 +19946,7 @@ define <3 x bfloat> @v_minnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_minnum_v3bf16:
@@ -24318,6 +24375,7 @@ define <3 x bfloat> @v_maxnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_maxnum_v3bf16:
@@ -30476,6 +30534,7 @@ define bfloat @v_exp_bf16(bfloat %a) #0 {
; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x3fb8aa3b
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v2, v1, s0, neg(0) op_sel_hi:[1,0,0]
@@ -30944,6 +31003,7 @@ define bfloat @v_exp10_bf16(bfloat %a) #0 {
; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x40549a78
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v2, v1, s0, neg(0) op_sel_hi:[1,0,0]
@@ -31605,23 +31665,42 @@ define bfloat @v_round_bf16(bfloat %a) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_round_bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_lshlrev_b32_e32 v1, 16, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_trunc_f32_e32 v2, v1
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v2, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_cmp_ge_f32_e64 s0, |v0|, 0.5
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
-; GFX1250-NEXT: v_add_f32_e32 v0, v2, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_round_bf16:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_trunc_f32_e32 v2, v1
+; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v2, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_cmp_ge_f32_e64 s0, |v0|, 0.5
+; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
+; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_round_bf16:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_trunc_f32_e32 v2, v1
+; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v2, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_cmp_ge_f32_e64 s0, |v0|, 0.5
+; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
+; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%op = call bfloat @llvm.round.bf16(bfloat %a)
ret bfloat %op
}
@@ -33320,27 +33399,51 @@ define <3 x i16> @v_fptosi_v3bf16_to_v3i16(<3 x bfloat> %x) #0 {
; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fptosi_v3bf16_to_v3i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cvt_pk_i16_f32 v0, v0, v2
-; GFX11-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fptosi_v3bf16_to_v3i16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cvt_pk_i16_f32 v0, v0, v2
+; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_fptosi_v3bf16_to_v3i16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_cvt_pk_i16_f32 v0, v0, v2
-; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX11FAKE16-LABEL: v_fptosi_v3bf16_to_v3i16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cvt_pk_i16_f32 v0, v0, v2
+; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250TRUE16-LABEL: v_fptosi_v3bf16_to_v3i16:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250TRUE16-NEXT: v_cvt_pk_i16_f32 v0, v0, v2
+; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_fptosi_v3bf16_to_v3i16:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
+; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250FAKE16-NEXT: v_cvt_pk_i16_f32 v0, v0, v2
+; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%op = fptosi <3 x bfloat> %x to <3 x i16>
ret <3 x i16> %op
}
@@ -35106,6 +35209,7 @@ define bfloat @v_sitofp_i16_to_bf16(i16 %x) #0 {
;
; GFX11TRUE16-LABEL: v_sitofp_i16_to_bf16:
; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -35136,15 +35240,26 @@ define bfloat @v_sitofp_i16_to_bf16(i16 %x) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_sitofp_i16_to_bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_sitofp_i16_to_bf16:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_sitofp_i16_to_bf16:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%op = sitofp i16 %x to bfloat
ret bfloat %op
}
@@ -35454,6 +35569,7 @@ define <3 x bfloat> @v_sitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v3i16_to_v3bf16:
@@ -35502,6 +35618,7 @@ define <3 x bfloat> @v_sitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
@@ -36152,6 +36269,7 @@ define <3 x bfloat> @v_sitofp_v3i32_to_v3bf16(<3 x i32> %x) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
@@ -36195,6 +36313,7 @@ define <3 x bfloat> @v_sitofp_v3i32_to_v3bf16(<3 x i32> %x) #0 {
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
@@ -37389,6 +37508,7 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) #0 {
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v3i64_to_v3bf16:
@@ -37507,6 +37627,7 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) #0 {
; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v0, v5
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -38646,6 +38767,7 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v3i16_to_v3bf16:
@@ -38698,6 +38820,7 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v3, v0, s0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v1, v2
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -39373,6 +39496,7 @@ define <3 x bfloat> @v_uitofp_v3i32_to_v3bf16(<3 x i32> %x) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
@@ -39416,6 +39540,7 @@ define <3 x bfloat> @v_uitofp_v3i32_to_v3bf16(<3 x i32> %x) #0 {
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
@@ -40408,6 +40533,7 @@ define <3 x bfloat> @v_uitofp_v3i64_to_v3bf16(<3 x i64> %x) #0 {
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v3i64_to_v3bf16:
@@ -40504,6 +40630,7 @@ define <3 x bfloat> @v_uitofp_v3i64_to_v3bf16(<3 x i64> %x) #0 {
; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v0, v5
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -46617,12 +46744,22 @@ define bfloat @v_fma_bf16(bfloat %a, bfloat %b, bfloat %c) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_fma_bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_fma_bf16:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_fma_bf16:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%op = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c)
ret bfloat %op
}
@@ -47019,6 +47156,7 @@ define <3 x bfloat> @v_fma_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat>
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fma_v3bf16:
@@ -51585,12 +51723,22 @@ define bfloat @v_fmuladd_bf16(bfloat %a, bfloat %b, bfloat %c) #0 {
; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: v_fmuladd_bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250TRUE16-LABEL: v_fmuladd_bf16:
+; GFX1250TRUE16: ; %bb.0:
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250TRUE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250FAKE16-LABEL: v_fmuladd_bf16:
+; GFX1250FAKE16: ; %bb.0:
+; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
%op = call bfloat @llvm.fmuladd.bf16(bfloat %a, bfloat %b, bfloat %c)
ret bfloat %op
}
@@ -52007,6 +52155,7 @@ define <3 x bfloat> @v_fmuladd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfl
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmuladd_v3bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/bitop3.ll b/llvm/test/CodeGen/AMDGPU/bitop3.ll
index a4c5d5649c226..7e3fcafbcc758 100644
--- a/llvm/test/CodeGen/AMDGPU/bitop3.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitop3.ll
@@ -555,6 +555,7 @@ define amdgpu_ps half @not_and_not_and_not_and_b16(i16 %a, i16 %b, i16 %c) {
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:1
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%nota = xor i16 %a, -1
%notb = xor i16 %b, -1
@@ -593,6 +594,7 @@ define amdgpu_ps half @not_and_not_and_and_b16(i16 %a, i16 %b, i16 %c) {
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:2
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%nota = xor i16 %a, -1
%notb = xor i16 %b, -1
@@ -630,6 +632,7 @@ define amdgpu_ps half @not_and_and_not_and_b16(i16 %a, i16 %b, i16 %c) {
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:4
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%nota = xor i16 %a, -1
%notc = xor i16 %c, -1
diff --git a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
index f8b35e54e3bc0..099d3b47cbb28 100644
--- a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
@@ -80,11 +80,13 @@ define amdgpu_kernel void @br_cc_f16(
; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
; GFX11-TRUE16-NEXT: .LBB0_2: ; %two
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -195,6 +197,7 @@ define amdgpu_kernel void @br_cc_f16_imm_a(
; GFX11-TRUE16-NEXT: .LBB1_2: ; %two
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -295,6 +298,7 @@ define amdgpu_kernel void @br_cc_f16_imm_b(
; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
; GFX11-TRUE16-NEXT: .LBB2_2: ; %two
diff --git a/llvm/test/CodeGen/AMDGPU/bswap.ll b/llvm/test/CodeGen/AMDGPU/bswap.ll
index 63433b36e62da..91ebc8b979f8b 100644
--- a/llvm/test/CodeGen/AMDGPU/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/bswap.ll
@@ -600,13 +600,22 @@ define i32 @v_bswap_i16_sext_to_i32(i16 %src) {
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_bswap_i16_sext_to_i32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-REAL16-LABEL: v_bswap_i16_sext_to_i32:
+; GFX11-REAL16: ; %bb.0:
+; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REAL16-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
+; GFX11-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11-REAL16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_bswap_i16_sext_to_i32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = sext i16 %bswap to i32
ret i32 %zext
diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
index 5c0f2c42e813c..59a90a30e7269 100644
--- a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
@@ -72,6 +72,7 @@ define void @undef_lo_v2i16(i16 %arg0) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-TRUE16-NEXT: ;;#ASMSTART
; GFX11-TRUE16-NEXT: ; use v0
; GFX11-TRUE16-NEXT: ;;#ASMEND
@@ -145,6 +146,7 @@ define void @undef_lo_v2f16(half %arg0) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-TRUE16-NEXT: ;;#ASMSTART
; GFX11-TRUE16-NEXT: ; use v0
; GFX11-TRUE16-NEXT: ;;#ASMEND
@@ -229,6 +231,7 @@ define void @undef_lo_op_v2f16(half %arg0) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: ;;#ASMSTART
@@ -315,6 +318,7 @@ define void @undef_lo_op_v2i16(i16 %arg0) {
; GFX11-TRUE16-SDAG: ; %bb.0:
; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-SDAG-NEXT: v_pk_add_u16 v0, 0x63, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
@@ -326,6 +330,7 @@ define void @undef_lo_op_v2i16(i16 %arg0) {
; GFX11-TRUE16-GISEL: ; %bb.0:
; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-GISEL-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-GISEL-NEXT: v_pk_add_u16 v0, 0x630063, v0
; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
@@ -343,6 +348,7 @@ define void @undef_lo3_v4i16(i16 %arg0) {
; GFX8-SDAG: ; %bb.0:
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX8-SDAG-NEXT: ;;#ASMSTART
; GFX8-SDAG-NEXT: ; use v[0:1]
; GFX8-SDAG-NEXT: ;;#ASMEND
@@ -363,6 +369,7 @@ define void @undef_lo3_v4i16(i16 %arg0) {
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX9-SDAG-NEXT: ;;#ASMSTART
; GFX9-SDAG-NEXT: ; use v[0:1]
; GFX9-SDAG-NEXT: ;;#ASMEND
@@ -374,6 +381,7 @@ define void @undef_lo3_v4i16(i16 %arg0) {
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0xffff
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, s4, v1
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX9-GISEL-NEXT: ;;#ASMSTART
; GFX9-GISEL-NEXT: ; use v[0:1]
; GFX9-GISEL-NEXT: ;;#ASMEND
@@ -383,6 +391,7 @@ define void @undef_lo3_v4i16(i16 %arg0) {
; GFX11-FAKE16-SDAG: ; %bb.0:
; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
; GFX11-FAKE16-SDAG-NEXT: ; use v[0:1]
; GFX11-FAKE16-SDAG-NEXT: ;;#ASMEND
@@ -394,6 +403,7 @@ define void @undef_lo3_v4i16(i16 %arg0) {
; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e64 v1, 0xffff, s0
; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
; GFX11-FAKE16-GISEL-NEXT: ; use v[0:1]
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
@@ -403,6 +413,8 @@ define void @undef_lo3_v4i16(i16 %arg0) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
; GFX11-TRUE16-NEXT: ;;#ASMSTART
; GFX11-TRUE16-NEXT: ; use v[0:1]
; GFX11-TRUE16-NEXT: ;;#ASMEND
@@ -417,6 +429,7 @@ define void @undef_lo3_v4f16(half %arg0) {
; GFX8-SDAG: ; %bb.0:
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX8-SDAG-NEXT: ;;#ASMSTART
; GFX8-SDAG-NEXT: ; use v[0:1]
; GFX8-SDAG-NEXT: ;;#ASMEND
@@ -437,6 +450,7 @@ define void @undef_lo3_v4f16(half %arg0) {
; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX9-SDAG-NEXT: ;;#ASMSTART
; GFX9-SDAG-NEXT: ; use v[0:1]
; GFX9-SDAG-NEXT: ;;#ASMEND
@@ -448,6 +462,7 @@ define void @undef_lo3_v4f16(half %arg0) {
; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0xffff
; GFX9-GISEL-NEXT: v_and_b32_e32 v1, s4, v1
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX9-GISEL-NEXT: ;;#ASMSTART
; GFX9-GISEL-NEXT: ; use v[0:1]
; GFX9-GISEL-NEXT: ;;#ASMEND
@@ -457,6 +472,7 @@ define void @undef_lo3_v4f16(half %arg0) {
; GFX11-FAKE16-SDAG: ; %bb.0:
; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
; GFX11-FAKE16-SDAG-NEXT: ; use v[0:1]
; GFX11-FAKE16-SDAG-NEXT: ;;#ASMEND
@@ -468,6 +484,7 @@ define void @undef_lo3_v4f16(half %arg0) {
; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e64 v1, 0xffff, s0
; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
; GFX11-FAKE16-GISEL-NEXT: ; use v[0:1]
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
@@ -477,6 +494,8 @@ define void @undef_lo3_v4f16(half %arg0) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
; GFX11-TRUE16-NEXT: ;;#ASMSTART
; GFX11-TRUE16-NEXT: ; use v[0:1]
; GFX11-TRUE16-NEXT: ;;#ASMEND
@@ -492,6 +511,7 @@ define void @undef_lo2_v4i16(<2 x i16> %arg0) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-SDAG-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX8-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX8-SDAG-NEXT: ;;#ASMSTART
; GFX8-SDAG-NEXT: ; use v[0:1]
; GFX8-SDAG-NEXT: ;;#ASMEND
@@ -513,6 +533,7 @@ define void @undef_lo2_v4i16(<2 x i16> %arg0) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
; GFX9-NEXT: v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use v[0:1]
; GFX9-NEXT: ;;#ASMEND
@@ -522,6 +543,7 @@ define void @undef_lo2_v4i16(<2 x i16> %arg0) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-NEXT: ;;#ASMSTART
; GFX11-FAKE16-NEXT: ; use v[0:1]
; GFX11-FAKE16-NEXT: ;;#ASMEND
@@ -531,6 +553,7 @@ define void @undef_lo2_v4i16(<2 x i16> %arg0) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
; GFX11-TRUE16-NEXT: ;;#ASMSTART
; GFX11-TRUE16-NEXT: ; use v[0:1]
; GFX11-TRUE16-NEXT: ;;#ASMEND
@@ -546,6 +569,7 @@ define void @undef_lo2_v4f16(<2 x half> %arg0) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-SDAG-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX8-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX8-SDAG-NEXT: ;;#ASMSTART
; GFX8-SDAG-NEXT: ; use v[0:1]
; GFX8-SDAG-NEXT: ;;#ASMEND
@@ -567,6 +591,7 @@ define void @undef_lo2_v4f16(<2 x half> %arg0) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
; GFX9-NEXT: v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use v[0:1]
; GFX9-NEXT: ;;#ASMEND
@@ -576,6 +601,7 @@ define void @undef_lo2_v4f16(<2 x half> %arg0) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-NEXT: ;;#ASMSTART
; GFX11-FAKE16-NEXT: ; use v[0:1]
; GFX11-FAKE16-NEXT: ;;#ASMEND
@@ -585,6 +611,7 @@ define void @undef_lo2_v4f16(<2 x half> %arg0) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
; GFX11-TRUE16-NEXT: ;;#ASMSTART
; GFX11-TRUE16-NEXT: ; use v[0:1]
; GFX11-TRUE16-NEXT: ;;#ASMEND
@@ -649,13 +676,23 @@ define void @undef_hi_v2i16(i16 %arg0) {
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: undef_hi_v2i16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-NEXT: ; use v0
-; GFX11-TRUE16-NEXT: ;;#ASMEND
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-SDAG-LABEL: undef_hi_v2i16:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-SDAG-NEXT: ; use v0
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
+; GFX11-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-GISEL-LABEL: undef_hi_v2i16:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-GISEL-NEXT: ; use v0
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMEND
+; GFX11-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
%undef.hi = insertelement <2 x i16> poison, i16 %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<2 x i16> %undef.hi);
ret void
@@ -716,13 +753,23 @@ define void @undef_hi_v2f16(half %arg0) {
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: undef_hi_v2f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-NEXT: ; use v0
-; GFX11-TRUE16-NEXT: ;;#ASMEND
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-SDAG-LABEL: undef_hi_v2f16:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-SDAG-NEXT: ; use v0
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
+; GFX11-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-GISEL-LABEL: undef_hi_v2f16:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-GISEL-NEXT: ; use v0
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMEND
+; GFX11-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
%undef.hi = insertelement <2 x half> poison, half %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<2 x half> %undef.hi);
ret void
@@ -806,6 +853,7 @@ define void @undef_hi_op_v2f16(half %arg0) {
;
; GFX11-TRUE16-GISEL-LABEL: undef_hi_op_v2f16:
; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-GISEL-NEXT: v_pk_add_f16 v0, v0, 1.0 op_sel_hi:[1,0]
; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
@@ -887,6 +935,7 @@ define void @undef_hi_op_v2i16(i16 %arg0) {
; GFX11-TRUE16-SDAG: ; %bb.0:
; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-SDAG-NEXT: v_add_nc_u16 v0.l, 0x63, v0.l
+; GFX11-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
; GFX11-TRUE16-SDAG-NEXT: ; use v0
; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
@@ -894,6 +943,7 @@ define void @undef_hi_op_v2i16(i16 %arg0) {
;
; GFX11-TRUE16-GISEL-LABEL: undef_hi_op_v2i16:
; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-GISEL-NEXT: v_pk_add_u16 v0, 0x630063, v0
; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
@@ -909,6 +959,7 @@ define void @undef_hi_op_v2i16(i16 %arg0) {
define void @undef_hi3_v4i16(i16 %arg0) {
; GFX8-SDAG-LABEL: undef_hi3_v4i16:
; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: ;;#ASMSTART
; GFX8-SDAG-NEXT: ; use v[0:1]
@@ -927,6 +978,7 @@ define void @undef_hi3_v4i16(i16 %arg0) {
;
; GFX9-SDAG-LABEL: undef_hi3_v4i16:
; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: ;;#ASMSTART
; GFX9-SDAG-NEXT: ; use v[0:1]
@@ -938,6 +990,7 @@ define void @undef_hi3_v4i16(i16 %arg0) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, s4, 16, v0
+; GFX9-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX9-GISEL-NEXT: ;;#ASMSTART
; GFX9-GISEL-NEXT: ; use v[0:1]
; GFX9-GISEL-NEXT: ;;#ASMEND
@@ -945,6 +998,7 @@ define void @undef_hi3_v4i16(i16 %arg0) {
;
; GFX11-FAKE16-SDAG-LABEL: undef_hi3_v4i16:
; GFX11-FAKE16-SDAG: ; %bb.0:
+; GFX11-FAKE16-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
; GFX11-FAKE16-SDAG-NEXT: ; use v[0:1]
@@ -955,6 +1009,7 @@ define void @undef_hi3_v4i16(i16 %arg0) {
; GFX11-FAKE16-GISEL: ; %bb.0:
; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
@@ -962,13 +1017,25 @@ define void @undef_hi3_v4i16(i16 %arg0) {
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: undef_hi3_v4i16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-NEXT: ; use v[0:1]
-; GFX11-TRUE16-NEXT: ;;#ASMEND
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-SDAG-LABEL: undef_hi3_v4i16:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-SDAG-NEXT: ; use v[0:1]
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
+; GFX11-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-GISEL-LABEL: undef_hi3_v4i16:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-GISEL-NEXT: ; use v[0:1]
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMEND
+; GFX11-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
%undef.hi = insertelement <4 x i16> poison, i16 %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<4 x i16> %undef.hi);
ret void
@@ -977,6 +1044,7 @@ define void @undef_hi3_v4i16(i16 %arg0) {
define void @undef_hi3_v4f16(half %arg0) {
; GFX8-SDAG-LABEL: undef_hi3_v4f16:
; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: ;;#ASMSTART
; GFX8-SDAG-NEXT: ; use v[0:1]
@@ -995,6 +1063,7 @@ define void @undef_hi3_v4f16(half %arg0) {
;
; GFX9-SDAG-LABEL: undef_hi3_v4f16:
; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: ;;#ASMSTART
; GFX9-SDAG-NEXT: ; use v[0:1]
@@ -1006,6 +1075,7 @@ define void @undef_hi3_v4f16(half %arg0) {
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, s4, 16, v0
+; GFX9-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX9-GISEL-NEXT: ;;#ASMSTART
; GFX9-GISEL-NEXT: ; use v[0:1]
; GFX9-GISEL-NEXT: ;;#ASMEND
@@ -1013,6 +1083,7 @@ define void @undef_hi3_v4f16(half %arg0) {
;
; GFX11-FAKE16-SDAG-LABEL: undef_hi3_v4f16:
; GFX11-FAKE16-SDAG: ; %bb.0:
+; GFX11-FAKE16-SDAG-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-SDAG-NEXT: ;;#ASMSTART
; GFX11-FAKE16-SDAG-NEXT: ; use v[0:1]
@@ -1023,6 +1094,7 @@ define void @undef_hi3_v4f16(half %arg0) {
; GFX11-FAKE16-GISEL: ; %bb.0:
; GFX11-FAKE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX11-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMSTART
@@ -1030,13 +1102,25 @@ define void @undef_hi3_v4f16(half %arg0) {
; GFX11-FAKE16-GISEL-NEXT: ;;#ASMEND
; GFX11-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: undef_hi3_v4f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-NEXT: ; use v[0:1]
-; GFX11-TRUE16-NEXT: ;;#ASMEND
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-SDAG-LABEL: undef_hi3_v4f16:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-SDAG-NEXT: ; use v[0:1]
+; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
+; GFX11-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-GISEL-LABEL: undef_hi3_v4f16:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-GISEL-NEXT: ; use v[0:1]
+; GFX11-TRUE16-GISEL-NEXT: ;;#ASMEND
+; GFX11-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
%undef.hi = insertelement <4 x half> poison, half %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<4 x half> %undef.hi);
ret void
@@ -1045,6 +1129,7 @@ define void @undef_hi3_v4f16(half %arg0) {
define void @undef_hi2_v4i16(<2 x i16> %arg0) {
; GFX8-LABEL: undef_hi2_v4i16:
; GFX8: ; %bb.0:
+; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use v[0:1]
@@ -1053,6 +1138,7 @@ define void @undef_hi2_v4i16(<2 x i16> %arg0) {
;
; GFX9-LABEL: undef_hi2_v4i16:
; GFX9: ; %bb.0:
+; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use v[0:1]
@@ -1061,6 +1147,7 @@ define void @undef_hi2_v4i16(<2 x i16> %arg0) {
;
; GFX11-LABEL: undef_hi2_v4i16:
; GFX11: ; %bb.0:
+; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use v[0:1]
@@ -1074,6 +1161,7 @@ define void @undef_hi2_v4i16(<2 x i16> %arg0) {
define void @undef_hi2_v4f16(<2 x half> %arg0) {
; GFX8-LABEL: undef_hi2_v4f16:
; GFX8: ; %bb.0:
+; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use v[0:1]
@@ -1082,6 +1170,7 @@ define void @undef_hi2_v4f16(<2 x half> %arg0) {
;
; GFX9-LABEL: undef_hi2_v4f16:
; GFX9: ; %bb.0:
+; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use v[0:1]
@@ -1090,6 +1179,7 @@ define void @undef_hi2_v4f16(<2 x half> %arg0) {
;
; GFX11-LABEL: undef_hi2_v4f16:
; GFX11: ; %bb.0:
+; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
index 062f682bf52ad..90ee1369f1ae5 100644
--- a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
@@ -52,6 +52,7 @@ define <2 x half> @chain_hi_to_lo_private() {
; GFX11-TRUE16: ; %bb.0: ; %bb
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v0, off, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v0, off, s0
@@ -118,6 +119,7 @@ define <2 x half> @chain_hi_to_lo_private_different_bases(ptr addrspace(5) %base
; GFX11-TRUE16: ; %bb.0: ; %bb
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v0, v0, off
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v0, v1, off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -180,6 +182,7 @@ define <2 x half> @chain_hi_to_lo_arithmatic(ptr addrspace(5) %base, half %in) {
; GFX11-TRUE16: ; %bb.0: ; %bb
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.l, 1.0, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v1, v0, off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
@@ -228,6 +231,7 @@ define <2 x half> @chain_hi_to_lo_group() {
; GFX11-TRUE16: ; %bb.0: ; %bb
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ds_load_u16_d16 v0, v1 offset:2
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: ds_load_u16_d16_hi v0, v1
@@ -277,6 +281,7 @@ define <2 x half> @chain_hi_to_lo_group_different_bases(ptr addrspace(3) %base_l
; GFX11-TRUE16: ; %bb.0: ; %bb
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: ds_load_u16_d16 v0, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: ds_load_u16_d16_hi v0, v1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -332,6 +337,7 @@ define <2 x half> @chain_hi_to_lo_global() {
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v[1:2], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -379,6 +385,7 @@ define <2 x half> @chain_hi_to_lo_global_different_bases(ptr addrspace(1) %base_
; GFX11-TRUE16: ; %bb.0: ; %bb
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -464,6 +471,7 @@ define <2 x half> @chain_hi_to_lo_flat(ptr inreg %ptr) {
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-TRUE16-NEXT: flat_load_d16_b16 v0, v[0:1] offset:2
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: flat_load_d16_hi_b16 v0, v[1:2]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -514,6 +522,7 @@ define <2 x half> @chain_hi_to_lo_flat_different_bases(ptr %base_lo, ptr %base_h
; GFX11-TRUE16: ; %bb.0: ; %bb
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: flat_load_d16_b16 v0, v[0:1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: flat_load_d16_hi_b16 v0, v[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -666,6 +675,7 @@ define amdgpu_kernel void @vload2_private(ptr addrspace(1) nocapture readonly %i
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[0:1]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll b/llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll
index f4665137393b3..4a062a50e900e 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-avoid-coalesce-class-with-no-registers.ll
@@ -13,6 +13,21 @@ define void @no_introduce_vreg_1024() #0 {
; CHECK-NEXT: ; def v[0:7]
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: v_mov_b32_e32 v9, v0
+; CHECK-NEXT: ; implicit-def: $vgpr0
+; CHECK-NEXT: ; implicit-def: $vgpr1
+; CHECK-NEXT: ; implicit-def: $vgpr2
+; CHECK-NEXT: ; implicit-def: $vgpr3
+; CHECK-NEXT: ; implicit-def: $vgpr4
+; CHECK-NEXT: ; implicit-def: $vgpr5
+; CHECK-NEXT: ; implicit-def: $vgpr6
+; CHECK-NEXT: ; implicit-def: $vgpr7
+; CHECK-NEXT: ; implicit-def: $vgpr8
+; CHECK-NEXT: ; implicit-def: $vgpr10
+; CHECK-NEXT: ; implicit-def: $vgpr11
+; CHECK-NEXT: ; implicit-def: $vgpr12
+; CHECK-NEXT: ; implicit-def: $vgpr13
+; CHECK-NEXT: ; implicit-def: $vgpr14
+; CHECK-NEXT: ; implicit-def: $vgpr15
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; use v[0:15]
; CHECK-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll b/llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
index df54ebc2b573c..74f30400cc89a 100644
--- a/llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
+++ b/llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -amdgpu-sched-strategy=coexec --enable-post-misched=0 %s -o - 2>&1 | FileCheck %s
; The coexec scheduler strategy pushes RewriteMFMAForm into its pipeline so MFMA
@@ -16,6 +17,241 @@
target triple = "amdgcn-amd-amdhsa"
define amdgpu_kernel void @v5_local_prefetch() #0 {
+; CHECK-LABEL: v5_local_prefetch:
+; CHECK: ; %bb.0: ; %.lr.ph
+; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: v_mov_b32_e32 v9, v2
+; CHECK-NEXT: v_mov_b32_e32 v11, v2
+; CHECK-NEXT: v_mov_b32_e32 v12, v2
+; CHECK-NEXT: v_mov_b32_e32 v13, v2
+; CHECK-NEXT: v_mov_b32_e32 v15, v2
+; CHECK-NEXT: v_mov_b32_e32 v16, v2
+; CHECK-NEXT: v_mov_b32_e32 v17, v2
+; CHECK-NEXT: v_mov_b32_e32 v19, v2
+; CHECK-NEXT: v_mov_b32_e32 v20, v2
+; CHECK-NEXT: v_mov_b32_e32 v25, v2
+; CHECK-NEXT: v_mov_b32_e32 v27, v2
+; CHECK-NEXT: v_mov_b32_e32 v31, v2
+; CHECK-NEXT: v_mov_b32_e32 v35, v2
+; CHECK-NEXT: v_mov_b32_e32 v36, v2
+; CHECK-NEXT: v_mov_b32_e32 v37, v2
+; CHECK-NEXT: v_mov_b32_e32 v39, v2
+; CHECK-NEXT: v_mov_b32_e32 v40, v2
+; CHECK-NEXT: v_mov_b32_e32 v41, v2
+; CHECK-NEXT: v_mov_b32_e32 v43, v2
+; CHECK-NEXT: v_mov_b32_e32 v44, v2
+; CHECK-NEXT: v_mov_b32_e32 v45, v2
+; CHECK-NEXT: v_mov_b32_e32 v47, v2
+; CHECK-NEXT: v_mov_b32_e32 v51, v2
+; CHECK-NEXT: v_mov_b32_e32 v5, v2
+; CHECK-NEXT: v_mov_b32_e32 v8, 0
+; CHECK-NEXT: v_mov_b32_e32 v10, 0
+; CHECK-NEXT: v_mov_b32_e32 v14, 0
+; CHECK-NEXT: v_mov_b32_e32 v18, 0
+; CHECK-NEXT: v_mov_b32_e32 v24, 0
+; CHECK-NEXT: v_mov_b32_e32 v26, 0
+; CHECK-NEXT: v_mov_b32_e32 v30, 0
+; CHECK-NEXT: v_mov_b32_e32 v54, 0
+; CHECK-NEXT: v_mov_b32_e32 v34, 0
+; CHECK-NEXT: v_mov_b32_e32 v38, 0
+; CHECK-NEXT: v_mov_b32_e32 v42, 0
+; CHECK-NEXT: v_mov_b32_e32 v46, 0
+; CHECK-NEXT: v_mov_b32_e32 v50, 0
+; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: s_mov_b32 s1, s0
+; CHECK-NEXT: s_mov_b32 s2, s0
+; CHECK-NEXT: s_mov_b32 s3, s0
+; CHECK-NEXT: v_mov_b64_e32 v[62:63], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[60:61], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[66:67], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[64:65], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[70:71], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[68:69], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[74:75], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[72:73], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[78:79], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[76:77], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[82:83], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[80:81], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[86:87], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[84:85], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[90:91], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[88:89], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[94:95], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[92:93], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[98:99], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[96:97], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[102:103], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[100:101], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[106:107], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[104:105], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[110:111], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[108:109], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[114:115], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[112:113], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[118:119], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[116:117], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[122:123], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[120:121], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[126:127], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[124:125], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[130:131], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[128:129], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[134:135], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[132:133], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[138:139], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[136:137], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[142:143], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[140:141], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[146:147], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[144:145], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[150:151], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[148:149], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[154:155], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[152:153], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[158:159], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[156:157], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[162:163], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[160:161], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[166:167], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[164:165], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[170:171], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[168:169], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[174:175], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[172:173], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[178:179], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[176:177], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[182:183], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[180:181], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[186:187], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[184:185], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[190:191], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[188:189], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[194:195], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[192:193], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[198:199], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[196:197], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[202:203], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[200:201], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[206:207], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[204:205], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[210:211], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[208:209], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[214:215], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[212:213], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[218:219], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[216:217], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[222:223], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[220:221], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[226:227], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[224:225], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[230:231], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[228:229], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[234:235], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[232:233], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[238:239], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[236:237], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[242:243], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[240:241], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[246:247], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[244:245], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[250:251], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[248:249], s[0:1]
+; CHECK-NEXT: v_mov_b64_e32 v[254:255], s[2:3]
+; CHECK-NEXT: v_mov_b64_e32 v[252:253], s[0:1]
+; CHECK-NEXT: v_accvgpr_write_b32 a0, s0
+; CHECK-NEXT: v_accvgpr_write_b32 a1, s1
+; CHECK-NEXT: v_accvgpr_write_b32 a2, s2
+; CHECK-NEXT: v_accvgpr_write_b32 a3, s3
+; CHECK-NEXT: v_accvgpr_write_b32 a7, s3
+; CHECK-NEXT: v_accvgpr_write_b32 a6, s2
+; CHECK-NEXT: v_accvgpr_write_b32 a5, s1
+; CHECK-NEXT: v_accvgpr_write_b32 a4, s0
+; CHECK-NEXT: v_accvgpr_write_b32 a11, s3
+; CHECK-NEXT: v_accvgpr_write_b32 a10, s2
+; CHECK-NEXT: v_accvgpr_write_b32 a9, s1
+; CHECK-NEXT: v_accvgpr_write_b32 a8, s0
+; CHECK-NEXT: v_accvgpr_write_b32 a15, s3
+; CHECK-NEXT: v_accvgpr_write_b32 a14, s2
+; CHECK-NEXT: v_accvgpr_write_b32 a13, s1
+; CHECK-NEXT: v_accvgpr_write_b32 a12, s0
+; CHECK-NEXT: v_mov_b32_e32 v56, 0
+; CHECK-NEXT: s_and_b64 vcc, exec, -1
+; CHECK-NEXT: ds_read_b128 a[16:19], v2
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a17
+; CHECK-NEXT: v_accvgpr_write_b32 a19, s3
+; CHECK-NEXT: v_accvgpr_write_b32 a18, s2
+; CHECK-NEXT: v_accvgpr_write_b32 a17, s1
+; CHECK-NEXT: v_accvgpr_write_b32 a16, s0
+; CHECK-NEXT: .p2align 5, , 4
+; CHECK-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[10:13], v[72:75], v[76:79], v[10:13]
+; CHECK-NEXT: s_nop 3
+; CHECK-NEXT: v_mov_b32_e32 v4, v56
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[14:17], v[88:91], v[92:95], v[14:17]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[38:41], v[196:199], v[200:203], v[38:41]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[42:45], v[212:215], v[216:219], v[42:45]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[10:13], v[80:83], v[84:87], v[10:13]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[14:17], v[96:99], v[100:103], v[14:17]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[38:41], v[204:207], v[208:211], v[38:41]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[42:45], v[220:223], v[224:227], v[42:45]
+; CHECK-NEXT: v_mov_b32_e32 v3, v2
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[32:35], v[0:3], v[184:187], v[34:37]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[34:37], v[188:191], v[192:195], v[32:35]
+; CHECK-NEXT: v_mov_b32_e32 v6, v2
+; CHECK-NEXT: v_mov_b32_e32 v7, v2
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[6:9], v[0:3], v[60:63], v[6:9]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[6:9], v[64:67], v[68:71], v[6:9]
+; CHECK-NEXT: v_mov_b32_e32 v21, v2
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[18:21], v[104:107], v[108:111], v[18:21]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[18:21], v[112:115], v[116:119], v[18:21]
+; CHECK-NEXT: v_mov_b32_e32 v22, v2
+; CHECK-NEXT: v_mov_b32_e32 v23, v2
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[22:25], v[120:123], v[124:127], v[22:25]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[22:25], v[128:131], v[132:135], v[22:25]
+; CHECK-NEXT: v_mov_b32_e32 v28, v2
+; CHECK-NEXT: v_mov_b32_e32 v29, v2
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[26:29], v[136:139], v[140:143], v[26:29]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[26:29], v[144:147], v[148:151], v[26:29]
+; CHECK-NEXT: v_mov_b32_e32 v32, v2
+; CHECK-NEXT: v_mov_b32_e32 v33, v2
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[28:31], v[152:155], v[156:159], v[30:33]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[30:33], v[160:163], v[164:167], v[28:31]
+; CHECK-NEXT: ; implicit-def: $vgpr55
+; CHECK-NEXT: ; implicit-def: $vgpr56
+; CHECK-NEXT: ; implicit-def: $vgpr57
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[52:55], v[168:171], v[172:175], v[54:57]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[54:57], v[176:179], v[180:183], v[52:55]
+; CHECK-NEXT: v_mov_b32_e32 v48, v2
+; CHECK-NEXT: v_mov_b32_e32 v49, v2
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[46:49], v[228:231], v[232:235], v[46:49]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[46:49], v[236:239], v[240:243], v[46:49]
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: v_mov_b32_e32 v52, v2
+; CHECK-NEXT: v_mov_b32_e32 v53, v2
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[48:51], v[244:247], v[248:251], v[50:53]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[50:53], v[252:255], a[0:3], v[48:51]
+; CHECK-NEXT: v_mov_b32_e32 v3, 1.0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[56:59], a[4:7], a[8:11], v[2:5]
+; CHECK-NEXT: v_mfma_f32_16x16x32_f16 v[56:59], a[12:15], a[16:19], v[56:59]
+; CHECK-NEXT: s_nop 1
+; CHECK-NEXT: v_mov_b32_e32 v5, v4
+; CHECK-NEXT: s_mov_b64 vcc, vcc
+; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
+; CHECK-NEXT: ; %bb.2: ; %DummyReturnBlock
+; CHECK-NEXT: s_endpgm
.lr.ph:
%0 = load <8 x half>, ptr addrspace(3) null, align 16
%1 = shufflevector <8 x half> %0, <8 x half> zeroinitializer, <2 x i32> <i32 0, i32 1>
diff --git a/llvm/test/CodeGen/AMDGPU/ctpop64.ll b/llvm/test/CodeGen/AMDGPU/ctpop64.ll
index 2320432d67a8b..55df690c6246a 100644
--- a/llvm/test/CodeGen/AMDGPU/ctpop64.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctpop64.ll
@@ -648,6 +648,7 @@ define amdgpu_kernel void @s_ctpop_i65(ptr addrspace(1) noalias %out, i65 %val)
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: s_load_u8 s6, s[4:5], 0x34
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: ; implicit-def: $sgpr7
; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_and_b64 s[4:5], s[6:7], 1
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index bb9595d8592c0..c316d869ceca3 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -265,11 +265,18 @@ define float @v_uitofp_i8_to_f32(i8 %arg0) nounwind {
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_uitofp_i8_to_f32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_i8_to_f32:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_uitofp_i8_to_f32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cvt = uitofp i8 %arg0 to float
ret float %cvt
}
@@ -303,6 +310,7 @@ define <2 x float> @v_uitofp_v2i8_to_v2f32(i16 %arg0) nounwind {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte0_e32 v0, v1
; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte1_e32 v1, v1
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index 3aa89a7210ca0..ac25a6daa9093 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -1609,6 +1609,7 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
@@ -1711,6 +1712,7 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
@@ -2114,6 +2116,7 @@ define half @fmul_select_f16_test5(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
@@ -2226,6 +2229,7 @@ define half @fmul_select_f16_test6(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, 0xc800, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test6:
@@ -2336,6 +2340,7 @@ define half @fmul_select_f16_test7(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, 0x4800, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test7:
@@ -2420,6 +2425,7 @@ define half @fmul_select_f16_test8(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.h, 0, 0x8000, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test8:
@@ -2519,6 +2525,7 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2620,6 +2627,7 @@ define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.a
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
@@ -2713,6 +2721,7 @@ define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.ar
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
diff --git a/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll b/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
index 95385b7cb14bc..4335ce7b41883 100644
--- a/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
+++ b/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
@@ -57,8 +57,9 @@ define noundef i64 @srem64_3(i64 noundef %i) {
; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v5
; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 3, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v5
-; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[2:3]
+; GFX942-NEXT: v_mov_b32_e32 v6, v5
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[6:7]
; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
@@ -144,8 +145,9 @@ define noundef i64 @srem64_6(i64 noundef %i) {
; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v5
; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 3, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v5
-; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[2:3]
+; GFX942-NEXT: v_mov_b32_e32 v6, v5
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[6:7]
; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
@@ -219,9 +221,10 @@ define noundef i64 @urem64_3(i64 noundef %i) {
; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, s2, v[2:3]
; GFX942-NEXT: v_alignbit_b32 v2, v3, v2, 1
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 3, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v5
-; GFX942-NEXT: v_lshrrev_b32_e32 v3, 1, v3
-; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[2:3]
+; GFX942-NEXT: v_mov_b32_e32 v6, v5
+; GFX942-NEXT: v_lshrrev_b32_e32 v2, 1, v3
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, v[6:7]
; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
@@ -289,9 +292,10 @@ define noundef i64 @urem64_6(i64 noundef %i) {
; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, s2, v[2:3]
; GFX942-NEXT: v_alignbit_b32 v2, v3, v2, 2
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 6, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v5
-; GFX942-NEXT: v_lshrrev_b32_e32 v3, 2, v3
-; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 6, v[2:3]
+; GFX942-NEXT: v_mov_b32_e32 v6, v5
+; GFX942-NEXT: v_lshrrev_b32_e32 v2, 2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 6, v[6:7]
; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
@@ -1066,8 +1070,9 @@ define noundef i64 @srem64_i32max(i64 noundef %i) {
; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[6:7], 0, v[4:5]
; GFX942-NEXT: s_brev_b32 s2, -2
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, s2, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v5
-; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, s2, v[2:3]
+; GFX942-NEXT: v_mov_b32_e32 v6, v5
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, s2, v[6:7]
; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
@@ -1247,9 +1252,10 @@ define noundef i64 @urem64_i32max(i64 noundef %i) {
; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]
; GFX942-NEXT: v_alignbit_b32 v2, v3, v2, 30
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, s2, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v5
-; GFX942-NEXT: v_lshrrev_b32_e32 v3, 30, v3
-; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, s2, v[2:3]
+; GFX942-NEXT: v_mov_b32_e32 v6, v5
+; GFX942-NEXT: v_lshrrev_b32_e32 v2, 30, v3
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, s2, v[6:7]
; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index e3c8eaacf88fe..a094e0c5b4f45 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -1343,8 +1343,9 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GFX9-G-NEXT: v_or_b32_e32 v12, v12, v8
; GFX9-G-NEXT: v_and_b32_e32 v8, 1, v28
-; GFX9-G-NEXT: v_mov_b32_e32 v0, v8
+; GFX9-G-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX9-G-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GFX9-G-NEXT: v_mov_b32_e32 v0, v8
; GFX9-G-NEXT: v_mov_b32_e32 v1, v9
; GFX9-G-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GFX9-G-NEXT: s_cbranch_execnz .LBB0_3
@@ -3411,6 +3412,7 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-NEXT: v_or_b32_e32 v11, v19, v21
; GFX9-G-NEXT: v_lshlrev_b64 v[8:9], 1, v[8:9]
; GFX9-G-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
+; GFX9-G-NEXT: ; implicit-def: $vgpr10_vgpr11
; GFX9-G-NEXT: v_or_b32_e32 v8, v8, v0
; GFX9-G-NEXT: v_and_b32_e32 v0, 1, v12
; GFX9-G-NEXT: v_mov_b32_e32 v11, v1
diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
index c013a1d779f36..981a8088ec0ea 100644
--- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
@@ -582,8 +582,9 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GISEL-NEXT: v_or_b32_e32 v8, v8, v16
; GISEL-NEXT: v_and_b32_e32 v16, 1, v36
-; GISEL-NEXT: v_mov_b32_e32 v0, v16
+; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v0, v16
; GISEL-NEXT: v_mov_b32_e32 v1, v17
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execnz .LBB0_3
@@ -761,6 +762,7 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc
; GISEL-NEXT: v_or_b32_e32 v13, v1, v11
; GISEL-NEXT: v_mov_b32_e32 v0, v6
+; GISEL-NEXT: ; implicit-def: $vgpr10_vgpr11
; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc
; GISEL-NEXT: v_mov_b32_e32 v1, v7
; GISEL-NEXT: v_and_b32_e32 v6, v34, v22
@@ -1382,6 +1384,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v19, v27, v29
; GISEL-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19]
+; GISEL-NEXT: ; implicit-def: $vgpr18_vgpr19
; GISEL-NEXT: v_or_b32_e32 v2, v2, v0
; GISEL-NEXT: v_and_b32_e32 v0, 1, v20
; GISEL-NEXT: v_mov_b32_e32 v19, v1
@@ -1545,6 +1548,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v1, v21, v7
; GISEL-NEXT: v_and_b32_e32 v4, 1, v30
; GISEL-NEXT: v_mov_b32_e32 v21, v5
+; GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
; GISEL-NEXT: v_addc_u32_e32 v17, vcc, -1, v17, vcc
; GISEL-NEXT: v_mov_b32_e32 v20, v4
; GISEL-NEXT: v_and_b32_e32 v4, v30, v12
@@ -2244,8 +2248,9 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GISEL-NEXT: v_or_b32_e32 v21, v21, v23
; GISEL-NEXT: v_and_b32_e32 v23, 1, v39
-; GISEL-NEXT: v_mov_b32_e32 v0, v23
+; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1
; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GISEL-NEXT: v_mov_b32_e32 v0, v23
; GISEL-NEXT: v_mov_b32_e32 v1, v24
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GISEL-NEXT: s_cbranch_execnz .LBB4_3
@@ -2408,17 +2413,18 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v15, v1, v3
; GISEL-NEXT: v_lshl_b64 v[0:1], v[24:25], 1
; GISEL-NEXT: v_addc_u32_e32 v37, vcc, -1, v37, vcc
-; GISEL-NEXT: v_lshrrev_b32_e32 v24, 31, v25
-; GISEL-NEXT: v_lshrrev_b32_e32 v25, 31, v21
+; GISEL-NEXT: v_lshl_b64 v[2:3], v[26:27], 1
+; GISEL-NEXT: v_lshrrev_b32_e32 v27, 31, v21
; GISEL-NEXT: v_lshl_b64 v[20:21], v[20:21], 1
; GISEL-NEXT: v_addc_u32_e32 v38, vcc, -1, v38, vcc
-; GISEL-NEXT: v_lshl_b64 v[2:3], v[26:27], 1
-; GISEL-NEXT: v_or_b32_e32 v0, v0, v25
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v27
; GISEL-NEXT: v_addc_u32_e32 v39, vcc, -1, v39, vcc
+; GISEL-NEXT: v_lshrrev_b32_e32 v26, 31, v25
; GISEL-NEXT: v_or_b32_e32 v20, v20, v22
; GISEL-NEXT: v_sub_i32_e32 v22, vcc, v48, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v24
+; GISEL-NEXT: v_or_b32_e32 v2, v2, v26
; GISEL-NEXT: v_subb_u32_e32 v22, vcc, v49, v1, vcc
+; GISEL-NEXT: ; implicit-def: $vgpr24_vgpr25
; GISEL-NEXT: v_subb_u32_e32 v22, vcc, v50, v2, vcc
; GISEL-NEXT: v_or_b32_e32 v24, v36, v38
; GISEL-NEXT: v_or_b32_e32 v25, v37, v39
@@ -2453,7 +2459,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v31, v18, 0
; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v31, v28, 0
-; GISEL-NEXT: v_mul_lo_u32 v36, v30, v18
+; GISEL-NEXT: v_mul_lo_u32 v18, v30, v18
; GISEL-NEXT: v_mul_lo_u32 v3, v35, v3
; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v30, v33, v[0:1]
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v35, v2, 0
@@ -2461,31 +2467,33 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v16, v28, v[14:15]
; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v35, v20, 0
; GISEL-NEXT: v_mad_u64_u32 v[26:27], vcc, v31, v33, v[23:24]
-; GISEL-NEXT: v_mul_lo_u32 v23, v31, v19
-; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v34, v21, v[0:1]
+; GISEL-NEXT: v_mul_lo_u32 v31, v31, v19
+; GISEL-NEXT: v_mad_u64_u32 v[23:24], s[4:5], v34, v21, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr19
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v30, v28, v[26:27]
-; GISEL-NEXT: v_addc_u32_e64 v23, s[4:5], v25, v23, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v23, vcc, v23, v36, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v16, v33, v[23:24]
+; GISEL-NEXT: v_addc_u32_e64 v25, s[4:5], v25, v31, s[4:5]
+; GISEL-NEXT: v_addc_u32_e32 v18, vcc, v25, v18, vcc
+; GISEL-NEXT: v_mad_u64_u32 v[25:26], s[4:5], v16, v33, v[18:19]
; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v10, v22
; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v11, v0, vcc
-; GISEL-NEXT: v_xor_b32_e32 v22, v10, v29
-; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v17, v28, v[24:25]
-; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v12, v20, v[18:19]
-; GISEL-NEXT: v_xor_b32_e32 v23, v0, v29
+; GISEL-NEXT: v_xor_b32_e32 v18, v10, v29
+; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v17, v28, v[25:26]
+; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v12, v20, v[23:24]
+; GISEL-NEXT: v_xor_b32_e32 v19, v0, v29
; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v8, v1, vcc
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v9, v10, vcc
; GISEL-NEXT: v_mad_u64_u32 v[8:9], vcc, v35, v21, v[15:16]
-; GISEL-NEXT: v_xor_b32_e32 v18, v0, v29
-; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v22, v29
+; GISEL-NEXT: v_xor_b32_e32 v22, v0, v29
+; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v18, v29
; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v34, v20, v[8:9]
; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], v17, v3, s[6:7]
; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v3, v2, vcc
+; GISEL-NEXT: ; implicit-def: $vgpr3
; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[6:7], v12, v21, v[2:3]
-; GISEL-NEXT: v_xor_b32_e32 v19, v1, v29
-; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], v23, v29, s[4:5]
-; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v18, v29, s[4:5]
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v19, v29, vcc
+; GISEL-NEXT: v_xor_b32_e32 v23, v1, v29
+; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], v19, v29, s[4:5]
+; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v22, v29, s[4:5]
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v23, v29, vcc
; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v13, v20, v[8:9]
; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v6, v14
; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v10, vcc
@@ -3052,8 +3060,9 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_lshl_b64 v[23:24], v[23:24], 1
; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
; GISEL-NEXT: v_and_b32_e32 v19, 1, v38
-; GISEL-NEXT: v_mov_b32_e32 v16, v19
+; GISEL-NEXT: ; implicit-def: $vgpr16_vgpr17
; GISEL-NEXT: v_or_b32_e32 v23, v23, v37
+; GISEL-NEXT: v_mov_b32_e32 v16, v19
; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GISEL-NEXT: v_mov_b32_e32 v17, v20
; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9]
@@ -3199,17 +3208,18 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v23, v17, v19
; GISEL-NEXT: v_lshl_b64 v[16:17], v[28:29], 1
; GISEL-NEXT: v_addc_u32_e32 v35, vcc, -1, v35, vcc
-; GISEL-NEXT: v_lshrrev_b32_e32 v28, 31, v29
-; GISEL-NEXT: v_lshrrev_b32_e32 v29, 31, v25
+; GISEL-NEXT: v_lshl_b64 v[18:19], v[30:31], 1
+; GISEL-NEXT: v_lshrrev_b32_e32 v31, 31, v25
; GISEL-NEXT: v_lshl_b64 v[24:25], v[24:25], 1
; GISEL-NEXT: v_addc_u32_e32 v36, vcc, -1, v36, vcc
-; GISEL-NEXT: v_lshl_b64 v[18:19], v[30:31], 1
-; GISEL-NEXT: v_or_b32_e32 v16, v16, v29
+; GISEL-NEXT: v_or_b32_e32 v16, v16, v31
; GISEL-NEXT: v_addc_u32_e32 v37, vcc, -1, v37, vcc
+; GISEL-NEXT: v_lshrrev_b32_e32 v30, 31, v29
; GISEL-NEXT: v_or_b32_e32 v24, v24, v26
; GISEL-NEXT: v_sub_i32_e32 v26, vcc, v38, v16
-; GISEL-NEXT: v_or_b32_e32 v18, v18, v28
+; GISEL-NEXT: v_or_b32_e32 v18, v18, v30
; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v39, v17, vcc
+; GISEL-NEXT: ; implicit-def: $vgpr28_vgpr29
; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v48, v18, vcc
; GISEL-NEXT: v_or_b32_e32 v28, v34, v36
; GISEL-NEXT: v_or_b32_e32 v29, v35, v37
@@ -3253,27 +3263,29 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_mul_lo_u32 v8, v8, v21
; GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v12, v24, 0
; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v14, v24, v[30:31]
-; GISEL-NEXT: v_mad_u64_u32 v[27:28], s[4:5], v9, v32, v[16:17]
+; GISEL-NEXT: v_mad_u64_u32 v[30:31], s[4:5], v9, v32, v[16:17]
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v29, v8, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v34, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v10, v33, v[8:9]
-; GISEL-NEXT: v_mad_u64_u32 v[8:9], vcc, v12, v25, v[21:22]
-; GISEL-NEXT: v_mul_lo_u32 v29, v12, v19
-; GISEL-NEXT: v_mul_lo_u32 v30, v13, v18
-; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v11, v32, v[16:17]
-; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v13, v24, v[8:9]
-; GISEL-NEXT: v_addc_u32_e64 v8, s[6:7], v23, v29, s[6:7]
-; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v30, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v14, v25, v[8:9]
+; GISEL-NEXT: v_addc_u32_e32 v27, vcc, v8, v34, vcc
+; GISEL-NEXT: ; implicit-def: $vgpr28
+; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v10, v33, v[27:28]
+; GISEL-NEXT: v_mad_u64_u32 v[16:17], vcc, v12, v25, v[21:22]
+; GISEL-NEXT: v_mul_lo_u32 v10, v12, v19
+; GISEL-NEXT: v_mul_lo_u32 v27, v13, v18
+; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v11, v32, v[8:9]
+; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[6:7], v13, v24, v[16:17]
+; GISEL-NEXT: v_addc_u32_e64 v10, s[6:7], v23, v10, s[6:7]
+; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v27, vcc
+; GISEL-NEXT: ; implicit-def: $vgpr11
+; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v14, v25, v[10:11]
; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v26
-; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], v1, v27, s[4:5]
-; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v2, v28, s[4:5]
+; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], v1, v30, s[4:5]
+; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v2, v31, s[4:5]
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v18, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v15, v24, v[12:13]
+; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v15, v24, v[12:13]
; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v4, v20
-; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v5, v10, vcc
-; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v6, v11, vcc
-; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v8, vcc
+; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v6, v9, vcc
+; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v10, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
%shl = urem <2 x i128> %lhs, %rhs
ret <2 x i128> %shl
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
index 8d62f86cba88a..c31037d7764b1 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
@@ -703,6 +703,12 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[2:3], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: s_cbranch_execnz .LBB3_3
; GFX9-NEXT: .LBB3_2: ; %T
; GFX9-NEXT: global_load_dwordx4 v[2:5], v[0:1], off offset:16 glc
@@ -710,6 +716,12 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: .LBB3_3: ; %exit
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v5 op_sel_hi:[0,0]
; GFX9-NEXT: s_movk_i32 s4, 0x8000
@@ -737,6 +749,12 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB3_3
; GFX11-TRUE16-NEXT: .LBB3_2: ; %T
@@ -744,6 +762,12 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX11-TRUE16-NEXT: .LBB3_3: ; %exit
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 15, v3.l
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v2, 15, v2 op_sel_hi:[0,1]
@@ -769,6 +793,12 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB3_3
; GFX11-FAKE16-NEXT: .LBB3_2: ; %T
@@ -776,6 +806,12 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
; GFX11-FAKE16-NEXT: .LBB3_3: ; %exit
; GFX11-FAKE16-NEXT: v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
@@ -940,6 +976,10 @@ define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[2:3], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: s_cbranch_execnz .LBB4_3
; GFX9-NEXT: .LBB4_2: ; %T
; GFX9-NEXT: global_load_dwordx4 v[2:5], v[0:1], off offset:16 glc
@@ -947,6 +987,10 @@ define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: .LBB4_3: ; %exit
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v7 op_sel_hi:[0,1]
; GFX9-NEXT: s_movk_i32 s4, 0x8000
@@ -974,6 +1018,10 @@ define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB4_3
; GFX11-TRUE16-NEXT: .LBB4_2: ; %T
@@ -981,6 +1029,10 @@ define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX11-TRUE16-NEXT: .LBB4_3: ; %exit
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
@@ -1006,6 +1058,10 @@ define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB4_3
; GFX11-FAKE16-NEXT: .LBB4_2: ; %T
@@ -1013,6 +1069,10 @@ define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
; GFX11-FAKE16-NEXT: .LBB4_3: ; %exit
; GFX11-FAKE16-NEXT: v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
@@ -1174,6 +1234,12 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[2:3], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: s_cbranch_execnz .LBB5_3
; GFX9-NEXT: .LBB5_2: ; %T
; GFX9-NEXT: global_load_dwordx4 v[2:5], v[0:1], off offset:16 glc
@@ -1181,6 +1247,12 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: .LBB5_3: ; %exit
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3900
; GFX9-NEXT: v_mov_b32_e32 v1, 0x3d00
@@ -1211,6 +1283,12 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB5_3
; GFX11-TRUE16-NEXT: .LBB5_2: ; %T
@@ -1218,6 +1296,12 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX11-TRUE16-NEXT: .LBB5_3: ; %exit
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x3900
@@ -1246,6 +1330,12 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB5_3
; GFX11-FAKE16-NEXT: .LBB5_2: ; %T
@@ -1253,6 +1343,12 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
; GFX11-FAKE16-NEXT: .LBB5_3: ; %exit
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3d00
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -1530,6 +1626,10 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[2:3], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: s_cbranch_execz .LBB7_3
; GFX9-NEXT: s_branch .LBB7_4
; GFX9-NEXT: .LBB7_2:
@@ -1540,6 +1640,10 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: .LBB7_4: ; %exit
; GFX9-NEXT: s_movk_i32 s35, 0x3801
; GFX9-NEXT: s_movk_i32 s34, 0x3800
@@ -1584,6 +1688,10 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[2:3], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB7_3
; GFX11-TRUE16-NEXT: s_branch .LBB7_4
@@ -1594,6 +1702,10 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX11-TRUE16-NEXT: .LBB7_4: ; %exit
; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0x3801, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x3900
@@ -1630,6 +1742,10 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB7_3
; GFX11-FAKE16-NEXT: s_branch .LBB7_4
@@ -1640,6 +1756,10 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
; GFX11-FAKE16-NEXT: .LBB7_4: ; %exit
; GFX11-FAKE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0x3801, v5
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0x3900
@@ -1848,6 +1968,10 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[2:3], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: s_cbranch_execz .LBB8_3
; GFX9-NEXT: s_branch .LBB8_4
; GFX9-NEXT: .LBB8_2:
@@ -1858,6 +1982,10 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
+; GFX9-NEXT: ; implicit-def: $vgpr0
; GFX9-NEXT: .LBB8_4: ; %exit
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3800
; GFX9-NEXT: v_mov_b32_e32 v1, 0x3900
@@ -1900,6 +2028,10 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[2:3], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB8_3
; GFX11-TRUE16-NEXT: s_branch .LBB8_4
@@ -1910,6 +2042,10 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX11-TRUE16-NEXT: .LBB8_4: ; %exit
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v7.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x3900
@@ -1946,6 +2082,10 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB8_3
; GFX11-FAKE16-NEXT: s_branch .LBB8_4
@@ -1956,6 +2096,10 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0
; GFX11-FAKE16-NEXT: .LBB8_4: ; %exit
; GFX11-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v5
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0x3900
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector.ll
index 130c8563c9a4c..6f5f114d0acc3 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector.ll
@@ -118,6 +118,18 @@ define <2 x i64> @extract_2xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[2:3], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB1_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB1_4
@@ -134,6 +146,18 @@ define <2 x i64> @extract_2xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB1_4: ; %exit
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v1, 0xffff8000
@@ -186,6 +210,14 @@ define <4 x i64> @extract_4xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[2:3], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB2_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB2_4
@@ -202,6 +234,14 @@ define <4 x i64> @extract_4xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB2_4: ; %exit
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v1, 0xffff8000
@@ -268,6 +308,22 @@ define <8 x i64> @extract_8xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %
; GCN-NEXT: buffer_load_dwordx4 v[16:19], v[2:3], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB3_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB3_4
@@ -292,6 +348,22 @@ define <8 x i64> @extract_8xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dwordx4 v[16:19], v[0:1], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB3_4: ; %exit
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v1, 0xffff8000
@@ -362,6 +434,18 @@ define <2 x double> @extract_2xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[2:3], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB4_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB4_4
@@ -378,6 +462,18 @@ define <2 x double> @extract_2xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB4_4: ; %exit
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_cmp_lt_f64_e32 vcc, -1.0, v[4:5]
@@ -430,6 +526,14 @@ define <4 x double> @extract_4xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[2:3], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB5_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB5_4
@@ -446,6 +550,14 @@ define <4 x double> @extract_4xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB5_4: ; %exit
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_cmp_nlt_f64_e32 vcc, -1.0, v[4:5]
@@ -512,6 +624,22 @@ define <8 x double> @extract_8xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i
; GCN-NEXT: buffer_load_dwordx4 v[16:19], v[2:3], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB6_2: ; %Flow
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GCN-NEXT: s_cbranch_execz .LBB6_4
@@ -536,6 +664,22 @@ define <8 x double> @extract_8xf64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dwordx4 v[16:19], v[0:1], s[8:11], 0 addr64 offset:48 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
+; GCN-NEXT: ; implicit-def: $vgpr0
; GCN-NEXT: .LBB6_4: ; %exit
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_cmp_nlt_f64_e32 vcc, -1.0, v[6:7]
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index c381b1806acdf..84a70fbb65b9b 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -904,8 +904,8 @@ entry:
define amdgpu_kernel void @double7_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-LABEL: double7_extelt:
; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x24
-; GCN-NEXT: s_load_dword s16, s[4:5], 0x2c
+; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
+; GCN-NEXT: s_load_dword s18, s[4:5], 0x2c
; GCN-NEXT: s_mov_b32 s0, 0
; GCN-NEXT: s_mov_b32 s13, 0x401c0000
; GCN-NEXT: s_mov_b32 s11, 0x40180000
@@ -920,11 +920,13 @@ define amdgpu_kernel void @double7_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_mov_b32 s8, s0
; GCN-NEXT: s_mov_b32 s10, s0
; GCN-NEXT: s_mov_b32 s12, s0
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: ; implicit-def: $sgpr14
+; GCN-NEXT: ; implicit-def: $sgpr15
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v15, s15
-; GCN-NEXT: s_lshl_b32 m0, s16, 1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_lshl_b32 m0, s18, 1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: v_mov_b32_e32 v4, s4
@@ -940,8 +942,8 @@ define amdgpu_kernel void @double7_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: v_mov_b32_e32 v14, s14
; GCN-NEXT: v_movrels_b32_e32 v16, v1
; GCN-NEXT: v_movrels_b32_e32 v15, v0
-; GCN-NEXT: v_mov_b32_e32 v0, s14
-; GCN-NEXT: v_mov_b32_e32 v1, s15
+; GCN-NEXT: v_mov_b32_e32 v0, s16
+; GCN-NEXT: v_mov_b32_e32 v1, s17
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[15:16]
; GCN-NEXT: s_endpgm
;
@@ -1184,6 +1186,8 @@ define amdgpu_kernel void @double15_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_mov_b32 s60, s36
; GCN-NEXT: s_mov_b32 s62, s36
; GCN-NEXT: s_mov_b32 s64, s36
+; GCN-NEXT: ; implicit-def: $sgpr66
+; GCN-NEXT: ; implicit-def: $sgpr67
; GCN-NEXT: v_mov_b32_e32 v0, s36
; GCN-NEXT: v_mov_b32_e32 v1, s37
; GCN-NEXT: v_mov_b32_e32 v31, s67
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
index 1b0a5217fbb2b..6810ec5522475 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
@@ -1068,12 +1068,20 @@ define amdgpu_kernel void @s_test_canonicalize_undef_v2bf16(ptr addrspace(1) %ou
}
define <2 x bfloat> @v_test_canonicalize_reg_undef_v2bf16(bfloat %val) #1 {
-; GFX1250-LABEL: v_test_canonicalize_reg_undef_v2bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_pk_mul_bf16 v0, 1.0, v0 op_sel_hi:[0,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; FAKE16-LABEL: v_test_canonicalize_reg_undef_v2bf16:
+; FAKE16: ; %bb.0:
+; FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; FAKE16-NEXT: s_wait_kmcnt 0x0
+; FAKE16-NEXT: v_pk_mul_bf16 v0, 1.0, v0 op_sel_hi:[0,1]
+; FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; REAL16-LABEL: v_test_canonicalize_reg_undef_v2bf16:
+; REAL16: ; %bb.0:
+; REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; REAL16-NEXT: s_wait_kmcnt 0x0
+; REAL16-NEXT: v_pk_mul_bf16 v0, 1.0, v0 op_sel_hi:[0,1]
+; REAL16-NEXT: s_set_pc_i64 s[30:31]
%vec = insertelement <2 x bfloat> poison, bfloat %val, i32 0
%canonicalized = call <2 x bfloat> @llvm.canonicalize.v2bf16(<2 x bfloat> %vec)
ret <2 x bfloat> %canonicalized
@@ -1094,6 +1102,7 @@ define <2 x bfloat> @v_test_canonicalize_undef_reg_v2bf16(bfloat %val) #1 {
; REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; REAL16-NEXT: s_wait_kmcnt 0x0
; REAL16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; REAL16-NEXT: ; implicit-def: $vgpr0_lo16
; REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; REAL16-NEXT: v_pk_mul_bf16 v0, 1.0, v0 op_sel_hi:[0,1]
; REAL16-NEXT: s_set_pc_i64 s[30:31]
@@ -1219,13 +1228,22 @@ define amdgpu_kernel void @s_test_canonicalize_undef_v4bf16(ptr addrspace(1) %ou
}
define <4 x bfloat> @v_test_canonicalize_reg_undef_undef_undef_v4bf16(bfloat %val) #1 {
-; GFX1250-LABEL: v_test_canonicalize_reg_undef_undef_undef_v4bf16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_pk_mul_bf16 v0, 1.0, v0 op_sel_hi:[0,1]
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0x7fc07fc0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; FAKE16-LABEL: v_test_canonicalize_reg_undef_undef_undef_v4bf16:
+; FAKE16: ; %bb.0:
+; FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; FAKE16-NEXT: s_wait_kmcnt 0x0
+; FAKE16-NEXT: v_pk_mul_bf16 v0, 1.0, v0 op_sel_hi:[0,1]
+; FAKE16-NEXT: v_mov_b32_e32 v1, 0x7fc07fc0
+; FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; REAL16-LABEL: v_test_canonicalize_reg_undef_undef_undef_v4bf16:
+; REAL16: ; %bb.0:
+; REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; REAL16-NEXT: s_wait_kmcnt 0x0
+; REAL16-NEXT: v_mov_b32_e32 v1, 0x7fc07fc0
+; REAL16-NEXT: v_pk_mul_bf16 v0, 1.0, v0 op_sel_hi:[0,1]
+; REAL16-NEXT: s_set_pc_i64 s[30:31]
%vec = insertelement <4 x bfloat> poison, bfloat %val, i32 0
%canonicalized = call <4 x bfloat> @llvm.canonicalize.v4bf16(<4 x bfloat> %vec)
ret <4 x bfloat> %canonicalized
@@ -1273,6 +1291,7 @@ define <4 x bfloat> @v_test_canonicalize_reg_undef_reg_reg_v4bf16(bfloat %val0,
; REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; REAL16-NEXT: s_wait_kmcnt 0x0
; REAL16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; REAL16-NEXT: v_pk_mul_bf16 v0, 1.0, v0 op_sel_hi:[0,1]
; REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; REAL16-NEXT: v_pk_mul_bf16 v1, 1.0, v1 op_sel_hi:[0,1]
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
index d82756506ff73..f9a5962dfc826 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
@@ -7165,6 +7165,7 @@ define <3 x float> @v_test_canonicalize_v3f32_flush(<3 x float> %arg) #1 {
;
; GFX1251-GISEL-TRUE16-LABEL: v_test_canonicalize_v3f32_flush:
; GFX1251-GISEL-TRUE16: ; %bb.0:
+; GFX1251-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX1251-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-TRUE16-NEXT: v_pk_mul_f32 v[0:1], 1.0, v[0:1] op_sel_hi:[0,1]
@@ -7181,6 +7182,7 @@ define <3 x float> @v_test_canonicalize_v3f32_flush(<3 x float> %arg) #1 {
;
; GFX1251-GISEL-FAKE16-LABEL: v_test_canonicalize_v3f32_flush:
; GFX1251-GISEL-FAKE16: ; %bb.0:
+; GFX1251-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr3
; GFX1251-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-FAKE16-NEXT: v_pk_mul_f32 v[0:1], 1.0, v[0:1] op_sel_hi:[0,1]
@@ -7541,6 +7543,7 @@ define <3 x double> @v_test_canonicalize_v3f64(<3 x double> %arg) #1 {
;
; GFX1251-GISEL-TRUE16-LABEL: v_test_canonicalize_v3f64:
; GFX1251-GISEL-TRUE16: ; %bb.0:
+; GFX1251-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX1251-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-TRUE16-NEXT: v_pk_max_num_f64 v[0:3], v[0:3], v[0:3]
@@ -7558,6 +7561,7 @@ define <3 x double> @v_test_canonicalize_v3f64(<3 x double> %arg) #1 {
;
; GFX1251-GISEL-FAKE16-LABEL: v_test_canonicalize_v3f64:
; GFX1251-GISEL-FAKE16: ; %bb.0:
+; GFX1251-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX1251-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1251-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1251-GISEL-FAKE16-NEXT: v_pk_max_num_f64 v[0:3], v[0:3], v[0:3]
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
index e78a0fd342e53..2122a63bcb29b 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
@@ -282,6 +282,8 @@ define amdgpu_kernel void @fcmp_f16_lt_abs(
; GFX12-TRUE16-NEXT: s_mov_b32 s15, s11
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s10
; GFX12-TRUE16-NEXT: s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index d999e548435ec..03241264e6f2d 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -44,11 +44,19 @@ define bfloat @v_copysign_bf16_bf16(bfloat %mag, bfloat %sign) {
; GFX10-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_copysign_bf16_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_copysign_bf16_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_copysign_bf16_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
%op = call bfloat @llvm.copysign.bf16(bfloat %mag, bfloat %sign)
ret bfloat %op
}
@@ -96,6 +104,8 @@ define bfloat @v_copysign_bf16_s_bf16(bfloat %mag, bfloat inreg %sign) {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -152,6 +162,8 @@ define bfloat @v_copysign_s_bf16_bf16(bfloat inreg %mag, bfloat %sign) {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -207,13 +219,22 @@ define bfloat @v_copysign_bf16_f32(bfloat %mag, float %sign.f32) {
; GFX10-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_copysign_bf16_f32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_copysign_bf16_f32:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_copysign_bf16_f32:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
%sign = fptrunc float %sign.f32 to bfloat
%op = call bfloat @llvm.copysign.bf16(bfloat %mag, bfloat %sign)
ret bfloat %op
@@ -261,13 +282,22 @@ define bfloat @v_copysign_bf16_f64(bfloat %mag, double %sign.f64) {
; GFX10-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_copysign_bf16_f64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_copysign_bf16_f64:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_copysign_bf16_f64:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
%sign = fptrunc double %sign.f64 to bfloat
%op = call bfloat @llvm.copysign.bf16(bfloat %mag, bfloat %sign)
ret bfloat %op
@@ -308,11 +338,19 @@ define bfloat @v_copysign_bf16_f16(bfloat %mag, half %sign.f16) {
; GFX10-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_copysign_bf16_f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_copysign_bf16_f16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_copysign_bf16_f16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
%sign = bitcast half %sign.f16 to bfloat
%op = call bfloat @llvm.copysign.bf16(bfloat %mag, bfloat %sign)
ret bfloat %op
@@ -365,6 +403,8 @@ define amdgpu_ps i32 @s_copysign_bf16_bf16(bfloat inreg %mag, bfloat inreg %sign
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -437,6 +477,7 @@ define amdgpu_ps i32 @s_copysign_bf16_f32(bfloat inreg %mag, float inreg %sign.f
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s1
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -510,6 +551,7 @@ define amdgpu_ps i32 @s_copysign_bf16_f64(bfloat inreg %mag, double inreg %sign.
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s2
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -581,6 +623,8 @@ define amdgpu_ps i32 @s_copysign_bf16_f16(bfloat inreg %mag, half inreg %sign.f1
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -651,6 +695,7 @@ define float @v_copysign_f32_bf16(float %mag, bfloat %sign.bf16) {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -716,6 +761,7 @@ define amdgpu_ps i32 @s_copysign_f32_bf16(float inreg %mag, bfloat inreg %sign.b
; GFX11TRUE16-LABEL: s_copysign_f32_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s1
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -772,11 +818,19 @@ define half @v_copysign_f16_bf16(half %mag, bfloat %sign.bf16) {
; GFX10-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_copysign_f16_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_copysign_f16_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_copysign_f16_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
%sign = bitcast bfloat %sign.bf16 to half
%op = call half @llvm.copysign.f16(half %mag, half %sign)
ret half %op
@@ -829,6 +883,8 @@ define amdgpu_ps i32 @s_copysign_f16_bf16(half inreg %mag, bfloat inreg %sign.bf
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -899,6 +955,7 @@ define double @v_copysign_f64_bf16(double %mag, bfloat %sign.bf16) {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v2.l
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -964,6 +1021,7 @@ define amdgpu_ps <2 x i32> @s_copysign_f64_bf16(double inreg %mag, bfloat inreg
; GFX11TRUE16-LABEL: s_copysign_f64_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v0
@@ -2852,6 +2910,7 @@ define amdgpu_ps i32 @s_copysign_out_f32_mag_f32_sign_bf16(float inreg %mag, bfl
; GFX11TRUE16-LABEL: s_copysign_out_f32_mag_f32_sign_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s1
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -2919,6 +2978,7 @@ define amdgpu_ps <2 x i32> @s_copysign_out_f64_mag_f64_sign_bf16(double inreg %m
; GFX11TRUE16-LABEL: s_copysign_out_f64_mag_f64_sign_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v0
@@ -2983,6 +3043,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_bf16_sign_f32(bfloat inreg %mag, f
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s1
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3047,6 +3108,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_bf16_sign_f64(bfloat inreg %mag, d
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s2
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -3143,6 +3205,8 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_f32_sign_bf16(float inreg %mag, bf
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
; GFX11TRUE16-NEXT: s_and_b32 s3, s3, exec_lo
; GFX11TRUE16-NEXT: s_cselect_b32 s0, s0, s2
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11TRUE16-NEXT: s_lshr_b32 s0, s0, 16
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
@@ -3293,6 +3357,7 @@ define <2 x float> @v_copysign_out_v2f32_mag_v2f32_sign_v2bf16(<2 x float> %mag,
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v3
@@ -3369,6 +3434,7 @@ define <2 x double> @v_copysign_out_v2f64_mag_v2f64_sign_v2bf16(<2 x double> %ma
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v4
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v5
@@ -4143,6 +4209,8 @@ define amdgpu_ps <2 x i32> @s_copysign_out_v2f32_mag_v2f32_sign_v2bf16(<2 x floa
; GFX11TRUE16-NEXT: s_lshr_b32 s3, s2, 16
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, s3
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v1
@@ -4242,6 +4310,8 @@ define amdgpu_ps <4 x i32> @s_copysign_out_v2f64_mag_v2f64_sign_v2bf16(<2 x doub
; GFX11TRUE16-NEXT: s_lshr_b32 s5, s4, 16
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s4
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, s5
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s3, v1
@@ -5019,6 +5089,8 @@ define <3 x float> @v_copysign_out_v3f32_mag_v3f32_sign_v3bf16(<3 x float> %mag,
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v3.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr4_lo16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v4
@@ -5109,6 +5181,8 @@ define <3 x double> @v_copysign_out_v3f64_mag_v3f64_sign_v3bf16(<3 x double> %ma
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v6
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v7
@@ -5276,6 +5350,7 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f32_sign_v3bf16(<3 x float> %ma
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v10, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v3
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v2, v4
@@ -5580,6 +5655,7 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v13, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v7
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
@@ -5798,6 +5874,7 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3bf16_sign_v3f32(<3 x bfloat> %m
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v2
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
@@ -5920,7 +5997,9 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3bf16_sign_v3f64(<3 x bfloat> %m
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v4
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v7
@@ -5928,6 +6007,7 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3bf16_sign_v3f64(<3 x bfloat> %m
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v4
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v3bf16_mag_v3bf16_sign_v3f64:
@@ -6117,6 +6197,8 @@ define <4 x float> @v_copysign_out_v4f32_mag_v4f32_sign_v4bf16(<4 x float> %mag,
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4
; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -6223,6 +6305,8 @@ define <4 x double> @v_copysign_out_v4f64_mag_v4f64_sign_v4bf16(<4 x double> %ma
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.h, v8.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.h, v9.l
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
+; GFX11TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v8
; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v9
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 3dace636df09b..4036a04b1f77f 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -43,6 +43,8 @@ define amdgpu_ps i16 @s_copysign_f16(half inreg %mag, half inreg %sign) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -361,11 +363,19 @@ define half @v_copysign_f16(half %mag, half %sign) {
; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_copysign_f16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_copysign_f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_copysign_f16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.copysign.f16(half %mag, half %sign)
ret half %result
}
@@ -664,6 +674,7 @@ define float @v_copysign_out_f32_mag_f32_sign_f16(float %mag, half %sign) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -709,6 +720,7 @@ define double @v_copysign_out_f64_mag_f64_sign_f16(double %mag, half %sign) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -751,13 +763,22 @@ define half @v_copysign_out_f16_mag_f16_sign_f32(half %mag, float %sign) {
; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_copysign_out_f16_mag_f16_sign_f32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_copysign_out_f16_mag_f16_sign_f32:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_copysign_out_f16_mag_f16_sign_f32:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sign.trunc = fptrunc float %sign to half
%out = call half @llvm.copysign.f16(half %mag, half %sign.trunc)
ret half %out
@@ -789,13 +810,22 @@ define half @v_copysign_out_f16_mag_f16_sign_f64(half %mag, double %sign) {
; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_copysign_out_f16_mag_f16_sign_f64:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_copysign_out_f16_mag_f16_sign_f64:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_copysign_out_f16_mag_f16_sign_f64:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%sign.trunc = fptrunc double %sign to half
%out = call half @llvm.copysign.f16(half %mag, half %sign.trunc)
ret half %out
@@ -830,6 +860,8 @@ define half @v_copysign_out_f16_mag_f32_sign_f16(float %mag, half %sign) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1027,8 +1059,10 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1236,11 +1270,13 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, hal
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xffe
; GFX11-TRUE16-NEXT: v_med3_i32 v1, s3, 0, 13
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
; GFX11-TRUE16-NEXT: s_or_b32 s3, s1, 0x1000
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s3, s4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s5, s4
@@ -2487,6 +2523,7 @@ define amdgpu_ps i32 @s_copysign_out_f32_mag_f32_sign_f16(float inreg %mag, half
; GFX11-TRUE16-LABEL: s_copysign_out_f32_mag_f32_sign_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -2536,6 +2573,7 @@ define amdgpu_ps <2 x i32> @s_copysign_out_f64_mag_f64_sign_f16(double inreg %ma
; GFX11-TRUE16-LABEL: s_copysign_out_f64_mag_f64_sign_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v0
@@ -2585,6 +2623,7 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f16_sign_f32(half inreg %mag, float
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -2634,6 +2673,7 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f16_sign_f64(half inreg %mag, doubl
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -2684,6 +2724,8 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f32_sign_f16(float inreg %mag, half
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -2798,6 +2840,7 @@ define <2 x float> @v_copysign_out_v2f32_mag_v2f32_sign_v2f16(<2 x float> %mag,
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v3
@@ -2857,6 +2900,7 @@ define <2 x double> @v_copysign_out_v2f64_mag_v2f64_sign_v2f16(<2 x double> %mag
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v5
@@ -3600,6 +3644,8 @@ define amdgpu_ps <2 x i32> @s_copysign_out_v2f32_mag_v2f32_sign_v2f16(<2 x float
; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s2, 16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, s3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v1
@@ -3674,6 +3720,8 @@ define amdgpu_ps <4 x i32> @s_copysign_out_v2f64_mag_v2f64_sign_v2f16(<2 x doubl
; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s4, 16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, s5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s3, v1
@@ -4377,6 +4425,8 @@ define <3 x float> @v_copysign_out_v3f32_mag_v3f32_sign_v3f16(<3 x float> %mag,
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v4
@@ -4446,6 +4496,8 @@ define <3 x double> @v_copysign_out_v3f64_mag_v3f64_sign_v3f16(<3 x double> %mag
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v7
@@ -4521,6 +4573,7 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f32_sign_v3f16(<3 x float> %mag, <
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v1
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v3
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v2, v4
@@ -5210,6 +5263,7 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f16_sign_v3f32(<3 x half> %mag, <3
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.h, v3
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v2
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v2
@@ -5287,7 +5341,9 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f16_sign_v3f64(<3 x half> %mag, <3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v7
@@ -5295,6 +5351,7 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f16_sign_v3f64(<3 x half> %mag, <3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f64:
@@ -5452,6 +5509,8 @@ define <4 x float> @v_copysign_out_v4f32_mag_v4f32_sign_v4f16(<4 x float> %mag,
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4
; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -5535,6 +5594,8 @@ define <4 x double> @v_copysign_out_v4f64_mag_v4f64_sign_v4f16(<4 x double> %mag
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v8
; GFX11-TRUE16-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -6706,6 +6767,7 @@ define amdgpu_ps i32 @s_copysign_f16_0_f32(float inreg %sign) {
; GFX11-TRUE16-LABEL: s_copysign_f16_0_f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x8000, v0
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
index 7b11922e75b4f..e566eb348c3a0 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
@@ -999,6 +999,7 @@ define amdgpu_kernel void @s_test_copysign_f32_fpext_f16(ptr addrspace(1) %out,
; GFX11-LABEL: s_test_copysign_f32_fpext_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_mov_b16_e32 v0.h, s3
@@ -1094,6 +1095,7 @@ define amdgpu_kernel void @s_test_copysign_f32_fpext_bf16(ptr addrspace(1) %out,
; GFX11-LABEL: s_test_copysign_f32_fpext_bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_mov_b16_e32 v0.h, s3
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
index 6c37316d33d03..faca7f46269d3 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
@@ -372,6 +372,7 @@ define amdgpu_kernel void @s_test_copysign_f64_f16(ptr addrspace(1) %out, [8 x i
; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x74
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x4c
; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
+; GFX11-NEXT: ; implicit-def: $vgpr0_lo16
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_mov_b16_e32 v0.h, s6
@@ -974,6 +975,7 @@ define double @v_test_copysign_f64_f16(ptr addrspace(1) %out, [8 x i32], double
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mov_b16_e32 v1.h, v20.l
+; GFX11-NEXT: ; implicit-def: $vgpr1_lo16
; GFX11-NEXT: v_mov_b32_e32 v0, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v11, v1
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll
index 5df61f19033a3..de8c9cea84529 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll
@@ -11,6 +11,7 @@ define amdgpu_gs i32 @vgpr16_copyto_sgpr() {
; CHECK-NEXT: ds_load_2addr_b32 v[0:1], v0 offset1:1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; CHECK-NEXT: ; implicit-def: $vgpr0_hi16
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: s_and_b32 s0, 0xffff, s0
diff --git a/llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll b/llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
index 0a4edd142d8db..6f397e6355e7e 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
@@ -167,6 +167,7 @@ define amdgpu_kernel void @load_i16_hi(ptr %arg, ptr %out) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: v_mov_b16_e32 v2.l, 0
+; GFX11-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: flat_load_d16_hi_b16 v2, v[0:1] offset:8
@@ -273,6 +274,7 @@ define amdgpu_kernel void @load_half_hi(ptr %arg, ptr %out) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: v_mov_b16_e32 v2.l, 0
+; GFX11-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: flat_load_d16_hi_b16 v2, v[0:1] offset:8
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
index 35aa5e401afe6..d73897bb54e5f 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
@@ -1929,12 +1929,12 @@ define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64_immneg128(ptr inreg %sb
; --------------------------------------------------------------------------------
define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi(ptr inreg %sbase, i32 %voffset) {
-; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_undef_hi:
-; GFX1250-SDAG: ; %bb.0:
-; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-SDAG-NEXT: flat_load_u16 v0, v0, s[2:3]
-; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-NEXT: ; return to shader part epilog
+; GFX1250-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16lo_undef_hi:
+; GFX1250-SDAG-FAKE16: ; %bb.0:
+; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v0, s[2:3]
+; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: flat_load_saddr_i16_d16lo_undef_hi:
; GFX1250-GISEL-FAKE16: ; %bb.0:
@@ -1946,10 +1946,19 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi(ptr inreg %sbase
; GFX1250-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
;
+; GFX1250-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16lo_undef_hi:
+; GFX1250-SDAG-TRUE16: ; %bb.0:
+; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v0, s[2:3]
+; GFX1250-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
; GFX1250-GISEL-TRUE16-LABEL: flat_load_saddr_i16_d16lo_undef_hi:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: flat_load_u16 v0, v0, s[2:3]
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
@@ -1968,12 +1977,12 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi(ptr inreg %sbase
}
define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi_immneg128(ptr inreg %sbase, i32 %voffset) {
-; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:
-; GFX1250-SDAG: ; %bb.0:
-; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-SDAG-NEXT: flat_load_u16 v0, v0, s[2:3] offset:-128
-; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-NEXT: ; return to shader part epilog
+; GFX1250-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:
+; GFX1250-SDAG-FAKE16: ; %bb.0:
+; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v0, s[2:3] offset:-128
+; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:
; GFX1250-GISEL-FAKE16: ; %bb.0:
@@ -1985,10 +1994,19 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi_immneg128(ptr in
; GFX1250-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
;
+; GFX1250-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:
+; GFX1250-SDAG-TRUE16: ; %bb.0:
+; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v0, s[2:3] offset:-128
+; GFX1250-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
; GFX1250-GISEL-TRUE16-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: flat_load_u16 v0, v0, s[2:3] offset:-128
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
@@ -2406,6 +2424,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi(ptr inreg %sbase
; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v0, s[2:3]
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX1250-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: flat_load_saddr_i16_d16hi_undef_hi:
@@ -2414,6 +2433,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi(ptr inreg %sbase
; GFX1250-GISEL-TRUE16-NEXT: flat_load_u16 v0, v0, s[2:3]
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_undef_hi:
@@ -2455,6 +2475,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi_immneg128(ptr in
; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v0, s[2:3] offset:-128
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX1250-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: flat_load_saddr_i16_d16hi_undef_hi_immneg128:
@@ -2463,6 +2484,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi_immneg128(ptr in
; GFX1250-GISEL-TRUE16-NEXT: flat_load_u16 v0, v0, s[2:3] offset:-128
; GFX1250-GISEL-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_undef_hi_immneg128:
@@ -2511,6 +2533,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi(ptr inreg %sbase,
; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_b16 v1, v0, s[2:3]
; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
@@ -2563,6 +2586,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi_immneg128(ptr inr
; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
@@ -2614,13 +2638,22 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi(ptr inreg %sbase,
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_b16 v1, v0, s[2:3]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
+; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_reg_hi:
+; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_b16 v1, v0, s[2:3]
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_reg_hi:
+; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_d16_hi_b16 v1, v0, s[2:3]
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i16, ptr %gep0
@@ -2658,13 +2691,22 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi_immneg128(ptr inre
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
+; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_reg_hi_immneg128:
+; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_reg_hi_immneg128:
+; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2703,13 +2745,22 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi(ptr inreg %
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_u8 v1, v0, s[2:3]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
+; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi:
+; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_u8 v1, v0, s[2:3]
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi:
+; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_d16_hi_u8 v1, v0, s[2:3]
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -2748,13 +2799,22 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128(p
; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
+; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
+; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
+; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
@@ -2806,13 +2866,22 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi(ptr inreg %
; GFX1250-GISEL-TRUE16-NEXT: v_and_or_b32 v0, 0xffff, v1, v0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_i8 v1, v0, s[2:3]
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
+; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi:
+; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_i8 v1, v0, s[2:3]
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi:
+; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_d16_hi_i8 v1, v0, s[2:3]
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%load = load i8, ptr %gep0
@@ -2863,13 +2932,22 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128(p
; GFX1250-GISEL-TRUE16-NEXT: v_and_or_b32 v0, 0xffff, v1, v0
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
-; GFX1250-NOECC: ; %bb.0:
-; GFX1250-NOECC-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NOECC-NEXT: flat_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
-; GFX1250-NOECC-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NOECC-NEXT: v_mov_b32_e32 v0, v1
-; GFX1250-NOECC-NEXT: ; return to shader part epilog
+; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
+; GFX1250-NOECC-SDAG-TRUE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: flat_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
+; GFX1250-NOECC-SDAG-FAKE16: ; %bb.0:
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: flat_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX1250-NOECC-SDAG-FAKE16-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr %gep0, i64 -128
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
index 728706c7cba3c..edba3b70f93e2 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
@@ -265,6 +265,7 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_hi_v(ptr addrspace(5) %i
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX11-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX11-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-NEXT: scratch_load_d16_hi_u8 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
@@ -273,6 +274,7 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_hi_v(ptr addrspace(5) %i
; GFX12-LABEL: test_scratch_load_i8_zext_to_d16_hi_v:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-NEXT: scratch_load_d16_hi_u8 v3, v0, off offset:1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[1:2], v3
@@ -304,6 +306,7 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_hi_v(ptr addrspace(5) %i
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_add_nc_u32_e32 v0, 1, v0
; GFX11-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX11-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-NEXT: scratch_load_d16_hi_i8 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
@@ -312,6 +315,7 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_hi_v(ptr addrspace(5) %i
; GFX12-LABEL: test_scratch_load_i8_sext_to_d16_hi_v:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-NEXT: scratch_load_d16_hi_i8 v3, v0, off offset:1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[1:2], v3
@@ -343,6 +347,7 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_hi_v(ptr addrspace(5) %in, p
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX11-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX11-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-NEXT: scratch_load_d16_hi_b16 v3, v0, off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[1:2], v3
@@ -351,6 +356,7 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_hi_v(ptr addrspace(5) %in, p
; GFX12-LABEL: test_scratch_load_i16_to_d16_hi_v:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-NEXT: scratch_load_d16_hi_b16 v3, v0, off offset:2
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[1:2], v3
@@ -701,6 +707,7 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_hi_s(ptr addrspace(5) in
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_mov_b16_e32 v2.l, -1
; GFX11-NEXT: s_add_i32 s0, s0, 1
+; GFX11-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-NEXT: scratch_load_d16_hi_u8 v2, off, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[0:1], v2
@@ -709,6 +716,7 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_hi_s(ptr addrspace(5) in
; GFX12-LABEL: test_scratch_load_i8_zext_to_d16_hi_s:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_mov_b16_e32 v2.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-NEXT: scratch_load_d16_hi_u8 v2, off, s0 offset:1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[0:1], v2
@@ -740,6 +748,7 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_hi_s(ptr addrspace(5) in
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_mov_b16_e32 v2.l, -1
; GFX11-NEXT: s_add_i32 s0, s0, 1
+; GFX11-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-NEXT: scratch_load_d16_hi_i8 v2, off, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[0:1], v2
@@ -748,6 +757,7 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_hi_s(ptr addrspace(5) in
; GFX12-LABEL: test_scratch_load_i8_sext_to_d16_hi_s:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_mov_b16_e32 v2.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-NEXT: scratch_load_d16_hi_i8 v2, off, s0 offset:1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[0:1], v2
@@ -779,6 +789,7 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_hi_s(ptr addrspace(5) inreg
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_mov_b16_e32 v2.l, -1
; GFX11-NEXT: s_add_i32 s0, s0, 2
+; GFX11-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-NEXT: scratch_load_d16_hi_b16 v2, off, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: flat_store_b32 v[0:1], v2
@@ -787,6 +798,7 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_hi_s(ptr addrspace(5) inreg
; GFX12-LABEL: test_scratch_load_i16_to_d16_hi_s:
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_mov_b16_e32 v2.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-NEXT: scratch_load_d16_hi_b16 v2, off, s0 offset:2
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[0:1], v2
@@ -1170,6 +1182,7 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_hi_svs(ptr addrspace(5)
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX11-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_add3_u32 v0, s0, v0, 1
; GFX11-NEXT: scratch_load_d16_hi_u8 v3, v0, off
@@ -1181,6 +1194,7 @@ define amdgpu_ps void @test_scratch_load_i8_zext_to_d16_hi_svs(ptr addrspace(5)
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-NEXT: scratch_load_d16_hi_u8 v3, v0, s0 offset:1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[1:2], v3
@@ -1215,6 +1229,7 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_hi_svs(ptr addrspace(5)
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX11-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_add3_u32 v0, s0, v0, 1
; GFX11-NEXT: scratch_load_d16_hi_i8 v3, v0, off
@@ -1226,6 +1241,7 @@ define amdgpu_ps void @test_scratch_load_i8_sext_to_d16_hi_svs(ptr addrspace(5)
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-NEXT: scratch_load_d16_hi_i8 v3, v0, s0 offset:1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[1:2], v3
@@ -1260,6 +1276,7 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_hi_svs(ptr addrspace(5) inre
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX11-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_add3_u32 v0, s0, v0, 2
; GFX11-NEXT: scratch_load_d16_hi_b16 v3, v0, off
@@ -1271,6 +1288,7 @@ define amdgpu_ps void @test_scratch_load_i16_to_d16_hi_svs(ptr addrspace(5) inre
; GFX12: ; %bb.0: ; %bb
; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX12-NEXT: v_mov_b16_e32 v3.l, -1
+; GFX12-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-NEXT: scratch_load_d16_hi_b16 v3, v0, s0 offset:2
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: flat_store_b32 v[1:2], v3
diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
index 8d1d08d1e7c68..fd68c979cce43 100644
--- a/llvm/test/CodeGen/AMDGPU/fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
@@ -44,6 +44,7 @@ define half @test_fma(half %x, half %y, half %z) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -82,6 +83,7 @@ define half @test_fma(half %x, half %y, half %z) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -129,6 +131,7 @@ define half @test_fmac(half %x, half %y, half %z) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v0.l, v1.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_fmac:
@@ -165,6 +168,7 @@ define half @test_fmac(half %x, half %y, half %z) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v0.l, v1.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_fmac:
@@ -218,6 +222,7 @@ define half @test_fmaak(half %x, half %y, half %z) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_fmaak_f16 v0.l, v0.l, v1.l, 0x4200
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_fmaak:
@@ -254,6 +259,7 @@ define half @test_fmaak(half %x, half %y, half %z) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_fmaak_f16 v0.l, v0.l, v1.l, 0x4200
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_fmaak:
@@ -307,6 +313,7 @@ define half @test_fmamk(half %x, half %y, half %z) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v2.l, 0x4200, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -345,6 +352,7 @@ define half @test_fmamk(half %x, half %y, half %z) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v2.l, 0x4200, v0.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
index 8ff27781b4e31..5f9dd0e5146c7 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
@@ -260,6 +260,7 @@ define <3 x half> @test_fmax_legacy_ugt_v3f16(<3 x half> %a, <3 x half> %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v2.h
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v1.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index c89576707f28d..230b7b13ef037 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -414,6 +414,7 @@ define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) {
; GFX1170-GISEL-TRUE16-LABEL: test_fmaximum_f16_vv:
; GFX1170-GISEL-TRUE16: ; %bb.0:
; GFX1170-GISEL-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1170-GISEL-FAKE16-LABEL: test_fmaximum_f16_vv:
@@ -434,6 +435,7 @@ define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) {
; GFX12-GISEL-TRUE16-LABEL: test_fmaximum_f16_vv:
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-FAKE16-LABEL: test_fmaximum_f16_vv:
@@ -478,6 +480,7 @@ define amdgpu_ps half @test_fmaximum_f16_ss(half inreg %a, half inreg %b) {
; GFX1170-GISEL-TRUE16-LABEL: test_fmaximum_f16_ss:
; GFX1170-GISEL-TRUE16: ; %bb.0:
; GFX1170-GISEL-TRUE16-NEXT: v_maximum_f16 v0.l, s0, s1
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1170-GISEL-FAKE16-LABEL: test_fmaximum_f16_ss:
@@ -631,6 +634,7 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b
; GFX1170-GISEL-TRUE16: ; %bb.0:
; GFX1170-GISEL-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX1170-GISEL-TRUE16-NEXT: v_maximum_f16 v1.l, v1.l, v3.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1170-GISEL-FAKE16-LABEL: test_fmaximum_v3f16_vv:
@@ -652,6 +656,7 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX12-GISEL-TRUE16-NEXT: v_maximum_f16 v1.l, v1.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-FAKE16-LABEL: test_fmaximum_v3f16_vv:
@@ -729,6 +734,7 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x ha
; GFX1170-GISEL-TRUE16: ; %bb.0:
; GFX1170-GISEL-TRUE16-NEXT: v_maximum_f16 v1.l, s1, s3
; GFX1170-GISEL-TRUE16-NEXT: v_pk_maximum_f16 v0, s0, s2
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s0, v1
; GFX1170-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, s0
@@ -1524,6 +1530,8 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
index bdbd980cc166b..7f2c1c50c9e3f 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
@@ -1558,6 +1558,7 @@ define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %
; GFX12-TRUE16-LABEL: s_fmaximum3_f16:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_maximum3_f16 v0.l, s0, s1, v0.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -1580,6 +1581,7 @@ define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %
; GFX1170-TRUE16-LABEL: s_fmaximum3_f16:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_maximum3_f16 v0.l, s0, s1, v0.l
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -4667,6 +4669,8 @@ define amdgpu_ps <2 x i32> @s_no_fmaximum3_f16__multi_use(half inreg %a, half in
; GFX1170-TRUE16-LABEL: s_no_fmaximum3_f16__multi_use:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: v_maximum_f16 v0.l, s0, s1
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-TRUE16-NEXT: v_maximum_f16 v1.l, v0.l, s2
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
index c9b3ff79366b5..1abe3013922c8 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
@@ -76,6 +76,7 @@ define <3 x half> @fmaximum3_v3f16(<3 x half> %a, <3 x half> %b, <3 x half> %c)
; GFX1250-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-REAL16-NEXT: v_pk_maximum3_f16 v0, v0, v2, v2
; GFX1250-GISEL-REAL16-NEXT: v_maximum3_f16 v1.l, v1.l, v3.l, v5.l
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-REAL16-NEXT: v_pk_maximum3_f16 v0, v4, v0, v0
; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
index 8ec4d3fb29535..d738eab000b05 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
@@ -1932,6 +1932,8 @@ define amdgpu_kernel void @test_fmax_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX12-GISEL-LABEL: test_fmax_f16_v_ieee_on:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: s_lshr_b32 s3, s2, 16
; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0.l, s2, s2
@@ -1963,10 +1965,16 @@ define amdgpu_ps half @test_fmax_f16_v_ieee_off(half %a, half %b) #0 {
; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: test_fmax_f16_v_ieee_off:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: test_fmax_f16_v_ieee_off:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: test_fmax_f16_v_ieee_off:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call half @llvm.maxnum.f16(half %a, half %b)
ret half %val
}
@@ -2054,6 +2062,8 @@ define amdgpu_kernel void @test_fmax_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-GISEL-NEXT: s_load_u16 s2, s[4:5], 0x2c
; GFX12-GISEL-NEXT: s_load_u16 s3, s[4:5], 0x2e
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0.l, s2, s2
; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1.l, s3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.ll b/llvm/test/CodeGen/AMDGPU/fmed3.ll
index 5e170cff3e32f..1a1972d66cd71 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.ll
@@ -8775,6 +8775,7 @@ define half @v_test_fmed3_r_i_i_f16_minimumnum_maximumnum(half %a) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_f16 v0.l, v0.l, 2.0, 4.0
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -9185,6 +9186,7 @@ define half @v_test_nnan_input_fmed3_r_i_i_f16_maximum_minimum(half %a) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_f16 v0.l, v0.l, 2.0, 4.0
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
index 46f969c23198a..816975f068d9a 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
@@ -261,6 +261,7 @@ define <3 x half> @test_fmin_legacy_ule_v3f16(<3 x half> %a, <3 x half> %b) #0 {
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v2.h
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v1.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 194bf6377bf2e..0e901e4a67521 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -414,6 +414,7 @@ define amdgpu_ps half @test_fminimum_f16_vv(half %a, half %b) {
; GFX1170-GISEL-TRUE16-LABEL: test_fminimum_f16_vv:
; GFX1170-GISEL-TRUE16: ; %bb.0:
; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1170-GISEL-FAKE16-LABEL: test_fminimum_f16_vv:
@@ -434,6 +435,7 @@ define amdgpu_ps half @test_fminimum_f16_vv(half %a, half %b) {
; GFX12-GISEL-TRUE16-LABEL: test_fminimum_f16_vv:
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-FAKE16-LABEL: test_fminimum_f16_vv:
@@ -478,6 +480,7 @@ define amdgpu_ps half @test_fminimum_f16_ss(half inreg %a, half inreg %b) {
; GFX1170-GISEL-TRUE16-LABEL: test_fminimum_f16_ss:
; GFX1170-GISEL-TRUE16: ; %bb.0:
; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, s0, s1
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1170-GISEL-FAKE16-LABEL: test_fminimum_f16_ss:
@@ -631,6 +634,7 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_vv(<3 x half> %a, <3 x half> %b
; GFX1170-GISEL-TRUE16: ; %bb.0:
; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v3.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1170-GISEL-FAKE16-LABEL: test_fminimum_v3f16_vv:
@@ -652,6 +656,7 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_vv(<3 x half> %a, <3 x half> %b
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-FAKE16-LABEL: test_fminimum_v3f16_vv:
@@ -729,6 +734,7 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_ss(<3 x half> inreg %a, <3 x ha
; GFX1170-GISEL-TRUE16: ; %bb.0:
; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, s1, s3
; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, s0, s2
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s0, v1
; GFX1170-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, s0
@@ -1524,6 +1530,8 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum3.ll b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
index 0cd4293a16116..fff559774fc6c 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
@@ -1558,6 +1558,7 @@ define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %
; GFX12-TRUE16-LABEL: s_fminimum3_f16:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_minimum3_f16 v0.l, s0, s1, v0.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -1580,6 +1581,7 @@ define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %
; GFX1170-TRUE16-LABEL: s_fminimum3_f16:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_minimum3_f16 v0.l, s0, s1, v0.l
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -4667,6 +4669,8 @@ define amdgpu_ps <2 x i32> @s_no_fminimum3_f16__multi_use(half inreg %a, half in
; GFX1170-TRUE16-LABEL: s_no_fminimum3_f16__multi_use:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: v_minimum_f16 v0.l, s0, s1
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1170-TRUE16-NEXT: v_minimum_f16 v1.l, v0.l, s2
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll b/llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
index 51618cae3398e..35bcbe72f0e98 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
@@ -76,6 +76,7 @@ define <3 x half> @fminimum3_v3f16(<3 x half> %a, <3 x half> %b, <3 x half> %c)
; GFX1250-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-REAL16-NEXT: v_pk_minimum3_f16 v0, v0, v2, v2
; GFX1250-GISEL-REAL16-NEXT: v_minimum3_f16 v1.l, v1.l, v3.l, v5.l
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-REAL16-NEXT: v_pk_minimum3_f16 v0, v4, v0, v0
; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.ll b/llvm/test/CodeGen/AMDGPU/fminnum.ll
index cf927b83c07de..42d83880c3c16 100644
--- a/llvm/test/CodeGen/AMDGPU/fminnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminnum.ll
@@ -1845,6 +1845,8 @@ define amdgpu_kernel void @test_fmin_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX12-GISEL-LABEL: test_fmin_f16_v_ieee_on:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: s_lshr_b32 s3, s2, 16
; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0.l, s2, s2
@@ -1876,10 +1878,16 @@ define amdgpu_ps half @test_fmin_f16_v_ieee_off(half %a, half %b) #0 {
; GFX9-NEXT: v_min_f16_e32 v0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: test_fmin_f16_v_ieee_off:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: test_fmin_f16_v_ieee_off:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: test_fmin_f16_v_ieee_off:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%val = call half @llvm.minnum.f16(half %a, half %b)
ret half %val
}
@@ -1967,6 +1975,8 @@ define amdgpu_kernel void @test_fmin_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-GISEL-NEXT: s_load_u16 s2, s[4:5], 0x2c
; GFX12-GISEL-NEXT: s_load_u16 s3, s[4:5], 0x2e
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_max_num_f16_e64 v0.l, s2, s2
; GFX12-GISEL-NEXT: v_max_num_f16_e64 v1.l, s3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
index 8e1c5b0db7e90..adb717b1c5924 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
@@ -83,6 +83,7 @@ define half @v_mul_42_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x5140, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_42_f16:
@@ -2713,6 +2714,7 @@ define half @v_mul_0x1pn23_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 2, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1pn23_f16:
@@ -2754,6 +2756,7 @@ define half @v_mul_0x1pn17_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x80, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1pn17_f16:
@@ -2795,6 +2798,7 @@ define half @v_mul_0x1pn16_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x100, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1pn16_f16:
@@ -2836,6 +2840,7 @@ define half @v_mul_0x1pn15_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x200, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1pn15_f16:
@@ -2876,6 +2881,7 @@ define half @v_mul_neg256_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xdc00, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg256_f16:
@@ -2916,6 +2922,7 @@ define half @v_mul_neg128_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xd800, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg128_f16:
@@ -2956,6 +2963,7 @@ define half @v_mul_neg64_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xd400, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg64_f16:
@@ -2996,6 +3004,7 @@ define half @v_mul_neg32_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xd000, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg32_f16:
@@ -3036,6 +3045,7 @@ define half @v_mul_neg16_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xcc00, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg16_f16:
@@ -3076,6 +3086,7 @@ define half @v_mul_neg8_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xc800, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg8_f16:
@@ -3116,6 +3127,7 @@ define half @v_mul_neg4_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, -4.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg4_f16:
@@ -3156,6 +3168,7 @@ define half @v_mul_neg2_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, -2.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg2_f16:
@@ -3196,6 +3209,7 @@ define half @v_mul_neg1_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg1_f16:
@@ -3236,6 +3250,7 @@ define half @v_mul_neg_half_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, -0.5, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg_half_f16:
@@ -3276,6 +3291,7 @@ define half @v_mul_neg_quarter_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0xb400, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_neg_quarter_f16:
@@ -3316,6 +3332,7 @@ define half @v_mul_quarter_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x3400, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_quarter_f16:
@@ -3356,6 +3373,7 @@ define half @v_mul_half_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.5, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_half_f16:
@@ -3417,6 +3435,7 @@ define half @v_mul_2_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 2.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_2_f16:
@@ -3457,6 +3476,7 @@ define half @v_mul_4_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 4.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_4_f16:
@@ -3497,6 +3517,7 @@ define half @v_mul_8_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x4800, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_8_f16:
@@ -3537,6 +3558,7 @@ define half @v_mul_16_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x4c00, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_16_f16:
@@ -3577,6 +3599,7 @@ define half @v_mul_32_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x5000, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_32_f16:
@@ -3617,6 +3640,7 @@ define half @v_mul_64_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x5400, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_64_f16:
@@ -3657,6 +3681,7 @@ define half @v_mul_128_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x5800, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_128_f16:
@@ -3697,6 +3722,7 @@ define half @v_mul_256_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x5c00, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_256_f16:
@@ -3738,6 +3764,7 @@ define half @v_mul_0x1p15_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x7800, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1p15_f16:
@@ -3779,6 +3806,7 @@ define half @v_mul_0x1p14_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x7400, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1p14_f16:
@@ -3828,6 +3856,7 @@ define half @v_fma_mul_add_32_f16(half %x, half %y) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v1.l, 0x5000, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3878,6 +3907,7 @@ define half @v_fma_mul_sub_32_f16(half %x, half %y) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, 0x5000, -v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_fma_mul_sub_32_f16:
@@ -3927,6 +3957,7 @@ define half @v_fma_mul_add_neg32_f16(half %x, half %y) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v1.l, 0xd000, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3977,6 +4008,7 @@ define half @v_mul_fabs_32_f16(half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e64 v0.l, 0x5000, |v0.l|
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_fabs_32_f16:
@@ -4026,6 +4058,7 @@ define half @v_mul_add_fma_fabs_32_f16(half %x, half %y) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_fma_f16 v0.l, |v0.l|, 0x5000, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_add_fma_fabs_32_f16:
@@ -4248,6 +4281,7 @@ define amdgpu_ps i32 @s_mul_32_f16(half inreg %x, half inreg %y) {
; GFX11-SDAG-TRUE16-LABEL: s_mul_32_f16:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e64 v0.l, 0x5000, s0
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog
@@ -4262,6 +4296,7 @@ define amdgpu_ps i32 @s_mul_32_f16(half inreg %x, half inreg %y) {
; GFX11-GISEL-TRUE16-LABEL: s_mul_32_f16:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e64 v0.l, 0x5000, s0
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog
@@ -5705,6 +5740,7 @@ define half @v_mul_f16_select_64_1(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5759,6 +5795,7 @@ define half @v_mul_f16_select_1_64(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5813,6 +5850,7 @@ define half @v_mul_f16_select_n1_n64(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5893,6 +5931,7 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5976,6 +6015,7 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6033,6 +6073,7 @@ define half @v_mul_f16_select_n128_n16(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6110,6 +6151,7 @@ define half @v_contract_mul_add_f16_select_64_1(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6190,6 +6232,7 @@ define half @v_contract_mul_add_f16_select_1_64(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6270,6 +6313,7 @@ define half @v_contract_mul_add_f16_select_n64_n1(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6350,6 +6394,7 @@ define half @v_contract_mul_add_f16_select_n1_n64(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6440,6 +6485,7 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6523,6 +6569,7 @@ define half @v_contract_mul_add_f16_select_128_4(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6613,6 +6660,7 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6696,6 +6744,7 @@ define half @v_contract_mul_add_f16_select_4_128(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -8436,6 +8485,7 @@ define half @v_constrained_fmul_32_f16(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x5000, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_constrained_fmul_32_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
index 5424ebfcffcd1..3805010ee0099 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
@@ -371,6 +371,7 @@ define amdgpu_kernel void @v_fneg_fabs_bf16(ptr addrspace(1) %out, ptr addrspace
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
index 00d53cd265c28..6cf4fe25f78ce 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
@@ -346,6 +346,7 @@ define amdgpu_kernel void @v_fneg_fabs_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
index 63aadaacbeb3a..080259554c5b9 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
@@ -307,6 +307,7 @@ define amdgpu_kernel void @v_fneg_fold_bf16(ptr addrspace(1) %out, ptr addrspace
; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x8000, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/fpext-free.ll b/llvm/test/CodeGen/AMDGPU/fpext-free.ll
index 10a925f9df687..ec48fc9592b75 100644
--- a/llvm/test/CodeGen/AMDGPU/fpext-free.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpext-free.ll
@@ -14,6 +14,7 @@ define float @fadd_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel_hi:[1,1,0]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -124,6 +125,7 @@ define float @fadd_fpext_fmul_f16_to_f32_commute(half %x, half %y, float %z) #0
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel_hi:[1,1,0]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -171,6 +173,7 @@ define float @fadd_muladd_fpext_fmul_f16_to_f32(float %x, float %y, half %u, hal
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
@@ -235,6 +238,7 @@ define float @fadd_muladd_fpext_fmul_f16_to_f32_commute(float %x, float %y, half
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v4, v0
@@ -297,6 +301,7 @@ define float @fadd_fmad_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
@@ -362,6 +367,7 @@ define float @fadd_fma_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half %
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
@@ -414,6 +420,7 @@ define float @fadd_fma_fpext_fmul_f16_to_f32_commute(float %x, float %y, half %u
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v4, v0
@@ -468,6 +475,7 @@ define float @fadd_fpext_fmuladd_f16_to_f32(float %x, half %y, half %z, half %u,
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0]
@@ -519,6 +527,7 @@ define float @fadd_fpext_fma_f16_to_f32(float %x, half %y, half %z, half %u, hal
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0]
@@ -570,6 +579,7 @@ define float @fadd_fpext_fma_f16_to_f32_commute(float %x, half %y, half %z, half
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0]
@@ -623,6 +633,7 @@ define float @fsub_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -666,16 +677,25 @@ entry:
; fold (fsub x, (fpext (fmul y, z)))
; -> (fma (fneg (fpext y)), (fpext z), x)
define float @fsub_fpext_fmul_f16_to_f32_commute(float %x, half %y, half %z) #0 {
-; GFX11-F32FLUSH-LABEL: fsub_fpext_fmul_f16_to_f32_commute:
-; GFX11-F32FLUSH: ; %bb.0: ; %entry
-; GFX11-F32FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-F32FLUSH-NEXT: v_fma_mix_f32 v0, -v1, v2, v0 op_sel_hi:[1,1,0]
-; GFX11-F32FLUSH-NEXT: s_setpc_b64 s[30:31]
+; GFX11-F32FLUSH-TRUE16-LABEL: fsub_fpext_fmul_f16_to_f32_commute:
+; GFX11-F32FLUSH-TRUE16: ; %bb.0: ; %entry
+; GFX11-F32FLUSH-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-F32FLUSH-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-F32FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-F32FLUSH-TRUE16-NEXT: v_fma_mix_f32 v0, -v1, v2, v0 op_sel_hi:[1,1,0]
+; GFX11-F32FLUSH-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-F32FLUSH-FAKE16-LABEL: fsub_fpext_fmul_f16_to_f32_commute:
+; GFX11-F32FLUSH-FAKE16: ; %bb.0: ; %entry
+; GFX11-F32FLUSH-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-F32FLUSH-FAKE16-NEXT: v_fma_mix_f32 v0, -v1, v2, v0 op_sel_hi:[1,1,0]
+; GFX11-F32FLUSH-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-F32DENORM-TRUE16-LABEL: fsub_fpext_fmul_f16_to_f32_commute:
; GFX11-F32DENORM-TRUE16: ; %bb.0: ; %entry
; GFX11-F32DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-F32DENORM-TRUE16-NEXT: v_mul_f16_e32 v1.l, v1.l, v2.l
+; GFX11-F32DENORM-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-F32DENORM-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-F32DENORM-TRUE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,0]
; GFX11-F32DENORM-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -723,6 +743,7 @@ define float @fsub_fpext_fneg_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -771,6 +792,7 @@ define float @fsub_fneg_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -819,6 +841,7 @@ define float @fsub_muladd_fpext_mul_f16_to_f32(float %x, float %y, float %z, hal
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2
@@ -884,6 +907,7 @@ define float @fsub_fpext_muladd_mul_f16_to_f32(half %x, half %y, float %z, half
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v0.l, v1.l
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v3 op_sel_hi:[0,1,1]
@@ -938,6 +962,7 @@ define float @fsub_muladd_fpext_mul_f16_to_f32_commute(float %x, float %y, float
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v2, v3 op_sel_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
@@ -1002,6 +1027,7 @@ define float @fsub_fpext_muladd_mul_f16_to_f32_commute(float %x, half %y, half %
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v3, -1.0, v0 op_sel_hi:[1,1,0]
@@ -1057,5 +1083,4 @@ declare half @llvm.fma.f16(half, half, half) #0
attributes #0 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11-F32DENORM: {{.*}}
-; GFX11-F32FLUSH-FAKE16: {{.*}}
-; GFX11-F32FLUSH-TRUE16: {{.*}}
+; GFX11-F32FLUSH: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
index f2a0193a655f0..354823bd6f55a 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
@@ -190,16 +190,17 @@ define i128 @fptosi_f64_to_i128(double %x) {
; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v15, v9, v[2:3]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v14, v8, 0
-; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v8, v[11:12]
-; GISEL-NEXT: v_mul_lo_u32 v6, v15, v10
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v6, v8, v[11:12]
+; GISEL-NEXT: v_mul_lo_u32 v4, v15, v10
; GISEL-NEXT: v_mul_lo_u32 v10, v14, v10
; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[6:7], v14, v9, v[1:2]
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v15, v8, v[11:12]
; GISEL-NEXT: v_addc_co_u32_e64 v3, s[8:9], v3, v10, s[8:9]
-; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v6, s[6:7]
-; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v4, v9, v[3:4]
+; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v4, s[6:7]
+; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v6, v9, v[3:4]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[4:5]
; GISEL-NEXT: ; implicit-def: $vgpr6
@@ -527,16 +528,17 @@ define i128 @fptosi_f32_to_i128(float %x) {
; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v6, v8, v[2:3]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v10, vcc
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v14, v0, 0, s[4:5]
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v15, v7, 0
-; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v7, v[12:13]
-; GISEL-NEXT: v_mul_lo_u32 v10, v6, v9
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v14, v7, v[12:13]
+; GISEL-NEXT: v_mul_lo_u32 v4, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v9, v15, v9
; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v15, v8, v[1:2]
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v6, v7, v[12:13]
; GISEL-NEXT: v_addc_co_u32_e64 v3, s[8:9], v3, v9, s[8:9]
-; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v10, s[6:7]
-; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[6:7], v4, v8, v[3:4]
+; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v4, s[6:7]
+; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: v_mad_u64_u32 v[9:10], s[6:7], v14, v8, v[3:4]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[4:5]
; GISEL-NEXT: ; implicit-def: $vgpr6
@@ -889,16 +891,17 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[4:5], v15, v8, v[2:3]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v9, vcc
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v14, v7, 0
-; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v7, v[11:12]
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v6, v7, v[11:12]
; GISEL-NEXT: v_mul_lo_u32 v9, v14, v13
-; GISEL-NEXT: v_mul_lo_u32 v6, v15, v13
+; GISEL-NEXT: v_mul_lo_u32 v4, v15, v13
; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[6:7], v14, v8, v[1:2]
; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v15, v7, v[11:12]
; GISEL-NEXT: v_addc_co_u32_e64 v3, s[8:9], v3, v9, s[8:9]
-; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v6, s[6:7]
-; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[6:7], v4, v8, v[3:4]
+; GISEL-NEXT: v_addc_co_u32_e64 v3, s[6:7], v3, v4, s[6:7]
+; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: v_mad_u64_u32 v[11:12], s[6:7], v6, v8, v[3:4]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v10, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v5, v3, 0, s[4:5]
; GISEL-NEXT: ; implicit-def: $vgpr6
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index dddcec6c10291..f52bb51fbb27f 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -170,6 +170,7 @@ define i16 @test_signed_i16_f32(float %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_pk_i16_f32 v0, v0, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i16 @llvm.fptosi.sat.i16.f32(float %f)
ret i16 %x
@@ -1682,6 +1683,7 @@ define i1 @test_signed_i1_f16(half %f) nounwind {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1704,6 +1706,7 @@ define i1 @test_signed_i1_f16(half %f) nounwind {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1715,6 +1718,7 @@ define i1 @test_signed_i1_f16(half %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i1 @llvm.fptosi.sat.i1.f16(half %f)
@@ -1802,6 +1806,7 @@ define i8 @test_signed_i8_f16(half %f) nounwind {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
; GFX12-GI-NEXT: v_mov_b16_e32 v0.h, 0xff80
; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, v0.h, 0x7f
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i8 @llvm.fptosi.sat.i8.f16(half %f)
ret i8 %x
@@ -1874,6 +1879,7 @@ define i16 @test_signed_i16_f16(half %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
ret i16 %x
@@ -2064,6 +2070,7 @@ define i1 @test_s_signed_i1_f16(half inreg %f) nounwind {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, -1, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2088,6 +2095,7 @@ define i1 @test_s_signed_i1_f16(half inreg %f) nounwind {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, -1, 0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2100,6 +2108,7 @@ define i1 @test_s_signed_i1_f16(half inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: s_sext_i32_i16 s0, s0
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2160,6 +2169,7 @@ define i8 @test_s_signed_i8_f16(half inreg %f) nounwind {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_movk_i32 s0, 0xff80
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, s0, 0x7f
@@ -2187,6 +2197,7 @@ define i8 @test_s_signed_i8_f16(half inreg %f) nounwind {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_movk_i32 s0, 0xff80
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2201,6 +2212,7 @@ define i8 @test_s_signed_i8_f16(half inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: s_sext_i32_i16 s0, s0
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -2283,6 +2295,7 @@ define i16 @test_s_signed_i16_f16(half inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
ret i16 %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index ff08c1ac4d30e..0eaa9f0afba04 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2621,10 +2621,14 @@ define <4 x i1> @test_signed_v4f16_v4i1(<4 x half> %f) {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
; GFX12-GI-NEXT: v_med3_i16 v1.l, v0.h, -1, 0
; GFX12-GI-NEXT: v_med3_i16 v2.l, v2.l, -1, 0
; GFX12-GI-NEXT: v_med3_i16 v3.l, v1.h, -1, 0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i1> @llvm.fptosi.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x
@@ -2833,10 +2837,14 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_med3_i16 v0.l, v0.l, v2.h, 0x7f
; GFX12-GI-NEXT: v_med3_i16 v1.l, v0.h, v2.h, 0x7f
; GFX12-GI-NEXT: v_med3_i16 v2.l, v2.l, v2.h, 0x7f
; GFX12-GI-NEXT: v_med3_i16 v3.l, v1.h, v2.h, 0x7f
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i8> @llvm.fptosi.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x
@@ -3365,12 +3373,16 @@ define <4 x i1> @test_s_signed_v4f16_v4i1(<4 x half> inreg %f) {
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s0
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
-; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_bfe_i32 v4, v0, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX11-TRUE16-NEXT: v_med3_i32 v0, v1, -1, 0
; GFX11-TRUE16-NEXT: v_med3_i32 v2, v4, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v0, v1, -1, 0
; GFX11-TRUE16-NEXT: v_med3_i32 v1, v5, -1, 0
; GFX11-TRUE16-NEXT: v_med3_i32 v3, v3, -1, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -3413,12 +3425,16 @@ define <4 x i1> @test_s_signed_v4f16_v4i1(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s0
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
-; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_bfe_i32 v4, v0, 0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX12-TRUE16-NEXT: v_med3_i32 v0, v1, -1, 0
; GFX12-TRUE16-NEXT: v_med3_i32 v2, v4, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v0, v1, -1, 0
; GFX12-TRUE16-NEXT: v_med3_i32 v1, v5, -1, 0
; GFX12-TRUE16-NEXT: v_med3_i32 v3, v3, -1, 0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -3437,6 +3453,10 @@ define <4 x i1> @test_s_signed_v4f16_v4i1(<4 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, s2
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.l, s3
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v2
@@ -3601,15 +3621,19 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-TRUE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
; GFX11-TRUE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
+; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
@@ -3675,17 +3699,21 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-TRUE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
; GFX12-TRUE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
+; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
@@ -3715,6 +3743,10 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, s2
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.l, s3
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v2
@@ -3900,7 +3932,11 @@ define <4 x i16> @test_s_signed_v4f16_v4i16(<4 x half> inreg %f) {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, s2
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.l, s0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-GI-NEXT: v_readfirstlane_b32 s3, v3
@@ -4272,7 +4308,15 @@ define <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
; GFX12-GI-NEXT: v_med3_i16 v5.l, v2.l, -1, 0
; GFX12-GI-NEXT: v_med3_i16 v6.l, v2.h, -1, 0
; GFX12-GI-NEXT: v_med3_i16 v7.l, v3.h, -1, 0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr8_hi16
; GFX12-GI-NEXT: v_mov_b32_e32 v2, v8
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr7_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x
@@ -4624,6 +4668,10 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v4.l, v1.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
+; GFX12-GI-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr7_hi16
; GFX12-GI-NEXT: v_med3_i16 v1.l, v0.h, v4.h, 0x7f
; GFX12-GI-NEXT: v_med3_i16 v8.l, v4.l, v4.h, 0x7f
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.h, v1.h
@@ -4637,6 +4685,10 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX12-GI-NEXT: v_med3_i16 v6.l, v2.h, v4.h, 0x7f
; GFX12-GI-NEXT: v_med3_i16 v7.l, v3.h, v4.h, 0x7f
; GFX12-GI-NEXT: v_mov_b32_e32 v2, v8
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x
@@ -5505,12 +5557,18 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s3
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v6, v0, -1, 0
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
@@ -5520,9 +5578,11 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s2, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s3
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v7.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v8, v1, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v9, v7, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, -1, 0
@@ -5582,6 +5642,8 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s3
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
@@ -5589,6 +5651,10 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s1
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v6, v0, -1, 0
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
@@ -5600,9 +5666,11 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v7.l, s0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v8, v1, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v9, v7, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, -1, 0
@@ -5622,28 +5690,35 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s0
; GFX12-GI-NEXT: s_lshr_b32 s0, s0, 16
-; GFX12-GI-NEXT: s_lshr_b32 s4, s1, 16
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, s0
-; GFX12-GI-NEXT: s_lshr_b32 s5, s2, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: s_lshr_b32 s4, s1, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s1
-; GFX12-GI-NEXT: s_lshr_b32 s1, s3, 16
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s4
+; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v2
; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: s_lshr_b32 s5, s2, 16
+; GFX12-GI-NEXT: s_lshr_b32 s1, s3, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: s_sext_i32_i16 s0, s0
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, s1
-; GFX12-GI-NEXT: s_sext_i32_i16 s0, s0
-; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v0
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s4
; GFX12-GI-NEXT: s_sext_i32_i16 s6, s6
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s0, s0, 0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s4, s6, 0
; GFX12-GI-NEXT: s_sext_i32_i16 s6, s7
; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s2
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s2, s6, 0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_sext_i32_i16 s0, s0
; GFX12-GI-NEXT: s_sext_i32_i16 s4, s4
; GFX12-GI-NEXT: s_sext_i32_i16 s6, s7
@@ -5651,6 +5726,7 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s5
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s5, s6, 0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_sext_i32_i16 s2, s2
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_sext_i32_i16 s5, s5
@@ -5659,6 +5735,7 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s3
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s6, s6, 0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_max_i32 s0, s0, -1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_sext_i32_i16 s3, s6
@@ -5932,6 +6009,7 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s4
; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s2
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, s4
@@ -5939,6 +6017,12 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s3
; GFX11-TRUE16-NEXT: s_movk_i32 s2, 0xff80
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
@@ -5960,6 +6044,7 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s0
; GFX11-TRUE16-NEXT: v_med3_i32 v9, v2, s2, 0x7f
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v0, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v3, v4
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v6, 0, 16
@@ -6058,6 +6143,7 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s4
; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s2
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6066,6 +6152,12 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s3
; GFX12-TRUE16-NEXT: s_movk_i32 s2, 0xff80
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
@@ -6088,6 +6180,7 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s0
; GFX12-TRUE16-NEXT: v_med3_i32 v9, v2, s2, 0x7f
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, v0, v1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v3, v4
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v6, 0, 16
@@ -6118,28 +6211,35 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s0
; GFX12-GI-NEXT: s_lshr_b32 s0, s0, 16
-; GFX12-GI-NEXT: s_lshr_b32 s4, s1, 16
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, s0
-; GFX12-GI-NEXT: s_lshr_b32 s5, s2, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: s_lshr_b32 s4, s1, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s1
-; GFX12-GI-NEXT: s_lshr_b32 s1, s3, 16
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s4
+; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v2
; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: s_lshr_b32 s5, s2, 16
+; GFX12-GI-NEXT: s_lshr_b32 s1, s3, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: s_sext_i32_i16 s0, s0
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, s1
-; GFX12-GI-NEXT: s_sext_i32_i16 s0, s0
-; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v0
-; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s4
; GFX12-GI-NEXT: s_sext_i32_i16 s6, s6
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s0, s0, 0x7f
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s4, s6, 0x7f
; GFX12-GI-NEXT: s_sext_i32_i16 s6, s7
; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s2
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s2, s6, 0x7f
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_sext_i32_i16 s0, s0
; GFX12-GI-NEXT: s_sext_i32_i16 s4, s4
; GFX12-GI-NEXT: s_sext_i32_i16 s6, s7
@@ -6147,6 +6247,7 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s5
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s5, s6, 0x7f
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_sext_i32_i16 s2, s2
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_sext_i32_i16 s5, s5
@@ -6155,6 +6256,7 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s3
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_i32 s6, s6, 0x7f
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_max_i32 s0, s0, 0xffffff80
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_sext_i32_i16 s3, s6
@@ -6437,22 +6539,30 @@ define <8 x i16> @test_s_signed_v8f16_v8i16(<8 x half> inreg %f) {
; GFX12-GI-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, s4
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v0.l, s1
; GFX12-GI-NEXT: s_lshr_b32 s1, s2, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s5, v2
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-GI-NEXT: s_lshr_b32 s1, s3, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s4, v1
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v1.l, s2
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v3.l, s3
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_i16_f16_e32 v4.l, s1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v3
+; GFX12-GI-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v4
; GFX12-GI-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX12-GI-NEXT: s_pack_ll_b32_b16 s1, s5, s1
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
index 0588678502265..166f80196db08 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
@@ -129,6 +129,7 @@ define i16 @test_unsigned_i16_f32(float %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_pk_u16_f32 v0, v0, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i16 @llvm.fptoui.sat.i16.f32(float %f)
ret i16 %x
@@ -1278,6 +1279,7 @@ define i1 @test_unsigned_i1_f16(half %f) nounwind {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_min_u16 v0.l, v0.l, 1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1300,6 +1302,7 @@ define i1 @test_unsigned_i1_f16(half %f) nounwind {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_min_u16 v0.l, v0.l, 1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1311,6 +1314,7 @@ define i1 @test_unsigned_i1_f16(half %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_min_u16 v0.l, v0.l, 1
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i1 @llvm.fptoui.sat.i1.f16(half %f)
@@ -1377,6 +1381,7 @@ define i8 @test_unsigned_i8_f16(half %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_min_u16 v0.l, 0xff, v0.l
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i8 @llvm.fptoui.sat.i8.f16(half %f)
@@ -1438,6 +1443,7 @@ define i16 @test_unsigned_i16_f16(half %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i16 @llvm.fptoui.sat.i16.f16(half %f)
ret i16 %x
@@ -1619,6 +1625,7 @@ define i1 @test_s_unsigned_i1_f16(half inreg %f) nounwind {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1643,6 +1650,7 @@ define i1 @test_s_unsigned_i1_f16(half inreg %f) nounwind {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1655,6 +1663,7 @@ define i1 @test_s_unsigned_i1_f16(half inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: s_and_b32 s0, 0xffff, s0
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1705,6 +1714,7 @@ define i8 @test_s_unsigned_i8_f16(half inreg %f) nounwind {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1729,6 +1739,7 @@ define i8 @test_s_unsigned_i8_f16(half inreg %f) nounwind {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1741,6 +1752,7 @@ define i8 @test_s_unsigned_i8_f16(half inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: s_and_b32 s0, 0xffff, s0
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1807,6 +1819,7 @@ define i16 @test_s_unsigned_i16_f16(half inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call i16 @llvm.fptoui.sat.i16.f16(half %f)
ret i16 %x
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index f8a5331960b0b..1ee8af29f1f72 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -2423,10 +2423,14 @@ define <4 x i1> @test_unsigned_v4f16_v4i1(<4 x half> %f) {
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, v1.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_min_u16 v0.l, v0.l, 1
; GFX12-GI-NEXT: v_min_u16 v1.l, v0.h, 1
; GFX12-GI-NEXT: v_min_u16 v2.l, v2.l, 1
; GFX12-GI-NEXT: v_min_u16 v3.l, v1.h, 1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i1> @llvm.fptoui.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x
@@ -2610,10 +2614,14 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, v1.l
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_min_u16 v0.l, 0xff, v0.l
; GFX12-GI-NEXT: v_min_u16 v1.l, 0xff, v0.h
; GFX12-GI-NEXT: v_min_u16 v2.l, 0xff, v2.l
; GFX12-GI-NEXT: v_min_u16 v3.l, 0xff, v1.h
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <4 x i8> @llvm.fptoui.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x
@@ -3129,6 +3137,10 @@ define <4 x i1> @test_s_unsigned_v4f16_v4i1(<4 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s3
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v2
@@ -3177,6 +3189,10 @@ define <4 x i1> @test_s_unsigned_v4f16_v4i1(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s3
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s2
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v2
@@ -3201,6 +3217,10 @@ define <4 x i1> @test_s_unsigned_v4f16_v4i1(<4 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s2
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v3.l, s3
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v2
@@ -3332,13 +3352,17 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s2
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s0
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
@@ -3396,15 +3420,19 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s2
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
@@ -3435,6 +3463,10 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s2
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v3.l, s3
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v2
@@ -3604,7 +3636,11 @@ define <4 x i16> @test_s_unsigned_v4f16_v4i16(<4 x half> inreg %f) {
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s2
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s1
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v3.l, s0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v2
; GFX12-GI-NEXT: v_readfirstlane_b32 s3, v3
@@ -3971,7 +4007,15 @@ define <8 x i1> @test_unsigned_v8f16_v8i1(<8 x half> %f) {
; GFX12-GI-NEXT: v_min_u16 v5.l, v2.l, 1
; GFX12-GI-NEXT: v_min_u16 v6.l, v2.h, 1
; GFX12-GI-NEXT: v_min_u16 v7.l, v3.h, 1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr8_hi16
; GFX12-GI-NEXT: v_mov_b32_e32 v2, v8
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr7_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x
@@ -4297,7 +4341,15 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; GFX12-GI-NEXT: v_min_u16 v5.l, 0xff, v2.l
; GFX12-GI-NEXT: v_min_u16 v6.l, 0xff, v2.h
; GFX12-GI-NEXT: v_min_u16 v7.l, 0xff, v3.h
+; GFX12-GI-NEXT: ; implicit-def: $vgpr8_hi16
; GFX12-GI-NEXT: v_mov_b32_e32 v2, v8
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr7_hi16
; GFX12-GI-NEXT: s_setpc_b64 s[30:31]
%x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x
@@ -5140,6 +5192,9 @@ define <8 x i1> @test_s_unsigned_v8f16_v8i1(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s2, 16
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s5
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, s3
@@ -5152,16 +5207,21 @@ define <8 x i1> @test_s_unsigned_v8f16_v8i1(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_min_u32_e32 v5, 1, v1
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s4
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v6, 1, v4
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 1, v8
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 1, v1
; GFX11-TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 1, v8
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_unsigned_v8f16_v8i1:
@@ -5219,6 +5279,9 @@ define <8 x i1> @test_s_unsigned_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s4
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s0, 16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, s3
@@ -5232,16 +5295,21 @@ define <8 x i1> @test_s_unsigned_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s4
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s1
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v6
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v6
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v6, 1, v4
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 1, v8
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 1, v1
; GFX12-TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 1, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v8f16_v8i1:
@@ -5253,47 +5321,54 @@ define <8 x i1> @test_s_unsigned_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s0
; GFX12-GI-NEXT: s_lshr_b32 s0, s0, 16
-; GFX12-GI-NEXT: s_lshr_b32 s4, s2, 16
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s0
-; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s1
; GFX12-GI-NEXT: s_lshr_b32 s1, s1, 16
-; GFX12-GI-NEXT: v_readfirstlane_b32 s5, v1
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s4
-; GFX12-GI-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v2
+; GFX12-GI-NEXT: v_readfirstlane_b32 s5, v1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: s_lshr_b32 s4, s2, 16
; GFX12-GI-NEXT: s_lshr_b32 s1, s3, 16
-; GFX12-GI-NEXT: s_and_b32 s5, 0xffff, s5
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s1
-; GFX12-GI-NEXT: s_and_b32 s6, 0xffff, s6
; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s2
-; GFX12-GI-NEXT: s_min_u32 s2, s5, 1
+; GFX12-GI-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX12-GI-NEXT: s_and_b32 s6, 0xffff, s6
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_min_u32 s2, s5, 1
; GFX12-GI-NEXT: s_min_u32 s5, s6, 1
-; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-GI-NEXT: s_and_b32 s4, 0xffff, s7
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s4
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s3
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s1
+; GFX12-GI-NEXT: s_and_b32 s4, 0xffff, s7
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_u32 s3, s4, 1
-; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v2
-; GFX12-GI-NEXT: s_and_b32 s1, 0xffff, s1
; GFX12-GI-NEXT: s_and_b32 s4, 0xffff, s6
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v2
+; GFX12-GI-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX12-GI-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_u32 s0, s0, 1
+; GFX12-GI-NEXT: s_and_b32 s6, 0xffff, s6
; GFX12-GI-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_u32 s4, s4, 1
; GFX12-GI-NEXT: s_min_u32 s1, s1, 1
-; GFX12-GI-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX12-GI-NEXT: s_min_u32 s7, s7, 1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_u32 s6, s6, 1
+; GFX12-GI-NEXT: s_min_u32 s7, s7, 1
; GFX12-GI-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s2
; GFX12-GI-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, s3
; GFX12-GI-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s1
@@ -5509,33 +5584,41 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s2
; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s4
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, s3
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s2
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s1
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s3
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, s1
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v1, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v3
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -5622,34 +5705,42 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s4
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, s3
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s2
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s1
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s3
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s2
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, s1
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, v1, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, v7, v3
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v4, v5
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -5674,47 +5765,54 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s0
; GFX12-GI-NEXT: s_lshr_b32 s0, s0, 16
-; GFX12-GI-NEXT: s_lshr_b32 s4, s2, 16
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s0
-; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s1
; GFX12-GI-NEXT: s_lshr_b32 s1, s1, 16
-; GFX12-GI-NEXT: v_readfirstlane_b32 s5, v1
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s4
-; GFX12-GI-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v2
+; GFX12-GI-NEXT: v_readfirstlane_b32 s5, v1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GI-NEXT: s_lshr_b32 s4, s2, 16
; GFX12-GI-NEXT: s_lshr_b32 s1, s3, 16
-; GFX12-GI-NEXT: s_and_b32 s5, 0xffff, s5
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s1
-; GFX12-GI-NEXT: s_and_b32 s6, 0xffff, s6
; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s2
-; GFX12-GI-NEXT: s_min_u32 s2, s5, 0xff
+; GFX12-GI-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX12-GI-NEXT: s_and_b32 s6, 0xffff, s6
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GI-NEXT: s_min_u32 s2, s5, 0xff
; GFX12-GI-NEXT: s_min_u32 s5, s6, 0xff
-; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-GI-NEXT: s_and_b32 s4, 0xffff, s7
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s4
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s3
+; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s1
+; GFX12-GI-NEXT: s_and_b32 s4, 0xffff, s7
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_u32 s3, s4, 0xff
-; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v2
-; GFX12-GI-NEXT: s_and_b32 s1, 0xffff, s1
; GFX12-GI-NEXT: s_and_b32 s4, 0xffff, s6
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v2
+; GFX12-GI-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX12-GI-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_u32 s0, s0, 0xff
+; GFX12-GI-NEXT: s_and_b32 s6, 0xffff, s6
; GFX12-GI-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_u32 s4, s4, 0xff
; GFX12-GI-NEXT: s_min_u32 s1, s1, 0xff
-; GFX12-GI-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX12-GI-NEXT: s_min_u32 s7, s7, 0xff
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_min_u32 s6, s6, 0xff
+; GFX12-GI-NEXT: s_min_u32 s7, s7, 0xff
; GFX12-GI-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s2
; GFX12-GI-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, s3
; GFX12-GI-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s1
@@ -5963,22 +6061,30 @@ define <8 x i16> @test_s_unsigned_v8f16_v8i16(<8 x half> inreg %f) {
; GFX12-GI-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s4
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v0.l, s1
; GFX12-GI-NEXT: s_lshr_b32 s1, s2, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s5, v2
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v2.l, s1
; GFX12-GI-NEXT: s_lshr_b32 s1, s3, 16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s4, v1
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v1.l, s2
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v3.l, s3
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: v_cvt_u16_f16_e32 v4.l, s1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-GI-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GI-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-GI-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s6, v3
+; GFX12-GI-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-GI-NEXT: v_readfirstlane_b32 s7, v4
; GFX12-GI-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX12-GI-NEXT: s_pack_ll_b32_b16 s1, s5, s1
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
index 604c5ff07a540..bfba1f1b345ba 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
@@ -1985,6 +1985,8 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
; GFX11-GISEL-TRUE16-LABEL: fptrunc_v2f32_to_v2f16:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -4018,6 +4020,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
@@ -5110,6 +5114,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX11-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
@@ -5138,6 +5143,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
@@ -5184,6 +5190,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1250-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null
@@ -5409,6 +5416,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX11-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e64 v0.l, |v0|
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
@@ -5437,6 +5445,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX11-GISEL-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
@@ -5485,6 +5494,7 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1250-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null
; GFX1250-SDAG-TRUE16-NEXT: s_endpgm
@@ -5717,6 +5727,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX11-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
@@ -5745,6 +5756,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
@@ -5791,6 +5803,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1250-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index d67f5016dbd31..4a9ca8dd3d0d8 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -1860,6 +1860,7 @@ define half @fabs_fptrunc_f32_to_f16(float %x) {
; GFX11-SAFE-GISEL: ; %bb.0:
; GFX11-SAFE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-SAFE-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-GISEL-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
; GFX11-SAFE-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1884,6 +1885,7 @@ define half @fabs_fptrunc_f32_to_f16(float %x) {
; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0:
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1948,6 +1950,7 @@ define half @fneg_fabs_fptrunc_f32_to_f16(float %x) {
; GFX11-SAFE-GISEL: ; %bb.0:
; GFX11-SAFE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-SAFE-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-GISEL-NEXT: v_or_b16 v0.l, 0x8000, v0.l
; GFX11-SAFE-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1972,6 +1975,7 @@ define half @fneg_fabs_fptrunc_f32_to_f16(float %x) {
; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0:
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2310,6 +2314,7 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
; GFX11-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SAFE-GISEL-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
+; GFX11-SAFE-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SAFE-GISEL-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
; GFX11-SAFE-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2461,6 +2466,7 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 6d8fdbbe03b77..84c0cfcdd36ff 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -516,6 +516,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB0_3
; GFX11-TRUE16-NEXT: s_branch .LBB0_8
; GFX11-TRUE16-NEXT: .LBB0_2:
@@ -595,8 +596,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v2, v3
; GFX11-TRUE16-NEXT: .LBB0_8: ; %Flow19
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.l
@@ -747,6 +750,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_cbranch_execz .LBB0_3
; GFX1150-TRUE16-NEXT: s_branch .LBB0_8
; GFX1150-TRUE16-NEXT: .LBB0_2:
@@ -829,7 +833,9 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
; GFX1150-TRUE16-NEXT: .LBB0_8: ; %Flow19
@@ -990,6 +996,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_cbranch_execz .LBB0_3
; GFX1200-TRUE16-NEXT: s_branch .LBB0_8
; GFX1200-TRUE16-NEXT: .LBB0_2:
@@ -1075,7 +1082,9 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
; GFX1200-TRUE16-NEXT: .LBB0_8: ; %Flow19
@@ -1586,6 +1595,7 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
@@ -1656,6 +1666,7 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
@@ -2071,6 +2082,7 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
@@ -2141,6 +2153,7 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
@@ -5874,6 +5887,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else20
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v2.l, vcc_lo
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB9_3
@@ -5955,8 +5969,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
; GFX11-TRUE16-NEXT: .LBB9_8:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
@@ -5972,6 +5988,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB9_11
; GFX11-TRUE16-NEXT: s_branch .LBB9_16
; GFX11-TRUE16-NEXT: .LBB9_10:
@@ -6051,8 +6068,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, v5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v5.l, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fff, v5, v6
; GFX11-TRUE16-NEXT: .LBB9_16: ; %Flow54
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
@@ -6306,6 +6325,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else20
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s6, s5
; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s7
@@ -6391,7 +6411,9 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX1150-TRUE16-NEXT: .LBB9_8:
@@ -6410,6 +6432,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s9
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_cbranch_execz .LBB9_11
; GFX1150-TRUE16-NEXT: s_branch .LBB9_16
; GFX1150-TRUE16-NEXT: .LBB9_10:
@@ -6492,7 +6515,9 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, s6
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
; GFX1150-TRUE16-NEXT: .LBB9_16: ; %Flow54
@@ -6772,6 +6797,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else20
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s6, s5
; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s7
@@ -6860,7 +6886,9 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX1200-TRUE16-NEXT: .LBB9_8:
@@ -6882,6 +6910,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s9
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_cbranch_execz .LBB9_11
; GFX1200-TRUE16-NEXT: s_branch .LBB9_16
; GFX1200-TRUE16-NEXT: .LBB9_10:
@@ -6968,7 +6997,9 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v2.l, s6
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
; GFX1200-TRUE16-NEXT: .LBB9_16: ; %Flow54
@@ -8970,6 +9001,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else86
; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_3
@@ -9051,8 +9083,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v5, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v4.l, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: v_bfi_b32 v4, 0x7fff, v4, v5
; GFX11-TRUE16-NEXT: .LBB10_8:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
@@ -9068,6 +9102,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_11
; GFX11-TRUE16-NEXT: s_branch .LBB10_16
; GFX11-TRUE16-NEXT: .LBB10_10:
@@ -9147,8 +9182,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v8, v7
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v7.l, v7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-TRUE16-NEXT: v_bfi_b32 v7, 0x7fff, v7, v8
; GFX11-TRUE16-NEXT: .LBB10_16:
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v10, |v1.l|
@@ -9161,6 +9198,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_19
; GFX11-TRUE16-NEXT: s_branch .LBB10_24
; GFX11-TRUE16-NEXT: .LBB10_18:
@@ -9240,8 +9278,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v8.l, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: v_bfi_b32 v8, 0x7fff, v8, v9
; GFX11-TRUE16-NEXT: .LBB10_24:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
@@ -9257,6 +9297,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_27
; GFX11-TRUE16-NEXT: s_branch .LBB10_32
; GFX11-TRUE16-NEXT: .LBB10_26:
@@ -9336,8 +9377,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v12, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v11.l, v11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
; GFX11-TRUE16-NEXT: v_bfi_b32 v11, 0x7fff, v11, v12
; GFX11-TRUE16-NEXT: .LBB10_32: ; %Flow124
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
@@ -9797,6 +9840,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else86
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s8, s6
; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s9
@@ -9882,7 +9926,9 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v1.l, s5
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX1150-TRUE16-NEXT: .LBB10_8:
@@ -9901,6 +9947,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s11
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_cbranch_execz .LBB10_11
; GFX1150-TRUE16-NEXT: s_branch .LBB10_16
; GFX1150-TRUE16-NEXT: .LBB10_10:
@@ -9983,7 +10030,9 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, s8
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
; GFX1150-TRUE16-NEXT: .LBB10_16:
@@ -10000,6 +10049,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_cbranch_execz .LBB10_19
; GFX1150-TRUE16-NEXT: s_branch .LBB10_24
; GFX1150-TRUE16-NEXT: .LBB10_18:
@@ -10082,7 +10132,9 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, s7
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
; GFX1150-TRUE16-NEXT: .LBB10_24:
@@ -10101,6 +10153,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s13
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1150-TRUE16-NEXT: s_cbranch_execz .LBB10_27
; GFX1150-TRUE16-NEXT: s_branch .LBB10_32
; GFX1150-TRUE16-NEXT: .LBB10_26:
@@ -10183,7 +10236,9 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v4.l, s10
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, v4
; GFX1150-TRUE16-NEXT: .LBB10_32: ; %Flow124
@@ -10697,6 +10752,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else86
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s8, s6
; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s9
@@ -10785,7 +10841,9 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, s5
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX1200-TRUE16-NEXT: .LBB10_8:
@@ -10807,6 +10865,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s11
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_cbranch_execz .LBB10_11
; GFX1200-TRUE16-NEXT: s_branch .LBB10_16
; GFX1200-TRUE16-NEXT: .LBB10_10:
@@ -10893,7 +10952,9 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v2.l, s8
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
; GFX1200-TRUE16-NEXT: .LBB10_16:
@@ -10913,6 +10974,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_cbranch_execz .LBB10_19
; GFX1200-TRUE16-NEXT: s_branch .LBB10_24
; GFX1200-TRUE16-NEXT: .LBB10_18:
@@ -10999,7 +11061,9 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v3.l, s7
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
; GFX1200-TRUE16-NEXT: .LBB10_24:
@@ -11021,6 +11085,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s13
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-TRUE16-NEXT: s_cbranch_execz .LBB10_27
; GFX1200-TRUE16-NEXT: s_branch .LBB10_32
; GFX1200-TRUE16-NEXT: .LBB10_26:
@@ -11107,7 +11172,9 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v4.l, s10
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, v4
; GFX1200-TRUE16-NEXT: .LBB10_32: ; %Flow124
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index be49838f86417..4e2e5b207281b 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -1829,6 +1829,7 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_v3i16:
@@ -1881,6 +1882,7 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h
; GFX12-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_fshr_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
index fea6a729ed986..4962a76f5ee14 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
@@ -1529,71 +1529,140 @@ define void @void_func_v32i32_i1_i8_i16_f32_inreg(<32 x i32> inreg %arg0, i1 inr
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: void_func_v32i32_i1_i8_i16_f32_inreg:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s8, v1
-; GFX11-NEXT: v_readfirstlane_b32 s9, v0
-; GFX11-NEXT: v_readfirstlane_b32 s12, v3
-; GFX11-NEXT: v_readfirstlane_b32 s13, v2
-; GFX11-NEXT: v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v1, s25
-; GFX11-NEXT: v_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27
-; GFX11-NEXT: v_readfirstlane_b32 s10, v5
-; GFX11-NEXT: v_readfirstlane_b32 s11, v4
-; GFX11-NEXT: v_readfirstlane_b32 s40, v7
-; GFX11-NEXT: v_readfirstlane_b32 s41, v6
-; GFX11-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v5, s21
-; GFX11-NEXT: v_dual_mov_b32 v6, s22 :: v_dual_mov_b32 v7, s23
-; GFX11-NEXT: v_readfirstlane_b32 s42, v13
-; GFX11-NEXT: v_readfirstlane_b32 s20, v12
-; GFX11-NEXT: v_readfirstlane_b32 s21, v11
-; GFX11-NEXT: v_readfirstlane_b32 s22, v10
-; GFX11-NEXT: v_readfirstlane_b32 s14, v9
-; GFX11-NEXT: v_readfirstlane_b32 s15, v8
-; GFX11-NEXT: v_readfirstlane_b32 s7, v14
-; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
-; GFX11-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19
-; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
-; GFX11-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3
-; GFX11-NEXT: v_readfirstlane_b32 s6, v15
-; GFX11-NEXT: v_dual_mov_b32 v8, s22 :: v_dual_mov_b32 v9, s21
-; GFX11-NEXT: v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v11, s42
-; GFX11-NEXT: v_readfirstlane_b32 s5, v16
-; GFX11-NEXT: v_dual_mov_b32 v12, s41 :: v_dual_mov_b32 v13, s40
-; GFX11-NEXT: v_dual_mov_b32 v14, s15 :: v_dual_mov_b32 v15, s14
-; GFX11-NEXT: v_readfirstlane_b32 s4, v17
-; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v17, s12
-; GFX11-NEXT: v_dual_mov_b32 v18, s11 :: v_dual_mov_b32 v19, s10
-; GFX11-NEXT: s_and_b32 s0, s7, 1
-; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b128 v[0:1], v[16:19], off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29
-; GFX11-NEXT: v_dual_mov_b32 v2, s9 :: v_dual_mov_b32 v3, s8
-; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s6
-; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v7, s4
-; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b8 v[0:1], v4, off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b8 v[0:1], v5, off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b16 v[0:1], v6, off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: global_store_b16 v[0:1], v7, off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v32i32_i1_i8_i16_f32_inreg:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v3
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v1, s25
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v5, s21
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s22 :: v_dual_mov_b32 v7, s23
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s20, v12
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s21, v11
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s22, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v14
+; GFX11-TRUE16-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v15
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s22 :: v_dual_mov_b32 v9, s21
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v11, s42
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s41 :: v_dual_mov_b32 v13, s40
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s15 :: v_dual_mov_b32 v15, s14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v17
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v17, s12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s11 :: v_dual_mov_b32 v19, s10
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s7, 1
+; GFX11-TRUE16-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b128 v[0:1], v[16:19], off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s9 :: v_dual_mov_b32 v3, s8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v7, s4
+; GFX11-TRUE16-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b8 v[0:1], v4, off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b8 v[0:1], v5, off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v6, off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v7, off dlc
+; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v32i32_i1_i8_i16_f32_inreg:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v1, s25
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v5, s21
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s22 :: v_dual_mov_b32 v7, s23
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s20, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s21, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s22, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v14
+; GFX11-FAKE16-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v15
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s22 :: v_dual_mov_b32 v9, s21
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v11, s42
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v16
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s41 :: v_dual_mov_b32 v13, s40
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s15 :: v_dual_mov_b32 v15, s14
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v17
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v17, s12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s11 :: v_dual_mov_b32 v19, s10
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s7, 1
+; GFX11-FAKE16-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b128 v[0:1], v[16:19], off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v1, s29
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s9 :: v_dual_mov_b32 v3, s8
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s6
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v7, s4
+; GFX11-FAKE16-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b8 v[0:1], v4, off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b8 v[0:1], v5, off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v6, off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v7, off dlc
+; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
store volatile <32 x i32> %arg0, ptr addrspace(1) poison
store volatile i1 %arg1, ptr addrspace(1) poison
store volatile i8 %arg2, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll
index 07dcad993ffe2..57ea725f7314e 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args.ll
@@ -1014,17 +1014,31 @@ define void @void_func_v3i8(<3 x i8> %arg0) #0 {
; GFX89-NEXT: s_waitcnt vmcnt(0)
; GFX89-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: void_func_v3i8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX11-NEXT: s_mov_b64 s[0:1], 2
-; GFX11-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: buffer_store_b8 v2, off, s[0:3], 0
-; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v3i8:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 2
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: buffer_store_b8 v2, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v3i8:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], 2
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: buffer_store_b8 v2, off, s[0:3], 0
+; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
store <3 x i8> %arg0, ptr addrspace(1) null
ret void
}
@@ -1078,18 +1092,35 @@ define void @void_func_v4i8(<4 x i8> %arg0) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: void_func_v4i8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
-; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v4i8:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v4i8:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
store <4 x i8> %arg0, ptr addrspace(1) null
ret void
}
@@ -1149,20 +1180,38 @@ define void @void_func_v5i8(<5 x i8> %arg0) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: void_func_v5i8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
-; GFX11-NEXT: s_mov_b64 s[0:1], 4
-; GFX11-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: buffer_store_b8 v4, off, s[0:3], 0
-; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v5i8:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 4
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: buffer_store_b8 v4, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v5i8:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], 4
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: buffer_store_b8 v4, off, s[0:3], 0
+; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
store <5 x i8> %arg0, ptr addrspace(1) null
ret void
}
@@ -1232,20 +1281,44 @@ define void @void_func_v8i8(<8 x i8> %arg0) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: void_func_v8i8:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v5, v6, v7, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v4
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v8i8:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v5, 16, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v8i8:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v7, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v5, 16, v4
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
store <8 x i8> %arg0, ptr addrspace(1) null
ret void
}
@@ -1349,9 +1422,26 @@ define void @void_func_v16i8(<16 x i8> %arg0) #0 {
;
; GFX11-TRUE16-LABEL: void_func_v16i8:
; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 0
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v9, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v11.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v14, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
@@ -1362,9 +1452,8 @@ define void @void_func_v16i8(<16 x i8> %arg0) #0 {
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v5, 16, v4
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v9, 16, v8
-; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v6, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v6, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1570,35 +1659,97 @@ define void @void_func_v32i8(<32 x i8> %arg0) #0 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: scratch_load_u8 v31, off, s32
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v14, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v9, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v10, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v4, v5, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v6, v7, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v2, v3, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v24, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v26, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v20, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v22, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v16, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v18, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v28, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v13, 16, v12
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v4, 16, v1
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v14, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v14.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v30.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v33, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v35, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v39, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v65, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v67, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v69, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v71, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v81, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v83, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v85, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v1, 16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v49, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v51, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v12, 16, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v9, 16, v8
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 16
; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v30, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v86, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v12, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v0, 16, v15
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v11, 16, v10
; GFX11-TRUE16-NEXT: buffer_store_b128 v[4:7], off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], 0
; GFX11-TRUE16-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
index 6922dc03f3203..d67aef651eb22 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
@@ -4733,9 +4733,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, 2 :: v_dual_mov_b32 v4, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b8 v[3:4], v2, off
; GFX11-TRUE16-NEXT: global_store_b16 v[40:41], v0, off
@@ -4959,11 +4960,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v3, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -5198,6 +5202,10 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v5
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v6
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v0, v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
@@ -5457,15 +5465,22 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v8
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v6, v7, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v5, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX11-TRUE16-NEXT: global_store_b64 v[40:41], v[0:1], off
; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
@@ -5806,111 +5821,249 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: test_call_external_void_func_v32i8_ret:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_mov_b32 s0, s33
-; GFX11-NEXT: s_mov_b32 s33, s32
-; GFX11-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
-; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: v_writelane_b32 v44, s0, 2
-; GFX11-NEXT: s_add_i32 s32, s32, 32
-; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Spill
-; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:12
-; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:8
-; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:4
-; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v43, s33
-; GFX11-NEXT: v_writelane_b32 v44, s30, 0
-; GFX11-NEXT: v_writelane_b32 v44, s31, 1
-; GFX11-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
-; GFX11-NEXT: v_dual_mov_b32 v42, 16 :: v_dual_mov_b32 v43, 0
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: global_load_b128 v[0:3], v[40:41], off
-; GFX11-NEXT: global_load_b128 v[16:19], v[42:43], off
-; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v0
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 24, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v11, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v13, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v15, 24, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v27, 24, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v19
-; GFX11-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
-; GFX11-NEXT: v_mov_b32_e32 v8, v2
-; GFX11-NEXT: v_mov_b32_e32 v12, v3
-; GFX11-NEXT: v_mov_b32_e32 v20, v17
-; GFX11-NEXT: v_mov_b32_e32 v24, v18
-; GFX11-NEXT: v_mov_b32_e32 v28, v19
-; GFX11-NEXT: v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
-; GFX11-NEXT: v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
-; GFX11-NEXT: v_mov_b32_e32 v19, v34
-; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_perm_b32 v12, v12, v13, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v14, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v8, v8, v9, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v10, v11, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v6, v7, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v6, v13, 16, v12
-; GFX11-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v5, v9, 16, v8
-; GFX11-NEXT: v_perm_b32 v1, v28, v29, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v4, v7, 16, v4
-; GFX11-NEXT: v_perm_b32 v7, v30, v31, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v20, v21, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v12, v22, v23, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v14, v18, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v10, v7, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v9, v9, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v11
-; GFX11-NEXT: v_lshl_or_b32 v7, v14, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v3, v2, 16, v0
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: global_store_b128 v[42:43], v[7:10], off
-; GFX11-NEXT: global_store_b128 v[40:41], v[3:6], off
-; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload
-; GFX11-NEXT: scratch_load_b32 v43, off, s33
-; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:4
-; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:8
-; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:12
-; GFX11-NEXT: v_readlane_b32 s30, v44, 0
-; GFX11-NEXT: v_readlane_b32 s31, v44, 1
-; GFX11-NEXT: s_mov_b32 s32, s33
-; GFX11-NEXT: v_readlane_b32 s0, v44, 2
-; GFX11-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-NEXT: scratch_load_b32 v44, off, s33 offset:16 ; 4-byte Folded Reload
-; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: s_mov_b32 s33, s0
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v32i8_ret:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT: s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 32
+; GFX11-TRUE16-NEXT: s_clause 0x3 ; 16-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s33
+; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s31, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v42, 16 :: v_dual_mov_b32 v43, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v[40:41], off
+; GFX11-TRUE16-NEXT: global_load_b128 v[16:19], v[42:43], off
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v24, v18
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v28, v19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v19, v34
+; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v44, 0
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v14, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v10, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v6, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v13, 16, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v28, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v7, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v30, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v20, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v22, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v7, 16, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v2, 16, v0
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: global_store_b128 v[42:43], v[7:10], off
+; GFX11-TRUE16-NEXT: global_store_b128 v[40:41], v[3:6], off
+; GFX11-TRUE16-NEXT: s_clause 0x3 ; 16-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s33
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:12
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v44, 1
+; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v44, 2
+; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s33 offset:16 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v32i8_ret:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT: s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 32
+; GFX11-FAKE16-NEXT: s_clause 0x3 ; 16-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:12
+; GFX11-FAKE16-NEXT: ; meta instruction
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 offset:8
+; GFX11-FAKE16-NEXT: ; meta instruction
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s33
+; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s31, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v40, 0 :: v_dual_mov_b32 v41, 0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v42, 16 :: v_dual_mov_b32 v43, 0
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: global_load_b128 v[0:3], v[40:41], off
+; GFX11-FAKE16-NEXT: global_load_b128 v[16:19], v[42:43], off
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 24, v0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 8, v16
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v16
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 24, v16
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 24, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 8, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 24, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v18
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 24, v18
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 8, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, v3
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v20, v17
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v24, v18
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v28, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v19, v34
+; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v13, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v14, v15, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v9, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v10, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v6, v7, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v28, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v30, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v20, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v22, v23, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v18, v19, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v7, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v0
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: global_store_b128 v[42:43], v[7:10], off
+; GFX11-FAKE16-NEXT: global_store_b128 v[40:41], v[3:6], off
+; GFX11-FAKE16-NEXT: s_clause 0x3 ; 16-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v43, off, s33
+; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:12
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v44, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v44, 1
+; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v44, 2
+; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT: scratch_load_b32 v44, off, s33 offset:16 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SCRATCH-LABEL: test_call_external_void_func_v32i8_ret:
; GFX10-SCRATCH: ; %bb.0:
@@ -17073,32 +17226,60 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: test_call_external_void_func_v1bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: s_mov_b32 s0, s33
-; GFX11-NEXT: s_mov_b32 s33, s32
-; GFX11-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s30, v40, 0
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
-; GFX11-NEXT: s_mov_b32 s32, s33
-; GFX11-NEXT: v_readlane_b32 s0, v40, 2
-; GFX11-NEXT: s_or_saveexec_b32 s1, -1
-; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: s_mov_b32 s33, s0
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v1bf16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT: s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v1bf16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT: s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SCRATCH-LABEL: test_call_external_void_func_v1bf16:
; GFX10-SCRATCH: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index dbf99aa1c8577..ea4f446336f44 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -13664,6 +13664,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v3, v0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
@@ -14252,6 +14253,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1]
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v4
@@ -14862,6 +14864,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v4
; GFX1250-TRUE16-NEXT: global_load_b32 v5, v[0:1], off
@@ -15471,6 +15474,7 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v3, v0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v3
@@ -16044,6 +16048,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1]
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v4, 3, v4
@@ -16638,6 +16643,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1]
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v4, 3, v4
@@ -17232,6 +17238,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1250-TRUE16-NEXT: .LBB60_1: ; %atomicrmw.start
; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -17714,6 +17721,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX1250-TRUE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX1250-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -18179,6 +18187,7 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1]
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v4
@@ -18794,6 +18803,7 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1]
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40
; GFX1250-TRUE16-NEXT: v_and_b32_e32 v4, 3, v4
diff --git a/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll b/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll
index f92ba7a8978b9..2c0c477e7a590 100644
--- a/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-extload-gfx11plus.ll
@@ -59,6 +59,7 @@ define amdgpu_kernel void @zextload_global_i8_to_i64(ptr addrspace(1) %out, ptr
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_u8 v0, v1, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
@@ -87,6 +88,7 @@ define amdgpu_kernel void @sextload_global_i8_to_i64(ptr addrspace(1) %out, ptr
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_i8 v0, v2, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
@@ -151,6 +153,7 @@ define amdgpu_kernel void @zextload_global_i16_to_i64(ptr addrspace(1) %out, ptr
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
@@ -179,6 +182,7 @@ define amdgpu_kernel void @sextload_global_i16_to_i64(ptr addrspace(1) %out, ptr
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-REAL16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-REAL16-NEXT: global_load_d16_b16 v0, v2, s[2:3]
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
index a090a1b804677..5279524a51e90 100644
--- a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
@@ -169,6 +169,7 @@ define i16 @test_v7i16_load_store(ptr addrspace(1) %ptr1, ptr addrspace(1) %ptr2
; GCN-GISEL-REAL16-NEXT: v_mov_b64_e32 v[18:19], 8
; GCN-GISEL-REAL16-NEXT: v_mov_b64_e32 v[20:21], 10
; GCN-GISEL-REAL16-NEXT: v_mov_b64_e32 v[22:23], 12
+; GCN-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GCN-GISEL-REAL16-NEXT: s_wait_loadcnt 0x0
; GCN-GISEL-REAL16-NEXT: v_pk_add_u16 v1, v6, v10
; GCN-GISEL-REAL16-NEXT: v_pk_add_u16 v4, v4, v8
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
index a72306dcd381a..764d5ab4aff72 100644
--- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
@@ -3914,6 +3914,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi(ptr addrspace(
; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_undef_hi:
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3]
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
@@ -3955,6 +3956,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi_immneg128(ptr
; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128:
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
@@ -4348,6 +4350,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi(ptr addrspace(1
; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
@@ -4364,6 +4367,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi(ptr addrspace(1
; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi:
; GFX12-SDAG-TRUE16: ; %bb.0:
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
@@ -4410,6 +4414,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi_immneg128(ptr a
; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
@@ -4426,6 +4431,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi_immneg128(ptr a
; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128:
; GFX12-SDAG-TRUE16: ; %bb.0:
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
@@ -4469,19 +4475,42 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_reg_hi(ptr addrspace(1)
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: global_load_saddr_i16_d16hi_reg_hi:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, v1
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_reg_hi:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: global_load_saddr_i16_d16hi_reg_hi:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v1
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-FAKE16-LABEL: global_load_saddr_i16_d16hi_reg_hi:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_reg_hi:
+; GFX12-SDAG-TRUE16: ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
+; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_d16hi_reg_hi:
+; GFX12-SDAG-FAKE16: ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
+; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_reg_hi:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3]
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%load = load i16, ptr addrspace(1) %gep0
@@ -4498,19 +4527,42 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_reg_hi_immneg128(ptr ad
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, v1
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v1
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-FAKE16-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128:
+; GFX12-SDAG-TRUE16: ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
+; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128:
+; GFX12-SDAG-FAKE16: ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
+; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
@@ -4528,19 +4580,42 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zexti8_reg_hi(ptr addrs
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3]
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, v1
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3]
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v1
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-FAKE16-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi:
+; GFX12-SDAG-TRUE16: ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3]
+; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi:
+; GFX12-SDAG-FAKE16: ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3]
+; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3]
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%load = load i8, ptr addrspace(1) %gep0
@@ -4558,19 +4633,42 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, v1
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v1
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-FAKE16-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
+; GFX12-SDAG-TRUE16: ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
+; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
+; GFX12-SDAG-FAKE16: ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
+; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
@@ -4589,19 +4687,42 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_sexti8_reg_hi(ptr addrs
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3]
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, v1
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3]
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v1
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-FAKE16-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi:
+; GFX12-SDAG-TRUE16: ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3]
+; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi:
+; GFX12-SDAG-FAKE16: ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3]
+; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3]
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%load = load i8, ptr addrspace(1) %gep0
@@ -4619,19 +4740,42 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v0, v1
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, v1
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-FAKE16-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
+; GFX12-SDAG-TRUE16: ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
+; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
+; GFX12-SDAG-FAKE16: ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
+; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v1
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
diff --git a/llvm/test/CodeGen/AMDGPU/gws_agpr.ll b/llvm/test/CodeGen/AMDGPU/gws_agpr.ll
index 37821363b3a5d..a19529d0e55eb 100644
--- a/llvm/test/CodeGen/AMDGPU/gws_agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/gws_agpr.ll
@@ -10,6 +10,7 @@ define void @gws_init_offset0() #0 {
; CHECK-NEXT: ; def a0
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_mov_b32 m0, 0
+; CHECK-NEXT: ; implicit-def: $agpr1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ds_gws_init a0 gds
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -27,6 +28,7 @@ define void @gws_init_offset63() #0 {
; CHECK-NEXT: ; def a0
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_mov_b32 m0, 0
+; CHECK-NEXT: ; implicit-def: $agpr1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ds_gws_init a0 offset:63 gds
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -44,6 +46,7 @@ define void @gws_init_sgpr_offset(i32 inreg %offset) #0 {
; CHECK-NEXT: ; def a0
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_lshl_b32 m0, s16, 16
+; CHECK-NEXT: ; implicit-def: $agpr1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ds_gws_init a0 gds
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -65,6 +68,7 @@ define amdgpu_kernel void @gws_init_agpr_offset() #0 {
; CHECK-NEXT: ; def a0
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_lshl_b32 m0, s0, 16
+; CHECK-NEXT: ; implicit-def: $agpr1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ds_gws_init a0 gds
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -88,6 +92,7 @@ define void @gws_init_agpr_offset_add1() #0 {
; SDAG-NEXT: ; def a0
; SDAG-NEXT: ;;#ASMEND
; SDAG-NEXT: s_lshl_b32 m0, s4, 16
+; SDAG-NEXT: ; implicit-def: $agpr1
; SDAG-NEXT: s_nop 0
; SDAG-NEXT: ds_gws_init a0 offset:1 gds
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -106,6 +111,7 @@ define void @gws_init_agpr_offset_add1() #0 {
; GISEL-NEXT: ; def a0
; GISEL-NEXT: ;;#ASMEND
; GISEL-NEXT: s_lshl_b32 m0, s4, 16
+; GISEL-NEXT: ; implicit-def: $agpr1
; GISEL-NEXT: s_nop 0
; GISEL-NEXT: ds_gws_init a0 gds
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -129,6 +135,7 @@ define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
; SDAG-NEXT: s_lshl_b32 m0, s1, 16
; SDAG-NEXT: s_waitcnt lgkmcnt(0)
; SDAG-NEXT: v_mov_b32_e32 v0, s0
+; SDAG-NEXT: ; implicit-def: $vgpr1
; SDAG-NEXT: ds_gws_init v0 offset:3 gds
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-NEXT: s_endpgm
@@ -145,6 +152,7 @@ define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
; GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GISEL-NEXT: v_mov_b32_e32 v0, s0
; GISEL-NEXT: s_lshl_b32 m0, s1, 16
+; GISEL-NEXT: ; implicit-def: $vgpr1
; GISEL-NEXT: s_nop 0
; GISEL-NEXT: ds_gws_init v0 gds
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -163,6 +171,7 @@ define void @gws_barrier_offset0() #0 {
; CHECK-NEXT: ; def a0
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_mov_b32 m0, 0
+; CHECK-NEXT: ; implicit-def: $agpr1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ds_gws_barrier a0 gds
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -180,6 +189,7 @@ define void @gws_barrier_offset63() #0 {
; CHECK-NEXT: ; def a0
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_mov_b32 m0, 0
+; CHECK-NEXT: ; implicit-def: $agpr1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ds_gws_barrier a0 offset:63 gds
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -197,6 +207,7 @@ define void @gws_barrier_sgpr_offset(i32 inreg %offset) #0 {
; CHECK-NEXT: ; def a0
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_lshl_b32 m0, s16, 16
+; CHECK-NEXT: ; implicit-def: $agpr1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ds_gws_barrier a0 gds
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -240,6 +251,7 @@ define void @gws_sema_br_offset0() #0 {
; CHECK-NEXT: ; def a0
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_mov_b32 m0, 0
+; CHECK-NEXT: ; implicit-def: $agpr1
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ds_gws_sema_br a0 gds
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
index fb5674310442d..06d5350f6d154 100644
--- a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
@@ -556,6 +556,7 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
@@ -637,6 +638,7 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -1882,6 +1884,7 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
@@ -1963,6 +1966,7 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index d42904f29aa59..e8cdb16465cab 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -6,31 +6,31 @@ define void @main(i1 %arg) #0 {
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
-; CHECK-NEXT: v_writelane_b32 v6, s36, 0
-; CHECK-NEXT: v_writelane_b32 v6, s37, 1
-; CHECK-NEXT: v_writelane_b32 v6, s38, 2
-; CHECK-NEXT: v_writelane_b32 v6, s39, 3
-; CHECK-NEXT: v_writelane_b32 v6, s48, 4
-; CHECK-NEXT: v_writelane_b32 v6, s49, 5
-; CHECK-NEXT: v_writelane_b32 v6, s50, 6
-; CHECK-NEXT: v_writelane_b32 v6, s51, 7
-; CHECK-NEXT: v_writelane_b32 v6, s52, 8
-; CHECK-NEXT: v_writelane_b32 v6, s53, 9
-; CHECK-NEXT: v_writelane_b32 v6, s54, 10
-; CHECK-NEXT: v_writelane_b32 v6, s55, 11
-; CHECK-NEXT: v_writelane_b32 v6, s64, 12
-; CHECK-NEXT: v_writelane_b32 v6, s65, 13
-; CHECK-NEXT: v_writelane_b32 v6, s66, 14
-; CHECK-NEXT: v_writelane_b32 v6, s67, 15
-; CHECK-NEXT: v_writelane_b32 v6, s68, 16
-; CHECK-NEXT: v_writelane_b32 v6, s69, 17
-; CHECK-NEXT: v_writelane_b32 v6, s70, 18
-; CHECK-NEXT: v_writelane_b32 v6, s71, 19
-; CHECK-NEXT: v_writelane_b32 v6, s30, 20
-; CHECK-NEXT: v_writelane_b32 v6, s31, 21
+; CHECK-NEXT: v_writelane_b32 v7, s36, 0
+; CHECK-NEXT: v_writelane_b32 v7, s37, 1
+; CHECK-NEXT: v_writelane_b32 v7, s38, 2
+; CHECK-NEXT: v_writelane_b32 v7, s39, 3
+; CHECK-NEXT: v_writelane_b32 v7, s48, 4
+; CHECK-NEXT: v_writelane_b32 v7, s49, 5
+; CHECK-NEXT: v_writelane_b32 v7, s50, 6
+; CHECK-NEXT: v_writelane_b32 v7, s51, 7
+; CHECK-NEXT: v_writelane_b32 v7, s52, 8
+; CHECK-NEXT: v_writelane_b32 v7, s53, 9
+; CHECK-NEXT: v_writelane_b32 v7, s54, 10
+; CHECK-NEXT: v_writelane_b32 v7, s55, 11
+; CHECK-NEXT: v_writelane_b32 v7, s64, 12
+; CHECK-NEXT: v_writelane_b32 v7, s65, 13
+; CHECK-NEXT: v_writelane_b32 v7, s66, 14
+; CHECK-NEXT: v_writelane_b32 v7, s67, 15
+; CHECK-NEXT: v_writelane_b32 v7, s68, 16
+; CHECK-NEXT: v_writelane_b32 v7, s69, 17
+; CHECK-NEXT: v_writelane_b32 v7, s70, 18
+; CHECK-NEXT: v_writelane_b32 v7, s71, 19
+; CHECK-NEXT: v_writelane_b32 v7, s30, 20
+; CHECK-NEXT: v_writelane_b32 v7, s31, 21
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_mov_b64 s[8:9], 0
; CHECK-NEXT: s_mov_b32 s68, 0
@@ -41,93 +41,93 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: ; kill: killed $sgpr8_sgpr9
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x130
-; CHECK-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane
+; CHECK-NEXT: ; implicit-def: $vgpr8 : SGPR spill to VGPR lane
; CHECK-NEXT: v_mov_b32_e32 v2, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s4
; CHECK-NEXT: s_load_dwordx16 s[36:51], s[68:69], 0x2f0
; CHECK-NEXT: s_mov_b32 s70, s68
-; CHECK-NEXT: v_writelane_b32 v7, s8, 0
-; CHECK-NEXT: v_writelane_b32 v7, s9, 1
-; CHECK-NEXT: v_writelane_b32 v7, s10, 2
-; CHECK-NEXT: v_writelane_b32 v7, s11, 3
-; CHECK-NEXT: v_writelane_b32 v7, s12, 4
-; CHECK-NEXT: v_writelane_b32 v7, s13, 5
-; CHECK-NEXT: v_writelane_b32 v7, s14, 6
-; CHECK-NEXT: v_writelane_b32 v7, s15, 7
-; CHECK-NEXT: v_writelane_b32 v7, s16, 8
-; CHECK-NEXT: v_writelane_b32 v7, s17, 9
-; CHECK-NEXT: v_writelane_b32 v7, s18, 10
-; CHECK-NEXT: v_writelane_b32 v7, s19, 11
-; CHECK-NEXT: v_writelane_b32 v7, s20, 12
-; CHECK-NEXT: v_writelane_b32 v7, s21, 13
-; CHECK-NEXT: v_writelane_b32 v7, s22, 14
-; CHECK-NEXT: v_writelane_b32 v7, s23, 15
-; CHECK-NEXT: v_writelane_b32 v7, s52, 16
-; CHECK-NEXT: v_writelane_b32 v7, s53, 17
-; CHECK-NEXT: v_writelane_b32 v7, s54, 18
-; CHECK-NEXT: v_writelane_b32 v7, s55, 19
-; CHECK-NEXT: v_writelane_b32 v7, s56, 20
-; CHECK-NEXT: v_writelane_b32 v7, s57, 21
-; CHECK-NEXT: v_writelane_b32 v7, s58, 22
-; CHECK-NEXT: v_writelane_b32 v7, s59, 23
-; CHECK-NEXT: v_writelane_b32 v7, s60, 24
-; CHECK-NEXT: v_writelane_b32 v7, s61, 25
-; CHECK-NEXT: v_writelane_b32 v7, s62, 26
-; CHECK-NEXT: v_writelane_b32 v7, s63, 27
-; CHECK-NEXT: v_writelane_b32 v7, s64, 28
-; CHECK-NEXT: v_writelane_b32 v7, s65, 29
-; CHECK-NEXT: v_writelane_b32 v7, s66, 30
+; CHECK-NEXT: v_writelane_b32 v8, s8, 0
+; CHECK-NEXT: v_writelane_b32 v8, s9, 1
+; CHECK-NEXT: v_writelane_b32 v8, s10, 2
+; CHECK-NEXT: v_writelane_b32 v8, s11, 3
+; CHECK-NEXT: v_writelane_b32 v8, s12, 4
+; CHECK-NEXT: v_writelane_b32 v8, s13, 5
+; CHECK-NEXT: v_writelane_b32 v8, s14, 6
+; CHECK-NEXT: v_writelane_b32 v8, s15, 7
+; CHECK-NEXT: v_writelane_b32 v8, s16, 8
+; CHECK-NEXT: v_writelane_b32 v8, s17, 9
+; CHECK-NEXT: v_writelane_b32 v8, s18, 10
+; CHECK-NEXT: v_writelane_b32 v8, s19, 11
+; CHECK-NEXT: v_writelane_b32 v8, s20, 12
+; CHECK-NEXT: v_writelane_b32 v8, s21, 13
+; CHECK-NEXT: v_writelane_b32 v8, s22, 14
+; CHECK-NEXT: v_writelane_b32 v8, s23, 15
+; CHECK-NEXT: v_writelane_b32 v8, s52, 16
+; CHECK-NEXT: v_writelane_b32 v8, s53, 17
+; CHECK-NEXT: v_writelane_b32 v8, s54, 18
+; CHECK-NEXT: v_writelane_b32 v8, s55, 19
+; CHECK-NEXT: v_writelane_b32 v8, s56, 20
+; CHECK-NEXT: v_writelane_b32 v8, s57, 21
+; CHECK-NEXT: v_writelane_b32 v8, s58, 22
+; CHECK-NEXT: v_writelane_b32 v8, s59, 23
+; CHECK-NEXT: v_writelane_b32 v8, s60, 24
+; CHECK-NEXT: v_writelane_b32 v8, s61, 25
+; CHECK-NEXT: v_writelane_b32 v8, s62, 26
+; CHECK-NEXT: v_writelane_b32 v8, s63, 27
+; CHECK-NEXT: v_writelane_b32 v8, s64, 28
+; CHECK-NEXT: v_writelane_b32 v8, s65, 29
+; CHECK-NEXT: v_writelane_b32 v8, s66, 30
; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x1f0
; CHECK-NEXT: s_mov_b32 s69, s68
; CHECK-NEXT: s_mov_b32 s71, s68
-; CHECK-NEXT: v_writelane_b32 v7, s67, 31
+; CHECK-NEXT: v_writelane_b32 v8, s67, 31
; CHECK-NEXT: image_sample_lz v1, v[1:2], s[60:67], s[68:71] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s52, v7, 0
+; CHECK-NEXT: v_readlane_b32 s52, v8, 0
; CHECK-NEXT: v_mov_b32_e32 v3, v2
-; CHECK-NEXT: v_readlane_b32 s53, v7, 1
-; CHECK-NEXT: v_readlane_b32 s54, v7, 2
-; CHECK-NEXT: v_readlane_b32 s55, v7, 3
-; CHECK-NEXT: v_readlane_b32 s56, v7, 4
-; CHECK-NEXT: v_readlane_b32 s57, v7, 5
-; CHECK-NEXT: v_readlane_b32 s58, v7, 6
-; CHECK-NEXT: v_readlane_b32 s59, v7, 7
+; CHECK-NEXT: v_readlane_b32 s53, v8, 1
+; CHECK-NEXT: v_readlane_b32 s54, v8, 2
+; CHECK-NEXT: v_readlane_b32 s55, v8, 3
+; CHECK-NEXT: v_readlane_b32 s56, v8, 4
+; CHECK-NEXT: v_readlane_b32 s57, v8, 5
+; CHECK-NEXT: v_readlane_b32 s58, v8, 6
+; CHECK-NEXT: v_readlane_b32 s59, v8, 7
; CHECK-NEXT: v_and_b32_e32 v5, 1, v0
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, v5
-; CHECK-NEXT: v_readlane_b32 s60, v7, 8
-; CHECK-NEXT: v_readlane_b32 s61, v7, 9
-; CHECK-NEXT: v_readlane_b32 s62, v7, 10
+; CHECK-NEXT: v_readlane_b32 s60, v8, 8
+; CHECK-NEXT: v_readlane_b32 s61, v8, 9
+; CHECK-NEXT: v_readlane_b32 s62, v8, 10
; CHECK-NEXT: image_sample_lz v4, v[2:3], s[52:59], s[68:71] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s63, v7, 11
-; CHECK-NEXT: v_readlane_b32 s64, v7, 12
-; CHECK-NEXT: v_readlane_b32 s65, v7, 13
-; CHECK-NEXT: v_readlane_b32 s66, v7, 14
-; CHECK-NEXT: v_readlane_b32 s67, v7, 15
+; CHECK-NEXT: v_readlane_b32 s63, v8, 11
+; CHECK-NEXT: v_readlane_b32 s64, v8, 12
+; CHECK-NEXT: v_readlane_b32 s65, v8, 13
+; CHECK-NEXT: v_readlane_b32 s66, v8, 14
+; CHECK-NEXT: v_readlane_b32 s67, v8, 15
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mul_f32_e32 v0, v4, v1
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execz .LBB0_3
; CHECK-NEXT: ; %bb.1: ; %bb48
-; CHECK-NEXT: v_readlane_b32 s52, v7, 16
-; CHECK-NEXT: v_readlane_b32 s60, v7, 24
-; CHECK-NEXT: v_readlane_b32 s61, v7, 25
-; CHECK-NEXT: v_readlane_b32 s62, v7, 26
-; CHECK-NEXT: v_readlane_b32 s63, v7, 27
-; CHECK-NEXT: v_readlane_b32 s64, v7, 28
-; CHECK-NEXT: v_readlane_b32 s65, v7, 29
-; CHECK-NEXT: v_readlane_b32 s66, v7, 30
-; CHECK-NEXT: v_readlane_b32 s67, v7, 31
+; CHECK-NEXT: v_readlane_b32 s52, v8, 16
+; CHECK-NEXT: v_readlane_b32 s60, v8, 24
+; CHECK-NEXT: v_readlane_b32 s61, v8, 25
+; CHECK-NEXT: v_readlane_b32 s62, v8, 26
+; CHECK-NEXT: v_readlane_b32 s63, v8, 27
+; CHECK-NEXT: v_readlane_b32 s64, v8, 28
+; CHECK-NEXT: v_readlane_b32 s65, v8, 29
+; CHECK-NEXT: v_readlane_b32 s66, v8, 30
+; CHECK-NEXT: v_readlane_b32 s67, v8, 31
; CHECK-NEXT: v_mov_b32_e32 v1, v2
; CHECK-NEXT: s_and_b64 vcc, exec, -1
-; CHECK-NEXT: v_readlane_b32 s53, v7, 17
-; CHECK-NEXT: v_readlane_b32 s54, v7, 18
-; CHECK-NEXT: v_readlane_b32 s55, v7, 19
+; CHECK-NEXT: v_readlane_b32 s53, v8, 17
+; CHECK-NEXT: v_readlane_b32 s54, v8, 18
+; CHECK-NEXT: v_readlane_b32 s55, v8, 19
; CHECK-NEXT: image_sample_lz v3, v[2:3], s[60:67], s[68:71] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s56, v7, 20
-; CHECK-NEXT: v_readlane_b32 s57, v7, 21
-; CHECK-NEXT: v_readlane_b32 s58, v7, 22
-; CHECK-NEXT: v_readlane_b32 s59, v7, 23
+; CHECK-NEXT: v_readlane_b32 s56, v8, 20
+; CHECK-NEXT: v_readlane_b32 s57, v8, 21
+; CHECK-NEXT: v_readlane_b32 s58, v8, 22
+; CHECK-NEXT: v_readlane_b32 s59, v8, 23
; CHECK-NEXT: .LBB0_2: ; %bb50
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
@@ -152,47 +152,50 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_mov_b32 s16, 0
; CHECK-NEXT: s_mov_b32 s17, s16
; CHECK-NEXT: v_mov_b32_e32 v0, s16
-; CHECK-NEXT: v_readlane_b32 s44, v7, 16
+; CHECK-NEXT: v_readlane_b32 s44, v8, 16
; CHECK-NEXT: v_mov_b32_e32 v1, s17
; CHECK-NEXT: s_mov_b32 s18, s16
; CHECK-NEXT: s_mov_b32 s19, s16
-; CHECK-NEXT: v_readlane_b32 s45, v7, 17
-; CHECK-NEXT: v_readlane_b32 s46, v7, 18
-; CHECK-NEXT: v_readlane_b32 s47, v7, 19
-; CHECK-NEXT: v_readlane_b32 s48, v7, 20
-; CHECK-NEXT: v_readlane_b32 s49, v7, 21
-; CHECK-NEXT: v_readlane_b32 s50, v7, 22
-; CHECK-NEXT: v_readlane_b32 s51, v7, 23
-; CHECK-NEXT: v_readlane_b32 s52, v7, 24
-; CHECK-NEXT: v_readlane_b32 s53, v7, 25
-; CHECK-NEXT: v_readlane_b32 s54, v7, 26
-; CHECK-NEXT: v_readlane_b32 s55, v7, 27
-; CHECK-NEXT: v_readlane_b32 s56, v7, 28
-; CHECK-NEXT: v_readlane_b32 s57, v7, 29
-; CHECK-NEXT: v_readlane_b32 s58, v7, 30
-; CHECK-NEXT: v_readlane_b32 s59, v7, 31
-; CHECK-NEXT: image_sample_lz v2, v[0:1], s[44:51], s[16:19] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s44, v7, 0
-; CHECK-NEXT: v_readlane_b32 s52, v7, 8
-; CHECK-NEXT: v_readlane_b32 s53, v7, 9
-; CHECK-NEXT: v_readlane_b32 s54, v7, 10
-; CHECK-NEXT: v_readlane_b32 s55, v7, 11
-; CHECK-NEXT: v_readlane_b32 s56, v7, 12
-; CHECK-NEXT: v_readlane_b32 s57, v7, 13
-; CHECK-NEXT: v_readlane_b32 s58, v7, 14
-; CHECK-NEXT: v_readlane_b32 s59, v7, 15
-; CHECK-NEXT: v_mov_b32_e32 v3, 0
-; CHECK-NEXT: v_mov_b32_e32 v4, v3
-; CHECK-NEXT: v_readlane_b32 s45, v7, 1
-; CHECK-NEXT: v_readlane_b32 s46, v7, 2
-; CHECK-NEXT: v_readlane_b32 s47, v7, 3
+; CHECK-NEXT: v_readlane_b32 s45, v8, 17
+; CHECK-NEXT: v_readlane_b32 s46, v8, 18
+; CHECK-NEXT: v_readlane_b32 s47, v8, 19
+; CHECK-NEXT: v_readlane_b32 s48, v8, 20
+; CHECK-NEXT: v_readlane_b32 s49, v8, 21
+; CHECK-NEXT: v_readlane_b32 s50, v8, 22
+; CHECK-NEXT: v_readlane_b32 s51, v8, 23
+; CHECK-NEXT: v_readlane_b32 s52, v8, 24
+; CHECK-NEXT: v_readlane_b32 s53, v8, 25
+; CHECK-NEXT: v_readlane_b32 s54, v8, 26
+; CHECK-NEXT: v_readlane_b32 s55, v8, 27
+; CHECK-NEXT: v_readlane_b32 s56, v8, 28
+; CHECK-NEXT: v_readlane_b32 s57, v8, 29
+; CHECK-NEXT: v_readlane_b32 s58, v8, 30
+; CHECK-NEXT: v_readlane_b32 s59, v8, 31
+; CHECK-NEXT: image_sample_lz v4, v[0:1], s[44:51], s[16:19] dmask:0x1
+; CHECK-NEXT: v_readlane_b32 s44, v8, 0
+; CHECK-NEXT: v_readlane_b32 s52, v8, 8
+; CHECK-NEXT: v_readlane_b32 s53, v8, 9
+; CHECK-NEXT: v_readlane_b32 s54, v8, 10
+; CHECK-NEXT: v_readlane_b32 s55, v8, 11
+; CHECK-NEXT: v_readlane_b32 s56, v8, 12
+; CHECK-NEXT: v_readlane_b32 s57, v8, 13
+; CHECK-NEXT: v_readlane_b32 s58, v8, 14
+; CHECK-NEXT: v_readlane_b32 s59, v8, 15
+; CHECK-NEXT: v_mov_b32_e32 v5, 0
+; CHECK-NEXT: v_mov_b32_e32 v6, v5
+; CHECK-NEXT: v_readlane_b32 s45, v8, 1
+; CHECK-NEXT: v_readlane_b32 s46, v8, 2
+; CHECK-NEXT: v_readlane_b32 s47, v8, 3
; CHECK-NEXT: image_sample_lz v0, v[0:1], s[52:59], s[24:27] dmask:0x1
-; CHECK-NEXT: v_readlane_b32 s48, v7, 4
-; CHECK-NEXT: v_readlane_b32 s49, v7, 5
-; CHECK-NEXT: v_readlane_b32 s50, v7, 6
-; CHECK-NEXT: v_readlane_b32 s51, v7, 7
+; CHECK-NEXT: v_readlane_b32 s48, v8, 4
+; CHECK-NEXT: v_readlane_b32 s49, v8, 5
+; CHECK-NEXT: v_readlane_b32 s50, v8, 6
+; CHECK-NEXT: v_readlane_b32 s51, v8, 7
+; CHECK-NEXT: ; implicit-def: $vgpr1
+; CHECK-NEXT: ; implicit-def: $vgpr2
+; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: s_waitcnt vmcnt(1)
-; CHECK-NEXT: buffer_store_dwordx3 v[2:4], off, s[16:19], 0
+; CHECK-NEXT: buffer_store_dwordx3 v[4:6], off, s[16:19], 0
; CHECK-NEXT: s_waitcnt vmcnt(1)
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
; CHECK-NEXT: ; implicit-def: $vgpr0
@@ -225,32 +228,32 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: .LBB0_10: ; %UnifiedReturnBlock
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
-; CHECK-NEXT: v_readlane_b32 s30, v6, 20
-; CHECK-NEXT: v_readlane_b32 s31, v6, 21
-; CHECK-NEXT: v_readlane_b32 s71, v6, 19
-; CHECK-NEXT: v_readlane_b32 s70, v6, 18
-; CHECK-NEXT: v_readlane_b32 s69, v6, 17
-; CHECK-NEXT: v_readlane_b32 s68, v6, 16
-; CHECK-NEXT: v_readlane_b32 s67, v6, 15
-; CHECK-NEXT: v_readlane_b32 s66, v6, 14
-; CHECK-NEXT: v_readlane_b32 s65, v6, 13
-; CHECK-NEXT: v_readlane_b32 s64, v6, 12
-; CHECK-NEXT: v_readlane_b32 s55, v6, 11
-; CHECK-NEXT: v_readlane_b32 s54, v6, 10
-; CHECK-NEXT: v_readlane_b32 s53, v6, 9
-; CHECK-NEXT: v_readlane_b32 s52, v6, 8
+; CHECK-NEXT: v_readlane_b32 s30, v7, 20
+; CHECK-NEXT: v_readlane_b32 s31, v7, 21
+; CHECK-NEXT: v_readlane_b32 s71, v7, 19
+; CHECK-NEXT: v_readlane_b32 s70, v7, 18
+; CHECK-NEXT: v_readlane_b32 s69, v7, 17
+; CHECK-NEXT: v_readlane_b32 s68, v7, 16
+; CHECK-NEXT: v_readlane_b32 s67, v7, 15
+; CHECK-NEXT: v_readlane_b32 s66, v7, 14
+; CHECK-NEXT: v_readlane_b32 s65, v7, 13
+; CHECK-NEXT: v_readlane_b32 s64, v7, 12
+; CHECK-NEXT: v_readlane_b32 s55, v7, 11
+; CHECK-NEXT: v_readlane_b32 s54, v7, 10
+; CHECK-NEXT: v_readlane_b32 s53, v7, 9
+; CHECK-NEXT: v_readlane_b32 s52, v7, 8
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_readlane_b32 s51, v6, 7
-; CHECK-NEXT: v_readlane_b32 s50, v6, 6
-; CHECK-NEXT: v_readlane_b32 s49, v6, 5
-; CHECK-NEXT: v_readlane_b32 s48, v6, 4
-; CHECK-NEXT: v_readlane_b32 s39, v6, 3
-; CHECK-NEXT: v_readlane_b32 s38, v6, 2
-; CHECK-NEXT: v_readlane_b32 s37, v6, 1
-; CHECK-NEXT: v_readlane_b32 s36, v6, 0
+; CHECK-NEXT: v_readlane_b32 s51, v7, 7
+; CHECK-NEXT: v_readlane_b32 s50, v7, 6
+; CHECK-NEXT: v_readlane_b32 s49, v7, 5
+; CHECK-NEXT: v_readlane_b32 s48, v7, 4
+; CHECK-NEXT: v_readlane_b32 s39, v7, 3
+; CHECK-NEXT: v_readlane_b32 s38, v7, 2
+; CHECK-NEXT: v_readlane_b32 s37, v7, 1
+; CHECK-NEXT: v_readlane_b32 s36, v7, 0
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/idot4s.ll b/llvm/test/CodeGen/AMDGPU/idot4s.ll
index 917dc51254396..8ed6418036333 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4s.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4s.ll
@@ -1140,6 +1140,8 @@ define amdgpu_kernel void @idot4_acc16_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-DL-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
; GFX11-DL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-DL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -1152,16 +1154,16 @@ define amdgpu_kernel void @idot4_acc16_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 8
; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v4.h, 8, v1.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
-; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v7.h, 8, v2.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.h
+; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v8.h, 8, v2.l
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v9.l, v2.h
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v7, 0, 8
; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v1.h, 8, v1.h
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 8
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v9, 0, 8
; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v2.h, 8, v2.h
-; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v4, v4, v7
+; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v4, v4, v8
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.l
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l
@@ -3361,6 +3363,7 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16: ; %bb.0: ; %entry
; GFX11-DL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-DL-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-DL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
@@ -3372,6 +3375,7 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 8, v3
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v3, 0, 8
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.h
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v0, 0, 8
@@ -3382,6 +3386,7 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v6, 0, 8
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v3
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v4.h
@@ -3390,6 +3395,7 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v2.l, v0.h, v0.l
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v3.l, v0.l
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index 1735e5c8c4ca2..f4ba0cba6835d 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -1938,6 +1938,7 @@ define amdgpu_kernel void @notdot4_mixedtypes2(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-DL-TRUE16-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0x3ff, v0
; GFX11-DL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-DL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -1949,6 +1950,7 @@ define amdgpu_kernel void @notdot4_mixedtypes2(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v4
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v4, 0, 8
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
@@ -1960,6 +1962,7 @@ define amdgpu_kernel void @notdot4_mixedtypes2(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v3
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v1.l, v0.l
; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v3.h
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -2707,6 +2710,7 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b16 v1.h, 8, v4.l
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v3.l, v4.l, v0.l
; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v2.l, v2.l, v6.l
+; GFX11-DL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.h, v0.h, v1.h
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
index 5d2259216e7f7..5c210c2641af1 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
@@ -7419,7 +7419,17 @@ define amdgpu_kernel void @multi_same_block(i32 %arg) {
; GENERIC: ; %bb.0: ; %bb
; GENERIC-NEXT: s_load_dword s0, s[4:5], 0x9
; GENERIC-NEXT: v_mov_b32_e32 v1, 0x41900000
+; GENERIC-NEXT: ; implicit-def: $vgpr2
+; GENERIC-NEXT: ; implicit-def: $vgpr3
+; GENERIC-NEXT: ; implicit-def: $vgpr4
+; GENERIC-NEXT: ; implicit-def: $vgpr5
+; GENERIC-NEXT: ; implicit-def: $vgpr6
+; GENERIC-NEXT: ; implicit-def: $vgpr7
+; GENERIC-NEXT: ; implicit-def: $vgpr8
; GENERIC-NEXT: v_mov_b32_e32 v9, 0x41b0cccd
+; GENERIC-NEXT: ; implicit-def: $vgpr10
+; GENERIC-NEXT: ; implicit-def: $vgpr11
+; GENERIC-NEXT: ; implicit-def: $vgpr12
; GENERIC-NEXT: s_waitcnt lgkmcnt(0)
; GENERIC-NEXT: s_add_i32 m0, s0, -16
; GENERIC-NEXT: v_movreld_b32_e32 v0, 4.0
@@ -7511,7 +7521,17 @@ define amdgpu_kernel void @multi_same_block(i32 %arg) {
; SI-MOVREL: ; %bb.0: ; %bb
; SI-MOVREL-NEXT: s_load_dword s0, s[4:5], 0x9
; SI-MOVREL-NEXT: v_mov_b32_e32 v1, 0x41900000
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr2
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr3
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr4
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr5
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr6
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr7
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr8
; SI-MOVREL-NEXT: v_mov_b32_e32 v9, 0x41b0cccd
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr10
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr11
+; SI-MOVREL-NEXT: ; implicit-def: $vgpr12
; SI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
; SI-MOVREL-NEXT: s_add_i32 m0, s0, -16
; SI-MOVREL-NEXT: v_movreld_b32_e32 v0, 4.0
@@ -7525,7 +7545,17 @@ define amdgpu_kernel void @multi_same_block(i32 %arg) {
; VI-MOVREL: ; %bb.0: ; %bb
; VI-MOVREL-NEXT: s_load_dword s0, s[4:5], 0x24
; VI-MOVREL-NEXT: v_mov_b32_e32 v1, 0x41900000
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr2
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr3
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr4
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr5
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr6
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr7
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr8
; VI-MOVREL-NEXT: v_mov_b32_e32 v9, 0x41b0cccd
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr10
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr11
+; VI-MOVREL-NEXT: ; implicit-def: $vgpr12
; VI-MOVREL-NEXT: s_waitcnt lgkmcnt(0)
; VI-MOVREL-NEXT: s_add_i32 m0, s0, -16
; VI-MOVREL-NEXT: v_movreld_b32_e32 v0, 4.0
@@ -7539,7 +7569,17 @@ define amdgpu_kernel void @multi_same_block(i32 %arg) {
; VI-IDXMODE: ; %bb.0: ; %bb
; VI-IDXMODE-NEXT: s_load_dword s0, s[4:5], 0x24
; VI-IDXMODE-NEXT: v_mov_b32_e32 v1, 0x41900000
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr2
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr3
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr4
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr5
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr6
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr7
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr8
; VI-IDXMODE-NEXT: v_mov_b32_e32 v9, 0x41b0cccd
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr10
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr11
+; VI-IDXMODE-NEXT: ; implicit-def: $vgpr12
; VI-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
; VI-IDXMODE-NEXT: s_add_i32 s0, s0, -16
; VI-IDXMODE-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
@@ -7555,7 +7595,17 @@ define amdgpu_kernel void @multi_same_block(i32 %arg) {
; GFX9-IDXMODE: ; %bb.0: ; %bb
; GFX9-IDXMODE-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v1, 0x41900000
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr2
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr3
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr4
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr5
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr6
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr7
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr8
; GFX9-IDXMODE-NEXT: v_mov_b32_e32 v9, 0x41b0cccd
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr10
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr11
+; GFX9-IDXMODE-NEXT: ; implicit-def: $vgpr12
; GFX9-IDXMODE-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-IDXMODE-NEXT: s_add_i32 s0, s0, -16
; GFX9-IDXMODE-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
index ea406781a4e79..efcb5d1cb1d3d 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
@@ -2525,6 +2525,8 @@ define amdgpu_kernel void @double7_inselt(ptr addrspace(1) %out, <7 x double> %v
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GCN-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x94
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x84
+; GCN-NEXT: ; implicit-def: $vgpr14
+; GCN-NEXT: ; implicit-def: $vgpr15
; GCN-NEXT: v_mov_b32_e32 v16, 0x3ff00000
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s8
@@ -3187,6 +3189,8 @@ define amdgpu_kernel void @double15_inselt(ptr addrspace(1) %out, <15 x double>
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x114
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x104
; GCN-NEXT: s_load_dwordx8 s[24:31], s[4:5], 0xe4
+; GCN-NEXT: ; implicit-def: $vgpr30
+; GCN-NEXT: ; implicit-def: $vgpr31
; GCN-NEXT: v_mov_b32_e32 v32, 0x3ff00000
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s8
diff --git a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
index 33424b7f0d16e..2bcea27a47153 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
@@ -1264,6 +1264,7 @@ define amdgpu_ps <4 x float> @load.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coor
;
; GFX90A-LABEL: load.f32.1d:
; GFX90A: ; %bb.0: ; %main_body
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_load v0, v0, s[0:7] dmask:0x1 unorm a16
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
@@ -1323,6 +1324,7 @@ define amdgpu_ps void @store_f32_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4
; GFX90A-NEXT: v_mov_b32_e32 v4, v3
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_store v[2:5], v0, s[0:7] dmask:0x1 unorm a16
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_endpgm
@@ -1380,6 +1382,7 @@ define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s)
; GFX90A-LABEL: atomic_swap_1d:
; GFX90A: ; %bb.0: ; %main_body
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: image_atomic_swap v0, v2, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 9325595c882f2..6e251889dbc18 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -407,6 +407,7 @@ define signext i16 @clpeak_imad_pat_i16(i16 signext %x, i16 signext %y) {
; GFX11-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -435,6 +436,7 @@ define signext i16 @clpeak_imad_pat_i16(i16 signext %x, i16 signext %y) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -469,6 +471,7 @@ define signext i16 @clpeak_imad_pat_i16(i16 signext %x, i16 signext %y) {
; GFX1200-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX1200-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -505,6 +508,7 @@ define signext i16 @clpeak_imad_pat_i16(i16 signext %x, i16 signext %y) {
; GFX1200-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX1200-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1200-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -571,6 +575,7 @@ define signext i16 @clpeak_imad_pat_i16(i16 signext %x, i16 signext %y) {
; GFX1250-SDAG-REAL16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX1250-SDAG-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-SDAG-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1250-SDAG-REAL16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -588,6 +593,7 @@ define signext i16 @clpeak_imad_pat_i16(i16 signext %x, i16 signext %y) {
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
@@ -5694,6 +5700,7 @@ define signext i8 @clpeak_imad_pat_i8(i8 signext %x, i8 signext %y) {
; GFX11-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5722,6 +5729,7 @@ define signext i8 @clpeak_imad_pat_i8(i8 signext %x, i8 signext %y) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -5756,6 +5764,7 @@ define signext i8 @clpeak_imad_pat_i8(i8 signext %x, i8 signext %y) {
; GFX1200-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX1200-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5792,6 +5801,7 @@ define signext i8 @clpeak_imad_pat_i8(i8 signext %x, i8 signext %y) {
; GFX1200-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX1200-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX1200-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -5858,6 +5868,7 @@ define signext i8 @clpeak_imad_pat_i8(i8 signext %x, i8 signext %y) {
; GFX1250-SDAG-REAL16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX1250-SDAG-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-SDAG-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX1250-SDAG-REAL16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -5875,6 +5886,7 @@ define signext i8 @clpeak_imad_pat_i8(i8 signext %x, i8 signext %y) {
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
@@ -6174,6 +6186,8 @@ define <2 x i8> @clpeak_imad_pat_v2i8(<2 x i8> %x, <2 x i8> %y) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v1.l, v0.h, v1.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: clpeak_imad_pat_v2i8:
@@ -6286,6 +6300,8 @@ define <2 x i8> @clpeak_imad_pat_v2i8(<2 x i8> %x, <2 x i8> %y) {
; GFX1200-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v1.l, v0.h, v1.h
+; GFX1200-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1200-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1200-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-GISEL-FAKE16-LABEL: clpeak_imad_pat_v2i8:
@@ -6413,6 +6429,8 @@ define <2 x i8> @clpeak_imad_pat_v2i8(<2 x i8> %x, <2 x i8> %y) {
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v1.l, v0.h, v1.h
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
; GFX1250-GISEL-LABEL: clpeak_imad_pat_v2i8:
; GFX1250-GISEL: ; %bb.0: ; %entry
@@ -6769,20 +6787,24 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v8, v2, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v8, v3, v[1:2]
; GFX10-GISEL-NEXT: v_add_co_u32 v1, vcc_lo, v0, v8
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr5
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v9, v2, v[4:5]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v1, v2, 0
; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v9, null, v6, v9, vcc_lo
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[7:8], null, v1, v3, v[5:6]
-; GFX10-GISEL-NEXT: v_add_co_u32 v8, vcc_lo, v0, 1
+; GFX10-GISEL-NEXT: v_add_co_u32 v10, vcc_lo, v0, 1
; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v0, null, 0, v6, vcc_lo
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v4, v8, 0
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr8
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v4, v10, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v9, v2, v[7:8]
; GFX10-GISEL-NEXT: v_add_co_u32 v7, vcc_lo, v4, 1
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v4, v0, v[6:7]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v5, v7, 0
-; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v2, vcc_lo
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v2, v8, v[3:4]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v5, v4, v[1:2]
+; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v2, vcc_lo
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v2, v10, v[3:4]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v5, v6, v[1:2]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr4
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v2, v7, v[3:4]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -6829,28 +6851,32 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v8, v3, v[1:2]
; GFX11-GISEL-NEXT: v_add_co_u32 v1, vcc_lo, v0, v8
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr5
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v9, v2, v[4:5]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v1, v2, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v10, null, v6, v9, vcc_lo
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v11, null, v6, v9, vcc_lo
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[7:8], null, v1, v3, v[5:6]
-; GFX11-GISEL-NEXT: v_add_co_u32 v11, vcc_lo, v0, 1
+; GFX11-GISEL-NEXT: v_add_co_u32 v12, vcc_lo, v0, 1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v0, null, 0, v6, vcc_lo
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v4, v11, 0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr8
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v4, v12, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v10, v2, v[7:8]
-; GFX11-GISEL-NEXT: v_add_co_u32 v9, vcc_lo, v4, 1
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v11, v2, v[7:8]
+; GFX11-GISEL-NEXT: v_add_co_u32 v8, vcc_lo, v4, 1
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v4, v0, v[6:7]
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v5, v9, 0
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v8, vcc_lo
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v5, v8, 0
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v9, vcc_lo
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr3
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v8, v11, v[2:3]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v5, v10, v[1:2]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v9, v12, v[2:3]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v5, v10, v[1:2]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr4
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v3, v9, v[6:7]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v6, v8, v[3:4]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-LABEL: clpeak_imad_pat_i64:
@@ -7596,46 +7622,54 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX10-GISEL-LABEL: clpeak_imad_pat_v2i64:
; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_add_co_u32 v11, vcc_lo, v0, 1
-; GFX10-GISEL-NEXT: v_add_co_u32 v15, s4, v2, 1
-; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v16, null, 0, v1, vcc_lo
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v11, v4, 0
-; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v3, s4
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v15, v6, 0
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v11, v5, v[1:2]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v15, v7, v[3:4]
-; GFX10-GISEL-NEXT: v_add_co_u32 v3, vcc_lo, v2, v15
-; GFX10-GISEL-NEXT: v_add_co_u32 v1, s4, v0, v11
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[12:13], null, v16, v4, v[8:9]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v17, v6, v[9:10]
+; GFX10-GISEL-NEXT: v_add_co_u32 v15, vcc_lo, v0, 1
+; GFX10-GISEL-NEXT: v_add_co_u32 v16, s4, v2, 1
+; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v1, vcc_lo
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v15, v4, 0
+; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v18, null, 0, v3, s4
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v16, v6, 0
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v15, v5, v[1:2]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v16, v7, v[3:4]
+; GFX10-GISEL-NEXT: v_add_co_u32 v3, vcc_lo, v2, v16
+; GFX10-GISEL-NEXT: v_add_co_u32 v1, s4, v0, v15
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr9
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr11
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[12:13], null, v17, v4, v[8:9]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v18, v6, v[10:11]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v1, v4, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v3, v6, 0
-; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v15, null, v12, v16, s4
+; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v15, null, v12, v17, s4
+; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v16, null, v13, v18, vcc_lo
+; GFX10-GISEL-NEXT: v_add_co_u32 v17, vcc_lo, v2, 1
; GFX10-GISEL-NEXT: v_add_co_u32 v18, s4, v0, 1
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v1, v5, v[9:10]
-; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v16, null, v13, v17, vcc_lo
-; GFX10-GISEL-NEXT: v_add_co_u32 v17, vcc_lo, v2, 1
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v3, v7, v[11:12]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v3, v7, v[11:12]
; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v12, s4
-; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v2, null, 0, v13, vcc_lo
+; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v13, vcc_lo
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[11:12], null, v8, v18, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v10, v17, 0
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v15, v4, v[0:1]
; GFX10-GISEL-NEXT: v_add_co_u32 v15, vcc_lo, v10, 1
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v16, v6, v[1:2]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v16, v6, v[2:3]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v8, v19, v[12:13]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v10, v2, v[14:15]
-; GFX10-GISEL-NEXT: v_add_co_u32 v10, s4, v8, 1
+; GFX10-GISEL-NEXT: v_add_co_u32 v12, s4, v8, 1
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v10, v9, v[14:15]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v13, v15, 0
; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v8, null, 0, v4, s4
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v11, v10, 0
-; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v12, null, 0, v5, vcc_lo
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v11, v12, 0
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr7
+; GFX10-GISEL-NEXT: v_add_co_ci_u32_e64 v14, null, 0, v5, vcc_lo
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr10
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v4, v18, v[6:7]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v5, v17, v[9:10]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[7:8], null, v11, v8, v[1:2]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v13, v12, v[3:4]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v6, v10, v[7:8]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v4, v15, v[8:9]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr8
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v13, v14, v[3:4]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr10
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v6, v12, v[7:8]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v4, v15, v[9:10]
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, v5
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -7699,55 +7733,64 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX11-GISEL-LABEL: clpeak_imad_pat_v2i64:
; GFX11-GISEL: ; %bb.0: ; %entry
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_co_u32 v11, vcc_lo, v0, 1
-; GFX11-GISEL-NEXT: v_add_co_u32 v15, s0, v2, 1
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v16, null, 0, v1, vcc_lo
+; GFX11-GISEL-NEXT: v_add_co_u32 v15, vcc_lo, v0, 1
+; GFX11-GISEL-NEXT: v_add_co_u32 v16, s0, v2, 1
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v1, vcc_lo
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v11, v4, 0
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v3, s0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v15, v6, 0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v15, v4, 0
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v18, null, 0, v3, s0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v16, v6, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v11, v5, v[1:2]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v15, v7, v[3:4]
-; GFX11-GISEL-NEXT: v_add_co_u32 v3, vcc_lo, v2, v15
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[12:13], null, v16, v4, v[8:9]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v17, v6, v[9:10]
-; GFX11-GISEL-NEXT: v_add_co_u32 v14, s0, v0, v11
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v15, v5, v[1:2]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v16, v7, v[3:4]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr9
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr11
+; GFX11-GISEL-NEXT: v_add_co_u32 v3, s0, v0, v15
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[12:13], null, v17, v4, v[8:9]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v18, v6, v[10:11]
+; GFX11-GISEL-NEXT: v_add_co_u32 v14, vcc_lo, v2, v16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v3, v6, 0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v14, v4, 0
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v18, null, v12, v16, s0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v3, v4, 0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v14, v6, 0
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v17, null, v12, v17, s0
; GFX11-GISEL-NEXT: v_add_co_u32 v20, s0, v0, 1
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v17, null, v13, v17, vcc_lo
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v18, null, v13, v18, vcc_lo
; GFX11-GISEL-NEXT: v_add_co_u32 v19, vcc_lo, v2, 1
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v14, v5, v[9:10]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v3, v7, v[11:12]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v3, v5, v[9:10]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v14, v7, v[11:12]
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v13, vcc_lo
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v10, v19, 0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr1
; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v12, s0
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v2, null, 0, v13, vcc_lo
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[11:12], null, v8, v20, 0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v10, v19, 0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[15:16], null, v18, v4, v[0:1]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v17, v6, v[1:2]
-; GFX11-GISEL-NEXT: v_add_co_u32 v16, vcc_lo, v10, 1
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[15:16], null, v17, v4, v[0:1]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v18, v6, v[2:3]
+; GFX11-GISEL-NEXT: v_add_co_u32 v18, vcc_lo, v10, 1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v8, v21, v[12:13]
-; GFX11-GISEL-NEXT: v_add_co_u32 v12, s0, v8, 1
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v10, v2, v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v13, v16, 0
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v15, s0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v11, v12, 0
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v14, null, 0, v4, vcc_lo
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[16:17], null, v10, v7, v[14:15]
+; GFX11-GISEL-NEXT: v_add_co_u32 v14, s0, v8, 1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v13, v18, 0
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v12, null, 0, v15, s0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v11, v14, 0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr6
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[7:8], null, v15, v20, v[5:6]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v4, v19, v[6:7]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v11, v10, v[1:2]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v13, v14, v[3:4]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v7, v12, v[4:5]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr17
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v4, v19, v[16:17]
+; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v4, vcc_lo
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v11, v12, v[1:2]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[11:12], null, v13, v21, v[3:4]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr10
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr12
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v8, v16, v[9:10]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v7, v14, v[9:10]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v8, v18, v[11:12]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, v5
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -10020,6 +10063,7 @@ define signext i16 @clpeak_imad_pat_i16_x2(i16 signext %x, i16 signext %y) {
; GFX11-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10064,6 +10108,7 @@ define signext i16 @clpeak_imad_pat_i16_x2(i16 signext %x, i16 signext %y) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -10114,6 +10159,7 @@ define signext i16 @clpeak_imad_pat_i16_x2(i16 signext %x, i16 signext %y) {
; GFX1200-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX1200-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10166,6 +10212,7 @@ define signext i16 @clpeak_imad_pat_i16_x2(i16 signext %x, i16 signext %y) {
; GFX1200-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX1200-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1200-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1200-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -10264,6 +10311,7 @@ define signext i16 @clpeak_imad_pat_i16_x2(i16 signext %x, i16 signext %y) {
; GFX1250-SDAG-REAL16-NEXT: v_mad_u16 v0.l, v0.h, v0.l, v0.h
; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-SDAG-REAL16-NEXT: v_mad_u16 v0.l, v0.l, v0.h, v0.l
+; GFX1250-SDAG-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-SDAG-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1250-SDAG-REAL16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -10291,6 +10339,7 @@ define signext i16 @clpeak_imad_pat_i16_x2(i16 signext %x, i16 signext %y) {
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-REAL16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
@@ -11956,9 +12005,10 @@ define i16 @other_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z, ptr addrspace(3) %
; GFX11-GISEL-TRUE16-LABEL: other_use_mul_mad_i16_var:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.h, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: v_mul_lo_u16 v1.h, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_mad_u16 v0.l, v0.l, v1.l, v2.l
-; GFX11-GISEL-TRUE16-NEXT: ds_store_b16_d16_hi v3, v0
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-TRUE16-NEXT: ds_store_b16_d16_hi v3, v1
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -12004,9 +12054,10 @@ define i16 @other_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z, ptr addrspace(3) %
; GFX1200-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX1200-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v0.h, v0.l, v1.l
+; GFX1200-GISEL-TRUE16-NEXT: v_mul_lo_u16 v1.h, v0.l, v1.l
; GFX1200-GISEL-TRUE16-NEXT: v_mad_u16 v0.l, v0.l, v1.l, v2.l
-; GFX1200-GISEL-TRUE16-NEXT: ds_store_b16_d16_hi v3, v0
+; GFX1200-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1200-GISEL-TRUE16-NEXT: ds_store_b16_d16_hi v3, v1
; GFX1200-GISEL-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX1200-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -12033,15 +12084,26 @@ define i16 @other_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z, ptr addrspace(3) %
; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
-; GFX1250-REAL16-LABEL: other_use_mul_mad_i16_var:
-; GFX1250-REAL16: ; %bb.0: ; %entry
-; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT: v_mul_lo_u16 v0.h, v0.l, v1.l
-; GFX1250-REAL16-NEXT: v_mad_u16 v0.l, v0.l, v1.l, v2.l
-; GFX1250-REAL16-NEXT: ds_store_b16_d16_hi v3, v0
-; GFX1250-REAL16-NEXT: s_wait_dscnt 0x0
-; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-SDAG-REAL16-LABEL: other_use_mul_mad_i16_var:
+; GFX1250-SDAG-REAL16: ; %bb.0: ; %entry
+; GFX1250-SDAG-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-REAL16-NEXT: v_mul_lo_u16 v0.h, v0.l, v1.l
+; GFX1250-SDAG-REAL16-NEXT: v_mad_u16 v0.l, v0.l, v1.l, v2.l
+; GFX1250-SDAG-REAL16-NEXT: ds_store_b16_d16_hi v3, v0
+; GFX1250-SDAG-REAL16-NEXT: s_wait_dscnt 0x0
+; GFX1250-SDAG-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-REAL16-LABEL: other_use_mul_mad_i16_var:
+; GFX1250-GISEL-REAL16: ; %bb.0: ; %entry
+; GFX1250-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: v_mul_lo_u16 v1.h, v0.l, v1.l
+; GFX1250-GISEL-REAL16-NEXT: v_mad_u16 v0.l, v0.l, v1.l, v2.l
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-GISEL-REAL16-NEXT: ds_store_b16_d16_hi v3, v1
+; GFX1250-GISEL-REAL16-NEXT: s_wait_dscnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
entry:
%mul = mul i16 %x, %y
%add0 = add i16 %mul, %z
@@ -12663,6 +12725,7 @@ declare i64 @llvm.amdgcn.mul.u24.i64(i32, i32)
declare i32 @llvm.amdgcn.mul.u24(i32, i32)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1250-REAL16: {{.*}}
; GFX6: {{.*}}
; GFX7: {{.*}}
; GFX900: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll b/llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll
index 55a5d50f06bbd..bf912d46f8aa3 100644
--- a/llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/invalid-cast-load-i1.ll
@@ -8,6 +8,7 @@ define amdgpu_kernel void @load_idx_idy(ptr addrspace(4) %disp, ptr %g) {
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT: ; implicit-def: $sgpr5
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_lshr_b32 s4, s6, 16
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
index 4bc09f2c9abe5..599a7c30dbc8d 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
@@ -195,44 +195,46 @@ define float @sitofp_i128_to_f32(i128 %x) {
; GISEL-NEXT: v_or_b32_e32 v12, v10, v12
; GISEL-NEXT: v_lshrrev_b64 v[9:10], v13, v[2:3]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
-; GISEL-NEXT: v_add_u32_e32 v14, 26, v5
+; GISEL-NEXT: v_add_u32_e32 v15, 26, v5
; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
-; GISEL-NEXT: v_sub_u32_e32 v11, 64, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v13, v9, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v10, v1, vcc
-; GISEL-NEXT: v_lshrrev_b64 v[9:10], v14, -1
-; GISEL-NEXT: v_lshlrev_b64 v[11:12], v11, -1
-; GISEL-NEXT: v_add_u32_e32 v5, 0xffffffda, v5
-; GISEL-NEXT: v_or_b32_e32 v15, v9, v11
-; GISEL-NEXT: v_or_b32_e32 v16, v10, v12
-; GISEL-NEXT: v_lshrrev_b64 v[11:12], v5, -1
-; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v15, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v11, v12, v16, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GISEL-NEXT: v_sub_u32_e32 v4, 64, v15
+; GISEL-NEXT: v_lshrrev_b64 v[11:12], v15, -1
+; GISEL-NEXT: v_lshlrev_b64 v[13:14], v4, -1
+; GISEL-NEXT: v_add_u32_e32 v4, 0xffffffda, v5
+; GISEL-NEXT: v_lshrrev_b64 v[4:5], v4, -1
+; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v1, vcc
+; GISEL-NEXT: v_or_b32_e32 v13, v11, v13
+; GISEL-NEXT: v_or_b32_e32 v14, v12, v14
+; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v13, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
+; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[4:5]
-; GISEL-NEXT: v_and_b32_e32 v2, v9, v2
-; GISEL-NEXT: v_and_b32_e32 v3, v10, v3
-; GISEL-NEXT: v_and_or_b32 v0, v5, v0, v2
-; GISEL-NEXT: v_and_or_b32 v1, v11, v1, v3
+; GISEL-NEXT: v_and_b32_e32 v2, v11, v2
+; GISEL-NEXT: v_and_b32_e32 v3, v12, v3
+; GISEL-NEXT: v_and_or_b32 v0, v4, v0, v2
+; GISEL-NEXT: v_and_or_b32 v1, v5, v1, v3
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr11_vgpr12
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_or_b32_e32 v3, v13, v0
-; GISEL-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-NEXT: v_mov_b32_e32 v1, v4
-; GISEL-NEXT: v_mov_b32_e32 v2, v5
-; GISEL-NEXT: v_mov_b32_e32 v3, v6
+; GISEL-NEXT: v_or_b32_e32 v9, v9, v0
+; GISEL-NEXT: v_mov_b32_e32 v0, v9
+; GISEL-NEXT: v_mov_b32_e32 v1, v10
+; GISEL-NEXT: v_mov_b32_e32 v2, v11
+; GISEL-NEXT: v_mov_b32_e32 v3, v12
; GISEL-NEXT: .LBB0_6: ; %Flow1
; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
; GISEL-NEXT: .LBB0_7: ; %Flow2
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; GISEL-NEXT: ; %bb.8: ; %itofp-sw-bb
; GISEL-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
; GISEL-NEXT: ; %bb.9: ; %itofp-sw-epilog
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
; GISEL-NEXT: v_bfe_u32 v2, v0, 2, 1
@@ -449,44 +451,46 @@ define float @uitofp_i128_to_f32(i128 %x) {
; GISEL-NEXT: v_or_b32_e32 v11, v9, v11
; GISEL-NEXT: v_lshrrev_b64 v[8:9], v12, v[2:3]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
-; GISEL-NEXT: v_add_u32_e32 v13, 26, v5
+; GISEL-NEXT: v_add_u32_e32 v14, 26, v5
; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
-; GISEL-NEXT: v_sub_u32_e32 v10, 64, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v12, v8, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v9, v1, vcc
-; GISEL-NEXT: v_lshrrev_b64 v[8:9], v13, -1
-; GISEL-NEXT: v_lshlrev_b64 v[10:11], v10, -1
-; GISEL-NEXT: v_add_u32_e32 v5, 0xffffffda, v5
-; GISEL-NEXT: v_or_b32_e32 v14, v8, v10
-; GISEL-NEXT: v_or_b32_e32 v15, v9, v11
-; GISEL-NEXT: v_lshrrev_b64 v[10:11], v5, -1
-; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v14, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v15, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GISEL-NEXT: v_sub_u32_e32 v4, 64, v14
+; GISEL-NEXT: v_lshrrev_b64 v[10:11], v14, -1
+; GISEL-NEXT: v_lshlrev_b64 v[12:13], v4, -1
+; GISEL-NEXT: v_add_u32_e32 v4, 0xffffffda, v5
+; GISEL-NEXT: v_lshrrev_b64 v[4:5], v4, -1
+; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc
+; GISEL-NEXT: v_or_b32_e32 v12, v10, v12
+; GISEL-NEXT: v_or_b32_e32 v13, v11, v13
+; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
+; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, -1, s[4:5]
-; GISEL-NEXT: v_and_b32_e32 v2, v8, v2
-; GISEL-NEXT: v_and_b32_e32 v3, v9, v3
-; GISEL-NEXT: v_and_or_b32 v0, v5, v0, v2
-; GISEL-NEXT: v_and_or_b32 v1, v10, v1, v3
+; GISEL-NEXT: v_and_b32_e32 v2, v10, v2
+; GISEL-NEXT: v_and_b32_e32 v3, v11, v3
+; GISEL-NEXT: v_and_or_b32 v0, v4, v0, v2
+; GISEL-NEXT: v_and_or_b32 v1, v5, v1, v3
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr10_vgpr11
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_or_b32_e32 v3, v12, v0
-; GISEL-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-NEXT: v_mov_b32_e32 v1, v4
-; GISEL-NEXT: v_mov_b32_e32 v2, v5
-; GISEL-NEXT: v_mov_b32_e32 v3, v6
+; GISEL-NEXT: v_or_b32_e32 v8, v8, v0
+; GISEL-NEXT: v_mov_b32_e32 v0, v8
+; GISEL-NEXT: v_mov_b32_e32 v1, v9
+; GISEL-NEXT: v_mov_b32_e32 v2, v10
+; GISEL-NEXT: v_mov_b32_e32 v3, v11
; GISEL-NEXT: .LBB1_6: ; %Flow1
; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
; GISEL-NEXT: .LBB1_7: ; %Flow2
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; GISEL-NEXT: ; %bb.8: ; %itofp-sw-bb
; GISEL-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
; GISEL-NEXT: ; %bb.9: ; %itofp-sw-epilog
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
; GISEL-NEXT: v_bfe_u32 v2, v0, 2, 1
@@ -644,6 +648,7 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_lshrrev_b64 v[0:1], 2, v[4:5]
; SDAG-NEXT: v_lshlrev_b32_e32 v7, 30, v6
; SDAG-NEXT: v_or_b32_e32 v10, v1, v7
+; SDAG-NEXT: ; implicit-def: $vgpr1
; SDAG-NEXT: v_and_b32_e32 v1, 0x800000, v5
; SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -666,6 +671,7 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v1, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SDAG-NEXT: ; implicit-def: $vgpr1
; SDAG-NEXT: ; implicit-def: $vgpr2
; SDAG-NEXT: ; implicit-def: $vgpr6_vgpr7
; SDAG-NEXT: ; implicit-def: $vgpr4_vgpr5
@@ -675,6 +681,7 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_lshlrev_b32_e32 v4, 29, v6
; SDAG-NEXT: v_or_b32_e32 v10, v1, v4
; SDAG-NEXT: v_mov_b32_e32 v8, v2
+; SDAG-NEXT: ; implicit-def: $vgpr5
; SDAG-NEXT: s_branch .LBB2_10
;
; GISEL-LABEL: sitofp_i128_to_f64:
@@ -803,6 +810,7 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_and_b32_e32 v10, 0x800000, v3
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
; GISEL-NEXT: v_lshl_or_b32 v10, v4, 30, v1
+; GISEL-NEXT: ; implicit-def: $vgpr1
; GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GISEL-NEXT: s_cbranch_execnz .LBB2_14
; GISEL-NEXT: .LBB2_10: ; %Flow
@@ -823,6 +831,7 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v1, vcc
+; GISEL-NEXT: ; implicit-def: $vgpr1
; GISEL-NEXT: ; implicit-def: $vgpr7
; GISEL-NEXT: ; implicit-def: $vgpr2
; GISEL-NEXT: s_branch .LBB2_2
@@ -830,6 +839,7 @@ define double @sitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_lshrrev_b64 v[0:1], 3, v[2:3]
; GISEL-NEXT: v_mov_b32_e32 v8, v7
; GISEL-NEXT: v_lshl_or_b32 v10, v4, 29, v1
+; GISEL-NEXT: ; implicit-def: $vgpr2
; GISEL-NEXT: s_branch .LBB2_10
%cvt = sitofp i128 %x to double
ret double %cvt
@@ -937,6 +947,7 @@ define double @uitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_and_or_b32 v0, v3, 1, v0
; SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0
; SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; SDAG-NEXT: ; implicit-def: $vgpr3
; SDAG-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; SDAG-NEXT: v_lshrrev_b64 v[4:5], 2, v[0:1]
; SDAG-NEXT: v_and_b32_e32 v3, 0x800000, v1
@@ -960,8 +971,9 @@ define double @uitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_add_u32_e32 v2, 0xffffffb5, v8
; SDAG-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
-; SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v1, vcc
; SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc
+; SDAG-NEXT: ; implicit-def: $vgpr0
+; SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v1, vcc
; SDAG-NEXT: ; implicit-def: $vgpr6
; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3
; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1
@@ -970,6 +982,7 @@ define double @uitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_lshrrev_b64 v[4:5], 3, v[0:1]
; SDAG-NEXT: v_alignbit_b32 v9, v2, v1, 3
; SDAG-NEXT: v_mov_b32_e32 v7, v6
+; SDAG-NEXT: ; implicit-def: $vgpr0
; SDAG-NEXT: s_branch .LBB3_10
;
; GISEL-LABEL: uitofp_i128_to_f64:
@@ -1084,9 +1097,10 @@ define double @uitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; GISEL-NEXT: v_mov_b32_e32 v9, 0x800000
; GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT: v_lshrrev_b64 v[4:5], 2, v[0:1]
; GISEL-NEXT: v_mov_b32_e32 v8, 0
; GISEL-NEXT: v_and_b32_e32 v9, 0x800000, v1
-; GISEL-NEXT: v_lshrrev_b64 v[4:5], 2, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr5
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GISEL-NEXT: v_lshlrev_b64 v[8:9], 30, v[2:3]
; GISEL-NEXT: v_lshrrev_b32_e32 v5, 2, v1
@@ -1111,13 +1125,15 @@ define double @uitofp_i128_to_f64(i128 %x) {
; GISEL-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
; GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc
+; GISEL-NEXT: ; implicit-def: $vgpr0
; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v1, vcc
; GISEL-NEXT: ; implicit-def: $vgpr6
; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GISEL-NEXT: s_branch .LBB3_2
; GISEL-NEXT: .LBB3_14: ; %itofp-if-then20
-; GISEL-NEXT: v_lshlrev_b64 v[2:3], 29, v[2:3]
; GISEL-NEXT: v_lshrrev_b64 v[4:5], 3, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: v_lshlrev_b64 v[2:3], 29, v[2:3]
; GISEL-NEXT: v_lshrrev_b32_e32 v0, 3, v1
; GISEL-NEXT: v_or_b32_e32 v9, v2, v0
; GISEL-NEXT: v_mov_b32_e32 v7, v6
@@ -1320,44 +1336,46 @@ define half @sitofp_i128_to_f16(i128 %x) {
; GISEL-NEXT: v_or_b32_e32 v12, v10, v12
; GISEL-NEXT: v_lshrrev_b64 v[9:10], v13, v[2:3]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
-; GISEL-NEXT: v_add_u32_e32 v14, 26, v5
+; GISEL-NEXT: v_add_u32_e32 v15, 26, v5
; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
-; GISEL-NEXT: v_sub_u32_e32 v11, 64, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v13, v9, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v10, v1, vcc
-; GISEL-NEXT: v_lshrrev_b64 v[9:10], v14, -1
-; GISEL-NEXT: v_lshlrev_b64 v[11:12], v11, -1
-; GISEL-NEXT: v_add_u32_e32 v5, 0xffffffda, v5
-; GISEL-NEXT: v_or_b32_e32 v15, v9, v11
-; GISEL-NEXT: v_or_b32_e32 v16, v10, v12
-; GISEL-NEXT: v_lshrrev_b64 v[11:12], v5, -1
-; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v15, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v11, v12, v16, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
-; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GISEL-NEXT: v_sub_u32_e32 v4, 64, v15
+; GISEL-NEXT: v_lshrrev_b64 v[11:12], v15, -1
+; GISEL-NEXT: v_lshlrev_b64 v[13:14], v4, -1
+; GISEL-NEXT: v_add_u32_e32 v4, 0xffffffda, v5
+; GISEL-NEXT: v_lshrrev_b64 v[4:5], v4, -1
+; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v1, vcc
+; GISEL-NEXT: v_or_b32_e32 v13, v11, v13
+; GISEL-NEXT: v_or_b32_e32 v14, v12, v14
+; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v13, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
+; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, -1, s[4:5]
-; GISEL-NEXT: v_and_b32_e32 v2, v9, v2
-; GISEL-NEXT: v_and_b32_e32 v3, v10, v3
-; GISEL-NEXT: v_and_or_b32 v0, v5, v0, v2
-; GISEL-NEXT: v_and_or_b32 v1, v11, v1, v3
+; GISEL-NEXT: v_and_b32_e32 v2, v11, v2
+; GISEL-NEXT: v_and_b32_e32 v3, v12, v3
+; GISEL-NEXT: v_and_or_b32 v0, v4, v0, v2
+; GISEL-NEXT: v_and_or_b32 v1, v5, v1, v3
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr11_vgpr12
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_or_b32_e32 v3, v13, v0
-; GISEL-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-NEXT: v_mov_b32_e32 v1, v4
-; GISEL-NEXT: v_mov_b32_e32 v2, v5
-; GISEL-NEXT: v_mov_b32_e32 v3, v6
+; GISEL-NEXT: v_or_b32_e32 v9, v9, v0
+; GISEL-NEXT: v_mov_b32_e32 v0, v9
+; GISEL-NEXT: v_mov_b32_e32 v1, v10
+; GISEL-NEXT: v_mov_b32_e32 v2, v11
+; GISEL-NEXT: v_mov_b32_e32 v3, v12
; GISEL-NEXT: .LBB4_6: ; %Flow1
; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
; GISEL-NEXT: .LBB4_7: ; %Flow2
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; GISEL-NEXT: ; %bb.8: ; %itofp-sw-bb
; GISEL-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
; GISEL-NEXT: ; %bb.9: ; %itofp-sw-epilog
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
; GISEL-NEXT: v_bfe_u32 v2, v0, 2, 1
@@ -1576,44 +1594,46 @@ define half @uitofp_i128_to_f16(i128 %x) {
; GISEL-NEXT: v_or_b32_e32 v11, v9, v11
; GISEL-NEXT: v_lshrrev_b64 v[8:9], v12, v[2:3]
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4
-; GISEL-NEXT: v_add_u32_e32 v13, 26, v5
+; GISEL-NEXT: v_add_u32_e32 v14, 26, v5
; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
-; GISEL-NEXT: v_sub_u32_e32 v10, 64, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v12, v8, v0, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v9, v1, vcc
-; GISEL-NEXT: v_lshrrev_b64 v[8:9], v13, -1
-; GISEL-NEXT: v_lshlrev_b64 v[10:11], v10, -1
-; GISEL-NEXT: v_add_u32_e32 v5, 0xffffffda, v5
-; GISEL-NEXT: v_or_b32_e32 v14, v8, v10
-; GISEL-NEXT: v_or_b32_e32 v15, v9, v11
-; GISEL-NEXT: v_lshrrev_b64 v[10:11], v5, -1
-; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v14, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v15, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
+; GISEL-NEXT: v_sub_u32_e32 v4, 64, v14
+; GISEL-NEXT: v_lshrrev_b64 v[10:11], v14, -1
+; GISEL-NEXT: v_lshlrev_b64 v[12:13], v4, -1
+; GISEL-NEXT: v_add_u32_e32 v4, 0xffffffda, v5
+; GISEL-NEXT: v_lshrrev_b64 v[4:5], v4, -1
+; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc
+; GISEL-NEXT: v_or_b32_e32 v12, v10, v12
+; GISEL-NEXT: v_or_b32_e32 v13, v11, v13
+; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14
+; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, -1, s[4:5]
-; GISEL-NEXT: v_and_b32_e32 v2, v8, v2
-; GISEL-NEXT: v_and_b32_e32 v3, v9, v3
-; GISEL-NEXT: v_and_or_b32 v0, v5, v0, v2
-; GISEL-NEXT: v_and_or_b32 v1, v10, v1, v3
+; GISEL-NEXT: v_and_b32_e32 v2, v10, v2
+; GISEL-NEXT: v_and_b32_e32 v3, v11, v3
+; GISEL-NEXT: v_and_or_b32 v0, v4, v0, v2
+; GISEL-NEXT: v_and_or_b32 v1, v5, v1, v3
; GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr10_vgpr11
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GISEL-NEXT: v_or_b32_e32 v3, v12, v0
-; GISEL-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-NEXT: v_mov_b32_e32 v1, v4
-; GISEL-NEXT: v_mov_b32_e32 v2, v5
-; GISEL-NEXT: v_mov_b32_e32 v3, v6
+; GISEL-NEXT: v_or_b32_e32 v8, v8, v0
+; GISEL-NEXT: v_mov_b32_e32 v0, v8
+; GISEL-NEXT: v_mov_b32_e32 v1, v9
+; GISEL-NEXT: v_mov_b32_e32 v2, v10
+; GISEL-NEXT: v_mov_b32_e32 v3, v11
; GISEL-NEXT: .LBB5_6: ; %Flow1
; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
; GISEL-NEXT: .LBB5_7: ; %Flow2
; GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
; GISEL-NEXT: ; %bb.8: ; %itofp-sw-bb
; GISEL-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
; GISEL-NEXT: ; %bb.9: ; %itofp-sw-epilog
; GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
; GISEL-NEXT: v_bfe_u32 v2, v0, 2, 1
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-args.ll b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
index 6fdc636020df5..b5c93fd22d0f9 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
@@ -4893,6 +4893,7 @@ define amdgpu_kernel void @i1_arg_sext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s6, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: ; implicit-def: $sgpr7
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
@@ -4906,6 +4907,7 @@ define amdgpu_kernel void @i1_arg_sext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-NEXT: ; implicit-def: $sgpr1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x10000
; VI-NEXT: v_mov_b32_e32 v0, s2
@@ -4919,6 +4921,7 @@ define amdgpu_kernel void @i1_arg_sext_i64(ptr addrspace(1) %out, i1 %x) nounwin
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s0, s[8:9], 0x8
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
+; GFX9-NEXT: ; implicit-def: $sgpr1
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x10000
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
index 50e7a3a322e09..ac94d321370db 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
@@ -402,17 +402,18 @@ define amdgpu_kernel void @v3i15_arg(ptr addrspace(1) nocapture %out, <3 x i15>
; GCN-LABEL: v3i15_arg:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
+; GCN-NEXT: ; implicit-def: $sgpr5
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_and_b32 s4, s3, 0xffff
-; GCN-NEXT: s_and_b32 s5, s2, 0x7fff
-; GCN-NEXT: s_lshr_b32 s6, s2, 1
+; GCN-NEXT: s_and_b32 s6, s2, 0x7fff
+; GCN-NEXT: s_lshr_b32 s7, s2, 1
; GCN-NEXT: s_lshl_b64 s[2:3], s[4:5], 30
-; GCN-NEXT: s_and_b32 s4, s6, 0x3fff8000
-; GCN-NEXT: s_and_b32 s6, s3, 0x1fff
-; GCN-NEXT: s_or_b32 s4, s5, s4
+; GCN-NEXT: s_and_b32 s4, s7, 0x3fff8000
+; GCN-NEXT: s_and_b32 s5, s3, 0x1fff
+; GCN-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NEXT: s_or_b32 s4, s6, s4
; GCN-NEXT: s_mov_b32 s5, 0
-; GCN-NEXT: v_mov_b32_e32 v1, s6
; GCN-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
; GCN-NEXT: global_store_short v0, v1, s[0:1] offset:4
; GCN-NEXT: v_mov_b32_e32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
index 7fd5b35783f30..533df59786908 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
@@ -183,17 +183,24 @@ define amdgpu_ps half @bitop3_b16_vvv(i16 %a, i16 %b, i16 %c) {
; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0xf
; GFX950-NEXT: ; return to shader part epilog
;
-; GFX1250-TRUE16-LABEL: bitop3_b16_vvv:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:0xf
-; GFX1250-TRUE16-NEXT: ; return to shader part epilog
+; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_vvv:
+; GFX1250-SDG-TRUE16: ; %bb.0:
+; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:0xf
+; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_vvv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0xf
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_vvv:
+; GFX1250-GISEL-TRUE16: ; %bb.0:
+; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:0xf
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 15)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
@@ -205,17 +212,24 @@ define amdgpu_ps half @bitop3_b16_svv(i16 inreg %a, i16 %b, i16 %c) {
; GFX950-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x10
; GFX950-NEXT: ; return to shader part epilog
;
-; GFX1250-TRUE16-LABEL: bitop3_b16_svv:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, v0.l, v1.l bitop3:0x10
-; GFX1250-TRUE16-NEXT: ; return to shader part epilog
+; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_svv:
+; GFX1250-SDG-TRUE16: ; %bb.0:
+; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, v0.l, v1.l bitop3:0x10
+; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_svv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x10
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_svv:
+; GFX1250-GISEL-TRUE16: ; %bb.0:
+; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, v0.l, v1.l bitop3:0x10
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 16)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
@@ -228,17 +242,24 @@ define amdgpu_ps half @bitop3_b16_ssv(i16 inreg %a, i16 inreg %b, i16 %c) {
; GFX950-NEXT: v_bitop3_b16 v0, s0, v1, v0 bitop3:0x11
; GFX950-NEXT: ; return to shader part epilog
;
-; GFX1250-TRUE16-LABEL: bitop3_b16_ssv:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x11
-; GFX1250-TRUE16-NEXT: ; return to shader part epilog
+; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_ssv:
+; GFX1250-SDG-TRUE16: ; %bb.0:
+; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x11
+; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_ssv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, s1, v0 bitop3:0x11
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_ssv:
+; GFX1250-GISEL-TRUE16: ; %bb.0:
+; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x11
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 17)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
@@ -252,13 +273,13 @@ define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c)
; GFX950-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x12
; GFX950-NEXT: ; return to shader part epilog
;
-; GFX1250-TRUE16-LABEL: bitop3_b16_sss:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
-; GFX1250-TRUE16-NEXT: ; return to shader part epilog
+; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_sss:
+; GFX1250-SDG-TRUE16: ; %bb.0:
+; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
+; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_sss:
; GFX1250-FAKE16: ; %bb.0:
@@ -267,6 +288,15 @@ define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c)
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, s1, v0 bitop3:0x12
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_sss:
+; GFX1250-GISEL-TRUE16: ; %bb.0:
+; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
+; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 18)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
@@ -285,17 +315,24 @@ define amdgpu_ps half @bitop3_b16_vvi(i16 %a, i16 %b) {
; GFX950-GISEL-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0x13
; GFX950-GISEL-NEXT: ; return to shader part epilog
;
-; GFX1250-TRUE16-LABEL: bitop3_b16_vvi:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x13
-; GFX1250-TRUE16-NEXT: ; return to shader part epilog
+; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_vvi:
+; GFX1250-SDG-TRUE16: ; %bb.0:
+; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x13
+; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_vvi:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 0x3e8 bitop3:0x13
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_vvi:
+; GFX1250-GISEL-TRUE16: ; %bb.0:
+; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x13
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 1000, i32 19)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
@@ -338,6 +375,7 @@ define amdgpu_ps half @bitop3_b16_vii(i16 %a) {
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3e8
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, 0x7d0, v0.h bitop3:0x14
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: bitop3_b16_vii:
@@ -395,6 +433,7 @@ define amdgpu_ps half @bitop3_b16_iii() {
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3e8
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, 0xbb8, v0.l, v0.h bitop3:0x15
+; GFX1250-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: bitop3_b16_iii:
@@ -411,3 +450,4 @@ define amdgpu_ps half @bitop3_b16_iii() {
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
+; GFX1250-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
index 2b0d33bcba978..d6f252c6642cf 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
@@ -178,6 +178,7 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte0_s(i32 inreg %a) {
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e32 v0.l, s0
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-REAL16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-GISEL-REAL16-NEXT: s_cvt_f32_f16 s0, s0
@@ -441,6 +442,7 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte0_s(i32 inreg %a) {
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e32 v0.l, s0
+; GFX1250-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3)
; GFX1250-GISEL-REAL16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-GISEL-REAL16-NEXT: s_cvt_f32_f16 s0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
index 8ad4c79233539..76097701f5454 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
@@ -1158,34 +1158,95 @@ define float @test_sext_cvt_f32_fp8(i16 %a) {
; GFX9X-NEXT: v_cvt_f32_fp8_sdwa v0, v0 src0_sel:BYTE_1
; GFX9X-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-LABEL: test_sext_cvt_f32_fp8:
-; GFX1170: ; %bb.0:
-; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
-; GFX1170-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: test_sext_cvt_f32_fp8:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: test_sext_cvt_f32_fp8:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: test_sext_cvt_f32_fp8:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-FAKE16-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: test_sext_cvt_f32_fp8:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1170-GISEL-LABEL: test_sext_cvt_f32_fp8:
+; GFX1170-GISEL: ; %bb.0:
+; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: test_sext_cvt_f32_fp8:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: test_sext_cvt_f32_fp8:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_sext_cvt_f32_fp8:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: test_sext_cvt_f32_fp8:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: test_sext_cvt_f32_fp8:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: test_sext_cvt_f32_fp8:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
%a.sext = sext i16 %a to i32
%ret = tail call float @llvm.amdgcn.cvt.f32.fp8(i32 %a.sext, i32 1)
ret float %ret
@@ -1199,34 +1260,95 @@ define float @test_sext_cvt_f32_bf8(i16 %a) {
; GFX9X-NEXT: v_cvt_f32_bf8_sdwa v0, v0 src0_sel:BYTE_1
; GFX9X-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-LABEL: test_sext_cvt_f32_bf8:
-; GFX1170: ; %bb.0:
-; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
-; GFX1170-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: test_sext_cvt_f32_bf8:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: test_sext_cvt_f32_bf8:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: test_sext_cvt_f32_bf8:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-FAKE16-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: test_sext_cvt_f32_bf8:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1170-GISEL-LABEL: test_sext_cvt_f32_bf8:
+; GFX1170-GISEL: ; %bb.0:
+; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: test_sext_cvt_f32_bf8:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: test_sext_cvt_f32_bf8:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_sext_cvt_f32_bf8:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: test_sext_cvt_f32_bf8:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: test_sext_cvt_f32_bf8:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: test_sext_cvt_f32_bf8:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
%a.sext = sext i16 %a to i32
%ret = tail call float @llvm.amdgcn.cvt.f32.bf8(i32 %a.sext, i32 1)
ret float %ret
@@ -1240,34 +1362,95 @@ define <2 x float> @test_sext_cvt_pk_f32_bf8_word1(i16 %a) {
; GFX9X-NEXT: v_cvt_pk_f32_bf8_sdwa v[0:1], v0 src0_sel:WORD_1
; GFX9X-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-LABEL: test_sext_cvt_pk_f32_bf8_word1:
-; GFX1170: ; %bb.0:
-; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
-; GFX1170-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: test_sext_cvt_pk_f32_bf8_word1:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-FAKE16-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: test_sext_cvt_pk_f32_bf8_word1:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1170-GISEL-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX1170-GISEL: ; %bb.0:
+; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: test_sext_cvt_pk_f32_bf8_word1:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0]
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
%a.sext = sext i16 %a to i32
%ret = tail call <2 x float> @llvm.amdgcn.cvt.pk.f32.bf8(i32 %a.sext, i1 true)
ret <2 x float> %ret
@@ -1281,34 +1464,95 @@ define <2 x float> @test_sext_cvt_pk_f32_fp8_word0(i16 %a) {
; GFX9X-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
; GFX9X-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1170-LABEL: test_sext_cvt_pk_f32_fp8_word0:
-; GFX1170: ; %bb.0:
-; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
-; GFX1170-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-TRUE16-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX1170-TRUE16: ; %bb.0:
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-TRUE16-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: test_sext_cvt_pk_f32_fp8_word0:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX1170-FAKE16-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX1170-FAKE16: ; %bb.0:
+; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-FAKE16-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250-LABEL: test_sext_cvt_pk_f32_fp8_word0:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1170-GISEL-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX1170-GISEL: ; %bb.0:
+; GFX1170-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1170-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1170-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-GISEL-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX1170-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1250-TRUE16-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-FAKE16-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: test_sext_cvt_pk_f32_fp8_word0:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
%a.sext = sext i16 %a to i32
%ret = tail call <2 x float> @llvm.amdgcn.cvt.pk.f32.fp8(i32 %a.sext, i1 false)
ret <2 x float> %ret
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
index d183754c6fe91..bd34de555b383 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
@@ -124,6 +124,7 @@ define half @v_exp2_f16(half %src) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_exp_f16_e32 v0.l, v0.l
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_exp2_f16:
@@ -134,6 +135,7 @@ define half @v_exp2_f16(half %src) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_exp_f16_e32 v0.l, v0.l
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%exp2 = call half @llvm.amdgcn.exp2.f16(half %src)
ret half %exp2
@@ -150,6 +152,7 @@ define half @v_exp2_f16_uniform(half inreg %src) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_exp_f16_e32 v0.l, s0
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_exp2_f16_uniform:
@@ -179,6 +182,7 @@ define half @v_fabs_exp2_f16(half %src) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_exp_f16_e64 v0.l, |v0.l|
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_fabs_exp2_f16:
@@ -189,6 +193,7 @@ define half @v_fabs_exp2_f16(half %src) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_exp_f16_e64 v0.l, |v0.l|
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call half @llvm.fabs.f16(half %src)
%exp2 = call half @llvm.amdgcn.exp2.f16(half %fabs.src)
@@ -206,6 +211,7 @@ define half @v_fneg_fabs_exp2_f16(half %src) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_exp_f16_e64 v0.l, -|v0.l|
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_fneg_fabs_exp2_f16:
@@ -216,6 +222,7 @@ define half @v_fneg_fabs_exp2_f16(half %src) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_exp_f16_e64 v0.l, -|v0.l|
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call half @llvm.fabs.f16(half %src)
%neg.fabs.src = fneg half %fabs.src
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll
index 3712b4782dede..b47bc3c13be5e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.gfx90a.ll
@@ -7,6 +7,7 @@ define amdgpu_ps void @atomic_swap_1d_agpr(<8 x i32> inreg %rsrc, i32 %s) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a0
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_atomic_swap a0, v0, s[0:7] dmask:0x1 unorm glc
; GFX90A-NEXT: s_endpgm
%data = call i32 asm "; def $0", "=a"()
@@ -39,6 +40,7 @@ define amdgpu_ps void @atomic_cmpswap_1d_agpr(<8 x i32> inreg %rsrc, i32 %s) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a1
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_atomic_cmpswap a[0:1], v0, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_endpgm
%cmp = call i32 asm "; def $0", "=a"()
@@ -54,6 +56,7 @@ define amdgpu_ps void @atomic_swap_1d_i64_agpr(<8 x i32> inreg %rsrc, i32 %s) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_atomic_swap a[0:1], v0, s[0:7] dmask:0x3 unorm glc
; GFX90A-NEXT: s_endpgm
%data = call i64 asm "; def $0", "=a"()
@@ -71,6 +74,7 @@ define amdgpu_ps void @atomic_cmpswap_1d_64_agpr(<8 x i32> inreg %rsrc, i32 %s)
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[2:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_atomic_cmpswap a[0:3], v0, s[0:7] dmask:0xf unorm glc
; GFX90A-NEXT: s_endpgm
%cmp = call i64 asm "; def $0", "=a"()
@@ -86,6 +90,7 @@ define amdgpu_ps void @atomic_swap_1d_agpr_noret(<8 x i32> inreg %rsrc, i32 %s)
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a0
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_atomic_swap a0, v0, s[0:7] dmask:0x1 unorm
; GFX90A-NEXT: s_endpgm
%data = call i32 asm "; def $0", "=a"()
@@ -115,6 +120,7 @@ define amdgpu_ps void @atomic_cmpswap_1d_agpr_noret(<8 x i32> inreg %rsrc, i32 %
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a1
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_atomic_cmpswap a[0:1], v0, s[0:7] dmask:0x3 unorm
; GFX90A-NEXT: s_endpgm
%cmp = call i32 asm "; def $0", "=a"()
@@ -129,6 +135,7 @@ define amdgpu_ps void @atomic_swap_1d_i64_agpr_noret(<8 x i32> inreg %rsrc, i32
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[0:1]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_atomic_swap a[0:1], v0, s[0:7] dmask:0x3 unorm
; GFX90A-NEXT: s_endpgm
%data = call i64 asm "; def $0", "=a"()
@@ -145,6 +152,7 @@ define amdgpu_ps void @atomic_cmpswap_1d_64_agpr_noret(<8 x i32> inreg %rsrc, i3
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def a[2:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: image_atomic_cmpswap a[0:3], v0, s[0:7] dmask:0xf unorm
; GFX90A-NEXT: s_endpgm
%cmp = call i64 asm "; def $0", "=a"()
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
index 44a4e8171ff33..51c5df7b2c308 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
@@ -4,35 +4,12 @@
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefixes=GCN %s
define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, i32 %s) {
-; GCN-LABEL: load_1d:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret <4 x float> %v
}
define amdgpu_ps <4 x float> @load_1d_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s) {
-; GCN-LABEL: load_1d_lwe:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v8, 0
-; GCN-NEXT: v_mov_b32_e32 v6, v0
-; GCN-NEXT: v_mov_b32_e32 v9, v8
-; GCN-NEXT: v_mov_b32_e32 v10, v8
-; GCN-NEXT: v_mov_b32_e32 v11, v8
-; GCN-NEXT: v_mov_b32_e32 v12, v8
-; GCN-NEXT: v_mov_b32_e32 v0, v8
-; GCN-NEXT: v_mov_b32_e32 v1, v9
-; GCN-NEXT: v_mov_b32_e32 v2, v10
-; GCN-NEXT: v_mov_b32_e32 v3, v11
-; GCN-NEXT: v_mov_b32_e32 v4, v12
-; GCN-NEXT: image_load v[0:4], v6, s[0:7] dmask:0xf unorm lwe
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: global_store_dword v8, v4, s[8:9]
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 2, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
@@ -179,12 +156,6 @@ main_body:
}
define amdgpu_ps <4 x float> @load_1d_addr_align(<8 x i32> inreg %rsrc, <2 x i32> %s) {
-; GCN-LABEL: load_1d_addr_align:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v0, v1
-; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%s1 = extractelement <2 x i32> %s, i32 1
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s1, <8 x i32> %rsrc, i32 0, i32 0)
@@ -192,10 +163,6 @@ main_body:
}
define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
-; GCN-LABEL: store_1d:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
-; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret void
@@ -272,119 +239,66 @@ main_body:
}
define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, i32 %s) {
-; GCN-LABEL: load_1d_V1:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_load v0, v0, s[0:7] dmask:0x8 unorm
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret float %v
}
define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, i32 %s) {
-; GCN-LABEL: load_1d_V2:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 9, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret <2 x float> %v
}
define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, i32 %s) {
-; GCN-LABEL: store_1d_V1:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v2, v1
-; GCN-NEXT: image_store v0, v2, s[0:7] dmask:0x2 unorm
-; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.f32.i32(float %vdata, i32 2, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret void
}
define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, i32 %s) {
-; GCN-LABEL: store_1d_V2:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc unorm
-; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v2f32.i32(<2 x float> %vdata, i32 12, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret void
}
define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, i32 %s) {
-; GCN-LABEL: load_1d_glc:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1)
ret <4 x float> %v
}
define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, i32 %s) {
-; GCN-LABEL: load_1d_slc:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
ret <4 x float> %v
}
define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, i32 %s) {
-; GCN-LABEL: load_1d_glc_slc:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3)
ret <4 x float> %v
}
define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
-; GCN-LABEL: store_1d_glc:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc
-; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1)
ret void
}
define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
-; GCN-LABEL: store_1d_slc:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc
-; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
ret void
}
define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
-; GCN-LABEL: store_1d_glc_slc:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc
-; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3)
ret void
}
define amdgpu_ps void @image_store_wait(<8 x i32> inreg %arg, <8 x i32> inreg %arg1, <8 x i32> inreg %arg2, <4 x float> %arg3, i32 %arg4) #0 {
-; GCN-LABEL: image_store_wait:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
-; GCN-NEXT: image_load v[0:3], v4, s[8:15] dmask:0xf unorm
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: image_store v[0:3], v4, s[16:23] dmask:0xf unorm
-; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %arg3, i32 15, i32 %arg4, <8 x i32> %arg, i32 0, i32 0)
%data = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %arg4, <8 x i32> %arg1, i32 0, i32 0)
@@ -403,12 +317,6 @@ define amdgpu_ps float @image_load_mmo(<8 x i32> inreg %rsrc, ptr addrspace(3) %
}
define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i32> %s) {
-; GCN-LABEL: getresinfo_1d:
-; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v0, v1
-; GCN-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ; return to shader part epilog
main_body:
%s1 = extractelement <2 x i32> %s, i32 1
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 15, i32 %s1, <8 x i32> %rsrc, i32 0, i32 0)
@@ -416,14 +324,6 @@ main_body:
}
define amdgpu_ps void @load_1d_agpr(<8 x i32> inreg %rsrc, i32 %s) {
-; GCN-LABEL: load_1d_agpr:
-; GCN: ; %bb.0:
-; GCN-NEXT: image_load a[0:3], v0, s[0:7] dmask:0xf unorm
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: ;;#ASMSTART
-; GCN-NEXT: ; use a[0:3]
-; GCN-NEXT: ;;#ASMEND
-; GCN-NEXT: s_endpgm
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
call void asm sideeffect "; use $0", "a"(<4 x float> %v)
ret void
@@ -472,13 +372,6 @@ define amdgpu_ps void @load_cube_agpr(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32
}
define amdgpu_ps void @store_1d_agpr(<8 x i32> inreg %rsrc, i32 %s) {
-; GCN-LABEL: store_1d_agpr:
-; GCN: ; %bb.0:
-; GCN-NEXT: ;;#ASMSTART
-; GCN-NEXT: ; def a[0:3]
-; GCN-NEXT: ;;#ASMEND
-; GCN-NEXT: image_store a[0:3], v0, s[0:7] dmask:0xf unorm
-; GCN-NEXT: s_endpgm
%vdata = call <4 x float> asm "; def $0", "=a"()
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
index 2b63fe1f79951..97028e1c0866f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
@@ -104,6 +104,7 @@ define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_gather4 v[0:3], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -124,6 +125,7 @@ define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -172,6 +174,7 @@ define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_gather4 v[0:3], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -192,6 +195,7 @@ define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -306,6 +310,7 @@ define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_gather4_cl v[0:3], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -326,6 +331,7 @@ define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -374,6 +380,7 @@ define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -394,6 +401,7 @@ define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -440,6 +448,7 @@ define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -460,6 +469,7 @@ define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -506,6 +516,7 @@ define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -526,6 +537,7 @@ define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -577,6 +589,8 @@ define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: image_gather4_b_cl v[0:3], v[2:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -597,6 +611,8 @@ define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -646,6 +662,8 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -666,6 +684,8 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX12PLUS-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
; GFX12PLUS-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -705,6 +725,7 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_gather4_l v[0:3], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -719,6 +740,7 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX12PLUS-TRUE16-LABEL: gather4_l_2d:
; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -755,6 +777,7 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX11-TRUE16-LABEL: gather4_c_l_2d:
; GFX11-TRUE16: ; %bb.0: ; %main_body
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -769,6 +792,7 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX12PLUS-TRUE16-LABEL: gather4_c_l_2d:
; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12PLUS-TRUE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -902,5 +926,3 @@ declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32, float, hal
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
attributes #2 = { nounwind readnone }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
index 0a6c56e9c8040..85542aed1253c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
@@ -307,6 +307,7 @@ define amdgpu_ps <4 x float> @load_2dmsaa_a16(<8 x i32> inreg %rsrc, i16 %s, i16
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -321,6 +322,7 @@ define amdgpu_ps <4 x float> @load_2dmsaa_a16(<8 x i32> inreg %rsrc, i16 %s, i16
; GFX12PLUS-TRUE16-LABEL: load_2dmsaa_a16:
; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12PLUS-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
index 270e150ee082a..04fc1e0ffb0e5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
@@ -14,14 +14,24 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: sample_d_1d:
-; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08]
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: sample_d_1d:
; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x00]
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-TRUE16-NEXT: ; return to shader part epilog
@@ -34,6 +44,8 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
;
; GFX13-TRUE16-LABEL: sample_d_1d:
; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX13-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x00]
; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX13-TRUE16-NEXT: ; return to shader part epilog
@@ -124,6 +136,8 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-TRUE16: ; %bb.0: ; %main_body
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x09,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08,0x02,0x03,0x05,0x06]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -140,6 +154,7 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-TRUE16: ; %bb.0: ; %main_body
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x03,0x05]
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-TRUE16-NEXT: ; return to shader part epilog
@@ -156,6 +171,7 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX13-TRUE16: ; %bb.0: ; %main_body
; GFX13-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
; GFX13-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX13-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x03,0x05]
; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX13-TRUE16-NEXT: ; return to shader part epilog
@@ -179,14 +195,24 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: sample_c_d_1d:
-; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xe8,0xf0,0x00,0x00,0x00,0x08]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xe8,0xf0,0x00,0x00,0x00,0x08]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xe8,0xf0,0x00,0x00,0x00,0x08]
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: sample_c_d_1d:
; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-TRUE16-NEXT: ; return to shader part epilog
@@ -199,6 +225,8 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
;
; GFX13-TRUE16-LABEL: sample_c_d_1d:
; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX13-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX13-TRUE16-NEXT: ; return to shader part epilog
@@ -281,14 +309,24 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: sample_d_cl_1d:
-; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0x7c,0xf1,0x00,0x00,0x00,0x08]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_cl_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0x7c,0xf1,0x00,0x00,0x00,0x08]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_cl_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0x7c,0xf1,0x00,0x00,0x00,0x08]
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: sample_d_cl_1d:
; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xd7,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-TRUE16-NEXT: ; return to shader part epilog
@@ -301,6 +339,8 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
;
; GFX13-TRUE16-LABEL: sample_d_cl_1d:
; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX13-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xe8,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX13-TRUE16-NEXT: ; return to shader part epilog
@@ -383,14 +423,24 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: sample_c_d_cl_1d:
-; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0x50,0xf1,0x00,0x00,0x00,0x08]
-; GFX11-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0x50,0xf1,0x00,0x00,0x00,0x08]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0x50,0xf1,0x00,0x00,0x00,0x08]
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: sample_c_d_cl_1d:
; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0xd5,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-TRUE16-NEXT: ; return to shader part epilog
@@ -403,6 +453,8 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
;
; GFX13-TRUE16-LABEL: sample_c_d_cl_1d:
; GFX13-TRUE16: ; %bb.0: ; %main_body
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX13-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX13-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xea,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x03]
; GFX13-TRUE16-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX13-TRUE16-NEXT: ; return to shader part epilog
@@ -638,3 +690,5 @@ declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
attributes #2 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
index 33d641247bc82..8331a998c0342 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
@@ -14,17 +14,33 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: sample_d_1d:
-; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12PLUS-LABEL: sample_d_1d:
-; GFX12PLUS: ; %bb.0: ; %main_body
-; GFX12PLUS-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
-; GFX12PLUS-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: image_sample_d_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-TRUE16-LABEL: sample_d_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -90,6 +106,8 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-TRUE16: ; %bb.0: ; %main_body
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -106,6 +124,7 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l
; GFX12PLUS-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12PLUS-TRUE16-NEXT: image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
@@ -129,17 +148,33 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: sample_c_d_1d:
-; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12PLUS-LABEL: sample_c_d_1d:
-; GFX12PLUS: ; %bb.0: ; %main_body
-; GFX12PLUS-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
-; GFX12PLUS-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -197,17 +232,33 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: sample_d_cl_1d:
-; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12PLUS-LABEL: sample_d_cl_1d:
-; GFX12PLUS: ; %bb.0: ; %main_body
-; GFX12PLUS-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
-; GFX12PLUS-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_cl_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_cl_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-TRUE16-LABEL: sample_d_cl_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12PLUS-TRUE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_d_cl_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: image_sample_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -265,17 +316,33 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX11-LABEL: sample_c_d_cl_1d:
-; GFX11: ; %bb.0: ; %main_body
-; GFX11-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: ; return to shader part epilog
-;
-; GFX12PLUS-LABEL: sample_c_d_cl_1d:
-; GFX12PLUS: ; %bb.0: ; %main_body
-; GFX12PLUS-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
-; GFX12PLUS-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX12PLUS-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12PLUS-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12PLUS-TRUE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12PLUS-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX12PLUS-FAKE16: ; %bb.0: ; %main_body
+; GFX12PLUS-FAKE16-NEXT: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
+; GFX12PLUS-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12PLUS-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
@@ -446,3 +513,6 @@ declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32, i
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
attributes #2 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX12PLUS: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
index 0a580d2232502..eccd932a7c9da 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
@@ -437,11 +437,6 @@ main_body:
}
define amdgpu_ps void @sample_d_1d_g16_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
-; GFX10_11-SDAG-LABEL: sample_d_1d_g16_nortn:
-; GFX10_11-SDAG: ; %bb.0: ; %main_body
-; GFX10_11-SDAG-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX10_11-SDAG-NEXT: s_endpgm
-;
; GFX10_11-GISEL-LABEL: sample_d_1d_g16_nortn:
; GFX10_11-GISEL: ; %bb.0: ; %main_body
; GFX10_11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -451,13 +446,10 @@ define amdgpu_ps void @sample_d_1d_g16_nortn(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10_11-GISEL-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX10_11-GISEL-NEXT: s_endpgm
;
-; GFX12PLUS-SDAG-LABEL: sample_d_1d_g16_nortn:
-; GFX12PLUS-SDAG: ; %bb.0: ; %main_body
-; GFX12PLUS-SDAG-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
-; GFX12PLUS-SDAG-NEXT: s_endpgm
-;
; GFX12PLUS-GISEL-TRUE16-LABEL: sample_d_1d_g16_nortn:
; GFX12PLUS-GISEL-TRUE16: ; %bb.0: ; %main_body
+; GFX12PLUS-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12PLUS-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12PLUS-GISEL-TRUE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX12PLUS-GISEL-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
index 054203e2de475..b534a383c0914 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
@@ -196,23 +196,42 @@ main_body:
}
define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
-; GFX11-TRUE16-LABEL: v_interp_f16:
-; GFX11-TRUE16: ; %bb.0: ; %main_body
-; GFX11-TRUE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX11-TRUE16-NEXT: s_mov_b32 m0, s2
-; GFX11-TRUE16-NEXT: lds_param_load v1, attr0.x wait_vdst:15
-; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
-; GFX11-TRUE16-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
-; GFX11-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
-; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-SDAG-LABEL: v_interp_f16:
+; GFX11-TRUE16-SDAG: ; %bb.0: ; %main_body
+; GFX11-TRUE16-SDAG-NEXT: s_mov_b32 s3, exec_lo
+; GFX11-TRUE16-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX11-TRUE16-SDAG-NEXT: lds_param_load v1, attr0.x wait_vdst:15
+; GFX11-TRUE16-SDAG-NEXT: s_mov_b32 exec_lo, s3
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v2, s1
+; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX11-TRUE16-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-GISEL-LABEL: v_interp_f16:
+; GFX11-TRUE16-GISEL: ; %bb.0: ; %main_body
+; GFX11-TRUE16-GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX11-TRUE16-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX11-TRUE16-GISEL-NEXT: lds_param_load v1, attr0.x wait_vdst:15
+; GFX11-TRUE16-GISEL-NEXT: s_mov_b32 exec_lo, s3
+; GFX11-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-GISEL-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX11-TRUE16-GISEL-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX11-TRUE16-GISEL-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-GISEL-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX11-TRUE16-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: v_interp_f16:
; GFX11-FAKE16: ; %bb.0: ; %main_body
@@ -232,23 +251,42 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: v_interp_f16:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: s_mov_b32 m0, s2
-; GFX12-TRUE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
-; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
-; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
-; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
-; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
+; GFX12-TRUE16-SDAG-LABEL: v_interp_f16:
+; GFX12-TRUE16-SDAG: ; %bb.0: ; %main_body
+; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s3, exec_lo
+; GFX12-TRUE16-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX12-TRUE16-SDAG-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
+; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 exec_lo, s3
+; GFX12-TRUE16-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-TRUE16-SDAG-NEXT: v_mov_b32_e32 v2, s1
+; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX12-TRUE16-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-GISEL-LABEL: v_interp_f16:
+; GFX12-TRUE16-GISEL: ; %bb.0: ; %main_body
+; GFX12-TRUE16-GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX12-TRUE16-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX12-TRUE16-GISEL-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
+; GFX12-TRUE16-GISEL-NEXT: s_mov_b32 exec_lo, s3
+; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX12-TRUE16-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: v_interp_f16:
; GFX12-FAKE16: ; %bb.0: ; %main_body
@@ -278,23 +316,42 @@ main_body:
}
define amdgpu_ps half @v_interp_rtz_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
-; GFX11-TRUE16-LABEL: v_interp_rtz_f16:
-; GFX11-TRUE16: ; %bb.0: ; %main_body
-; GFX11-TRUE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX11-TRUE16-NEXT: s_mov_b32 m0, s2
-; GFX11-TRUE16-NEXT: lds_param_load v1, attr0.x wait_vdst:15
-; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
-; GFX11-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
-; GFX11-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
-; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-SDAG-LABEL: v_interp_rtz_f16:
+; GFX11-TRUE16-SDAG: ; %bb.0: ; %main_body
+; GFX11-TRUE16-SDAG-NEXT: s_mov_b32 s3, exec_lo
+; GFX11-TRUE16-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX11-TRUE16-SDAG-NEXT: lds_param_load v1, attr0.x wait_vdst:15
+; GFX11-TRUE16-SDAG-NEXT: s_mov_b32 exec_lo, s3
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v2, s1
+; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-SDAG-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX11-TRUE16-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-GISEL-LABEL: v_interp_rtz_f16:
+; GFX11-TRUE16-GISEL: ; %bb.0: ; %main_body
+; GFX11-TRUE16-GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX11-TRUE16-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX11-TRUE16-GISEL-NEXT: lds_param_load v1, attr0.x wait_vdst:15
+; GFX11-TRUE16-GISEL-NEXT: s_mov_b32 exec_lo, s3
+; GFX11-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-GISEL-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX11-TRUE16-GISEL-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX11-TRUE16-GISEL-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-GISEL-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX11-TRUE16-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: v_interp_rtz_f16:
; GFX11-FAKE16: ; %bb.0: ; %main_body
@@ -314,23 +371,42 @@ define amdgpu_ps half @v_interp_rtz_f16(float inreg %i, float inreg %j, i32 inre
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v3, v0
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: v_interp_rtz_f16:
-; GFX12-TRUE16: ; %bb.0: ; %main_body
-; GFX12-TRUE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo
-; GFX12-TRUE16-NEXT: s_mov_b32 m0, s2
-; GFX12-TRUE16-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
-; GFX12-TRUE16-NEXT: s_mov_b32 exec_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
-; GFX12-TRUE16-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
-; GFX12-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
-; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
+; GFX12-TRUE16-SDAG-LABEL: v_interp_rtz_f16:
+; GFX12-TRUE16-SDAG: ; %bb.0: ; %main_body
+; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s3, exec_lo
+; GFX12-TRUE16-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX12-TRUE16-SDAG-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
+; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 exec_lo, s3
+; GFX12-TRUE16-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-TRUE16-SDAG-NEXT: v_mov_b32_e32 v2, s1
+; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX12-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-SDAG-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX12-TRUE16-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-GISEL-LABEL: v_interp_rtz_f16:
+; GFX12-TRUE16-GISEL: ; %bb.0: ; %main_body
+; GFX12-TRUE16-GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX12-TRUE16-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX12-TRUE16-GISEL-NEXT: ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
+; GFX12-TRUE16-GISEL-NEXT: s_mov_b32 exec_lo, s3
+; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX12-TRUE16-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: v_interp_rtz_f16:
; GFX12-FAKE16: ; %bb.0: ; %main_body
@@ -385,6 +461,7 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
; GFX11-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-GISEL-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX11-TRUE16-GISEL-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-GISEL-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: v_interp_f16_imm_params:
@@ -418,6 +495,7 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
; GFX12-TRUE16-GISEL-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX12-TRUE16-GISEL-NEXT: v_mov_b16_e32 v0.l, 0
; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX12-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-GISEL-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
; GFX12-TRUE16-GISEL-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v2, v3 wait_exp:7
@@ -481,3 +559,6 @@ declare void @llvm.amdgcn.exp.f16(i32, i32, float, float, float, float, i1, i1)
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-TRUE16: {{.*}}
+; GFX12-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
index 09dd07d07ed70..f60cc8647ba8f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
@@ -253,6 +253,7 @@ define amdgpu_cs void @phi_uniform(i64 inreg %s0_1, i64 inreg %s2, ptr addrspace
; GISEL_W32-NEXT: s_cbranch_scc1 .LBB5_2
; GISEL_W32-NEXT: ; %bb.1: ; %if
; GISEL_W32-NEXT: s_add_u32 s0, s0, 1
+; GISEL_W32-NEXT: ; implicit-def: $sgpr1
; GISEL_W32-NEXT: .LBB5_2: ; %endif
; GISEL_W32-NEXT: v_mov_b32_e32 v3, 0
; GISEL_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
@@ -265,6 +266,7 @@ define amdgpu_cs void @phi_uniform(i64 inreg %s0_1, i64 inreg %s2, ptr addrspace
; SDAG_W32-NEXT: s_cbranch_scc1 .LBB5_2
; SDAG_W32-NEXT: ; %bb.1: ; %if
; SDAG_W32-NEXT: s_add_u32 s0, s0, 1
+; SDAG_W32-NEXT: ; implicit-def: $sgpr1
; SDAG_W32-NEXT: .LBB5_2: ; %endif
; SDAG_W32-NEXT: s_mov_b32 s1, 0
; SDAG_W32-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll
index 6ff2231854044..40cfc1a4485a1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll
@@ -460,16 +460,28 @@ define double @v_permlane_bcast_f64_vvv(double %src0) {
;}
define void @v_permlane_bcast_i16(ptr addrspace(1) %out, i16 %src, i32 %src1, i32 %src2) {
-; GFX1250-LABEL: v_permlane_bcast_i16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s0, v3
-; GFX1250-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_permlane_bcast_b32 v2, v2, s0, s1
-; GFX1250-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-SDAG-LABEL: v_permlane_bcast_i16:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1250-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_permlane_bcast_b32 v2, v2, s0, s1
+; GFX1250-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: v_permlane_bcast_i16:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_permlane_bcast_b32 v2, v2, s0, s1
+; GFX1250-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
;
; GFX13-LABEL: v_permlane_bcast_i16:
; GFX13: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll
index 909b1247ef8e3..400d15186d906 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll
@@ -460,16 +460,28 @@ define double @v_permlane_down_f64_vvv(double %src0) {
;}
define void @v_permlane_down_i16(ptr addrspace(1) %out, i16 %src, i32 %src1, i32 %src2) {
-; GFX1250-LABEL: v_permlane_down_i16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s0, v3
-; GFX1250-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_permlane_down_b32 v2, v2, s0, s1
-; GFX1250-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-SDAG-LABEL: v_permlane_down_i16:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1250-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_permlane_down_b32 v2, v2, s0, s1
+; GFX1250-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: v_permlane_down_i16:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_permlane_down_b32 v2, v2, s0, s1
+; GFX1250-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
;
; GFX13-LABEL: v_permlane_down_i16:
; GFX13: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
index 1e6b33bd45a04..70db7bbc2f2c0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
@@ -11302,30 +11302,57 @@ define void @v_permlane16_half(ptr addrspace(1) %out, half %src0, i32 %src1, i32
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_permlane16_half:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v3
-; GFX11-NEXT: v_readfirstlane_b32 s1, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_permlane16_b32 v2, v2, s0, s1
-; GFX11-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-SDAG-LABEL: v_permlane16_half:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
+; GFX11-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_permlane16_half:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v3
-; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
-; GFX12-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: v_permlane16_half:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
+; GFX11-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-LABEL: v_permlane16_half:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
+; GFX12-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_permlane16_half:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
+; GFX12-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX13-LABEL: v_permlane16_half:
; GFX13: ; %bb.0:
@@ -11355,30 +11382,57 @@ define void @v_permlanex16_half(ptr addrspace(1) %out, half %src0, i32 %src1, i3
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_permlanex16_half:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v3
-; GFX11-NEXT: v_readfirstlane_b32 s1, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_permlanex16_b32 v2, v2, s0, s1
-; GFX11-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-SDAG-LABEL: v_permlanex16_half:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
+; GFX11-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_permlanex16_half:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v3
-; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
-; GFX12-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: v_permlanex16_half:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
+; GFX11-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-LABEL: v_permlanex16_half:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
+; GFX12-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_permlanex16_half:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
+; GFX12-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX13-LABEL: v_permlanex16_half:
; GFX13: ; %bb.0:
@@ -11413,6 +11467,7 @@ define void @v_permlane16_bfloat(ptr addrspace(1) %out, bfloat %src0, i32 %src1,
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
@@ -11427,6 +11482,7 @@ define void @v_permlane16_bfloat(ptr addrspace(1) %out, bfloat %src0, i32 %src1,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
@@ -11466,6 +11522,7 @@ define void @v_permlanex16_bfloat(ptr addrspace(1) %out, bfloat %src0, i32 %src1
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
@@ -11480,6 +11537,7 @@ define void @v_permlanex16_bfloat(ptr addrspace(1) %out, bfloat %src0, i32 %src1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
@@ -11514,30 +11572,57 @@ define void @v_permlane16_i16(ptr addrspace(1) %out, i16 %src0, i32 %src1, i32 %
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_permlane16_i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v3
-; GFX11-NEXT: v_readfirstlane_b32 s1, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_permlane16_b32 v2, v2, s0, s1
-; GFX11-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-SDAG-LABEL: v_permlane16_i16:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
+; GFX11-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_permlane16_i16:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v3
-; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
-; GFX12-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: v_permlane16_i16:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
+; GFX11-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-LABEL: v_permlane16_i16:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
+; GFX12-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_permlane16_i16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
+; GFX12-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX13-LABEL: v_permlane16_i16:
; GFX13: ; %bb.0:
@@ -11567,30 +11652,57 @@ define void @v_permlanex16_i16(ptr addrspace(1) %out, i16 %src0, i32 %src1, i32
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_permlanex16_i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v3
-; GFX11-NEXT: v_readfirstlane_b32 s1, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_permlanex16_b32 v2, v2, s0, s1
-; GFX11-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-SDAG-LABEL: v_permlanex16_i16:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
+; GFX11-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_permlanex16_i16:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v3
-; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
-; GFX12-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: v_permlanex16_i16:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
+; GFX11-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-LABEL: v_permlanex16_i16:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
+; GFX12-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_permlanex16_i16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
+; GFX12-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX13-LABEL: v_permlanex16_i16:
; GFX13: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll
index 4bfa627783112..9ddabeaf6d31b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll
@@ -460,16 +460,28 @@ define double @v_permlane_up_f64_vvv(double %src0) {
;}
define void @v_permlane_up_i16(ptr addrspace(1) %out, i16 %src, i32 %src1, i32 %src2) {
-; GFX1250-LABEL: v_permlane_up_i16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s0, v3
-; GFX1250-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_permlane_up_b32 v2, v2, s0, s1
-; GFX1250-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-SDAG-LABEL: v_permlane_up_i16:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1250-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_permlane_up_b32 v2, v2, s0, s1
+; GFX1250-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: v_permlane_up_i16:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_permlane_up_b32 v2, v2, s0, s1
+; GFX1250-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
;
; GFX13-LABEL: v_permlane_up_i16:
; GFX13: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll
index 5f97b8921f00c..a802c5b1aa3f1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll
@@ -460,16 +460,28 @@ define double @v_permlane_xor_f64_vvv(double %src0) {
;}
define void @v_permlane_xor_i16(ptr addrspace(1) %out, i16 %src, i32 %src1, i32 %src2) {
-; GFX1250-LABEL: v_permlane_xor_i16:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s0, v3
-; GFX1250-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_permlane_xor_b32 v2, v2, s0, s1
-; GFX1250-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-SDAG-LABEL: v_permlane_xor_i16:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1250-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_permlane_xor_b32 v2, v2, s0, s1
+; GFX1250-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-LABEL: v_permlane_xor_i16:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_permlane_xor_b32 v2, v2, s0, s1
+; GFX1250-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
;
; GFX13-LABEL: v_permlane_xor_i16:
; GFX13: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
index 8d35c7d2b59db..9c77cce15669d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
@@ -286,6 +286,7 @@ define amdgpu_kernel void @test_v_f64(ptr addrspace(1) %out, double %src0) #1 {
define void @test_half(ptr addrspace(1) %out, half %src0) {
; GFX11-SDAG-LABEL: test_half:
; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_permlane64_b32 v2, v2
; GFX11-SDAG-NEXT: global_store_b16 v[0:1], v2, off
@@ -305,6 +306,7 @@ define void @test_half(ptr addrspace(1) %out, half %src0) {
define void @test_bfloat(ptr addrspace(1) %out, bfloat %src0) {
; GFX11-SDAG-LABEL: test_bfloat:
; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_permlane64_b32 v2, v2
; GFX11-SDAG-NEXT: global_store_b16 v[0:1], v2, off
@@ -312,6 +314,7 @@ define void @test_bfloat(ptr addrspace(1) %out, bfloat %src0) {
;
; GFX11-GISEL-LABEL: test_bfloat:
; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: v_permlane64_b32 v2, v2
; GFX11-GISEL-NEXT: global_store_b16 v[0:1], v2, off
@@ -324,6 +327,7 @@ define void @test_bfloat(ptr addrspace(1) %out, bfloat %src0) {
define void @test_i16(ptr addrspace(1) %out, i16 %src0) {
; GFX11-SDAG-LABEL: test_i16:
; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_permlane64_b32 v2, v2
; GFX11-SDAG-NEXT: global_store_b16 v[0:1], v2, off
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
index 83d1e070b10e6..c6841de350db4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
@@ -29,12 +29,14 @@ define amdgpu_ps void @buffer_store_bf16(ptr addrspace(8) inreg %rsrc, bfloat %d
;
; GFX11-LABEL: buffer_store_bf16:
; GFX11: ; %bb.0:
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: buffer_store_b16 v0, v1, s[0:3], 0 offen
; GFX11-NEXT: s_endpgm
;
; GFX12-LABEL: buffer_store_bf16:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: buffer_store_b16 v0, v1, s[0:3], null offen
; GFX12-NEXT: s_endpgm
call void @llvm.amdgcn.raw.ptr.buffer.store.bf16(bfloat %data, ptr addrspace(8) %rsrc, i32 %offset, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
index 38f7ea12251ee..351c99ce5a730 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
@@ -69,6 +69,7 @@ define amdgpu_kernel void @rcp_f16(
; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
index dbf885a1072b8..c21e9fd02a2b6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
@@ -398,24 +398,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1164DAGISEL-LABEL: divergent_value_i16:
-; GFX1164DAGISEL: ; %bb.0: ; %entry
-; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1164DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0
-; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
-; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3
-; GFX1164DAGISEL-NEXT: s_add_i32 s2, s2, s4
-; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1164DAGISEL-NEXT: ; %bb.2:
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16:
+; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_add_i32 s2, s2, s4
+; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1164GISEL-LABEL: divergent_value_i16:
; GFX1164GISEL: ; %bb.0: ; %entry
@@ -436,24 +436,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off
; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1132DAGISEL-LABEL: divergent_value_i16:
-; GFX1132DAGISEL: ; %bb.0: ; %entry
-; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
-; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
-; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2
-; GFX1132DAGISEL-NEXT: s_add_i32 s0, s0, s3
-; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1132DAGISEL-NEXT: ; %bb.2:
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16:
+; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1
+; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2
+; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2
+; GFX1132DAGISEL-FAKE16-NEXT: s_add_i32 s0, s0, s3
+; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1132GISEL-LABEL: divergent_value_i16:
; GFX1132GISEL: ; %bb.0: ; %entry
@@ -473,6 +473,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16:
+; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-TRUE16-NEXT: s_add_i32 s2, s2, s4
+; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16:
+; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1
+; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2
+; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2
+; GFX1132DAGISEL-TRUE16-NEXT: s_add_i32 s0, s0, s3
+; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2:
+; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX12DAGISEL-LABEL: divergent_value_i16:
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4548,8 +4588,3 @@ entry:
}
attributes #0 = { nounwind }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1132DAGISEL-FAKE16: {{.*}}
-; GFX1132DAGISEL-TRUE16: {{.*}}
-; GFX1164DAGISEL-FAKE16: {{.*}}
-; GFX1164DAGISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
index ce7f8bac0da5f..e1ffec421da6e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
@@ -318,24 +318,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1164DAGISEL-LABEL: divergent_value_i16:
-; GFX1164DAGISEL: ; %bb.0: ; %entry
-; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1164DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164DAGISEL-NEXT: s_brev_b32 s2, 1
-; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
-; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3
-; GFX1164DAGISEL-NEXT: s_max_i32 s2, s2, s4
-; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1164DAGISEL-NEXT: ; %bb.2:
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16:
+; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-FAKE16-NEXT: s_brev_b32 s2, 1
+; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_max_i32 s2, s2, s4
+; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1164GISEL-LABEL: divergent_value_i16:
; GFX1164GISEL: ; %bb.0: ; %entry
@@ -356,24 +356,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off
; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1132DAGISEL-LABEL: divergent_value_i16:
-; GFX1132DAGISEL: ; %bb.0: ; %entry
-; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132DAGISEL-NEXT: s_brev_b32 s0, 1
-; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
-; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2
-; GFX1132DAGISEL-NEXT: s_max_i32 s0, s0, s3
-; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1132DAGISEL-NEXT: ; %bb.2:
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16:
+; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132DAGISEL-FAKE16-NEXT: s_brev_b32 s0, 1
+; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1
+; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2
+; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2
+; GFX1132DAGISEL-FAKE16-NEXT: s_max_i32 s0, s0, s3
+; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1132GISEL-LABEL: divergent_value_i16:
; GFX1132GISEL: ; %bb.0: ; %entry
@@ -393,6 +393,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16:
+; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1164DAGISEL-TRUE16-NEXT: s_brev_b32 s2, 1
+; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-TRUE16-NEXT: s_max_i32 s2, s2, s4
+; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16:
+; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1132DAGISEL-TRUE16-NEXT: s_brev_b32 s0, 1
+; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1
+; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2
+; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2
+; GFX1132DAGISEL-TRUE16-NEXT: s_max_i32 s0, s0, s3
+; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2:
+; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.max.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -3723,8 +3763,3 @@ endif:
}
attributes #0 = { nounwind }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1132DAGISEL-FAKE16: {{.*}}
-; GFX1132DAGISEL-TRUE16: {{.*}}
-; GFX1164DAGISEL-FAKE16: {{.*}}
-; GFX1164DAGISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
index b23b3096ca9f2..aa239181dd3ca 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
@@ -318,24 +318,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1164DAGISEL-LABEL: divergent_value_i16:
-; GFX1164DAGISEL: ; %bb.0: ; %entry
-; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1164DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164DAGISEL-NEXT: s_brev_b32 s2, -2
-; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
-; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3
-; GFX1164DAGISEL-NEXT: s_min_i32 s2, s2, s4
-; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1164DAGISEL-NEXT: ; %bb.2:
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16:
+; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-FAKE16-NEXT: s_brev_b32 s2, -2
+; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_min_i32 s2, s2, s4
+; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1164GISEL-LABEL: divergent_value_i16:
; GFX1164GISEL: ; %bb.0: ; %entry
@@ -356,24 +356,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off
; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1132DAGISEL-LABEL: divergent_value_i16:
-; GFX1132DAGISEL: ; %bb.0: ; %entry
-; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132DAGISEL-NEXT: s_brev_b32 s0, -2
-; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
-; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2
-; GFX1132DAGISEL-NEXT: s_min_i32 s0, s0, s3
-; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1132DAGISEL-NEXT: ; %bb.2:
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16:
+; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132DAGISEL-FAKE16-NEXT: s_brev_b32 s0, -2
+; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1
+; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2
+; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2
+; GFX1132DAGISEL-FAKE16-NEXT: s_min_i32 s0, s0, s3
+; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1132GISEL-LABEL: divergent_value_i16:
; GFX1132GISEL: ; %bb.0: ; %entry
@@ -393,6 +393,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16:
+; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1164DAGISEL-TRUE16-NEXT: s_brev_b32 s2, -2
+; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-TRUE16-NEXT: s_min_i32 s2, s2, s4
+; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16:
+; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1132DAGISEL-TRUE16-NEXT: s_brev_b32 s0, -2
+; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1
+; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2
+; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2
+; GFX1132DAGISEL-TRUE16-NEXT: s_min_i32 s0, s0, s3
+; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2:
+; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.min.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -3723,8 +3763,3 @@ endif:
}
attributes #0 = { nounwind }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1132DAGISEL-FAKE16: {{.*}}
-; GFX1132DAGISEL-TRUE16: {{.*}}
-; GFX1164DAGISEL-FAKE16: {{.*}}
-; GFX1164DAGISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
index bc4eab0eaa107..04fcdf27a87f2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
@@ -418,24 +418,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1164DAGISEL-LABEL: divergent_value_i16:
-; GFX1164DAGISEL: ; %bb.0: ; %entry
-; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1164DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0
-; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
-; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3
-; GFX1164DAGISEL-NEXT: s_sub_i32 s2, s2, s4
-; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1164DAGISEL-NEXT: ; %bb.2:
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16:
+; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_sub_i32 s2, s2, s4
+; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1164GISEL-LABEL: divergent_value_i16:
; GFX1164GISEL: ; %bb.0: ; %entry
@@ -456,24 +456,24 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off
; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1132DAGISEL-LABEL: divergent_value_i16:
-; GFX1132DAGISEL: ; %bb.0: ; %entry
-; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
-; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
-; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2
-; GFX1132DAGISEL-NEXT: s_sub_i32 s0, s0, s3
-; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1132DAGISEL-NEXT: ; %bb.2:
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16:
+; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1
+; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2
+; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2
+; GFX1132DAGISEL-FAKE16-NEXT: s_sub_i32 s0, s0, s3
+; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1132GISEL-LABEL: divergent_value_i16:
; GFX1132GISEL: ; %bb.0: ; %entry
@@ -493,6 +493,46 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16:
+; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-TRUE16-NEXT: s_sub_i32 s2, s2, s4
+; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16:
+; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132DAGISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s1
+; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2
+; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s1, s2
+; GFX1132DAGISEL-TRUE16-NEXT: s_sub_i32 s0, s0, s3
+; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2:
+; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX12DAGISEL-LABEL: divergent_value_i16:
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4676,8 +4716,3 @@ endif:
}
attributes #0 = { nounwind }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1132DAGISEL-FAKE16: {{.*}}
-; GFX1132DAGISEL-TRUE16: {{.*}}
-; GFX1164DAGISEL-FAKE16: {{.*}}
-; GFX1164DAGISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
index d0f767c4ea923..2a65218e9c25a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
@@ -74,6 +74,7 @@ define amdgpu_kernel void @rsq_f16(
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
+; SDAG-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
index aa994558162db..91fbab8d68d7a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
@@ -29,6 +29,7 @@ define half @v_sqrt_f16(half %src) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_sqrt_f16:
@@ -63,6 +64,7 @@ define half @v_fabs_sqrt_f16(half %src) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_sqrt_f16_e64 v0.l, |v0.l|
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_fabs_sqrt_f16:
@@ -98,6 +100,7 @@ define half @v_fneg_fabs_sqrt_f16(half %src) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_sqrt_f16_e64 v0.l, -|v0.l|
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_fneg_fabs_sqrt_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
index 573f4645c50e4..21adf569329a5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
@@ -313,6 +313,7 @@ define amdgpu_ps void @struct_buffer_store_f16(<4 x i32> inreg %rsrc, float %v1,
; GFX11-TRUE16-LABEL: struct_buffer_store_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, v1, s[0:3], 0 idxen
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -327,6 +328,7 @@ define amdgpu_ps void @struct_buffer_store_f16(<4 x i32> inreg %rsrc, float %v1,
; GFX12-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, v1, s[0:3], null idxen
; GFX12-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
index f0031dd3e93c0..d8cf2e346f54a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
@@ -89,6 +89,7 @@ define amdgpu_ps <3 x float> @sample_load(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -109,6 +110,7 @@ define amdgpu_ps <3 x float> @sample_load(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1150-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
@@ -129,6 +131,7 @@ define amdgpu_ps <3 x float> @sample_load(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
@@ -163,6 +166,7 @@ define amdgpu_ps <3 x float> @load_sample(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -183,6 +187,7 @@ define amdgpu_ps <3 x float> @load_sample(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1150-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
@@ -203,6 +208,7 @@ define amdgpu_ps <3 x float> @load_sample(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
index 5af8df6fce69b..94c95ae2a4dc7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
@@ -2621,25 +2621,47 @@ bb:
}
define amdgpu_ps void @test_swmmac_f32_16x16x64_bf16(<16 x bfloat> %A, <32 x bfloat> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
-; GFX1250-LABEL: test_swmmac_f32_16x16x64_bf16:
-; GFX1250: ; %bb.0: ; %bb
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
-; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
-; GFX1250-NEXT: global_store_b128 v[34:35], v[24:27], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: test_swmmac_f32_16x16x64_bf16:
+; GFX1250-FAKE16: ; %bb.0: ; %bb
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GFX1250-FAKE16-NEXT: s_clause 0x1
+; GFX1250-FAKE16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GFX1250-FAKE16-NEXT: s_endpgm
;
-; GISEL-LABEL: test_swmmac_f32_16x16x64_bf16:
-; GISEL: ; %bb.0: ; %bb
-; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
-; GISEL-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
-; GISEL-NEXT: s_clause 0x1
-; GISEL-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
-; GISEL-NEXT: global_store_b128 v[34:35], v[24:27], off
-; GISEL-NEXT: s_endpgm
+; GISEL-FAKE16-LABEL: test_swmmac_f32_16x16x64_bf16:
+; GISEL-FAKE16: ; %bb.0: ; %bb
+; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-FAKE16-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GISEL-FAKE16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GISEL-FAKE16-NEXT: s_clause 0x1
+; GISEL-FAKE16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GISEL-FAKE16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: test_swmmac_f32_16x16x64_bf16:
+; GFX1250-REAL16: ; %bb.0: ; %bb
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX1250-REAL16-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GFX1250-REAL16-NEXT: s_clause 0x1
+; GFX1250-REAL16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GFX1250-REAL16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GFX1250-REAL16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: test_swmmac_f32_16x16x64_bf16:
+; GISEL-REAL16: ; %bb.0: ; %bb
+; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-REAL16-NEXT: ; implicit-def: $vgpr32_hi16
+; GISEL-REAL16-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GISEL-REAL16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GISEL-REAL16-NEXT: s_clause 0x1
+; GISEL-REAL16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GISEL-REAL16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GISEL-REAL16-NEXT: s_endpgm
bb:
%res = call <8 x float> @llvm.amdgcn.swmmac.f32.16x16x64.bf16.v8f32.v16bf16.v32bf16.i16(i1 0, <16 x bfloat> %A, i1 0, <32 x bfloat> %B, <8 x float> %C, i16 %Index, i1 false, i1 true)
store <8 x float> %res, ptr addrspace(1) %out
@@ -2647,21 +2669,39 @@ bb:
}
define amdgpu_ps void @test_swmmac_bf16_16x16x64_bf16(<16 x bfloat> %A, <32 x bfloat> %B, <8 x bfloat> %C, i16 %Index, ptr addrspace(1) %out) {
-; GFX1250-LABEL: test_swmmac_bf16_16x16x64_bf16:
-; GFX1250: ; %bb.0: ; %bb
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
-; GFX1250-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
-; GFX1250-NEXT: global_store_b128 v[30:31], v[24:27], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: test_swmmac_bf16_16x16x64_bf16:
+; GFX1250-FAKE16: ; %bb.0: ; %bb
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GFX1250-FAKE16-NEXT: global_store_b128 v[30:31], v[24:27], off
+; GFX1250-FAKE16-NEXT: s_endpgm
;
-; GISEL-LABEL: test_swmmac_bf16_16x16x64_bf16:
-; GISEL: ; %bb.0: ; %bb
-; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
-; GISEL-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
-; GISEL-NEXT: global_store_b128 v[30:31], v[24:27], off
-; GISEL-NEXT: s_endpgm
+; GISEL-FAKE16-LABEL: test_swmmac_bf16_16x16x64_bf16:
+; GISEL-FAKE16: ; %bb.0: ; %bb
+; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-FAKE16-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
+; GISEL-FAKE16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GISEL-FAKE16-NEXT: global_store_b128 v[30:31], v[24:27], off
+; GISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: test_swmmac_bf16_16x16x64_bf16:
+; GFX1250-REAL16: ; %bb.0: ; %bb
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX1250-REAL16-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GFX1250-REAL16-NEXT: global_store_b128 v[30:31], v[24:27], off
+; GFX1250-REAL16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: test_swmmac_bf16_16x16x64_bf16:
+; GISEL-REAL16: ; %bb.0: ; %bb
+; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-REAL16-NEXT: ; implicit-def: $vgpr28_hi16
+; GISEL-REAL16-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
+; GISEL-REAL16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GISEL-REAL16-NEXT: global_store_b128 v[30:31], v[24:27], off
+; GISEL-REAL16-NEXT: s_endpgm
bb:
%res = call <8 x bfloat> @llvm.amdgcn.swmmac.bf16.16x16x64.bf16.v8bf16.v16bf16.v32bf16.i16(i1 0, <16 x bfloat> %A, i1 0, <32 x bfloat> %B, <8 x bfloat> %C, i16 %Index, i1 false, i1 true)
store <8 x bfloat> %res, ptr addrspace(1) %out
@@ -2669,25 +2709,47 @@ bb:
}
define amdgpu_ps void @test_swmmac_bf16f32_16x16x64_bf16(<16 x bfloat> %A, <32 x bfloat> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
-; GFX1250-LABEL: test_swmmac_bf16f32_16x16x64_bf16:
-; GFX1250: ; %bb.0: ; %bb
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
-; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
-; GFX1250-NEXT: global_store_b128 v[34:35], v[24:27], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: test_swmmac_bf16f32_16x16x64_bf16:
+; GFX1250-FAKE16: ; %bb.0: ; %bb
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GFX1250-FAKE16-NEXT: s_clause 0x1
+; GFX1250-FAKE16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GFX1250-FAKE16-NEXT: s_endpgm
;
-; GISEL-LABEL: test_swmmac_bf16f32_16x16x64_bf16:
-; GISEL: ; %bb.0: ; %bb
-; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
-; GISEL-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
-; GISEL-NEXT: s_clause 0x1
-; GISEL-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
-; GISEL-NEXT: global_store_b128 v[34:35], v[24:27], off
-; GISEL-NEXT: s_endpgm
+; GISEL-FAKE16-LABEL: test_swmmac_bf16f32_16x16x64_bf16:
+; GISEL-FAKE16: ; %bb.0: ; %bb
+; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-FAKE16-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GISEL-FAKE16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GISEL-FAKE16-NEXT: s_clause 0x1
+; GISEL-FAKE16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GISEL-FAKE16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: test_swmmac_bf16f32_16x16x64_bf16:
+; GFX1250-REAL16: ; %bb.0: ; %bb
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX1250-REAL16-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GFX1250-REAL16-NEXT: s_clause 0x1
+; GFX1250-REAL16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GFX1250-REAL16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GFX1250-REAL16-NEXT: s_endpgm
+;
+; GISEL-REAL16-LABEL: test_swmmac_bf16f32_16x16x64_bf16:
+; GISEL-REAL16: ; %bb.0: ; %bb
+; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-REAL16-NEXT: ; implicit-def: $vgpr32_hi16
+; GISEL-REAL16-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GISEL-REAL16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GISEL-REAL16-NEXT: s_clause 0x1
+; GISEL-REAL16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GISEL-REAL16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GISEL-REAL16-NEXT: s_endpgm
bb:
%res = call <8 x float> @llvm.amdgcn.swmmac.bf16f32.16x16x64.bf16.v8f32.v16bf16.v32bf16.i16(i1 0, <16 x bfloat> %A, i1 0, <32 x bfloat> %B, <8 x float> %C, i16 %Index, i1 false, i1 true)
store <8 x float> %res, ptr addrspace(1) %out
@@ -2804,16 +2866,19 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_fp8(<8 x i32> %A, <16 x i32
; GISEL-LABEL: test_swmmac_f16_16x16x128_fp8_fp8:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-NEXT: v_swmmac_f16_16x16x128_fp8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GISEL-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v30
+; GISEL-NEXT: ; implicit-def: $vgpr29
+; GISEL-NEXT: v_swmmac_f16_16x16x128_fp8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GISEL-NEXT: global_store_b128 v[32:33], v[24:27], off
; GISEL-NEXT: s_endpgm
;
; GFX1250-REAL16-LABEL: test_swmmac_f16_16x16x128_fp8_fp8:
; GFX1250-REAL16: ; %bb.0: ; %bb
; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x128_fp8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GFX1250-REAL16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr29
+; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x128_fp8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GFX1250-REAL16-NEXT: global_store_b128 v[30:31], v[24:27], off
; GFX1250-REAL16-NEXT: s_endpgm
bb:
@@ -2836,16 +2901,19 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_fp8_bf8(<8 x i32> %A, <16 x i32
; GISEL-LABEL: test_swmmac_f16_16x16x128_fp8_bf8:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-NEXT: v_swmmac_f16_16x16x128_fp8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GISEL-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v30
+; GISEL-NEXT: ; implicit-def: $vgpr29
+; GISEL-NEXT: v_swmmac_f16_16x16x128_fp8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GISEL-NEXT: global_store_b128 v[32:33], v[24:27], off
; GISEL-NEXT: s_endpgm
;
; GFX1250-REAL16-LABEL: test_swmmac_f16_16x16x128_fp8_bf8:
; GFX1250-REAL16: ; %bb.0: ; %bb
; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x128_fp8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GFX1250-REAL16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr29
+; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x128_fp8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GFX1250-REAL16-NEXT: global_store_b128 v[30:31], v[24:27], off
; GFX1250-REAL16-NEXT: s_endpgm
bb:
@@ -2868,16 +2936,19 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_fp8(<8 x i32> %A, <16 x i32
; GISEL-LABEL: test_swmmac_f16_16x16x128_bf8_fp8:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-NEXT: v_swmmac_f16_16x16x128_bf8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GISEL-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v30
+; GISEL-NEXT: ; implicit-def: $vgpr29
+; GISEL-NEXT: v_swmmac_f16_16x16x128_bf8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GISEL-NEXT: global_store_b128 v[32:33], v[24:27], off
; GISEL-NEXT: s_endpgm
;
; GFX1250-REAL16-LABEL: test_swmmac_f16_16x16x128_bf8_fp8:
; GFX1250-REAL16: ; %bb.0: ; %bb
; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x128_bf8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GFX1250-REAL16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr29
+; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x128_bf8_fp8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GFX1250-REAL16-NEXT: global_store_b128 v[30:31], v[24:27], off
; GFX1250-REAL16-NEXT: s_endpgm
bb:
@@ -2900,16 +2971,19 @@ define amdgpu_ps void @test_swmmac_f16_16x16x128_bf8_bf8(<8 x i32> %A, <16 x i32
; GISEL-LABEL: test_swmmac_f16_16x16x128_bf8_bf8:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-NEXT: v_swmmac_f16_16x16x128_bf8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GISEL-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v30
+; GISEL-NEXT: ; implicit-def: $vgpr29
+; GISEL-NEXT: v_swmmac_f16_16x16x128_bf8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GISEL-NEXT: global_store_b128 v[32:33], v[24:27], off
; GISEL-NEXT: s_endpgm
;
; GFX1250-REAL16-LABEL: test_swmmac_f16_16x16x128_bf8_bf8:
; GFX1250-REAL16: ; %bb.0: ; %bb
; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x128_bf8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GFX1250-REAL16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr29
+; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x128_bf8_bf8 v[24:27], v[0:7], v[8:23], v[28:29] matrix_b_reuse
; GFX1250-REAL16-NEXT: global_store_b128 v[30:31], v[24:27], off
; GFX1250-REAL16-NEXT: s_endpgm
bb:
@@ -2943,15 +3017,15 @@ bb:
}
define amdgpu_ps void @test_swmmac_f32_16x16x64_f16(<16 x half> %A, <32 x half> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
-; GFX1250-LABEL: test_swmmac_f32_16x16x64_f16:
-; GFX1250: ; %bb.0: ; %bb
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_swmmac_f32_16x16x64_f16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
-; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
-; GFX1250-NEXT: global_store_b128 v[34:35], v[24:27], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: test_swmmac_f32_16x16x64_f16:
+; GFX1250-FAKE16: ; %bb.0: ; %bb
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: v_swmmac_f32_16x16x64_f16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GFX1250-FAKE16-NEXT: s_clause 0x1
+; GFX1250-FAKE16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GFX1250-FAKE16-NEXT: s_endpgm
;
; GISEL-LABEL: test_swmmac_f32_16x16x64_f16:
; GISEL: ; %bb.0: ; %bb
@@ -2962,6 +3036,17 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_f16(<16 x half> %A, <32 x half>
; GISEL-NEXT: global_store_b128 v[36:37], v[24:27], off
; GISEL-NEXT: global_store_b128 v[36:37], v[28:31], off offset:16
; GISEL-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: test_swmmac_f32_16x16x64_f16:
+; GFX1250-REAL16: ; %bb.0: ; %bb
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX1250-REAL16-NEXT: v_swmmac_f32_16x16x64_f16 v[24:31], v[0:7], v[8:23], v32 matrix_b_reuse
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
+; GFX1250-REAL16-NEXT: s_clause 0x1
+; GFX1250-REAL16-NEXT: global_store_b128 v[34:35], v[28:31], off offset:16
+; GFX1250-REAL16-NEXT: global_store_b128 v[34:35], v[24:27], off
+; GFX1250-REAL16-NEXT: s_endpgm
bb:
%res = call <8 x float> @llvm.amdgcn.swmmac.f32.16x16x64.f16.v8f32.v16f16.v32f16.i16(i1 0, <16 x half> %A, i1 0, <32 x half> %B, <8 x float> %C, i16 %Index, i1 false, i1 true)
store <8 x float> %res, ptr addrspace(1) %out
@@ -2969,13 +3054,13 @@ bb:
}
define amdgpu_ps void @test_swmmac_f16_16x16x64_f16(<16 x half> %A, <32 x half> %B, <8 x half> %C, i16 %Index, ptr addrspace(1) %out) {
-; GFX1250-LABEL: test_swmmac_f16_16x16x64_f16:
-; GFX1250: ; %bb.0: ; %bb
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_swmmac_f16_16x16x64_f16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
-; GFX1250-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
-; GFX1250-NEXT: global_store_b128 v[30:31], v[24:27], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: test_swmmac_f16_16x16x64_f16:
+; GFX1250-FAKE16: ; %bb.0: ; %bb
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: v_swmmac_f16_16x16x64_f16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GFX1250-FAKE16-NEXT: global_store_b128 v[30:31], v[24:27], off
+; GFX1250-FAKE16-NEXT: s_endpgm
;
; GISEL-LABEL: test_swmmac_f16_16x16x64_f16:
; GISEL: ; %bb.0: ; %bb
@@ -2984,6 +3069,15 @@ define amdgpu_ps void @test_swmmac_f16_16x16x64_f16(<16 x half> %A, <32 x half>
; GISEL-NEXT: v_dual_mov_b32 v32, v29 :: v_dual_mov_b32 v33, v30
; GISEL-NEXT: global_store_b128 v[32:33], v[24:27], off
; GISEL-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: test_swmmac_f16_16x16x64_f16:
+; GFX1250-REAL16: ; %bb.0: ; %bb
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr28_hi16
+; GFX1250-REAL16-NEXT: v_swmmac_f16_16x16x64_f16 v[24:27], v[0:7], v[8:23], v28 matrix_b_reuse
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
+; GFX1250-REAL16-NEXT: global_store_b128 v[30:31], v[24:27], off
+; GFX1250-REAL16-NEXT: s_endpgm
bb:
%res = call <8 x half> @llvm.amdgcn.swmmac.f16.16x16x64.f16.v8f16.v16f16.v32f16.i16(i1 0, <16 x half> %A, i1 0, <32 x half> %B, <8 x half> %C, i16 %Index, i1 false, i1 true)
store <8 x half> %res, ptr addrspace(1) %out
@@ -3034,6 +3128,3 @@ declare <8 x half> @llvm.amdgcn.swmmac.f16.16x16x128.bf8.bf8.v8f16.v8i32.v16i32.
declare <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x128.iu8.v8i32.v8i32.v16i32.i64(i1 immarg, <8 x i32>, i1 immarg, <16 x i32>, <8 x i32>, i64 %Index, i1, i1)
declare <8 x float> @llvm.amdgcn.swmmac.f32.16x16x64.f16.v8f32.v16f16.v32f16.i16(i1, <16 x half>, i1, <32 x half>, <8 x float>, i16, i1, i1)
declare <8 x half> @llvm.amdgcn.swmmac.f16.16x16x64.f16.v8f16.v16f16.v32f16.i16(i1, <16 x half>, i1, <32 x half>, <8 x half>, i16, i1, i1)
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL-FAKE16: {{.*}}
-; GISEL-REAL16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
index 96a329d72aec9..47da6db4ad345 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
@@ -1974,6 +1974,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_bf16_negA(<16 x bfloat> %A, <32
; GFX1250-LABEL: test_swmmac_f32_16x16x64_bf16_negA:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr32_hi16
; GFX1250-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[1,0,0] neg_hi:[1,0,0]
; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GFX1250-NEXT: s_clause 0x1
@@ -1984,6 +1985,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_bf16_negA(<16 x bfloat> %A, <32
; GISEL-LABEL: test_swmmac_f32_16x16x64_bf16_negA:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: ; implicit-def: $vgpr32_hi16
; GISEL-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[1,0,0] neg_hi:[1,0,0]
; GISEL-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GISEL-NEXT: s_clause 0x1
@@ -2000,6 +2002,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_bf16_negB(<16 x bfloat> %A, <32
; GFX1250-LABEL: test_swmmac_f32_16x16x64_bf16_negB:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr32_hi16
; GFX1250-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[0,1,0] neg_hi:[0,1,0]
; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GFX1250-NEXT: s_clause 0x1
@@ -2010,6 +2013,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_bf16_negB(<16 x bfloat> %A, <32
; GISEL-LABEL: test_swmmac_f32_16x16x64_bf16_negB:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: ; implicit-def: $vgpr32_hi16
; GISEL-NEXT: v_swmmac_f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[0,1,0] neg_hi:[0,1,0]
; GISEL-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GISEL-NEXT: s_clause 0x1
@@ -2026,6 +2030,7 @@ define amdgpu_ps void @test_swmmac_bf16_16x16x64_bf16_negA(<16 x bfloat> %A, <32
; GFX1250-LABEL: test_swmmac_bf16_16x16x64_bf16_negA:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr28_hi16
; GFX1250-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 neg_lo:[1,0,0] neg_hi:[1,0,0]
; GFX1250-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
; GFX1250-NEXT: global_store_b128 v[30:31], v[24:27], off
@@ -2034,6 +2039,7 @@ define amdgpu_ps void @test_swmmac_bf16_16x16x64_bf16_negA(<16 x bfloat> %A, <32
; GISEL-LABEL: test_swmmac_bf16_16x16x64_bf16_negA:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: ; implicit-def: $vgpr28_hi16
; GISEL-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 neg_lo:[1,0,0] neg_hi:[1,0,0]
; GISEL-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
; GISEL-NEXT: global_store_b128 v[30:31], v[24:27], off
@@ -2048,6 +2054,7 @@ define amdgpu_ps void @test_swmmac_bf16_16x16x64_bf16_negB(<16 x bfloat> %A, <32
; GFX1250-LABEL: test_swmmac_bf16_16x16x64_bf16_negB:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr28_hi16
; GFX1250-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 neg_lo:[0,1,0] neg_hi:[0,1,0]
; GFX1250-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
; GFX1250-NEXT: global_store_b128 v[30:31], v[24:27], off
@@ -2056,6 +2063,7 @@ define amdgpu_ps void @test_swmmac_bf16_16x16x64_bf16_negB(<16 x bfloat> %A, <32
; GISEL-LABEL: test_swmmac_bf16_16x16x64_bf16_negB:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: ; implicit-def: $vgpr28_hi16
; GISEL-NEXT: v_swmmac_bf16_16x16x64_bf16 v[24:27], v[0:7], v[8:23], v28 neg_lo:[0,1,0] neg_hi:[0,1,0]
; GISEL-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
; GISEL-NEXT: global_store_b128 v[30:31], v[24:27], off
@@ -2070,6 +2078,7 @@ define amdgpu_ps void @test_swmmac_bf16f32_16x16x64_bf16_negA(<16 x bfloat> %A,
; GFX1250-LABEL: test_swmmac_bf16f32_16x16x64_bf16_negA:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr32_hi16
; GFX1250-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[1,0,0] neg_hi:[1,0,0]
; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GFX1250-NEXT: s_clause 0x1
@@ -2080,6 +2089,7 @@ define amdgpu_ps void @test_swmmac_bf16f32_16x16x64_bf16_negA(<16 x bfloat> %A,
; GISEL-LABEL: test_swmmac_bf16f32_16x16x64_bf16_negA:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: ; implicit-def: $vgpr32_hi16
; GISEL-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[1,0,0] neg_hi:[1,0,0]
; GISEL-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GISEL-NEXT: s_clause 0x1
@@ -2096,6 +2106,7 @@ define amdgpu_ps void @test_swmmac_bf16f32_16x16x64_bf16_negB(<16 x bfloat> %A,
; GFX1250-LABEL: test_swmmac_bf16f32_16x16x64_bf16_negB:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr32_hi16
; GFX1250-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[0,1,0] neg_hi:[0,1,0]
; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GFX1250-NEXT: s_clause 0x1
@@ -2106,6 +2117,7 @@ define amdgpu_ps void @test_swmmac_bf16f32_16x16x64_bf16_negB(<16 x bfloat> %A,
; GISEL-LABEL: test_swmmac_bf16f32_16x16x64_bf16_negB:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-NEXT: ; implicit-def: $vgpr32_hi16
; GISEL-NEXT: v_swmmac_bf16f32_16x16x64_bf16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[0,1,0] neg_hi:[0,1,0]
; GISEL-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GISEL-NEXT: s_clause 0x1
@@ -2170,6 +2182,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_f16_negA(<16 x half> %A, <32 x h
; GFX1250-LABEL: test_swmmac_f32_16x16x64_f16_negA:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr32_hi16
; GFX1250-NEXT: v_swmmac_f32_16x16x64_f16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[1,0,0] neg_hi:[1,0,0]
; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GFX1250-NEXT: s_clause 0x1
@@ -2196,6 +2209,7 @@ define amdgpu_ps void @test_swmmac_f32_16x16x64_f16_negB(<16 x half> %A, <32 x h
; GFX1250-LABEL: test_swmmac_f32_16x16x64_f16_negB:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr32_hi16
; GFX1250-NEXT: v_swmmac_f32_16x16x64_f16 v[24:31], v[0:7], v[8:23], v32 neg_lo:[0,1,0] neg_hi:[0,1,0]
; GFX1250-NEXT: v_dual_mov_b32 v35, v34 :: v_dual_mov_b32 v34, v33
; GFX1250-NEXT: s_clause 0x1
@@ -2222,6 +2236,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x64_f16_negA(<16 x half> %A, <32 x h
; GFX1250-LABEL: test_swmmac_f16_16x16x64_f16_negA:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr28_hi16
; GFX1250-NEXT: v_swmmac_f16_16x16x64_f16 v[24:27], v[0:7], v[8:23], v28 neg_lo:[1,0,0] neg_hi:[1,0,0]
; GFX1250-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
; GFX1250-NEXT: global_store_b128 v[30:31], v[24:27], off
@@ -2244,6 +2259,7 @@ define amdgpu_ps void @test_swmmac_f16_16x16x64_f16_negB(<16 x half> %A, <32 x h
; GFX1250-LABEL: test_swmmac_f16_16x16x64_f16_negB:
; GFX1250: ; %bb.0: ; %bb
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: ; implicit-def: $vgpr28_hi16
; GFX1250-NEXT: v_swmmac_f16_16x16x64_f16 v[24:27], v[0:7], v[8:23], v28 neg_lo:[0,1,0] neg_hi:[0,1,0]
; GFX1250-NEXT: v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v30, v29
; GFX1250-NEXT: global_store_b128 v[30:31], v[24:27], off
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
index 588232df486b7..ee57856a57a01 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
@@ -2073,6 +2073,7 @@ define void @test_writelane_half(ptr addrspace(1) %out, half %src, i32 %src1) {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_load_u16 v4, v[0:1], off
+; GFX1100-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s0, v2
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -2229,6 +2230,7 @@ define void @test_writelane_bfloat(ptr addrspace(1) %out, bfloat %src, i32 %src1
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_load_u16 v4, v[0:1], off
+; GFX1100-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s0, v2
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -2265,6 +2267,7 @@ define void @test_writelane_bfloat(ptr addrspace(1) %out, bfloat %src, i32 %src1
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: global_load_u16 v4, v[0:1], off
+; GFX1100-GISEL-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0)
@@ -2307,6 +2310,7 @@ define void @test_writelane_i16(ptr addrspace(1) %out, i16 %src, i32 %src1) {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_load_u16 v4, v[0:1], off
+; GFX1100-SDAG-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s0, v2
; GFX1100-SDAG-NEXT: v_readfirstlane_b32 s1, v3
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
index 7b361cac9410d..83d4222f22bf8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
@@ -21,6 +21,7 @@ define amdgpu_gs half @v_fptrunc_round_f32_to_f16_tonearest(float %a) {
; GFX11-GISEL-LABEL: v_fptrunc_round_f32_to_f16_tonearest:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: ; return to shader part epilog
;
; GISEL-LABEL: v_fptrunc_round_f32_to_f16_tonearest:
@@ -28,10 +29,16 @@ define amdgpu_gs half @v_fptrunc_round_f32_to_f16_tonearest(float %a) {
; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: v_fptrunc_round_f32_to_f16_tonearest:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: v_cvt_f16_f32_e64 v0.l, v0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: v_fptrunc_round_f32_to_f16_tonearest:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: v_fptrunc_round_f32_to_f16_tonearest:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.tonearest")
ret half %res
}
@@ -53,6 +60,7 @@ define amdgpu_gs half @v_fptrunc_round_f32_to_f16_upward(float %a) {
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: ; return to shader part epilog
;
; GISEL-LABEL: v_fptrunc_round_f32_to_f16_upward:
@@ -61,11 +69,18 @@ define amdgpu_gs half @v_fptrunc_round_f32_to_f16_upward(float %a) {
; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: v_fptrunc_round_f32_to_f16_upward:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
-; GFX12-NEXT: v_cvt_f16_f32_e64 v0.l, v0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: v_fptrunc_round_f32_to_f16_upward:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
+; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: v_fptrunc_round_f32_to_f16_upward:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
+; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward")
ret half %res
}
@@ -87,6 +102,7 @@ define amdgpu_gs half @v_fptrunc_round_f32_to_f16_downward(float %a) {
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: ; return to shader part epilog
;
; GISEL-LABEL: v_fptrunc_round_f32_to_f16_downward:
@@ -95,11 +111,18 @@ define amdgpu_gs half @v_fptrunc_round_f32_to_f16_downward(float %a) {
; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GISEL-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: v_fptrunc_round_f32_to_f16_downward:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 1
-; GFX12-NEXT: v_cvt_f16_f32_e64 v0.l, v0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: v_fptrunc_round_f32_to_f16_downward:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 1
+; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: v_fptrunc_round_f32_to_f16_downward:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 1
+; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: ; return to shader part epilog
%res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.downward")
ret half %res
}
@@ -118,6 +141,7 @@ define amdgpu_gs half @v_fptrunc_round_f32_to_f16_towardzero(float %a) {
; GFX11-GISEL-LABEL: v_fptrunc_round_f32_to_f16_towardzero:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e32 v0, v0, v0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: ; return to shader part epilog
;
; GISEL-LABEL: v_fptrunc_round_f32_to_f16_towardzero:
@@ -133,6 +157,7 @@ define amdgpu_gs half @v_fptrunc_round_f32_to_f16_towardzero(float %a) {
; GFX12-GISEL-LABEL: v_fptrunc_round_f32_to_f16_towardzero:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e32 v0, v0, v0
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-NEXT: ; return to shader part epilog
%res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.towardzero")
ret half %res
@@ -181,11 +206,13 @@ define amdgpu_gs <2 x half> @v_fptrunc_round_poison_to_v2f16_towardzero(float %a
; GFX11-SDAG-LABEL: v_fptrunc_round_poison_to_v2f16_towardzero:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: v_cvt_pk_rtz_f16_f32_e64 v0, v0, s0
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-LABEL: v_fptrunc_round_poison_to_v2f16_towardzero:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e32 v0, v0, v0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: ; return to shader part epilog
;
; GISEL-LABEL: v_fptrunc_round_poison_to_v2f16_towardzero:
@@ -198,11 +225,13 @@ define amdgpu_gs <2 x half> @v_fptrunc_round_poison_to_v2f16_towardzero(float %a
; GFX12-SDAG-LABEL: v_fptrunc_round_poison_to_v2f16_towardzero:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_cvt_pk_rtz_f16_f32_e64 v0, v0, s0
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-LABEL: v_fptrunc_round_poison_to_v2f16_towardzero:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e32 v0, v0, v0
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-NEXT: ; return to shader part epilog
%lo = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.towardzero")
%tmp = insertelement <2 x half> poison, half %lo, i32 0
@@ -505,6 +534,7 @@ define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_upward(float inreg %a, ptr addr
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, s0
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v0
@@ -514,6 +544,7 @@ define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_upward(float inreg %a, ptr addr
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, s0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
@@ -555,6 +586,7 @@ define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_downward(float inreg %a, ptr ad
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, s0
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v0
@@ -564,6 +596,7 @@ define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_downward(float inreg %a, ptr ad
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, s0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
@@ -610,6 +643,7 @@ define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_towardzero(float inreg %a, ptr
; GFX11-GISEL-LABEL: s_fptrunc_round_f32_to_f16_towardzero:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e32 v0, s0, v0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
@@ -954,6 +988,8 @@ define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_upward(<2 x float> in
; GFX11-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, s0
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, s1
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -967,6 +1003,8 @@ define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_upward(<2 x float> in
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, s0
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v1.l, s1
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v1
@@ -1021,6 +1059,8 @@ define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_downward(<2 x float>
; GFX11-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, s0
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, s1
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -1034,6 +1074,8 @@ define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_downward(<2 x float>
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, s0
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v1.l, s1
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v1
@@ -1097,6 +1139,8 @@ define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_towardzero(<2 x float
; GFX11-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e32 v0, s0, v0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_cvt_pk_rtz_f16_f32_e32 v1, s1, v0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
@@ -1178,6 +1222,10 @@ define amdgpu_gs void @s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls(<2 x
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v3.l, s1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v4.l, s2
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v5.l, s3
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v3
@@ -1188,6 +1236,8 @@ define amdgpu_gs void @s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls(<2 x
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v2.l, s2
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v3.l, s3
; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s1, s4, s5
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v2
@@ -1296,6 +1346,7 @@ define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_upward(<3 x float> %
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v3.h, v1
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v3.l, v0
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, v2
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, v3
; GFX11-SDAG-NEXT: ; return to shader part epilog
@@ -1306,6 +1357,7 @@ define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_upward(<3 x float> %
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.h, v1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v1.l, v2
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-NEXT: ; return to shader part epilog
;
; GISEL-LABEL: v_fptrunc_round_v3f32_to_v3f16_upward:
@@ -1325,6 +1377,7 @@ define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_upward(<3 x float> %
; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v3.h, v1
; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v3.l, v0
; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, v2
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v3
; GFX12-SDAG-NEXT: ; return to shader part epilog
@@ -1335,6 +1388,7 @@ define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_upward(<3 x float> %
; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v0.h, v1
; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v1.l, v2
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-NEXT: ; return to shader part epilog
%res = call <3 x half> @llvm.fptrunc.round.v3f16.v3f32(<3 x float> %a, metadata !"round.upward")
ret <3 x half> %res
@@ -1356,6 +1410,7 @@ define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_downward(<3 x float>
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v3.h, v1
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v3.l, v0
; GFX11-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, v2
+; GFX11-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, v3
; GFX11-SDAG-NEXT: ; return to shader part epilog
@@ -1366,6 +1421,7 @@ define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_downward(<3 x float>
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v0.h, v1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v1.l, v2
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-NEXT: ; return to shader part epilog
;
; GISEL-LABEL: v_fptrunc_round_v3f32_to_v3f16_downward:
@@ -1385,6 +1441,7 @@ define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_downward(<3 x float>
; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v3.h, v1
; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v3.l, v0
; GFX12-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, v2
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v3
; GFX12-SDAG-NEXT: ; return to shader part epilog
@@ -1395,6 +1452,7 @@ define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_downward(<3 x float>
; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, v0
; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v0.h, v1
; GFX12-GISEL-NEXT: v_cvt_f16_f32_e64 v1.l, v2
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-NEXT: ; return to shader part epilog
%res = call <3 x half> @llvm.fptrunc.round.v3f16.v3f32(<3 x float> %a, metadata !"round.downward")
ret <3 x half> %res
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
index e239f37a8c055..711a0bd1403d3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
@@ -51,6 +51,7 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -73,6 +74,7 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -108,7 +110,9 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -130,7 +134,9 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -222,6 +228,7 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i32_only_use_fract:
@@ -238,6 +245,7 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i32_only_use_fract:
@@ -283,6 +291,7 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -303,6 +312,7 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -333,6 +343,7 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -353,6 +364,7 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -428,6 +440,8 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -459,6 +473,8 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h
; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -537,6 +553,8 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -568,6 +586,8 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -787,6 +807,8 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -813,6 +835,8 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -874,6 +898,8 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -900,6 +926,8 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
@@ -1017,6 +1045,8 @@ define { half, i16 } @test_frexp_f16_i16(half %a) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1039,6 +1069,8 @@ define { half, i16 } @test_frexp_f16_i16(half %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v2.l, v0.l
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1130,6 +1162,7 @@ define half @test_frexp_f16_i16_only_use_fract(half %a) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i16_only_use_fract:
@@ -1146,6 +1179,7 @@ define half @test_frexp_f16_i16_only_use_fract(half %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i16_only_use_fract:
@@ -1231,6 +1265,7 @@ define i16 @test_frexp_f16_i16_only_use_exp(half %a) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i16_only_use_exp:
@@ -1247,6 +1282,7 @@ define i16 @test_frexp_f16_i16_only_use_exp(half %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i16_only_use_exp:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
index 01b47d83a7a93..a343b852a1ee9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
@@ -215,6 +215,7 @@ define half @test_ldexp_f16_i8(half %a, i8 %b) {
;
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_f16_i8:
; GFX11-SDAG-TRUE16: ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -254,6 +255,7 @@ define half @test_ldexp_f16_i8(half %a, i8 %b) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
@@ -310,6 +312,7 @@ define half @test_ldexp_f16_i16(half %a, i16 %b) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_ldexp_f16_i16:
@@ -388,6 +391,7 @@ define half @test_ldexp_f16_i32(half %a, i32 %b) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
@@ -695,6 +699,7 @@ define <3 x half> @test_ldexp_v3f16_v3i32(<3 x half> %a, <3 x i32> %b) {
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v2, v2, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v3, v3, s0, 0x7fff
@@ -771,6 +776,7 @@ define <3 x half> @test_ldexp_v3f16_v3i32(<3 x half> %a, <3 x i32> %b) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v5, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v5
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v3, 0xffff8000, v3, v5
@@ -850,6 +856,7 @@ define <3 x half> @test_ldexp_v3f16_v3i16(<3 x half> %a, <3 x i16> %b) {
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_ldexp_v3f16_v3i16:
@@ -909,6 +916,7 @@ define <3 x half> @test_ldexp_v3f16_v3i16(<3 x half> %a, <3 x i16> %b) {
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.h
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v1.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_ldexp_v3f16_v3i16:
@@ -1320,6 +1328,7 @@ define amdgpu_ps half @test_ldexp_f16_i16_uniform(half inreg %a, i16 inreg %b) {
; GFX11-GISEL-TRUE16-LABEL: test_ldexp_f16_i16_uniform:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, s0, s1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-FAKE16-LABEL: test_ldexp_f16_i16_uniform:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index 9357b373c3d13..71c476a010195 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -6598,6 +6598,7 @@ define half @v_log_f16(half %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log_f16:
@@ -6665,6 +6666,7 @@ define half @v_log_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log_fabs_f16:
@@ -6733,6 +6735,7 @@ define half @v_log_fneg_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log_fneg_fabs_f16:
@@ -6802,6 +6805,7 @@ define half @v_log_fneg_f16(half %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log_fneg_f16:
@@ -6873,6 +6877,7 @@ define half @v_log_f16_afn(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6942,6 +6947,7 @@ define half @v_log_f16_fast(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7848,6 +7854,7 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, s0, 0
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, s0, 0
+; GFX1100-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_v3f16:
@@ -7886,6 +7893,7 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, v4, 0
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v4, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log_v3f16:
@@ -7990,6 +7998,7 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -8019,6 +8028,7 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -8552,6 +8562,7 @@ define half @v_log_f16_fpmath(half %x) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -8805,6 +8816,7 @@ define <3 x half> @v_log_v3f16_fpmath(<3 x half> %x) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pk_mul_f16 v0, 0x398c398c, v0
; GFX1100-GISEL-TRUE16-NEXT: v_pk_mul_f16 v1, 0x398c, v1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 97d706c38020f..5e22091d8b578 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -6598,6 +6598,7 @@ define half @v_log10_f16(half %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log10_f16:
@@ -6665,6 +6666,7 @@ define half @v_log10_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log10_fabs_f16:
@@ -6733,6 +6735,7 @@ define half @v_log10_fneg_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log10_fneg_fabs_f16:
@@ -6802,6 +6805,7 @@ define half @v_log10_fneg_f16(half %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log10_fneg_f16:
@@ -6873,6 +6877,7 @@ define half @v_log10_f16_afn(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6942,6 +6947,7 @@ define half @v_log10_f16_fast(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7848,6 +7854,7 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, s0, 0
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, s0, 0
+; GFX1100-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_v3f16:
@@ -7886,6 +7893,7 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, v4, 0
; GFX1100-GISEL-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v4, 0
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log10_v3f16:
@@ -7990,6 +7998,7 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -8019,6 +8028,7 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -8552,6 +8562,7 @@ define half @v_log10_f16_fpmath(half %x) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -8805,6 +8816,7 @@ define <3 x half> @v_log10_v3f16_fpmath(<3 x half> %x) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pk_mul_f16 v0, 0x34d134d1, v0
; GFX1100-GISEL-TRUE16-NEXT: v_pk_mul_f16 v1, 0x34d1, v1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index 7ef457c70b789..75e4900371741 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -3842,6 +3842,7 @@ define half @v_log2_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log2_f16:
@@ -3900,6 +3901,7 @@ define half @v_log2_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log2_fabs_f16:
@@ -3959,6 +3961,7 @@ define half @v_log2_fneg_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log2_fneg_fabs_f16:
@@ -4019,6 +4022,7 @@ define half @v_log2_fneg_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log2_fneg_f16:
@@ -4078,6 +4082,7 @@ define half @v_log2_f16_fast(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log2_f16_fast:
@@ -4676,6 +4681,7 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_v3f16:
@@ -4696,6 +4702,7 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log2_v3f16:
@@ -4786,6 +4793,7 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_v3f16_fast:
@@ -4806,6 +4814,7 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-FAKE16-LABEL: v_log2_v3f16_fast:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
index a60741905bdbd..38198bf4811b3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
@@ -662,6 +662,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, s0, s1
; GFX11-TRUE16-NEXT: v_max_f16_e64 v0.l, s0, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -687,6 +688,7 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) {
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-TRUE16-NEXT: v_maximum_f16 v0.l, s0, s1
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX1170-TRUE16-NEXT: ;;#ASMSTART
@@ -1337,6 +1339,7 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) {
; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v2.h
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s1
@@ -1551,6 +1554,7 @@ define <3 x half> @v_maximum_v3f16__nsz(<3 x half> %src0, <3 x half> %src1) {
; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v2.h
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
index cd01dfc2d3dc8..dcded778243d9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
@@ -575,6 +575,7 @@ define void @s_minimum_f16(half inreg %src0, half inreg %src1) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, s0, s1
; GFX11-TRUE16-NEXT: v_min_f16_e64 v0.l, s0, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -600,6 +601,7 @@ define void @s_minimum_f16(half inreg %src0, half inreg %src1) {
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-TRUE16-NEXT: v_minimum_f16 v0.l, s0, s1
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX1170-TRUE16-NEXT: ;;#ASMSTART
@@ -1119,6 +1121,7 @@ define <3 x half> @v_minimum_v3f16(<3 x half> %src0, <3 x half> %src1) {
; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v2.h
; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s1
@@ -1284,6 +1287,7 @@ define <3 x half> @v_minimum_v3f16__nsz(<3 x half> %src0, <3 x half> %src1) {
; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v2.h
; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
index 802ffc1e7ea7b..728d5dfc33c00 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
@@ -761,6 +761,8 @@ define amdgpu_kernel void @round_v8f32(ptr addrspace(1) %out, <8 x float> %in) #
; R600-NEXT: ADD T0.X, T3.W, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; R600-NEXT: ADD_INT * T2.X, PS, literal.x,
+; R600-NEXT: 4(5.605194e-45), 0(0.000000e+00)
%result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
store <8 x float> %result, ptr addrspace(1) %out
ret void
@@ -830,6 +832,8 @@ define amdgpu_kernel void @round_f16(ptr addrspace(1) %out, i32 %x.arg) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, s2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
@@ -992,6 +996,9 @@ define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s2, 16
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, s2
@@ -1005,6 +1012,7 @@ define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s6, |v1.l|, 0.5
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s7, |v1.h|, 0.5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0, 0x3c00, s6
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0, 0x3c00, s7
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
index 983dce4ac1170..d280b80d95df2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
@@ -125,6 +125,7 @@ define amdgpu_kernel void @sqrt_f16(
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s10, s6
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s11, s7
+; GFX12-TRUE16-SDAG-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s9, s3
@@ -270,6 +271,8 @@ define amdgpu_kernel void @sqrt_v2f16(
; GFX11-TRUE16-GISEL-LABEL: sqrt_v2f16:
; GFX11-TRUE16-GISEL: ; %bb.0: ; %entry
; GFX11-TRUE16-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-GISEL-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX11-TRUE16-GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -428,10 +431,16 @@ define amdgpu_ps half @sqrt_f16_s(half inreg %x) {
; VI-NEXT: v_sqrt_f16_e32 v0, s0
; VI-NEXT: ; return to shader part epilog
;
-; GFX11-TRUE16-LABEL: sqrt_f16_s:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-SDAG-LABEL: sqrt_f16_s:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: v_sqrt_f16_e32 v0.l, s0
+; GFX11-TRUE16-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-GISEL-LABEL: sqrt_f16_s:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: v_sqrt_f16_e32 v0.l, s0
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: sqrt_f16_s:
; GFX11-FAKE16: ; %bb.0:
@@ -470,20 +479,32 @@ define amdgpu_ps half @sqrt_f16_v(half %x) {
; VI-NEXT: v_sqrt_f16_e32 v0, v0
; VI-NEXT: ; return to shader part epilog
;
-; GFX11-TRUE16-LABEL: sqrt_f16_v:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-SDAG-LABEL: sqrt_f16_v:
+; GFX11-TRUE16-SDAG: ; %bb.0:
+; GFX11-TRUE16-SDAG-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-GISEL-LABEL: sqrt_f16_v:
+; GFX11-TRUE16-GISEL: ; %bb.0:
+; GFX11-TRUE16-GISEL-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-GISEL-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: sqrt_f16_v:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
-; GFX12-TRUE16-LABEL: sqrt_f16_v:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: ; return to shader part epilog
+; GFX12-TRUE16-SDAG-LABEL: sqrt_f16_v:
+; GFX12-TRUE16-SDAG: ; %bb.0:
+; GFX12-TRUE16-SDAG-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-GISEL-LABEL: sqrt_f16_v:
+; GFX12-TRUE16-GISEL: ; %bb.0:
+; GFX12-TRUE16-GISEL-NEXT: v_sqrt_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-TRUE16-GISEL-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: sqrt_f16_v:
; GFX12-FAKE16: ; %bb.0:
@@ -492,3 +513,5 @@ define amdgpu_ps half @sqrt_f16_v(half %x) {
%result = call half @llvm.sqrt.f16(half %x)
ret half %result
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 589ea74948d2a..c9f7c280604d2 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -1062,6 +1062,7 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i32(ptr addrspace(1) %out
; GFX12-NEXT: global_load_d16_u8 v0, v2, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_lshrrev_b32_e32 v1, 1, v1
@@ -1240,13 +1241,14 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i32(ptr addrspace(1) %out
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v3, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_d16_u8 v1, v3, s[2:3]
+; GFX12-NEXT: global_load_d16_u8 v2, v3, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-NEXT: v_lshrrev_b32_e32 v2, 2, v0
-; GFX12-NEXT: v_and_b32_e32 v0, 1, v1
-; GFX12-NEXT: v_bfe_u32 v1, v1, 1, 1
+; GFX12-NEXT: v_and_b32_e32 v0, 1, v2
+; GFX12-NEXT: v_bfe_u32 v1, v2, 1, 1
+; GFX12-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 2, v2
; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX12-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX12-NEXT: s_endpgm
@@ -1274,6 +1276,7 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i32(ptr addrspace(1) %out
; GFX1250-REAL16-NEXT: v_mov_b32_e32 v3, 0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_u8 v0, v3, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-REAL16-NEXT: s_and_b32 s3, 0xffff, s2
@@ -1457,6 +1460,7 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i32(ptr addrspace(1) %out
; GFX12-NEXT: global_load_d16_u8 v1, v4, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX12-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-NEXT: v_and_b32_e32 v0, 1, v1
; GFX12-NEXT: v_bfe_u32 v2, v1, 2, 1
; GFX12-NEXT: v_bfe_u32 v1, v1, 1, 1
@@ -1489,6 +1493,7 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i32(ptr addrspace(1) %out
; GFX1250-REAL16-NEXT: v_mov_b32_e32 v4, 0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_u8 v0, v4, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-REAL16-NEXT: s_and_b32 s3, 0xffff, s2
@@ -1708,6 +1713,7 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
; GFX12-NEXT: global_load_d16_u8 v0, v8, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10005
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_and_b32 v0, 0xffff, v0
@@ -1760,6 +1766,7 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
; GFX1250-REAL16-NEXT: v_mov_b32_e32 v8, 0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_u8 v0, v8, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-REAL16-NEXT: s_and_b32 s5, 0xffff, s2
@@ -2085,10 +2092,11 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_b16 v0, v16, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s3, v0
; GFX12-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-NEXT: v_readfirstlane_b32 s3, v0
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10003
+; GFX12-NEXT: s_and_b32 s3, 0xffff, s3
; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10001
; GFX12-NEXT: s_bfe_u32 s6, s2, 0x10007
; GFX12-NEXT: s_bfe_u32 s7, s2, 0x10009
@@ -2119,46 +2127,88 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v16, v[12:15], s[0:1]
; GFX12-NEXT: s_endpgm
;
-; GFX1250-LABEL: constant_zextload_v16i1_to_v16i32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v16, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v0, v16, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1250-NEXT: s_and_b32 s6, 0xffff, s2
-; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10001
-; GFX1250-NEXT: s_bfe_u32 s5, s2, 0x10007
-; GFX1250-NEXT: s_bfe_u32 s7, s2, 0x10009
-; GFX1250-NEXT: s_bfe_u32 s8, s2, 0x1000d
-; GFX1250-NEXT: s_and_b32 s9, s2, 1
-; GFX1250-NEXT: s_bfe_u32 s10, s2, 0x1000a
-; GFX1250-NEXT: s_bfe_u32 s2, s2, 0x1000c
-; GFX1250-NEXT: s_bfe_u32 s11, s6, 0x10005
-; GFX1250-NEXT: s_bfe_u32 s12, s6, 0x1000b
-; GFX1250-NEXT: s_lshr_b32 s13, s6, 15
-; GFX1250-NEXT: s_bfe_u32 s14, s6, 0x10002
-; GFX1250-NEXT: s_bfe_u32 s15, s6, 0x10006
-; GFX1250-NEXT: s_bfe_u32 s16, s6, 0x10004
-; GFX1250-NEXT: s_bfe_u32 s17, s6, 0x10008
-; GFX1250-NEXT: s_bfe_u32 s6, s6, 0x1000e
-; GFX1250-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
-; GFX1250-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s13
-; GFX1250-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
-; GFX1250-NEXT: v_dual_mov_b32 v4, s17 :: v_dual_mov_b32 v7, s12
-; GFX1250-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, s9
-; GFX1250-NEXT: v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s11
-; GFX1250-NEXT: v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v14, s14
-; GFX1250-NEXT: v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v15, s3
-; GFX1250-NEXT: s_clause 0x3
-; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
-; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
-; GFX1250-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v16, v[12:15], s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: constant_zextload_v16i1_to_v16i32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v16, 0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: global_load_u16 v0, v16, s[2:3] nv
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-FAKE16-NEXT: s_and_b32 s6, 0xffff, s2
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x10003
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s4, s2, 0x10001
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s5, s2, 0x10007
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s7, s2, 0x10009
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s8, s2, 0x1000d
+; GFX1250-FAKE16-NEXT: s_and_b32 s9, s2, 1
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s10, s2, 0x1000a
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s2, s2, 0x1000c
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s11, s6, 0x10005
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s12, s6, 0x1000b
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s13, s6, 15
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s14, s6, 0x10002
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s15, s6, 0x10006
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s16, s6, 0x10004
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s17, s6, 0x10008
+; GFX1250-FAKE16-NEXT: s_bfe_u32 s6, s6, 0x1000e
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s13
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v4, s17 :: v_dual_mov_b32 v7, s12
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, s9
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s11
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v14, s14
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v15, s3
+; GFX1250-FAKE16-NEXT: s_clause 0x3
+; GFX1250-FAKE16-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX1250-FAKE16-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX1250-FAKE16-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v16, v[12:15], s[0:1]
+; GFX1250-FAKE16-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: constant_zextload_v16i1_to_v16i32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-REAL16-NEXT: v_mov_b32_e32 v16, 0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: global_load_u16 v0, v16, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-REAL16-NEXT: s_and_b32 s6, 0xffff, s2
+; GFX1250-REAL16-NEXT: s_bfe_u32 s3, s2, 0x10003
+; GFX1250-REAL16-NEXT: s_bfe_u32 s4, s2, 0x10001
+; GFX1250-REAL16-NEXT: s_bfe_u32 s5, s2, 0x10007
+; GFX1250-REAL16-NEXT: s_bfe_u32 s7, s2, 0x10009
+; GFX1250-REAL16-NEXT: s_bfe_u32 s8, s2, 0x1000d
+; GFX1250-REAL16-NEXT: s_and_b32 s9, s2, 1
+; GFX1250-REAL16-NEXT: s_bfe_u32 s10, s2, 0x1000a
+; GFX1250-REAL16-NEXT: s_bfe_u32 s2, s2, 0x1000c
+; GFX1250-REAL16-NEXT: s_bfe_u32 s11, s6, 0x10005
+; GFX1250-REAL16-NEXT: s_bfe_u32 s12, s6, 0x1000b
+; GFX1250-REAL16-NEXT: s_lshr_b32 s13, s6, 15
+; GFX1250-REAL16-NEXT: s_bfe_u32 s14, s6, 0x10002
+; GFX1250-REAL16-NEXT: s_bfe_u32 s15, s6, 0x10006
+; GFX1250-REAL16-NEXT: s_bfe_u32 s16, s6, 0x10004
+; GFX1250-REAL16-NEXT: s_bfe_u32 s17, s6, 0x10008
+; GFX1250-REAL16-NEXT: s_bfe_u32 s6, s6, 0x1000e
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s13
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v4, s17 :: v_dual_mov_b32 v7, s12
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, s9
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s11
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v14, s14
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v15, s3
+; GFX1250-REAL16-NEXT: s_clause 0x3
+; GFX1250-REAL16-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX1250-REAL16-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX1250-REAL16-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX1250-REAL16-NEXT: global_store_b128 v16, v[12:15], s[0:1]
+; GFX1250-REAL16-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = zext <16 x i1> %load to <16 x i32>
store <16 x i32> %ext, ptr addrspace(1) %out
@@ -5089,6 +5139,7 @@ define amdgpu_kernel void @constant_sextload_i1_to_i64(ptr addrspace(1) %out, pt
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u8 s2, s[2:3], 0x0
+; GFX12-NEXT: ; implicit-def: $sgpr3
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX12-NEXT: v_mov_b32_e32 v2, 0
@@ -5103,6 +5154,7 @@ define amdgpu_kernel void @constant_sextload_i1_to_i64(ptr addrspace(1) %out, pt
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0 nv
+; GFX1250-NEXT: ; implicit-def: $sgpr3
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -5255,6 +5307,7 @@ define amdgpu_kernel void @constant_sextload_v1i1_to_v1i64(ptr addrspace(1) %out
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u8 s2, s[2:3], 0x0
+; GFX12-NEXT: ; implicit-def: $sgpr3
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX12-NEXT: v_mov_b32_e32 v2, 0
@@ -5269,6 +5322,7 @@ define amdgpu_kernel void @constant_sextload_v1i1_to_v1i64(ptr addrspace(1) %out
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u8 s2, s[2:3], 0x0 nv
+; GFX1250-NEXT: ; implicit-def: $sgpr3
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -5345,18 +5399,17 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_mov_b32_e32 v3, v1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_u8 v0, v1, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX12-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX12-NEXT: v_and_b32_e32 v2, 1, v0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 1, v0
+; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v2, 0xffff, v3
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
;
@@ -5387,6 +5440,7 @@ define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX1250-REAL16-NEXT: v_mov_b32_e32 v3, v1
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-REAL16-NEXT: s_and_b32 s3, 0xffff, s2
@@ -5470,6 +5524,7 @@ define amdgpu_kernel void @constant_sextload_v2i1_to_v2i64(ptr addrspace(1) %out
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v4, 0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_u8 v0, v4, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5589,6 +5644,7 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX12-NEXT: global_load_d16_u8 v0, v5, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: v_bfe_u32 v2, v0, 1, 1
; GFX12-NEXT: v_dual_mov_b32 v3, v5 :: v_dual_and_b32 v0, 1, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
@@ -5635,6 +5691,7 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX1250-REAL16-NEXT: v_mov_b32_e32 v3, v1
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-REAL16-NEXT: s_and_b32 s3, 0xffff, s2
@@ -5742,6 +5799,7 @@ define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v6, 0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_u8 v0, v6, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5879,6 +5937,7 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX12-NEXT: global_load_d16_u8 v0, v1, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10002
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
@@ -5935,6 +5994,7 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX1250-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_u8 v0, v1, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-REAL16-NEXT: s_and_b32 s3, 0xffff, s2
@@ -6053,6 +6113,7 @@ define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v8, 0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_u8 v0, v8, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -6243,15 +6304,16 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX12-NEXT: v_mov_b32_e32 v15, v1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_u8 v12, v1, s[2:3]
-; GFX12-NEXT: v_mov_b32_e32 v3, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v0, 0xffff, v12
+; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 0xffff, v12
+; GFX12-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX12-NEXT: v_mov_b32_e32 v5, v1
; GFX12-NEXT: v_bfe_u32 v6, v12, 5, 1
; GFX12-NEXT: v_bfe_u32 v4, v12, 4, 1
; GFX12-NEXT: v_bfe_u32 v10, v12, 3, 1
-; GFX12-NEXT: v_bfe_u32 v8, v12, 2, 1
; GFX12-NEXT: v_lshrrev_b32_e32 v2, 7, v0
; GFX12-NEXT: v_bfe_u32 v0, v0, 6, 1
+; GFX12-NEXT: v_bfe_u32 v8, v12, 2, 1
; GFX12-NEXT: v_bfe_u32 v14, v12, 1, 1
; GFX12-NEXT: v_and_b32_e32 v12, 1, v12
; GFX12-NEXT: s_clause 0x3
@@ -6342,22 +6404,28 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX8-LABEL: constant_sextload_v8i1_to_v8i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-NEXT: ; implicit-def: $sgpr5
+; GFX8-NEXT: ; implicit-def: $sgpr7
+; GFX8-NEXT: ; implicit-def: $sgpr9
+; GFX8-NEXT: ; implicit-def: $sgpr11
+; GFX8-NEXT: ; implicit-def: $sgpr13
+; GFX8-NEXT: ; implicit-def: $sgpr15
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: ; implicit-def: $sgpr3
; GFX8-NEXT: v_mov_b32_e32 v17, s1
; GFX8-NEXT: v_mov_b32_e32 v16, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_readfirstlane_b32 s3, v0
-; GFX8-NEXT: s_lshr_b32 s2, s3, 6
-; GFX8-NEXT: s_lshr_b32 s4, s3, 7
-; GFX8-NEXT: s_lshr_b32 s6, s3, 4
-; GFX8-NEXT: s_lshr_b32 s8, s3, 5
-; GFX8-NEXT: s_lshr_b32 s10, s3, 2
-; GFX8-NEXT: s_lshr_b32 s12, s3, 3
-; GFX8-NEXT: s_lshr_b32 s14, s3, 1
-; GFX8-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NEXT: v_readfirstlane_b32 s16, v0
+; GFX8-NEXT: s_lshr_b32 s2, s16, 6
+; GFX8-NEXT: s_lshr_b32 s4, s16, 7
+; GFX8-NEXT: s_lshr_b32 s6, s16, 4
+; GFX8-NEXT: s_lshr_b32 s8, s16, 5
+; GFX8-NEXT: s_lshr_b32 s10, s16, 2
+; GFX8-NEXT: s_lshr_b32 s12, s16, 3
+; GFX8-NEXT: s_lshr_b32 s14, s16, 1
; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
; GFX8-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
@@ -6384,6 +6452,7 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX8-NEXT: v_mov_b32_e32 v11, s9
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
@@ -6455,25 +6524,30 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v16, 0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-NEXT: ; implicit-def: $sgpr5
+; GFX12-NEXT: ; implicit-def: $sgpr7
+; GFX12-NEXT: ; implicit-def: $sgpr9
+; GFX12-NEXT: ; implicit-def: $sgpr11
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: ; implicit-def: $sgpr15
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_u8 v0, v16, s[2:3]
+; GFX12-NEXT: ; implicit-def: $sgpr3
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s3, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_mov_b32_e32 v9, s3
-; GFX12-NEXT: s_lshr_b32 s2, s3, 6
-; GFX12-NEXT: s_lshr_b32 s4, s3, 7
-; GFX12-NEXT: s_lshr_b32 s6, s3, 4
-; GFX12-NEXT: s_lshr_b32 s8, s3, 5
-; GFX12-NEXT: s_lshr_b32 s10, s3, 2
-; GFX12-NEXT: s_lshr_b32 s12, s3, 3
-; GFX12-NEXT: s_lshr_b32 s14, s3, 1
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_readfirstlane_b32 s16, v0
+; GFX12-NEXT: s_lshr_b32 s2, s16, 6
+; GFX12-NEXT: s_lshr_b32 s4, s16, 7
; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v9, s16 :: v_dual_mov_b32 v0, s2
+; GFX12-NEXT: s_lshr_b32 s6, s16, 4
+; GFX12-NEXT: s_lshr_b32 s8, s16, 5
+; GFX12-NEXT: s_lshr_b32 s10, s16, 2
+; GFX12-NEXT: s_lshr_b32 s12, s16, 3
; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_bfe_i32 v12, v9, 0, 1
+; GFX12-NEXT: s_lshr_b32 s14, s16, 1
; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
@@ -6494,46 +6568,100 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX12-NEXT: global_store_b128 v16, v[12:15], s[0:1]
; GFX12-NEXT: s_endpgm
;
-; GFX1250-LABEL: constant_sextload_v8i1_to_v8i64:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v16, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u8 v0, v16, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s3, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_mov_b32_e32 v10, s3
-; GFX1250-NEXT: s_lshr_b32 s2, s3, 6
-; GFX1250-NEXT: s_lshr_b32 s4, s3, 7
-; GFX1250-NEXT: s_lshr_b32 s6, s3, 4
-; GFX1250-NEXT: s_lshr_b32 s8, s3, 5
-; GFX1250-NEXT: s_lshr_b32 s10, s3, 2
-; GFX1250-NEXT: s_lshr_b32 s12, s3, 3
-; GFX1250-NEXT: s_lshr_b32 s14, s3, 1
-; GFX1250-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX1250-NEXT: v_mov_b32_e32 v0, s2
-; GFX1250-NEXT: v_bfe_i32 v12, v10, 0, 1
-; GFX1250-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
-; GFX1250-NEXT: v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s6
-; GFX1250-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
-; GFX1250-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
-; GFX1250-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s12
-; GFX1250-NEXT: v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v14, s14
-; GFX1250-NEXT: v_dual_ashrrev_i32 v13, 31, v12 :: v_dual_mov_b32 v15, s15
-; GFX1250-NEXT: s_clause 0x3
-; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
-; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
-; GFX1250-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v16, v[12:15], s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: constant_sextload_v8i1_to_v8i64:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v16, 0
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr5
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr7
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr9
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr11
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr13
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr15
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: global_load_u8 v0, v16, s[2:3] nv
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr3
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-FAKE16-NEXT: v_readfirstlane_b32 s16, v0
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s2, s16, 6
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s4, s16, 7
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v0, s2
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s6, s16, 4
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s8, s16, 5
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s10, s16, 2
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s12, s16, 3
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v12, v10, 0, 1
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s14, s16, 1
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s6
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s12
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v14, s14
+; GFX1250-FAKE16-NEXT: v_dual_ashrrev_i32 v13, 31, v12 :: v_dual_mov_b32 v15, s15
+; GFX1250-FAKE16-NEXT: s_clause 0x3
+; GFX1250-FAKE16-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX1250-FAKE16-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX1250-FAKE16-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v16, v[12:15], s[0:1]
+; GFX1250-FAKE16-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: constant_sextload_v8i1_to_v8i64:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-REAL16-NEXT: v_mov_b32_e32 v16, 0
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr5
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr7
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr9
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr11
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr13
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr15
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: global_load_u8 v0, v16, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr3
+; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s16, v0
+; GFX1250-REAL16-NEXT: s_lshr_b32 s2, s16, 6
+; GFX1250-REAL16-NEXT: s_lshr_b32 s4, s16, 7
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v0, s2
+; GFX1250-REAL16-NEXT: s_lshr_b32 s6, s16, 4
+; GFX1250-REAL16-NEXT: s_lshr_b32 s8, s16, 5
+; GFX1250-REAL16-NEXT: s_lshr_b32 s10, s16, 2
+; GFX1250-REAL16-NEXT: s_lshr_b32 s12, s16, 3
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX1250-REAL16-NEXT: v_bfe_i32 v12, v10, 0, 1
+; GFX1250-REAL16-NEXT: s_lshr_b32 s14, s16, 1
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s6
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s12
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v14, s14
+; GFX1250-REAL16-NEXT: v_dual_ashrrev_i32 v13, 31, v12 :: v_dual_mov_b32 v15, s15
+; GFX1250-REAL16-NEXT: s_clause 0x3
+; GFX1250-REAL16-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX1250-REAL16-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX1250-REAL16-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX1250-REAL16-NEXT: global_store_b128 v16, v[12:15], s[0:1]
+; GFX1250-REAL16-NEXT: s_endpgm
%load = load <8 x i1>, ptr addrspace(4) %in
%ext = sext <8 x i1> %load to <8 x i64>
store <8 x i64> %ext, ptr addrspace(1) %out
@@ -6768,14 +6896,15 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_b16 v0, v3, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-NEXT: v_and_b32_e32 v6, 0xffff, v0
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000a
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_bfe_u32 v4, v6, 11, 1
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000a
+; GFX12-NEXT: v_bfe_u32 v0, v6, 8, 1
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10009
-; GFX12-NEXT: v_bfe_u32 v0, v6, 8, 1
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000c
; GFX12-NEXT: v_lshrrev_b32_e32 v8, 15, v6
; GFX12-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:80
@@ -6869,6 +6998,7 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX1250-REAL16-NEXT: v_mov_b32_e32 v1, v3
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_u16 v0, v3, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-REAL16-NEXT: s_and_b32 s3, 0xffff, s2
@@ -7001,30 +7131,44 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX8-LABEL: constant_sextload_v16i1_to_v16i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-NEXT: ; implicit-def: $sgpr5
+; GFX8-NEXT: ; implicit-def: $sgpr7
+; GFX8-NEXT: ; implicit-def: $sgpr9
+; GFX8-NEXT: ; implicit-def: $sgpr11
+; GFX8-NEXT: ; implicit-def: $sgpr13
+; GFX8-NEXT: ; implicit-def: $sgpr15
+; GFX8-NEXT: ; implicit-def: $sgpr17
+; GFX8-NEXT: ; implicit-def: $sgpr19
+; GFX8-NEXT: ; implicit-def: $sgpr21
+; GFX8-NEXT: ; implicit-def: $sgpr23
+; GFX8-NEXT: ; implicit-def: $sgpr25
+; GFX8-NEXT: ; implicit-def: $sgpr27
+; GFX8-NEXT: ; implicit-def: $sgpr29
+; GFX8-NEXT: ; implicit-def: $sgpr31
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
+; GFX8-NEXT: ; implicit-def: $sgpr3
; GFX8-NEXT: v_mov_b32_e32 v19, s1
; GFX8-NEXT: v_mov_b32_e32 v18, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_readfirstlane_b32 s3, v0
-; GFX8-NEXT: s_lshr_b32 s2, s3, 14
-; GFX8-NEXT: s_lshr_b32 s4, s3, 15
-; GFX8-NEXT: s_lshr_b32 s6, s3, 12
-; GFX8-NEXT: s_lshr_b32 s8, s3, 13
-; GFX8-NEXT: s_lshr_b32 s10, s3, 10
-; GFX8-NEXT: s_lshr_b32 s12, s3, 11
-; GFX8-NEXT: s_lshr_b32 s14, s3, 8
-; GFX8-NEXT: s_lshr_b32 s16, s3, 9
-; GFX8-NEXT: s_lshr_b32 s18, s3, 6
-; GFX8-NEXT: s_lshr_b32 s20, s3, 7
-; GFX8-NEXT: s_lshr_b32 s22, s3, 4
-; GFX8-NEXT: s_lshr_b32 s24, s3, 5
-; GFX8-NEXT: s_lshr_b32 s26, s3, 2
-; GFX8-NEXT: s_lshr_b32 s28, s3, 3
-; GFX8-NEXT: s_lshr_b32 s30, s3, 1
-; GFX8-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NEXT: v_readfirstlane_b32 s33, v0
+; GFX8-NEXT: s_lshr_b32 s2, s33, 14
+; GFX8-NEXT: s_lshr_b32 s4, s33, 15
+; GFX8-NEXT: s_lshr_b32 s6, s33, 12
+; GFX8-NEXT: s_lshr_b32 s8, s33, 13
+; GFX8-NEXT: s_lshr_b32 s10, s33, 10
+; GFX8-NEXT: s_lshr_b32 s12, s33, 11
+; GFX8-NEXT: s_lshr_b32 s14, s33, 8
+; GFX8-NEXT: s_lshr_b32 s16, s33, 9
+; GFX8-NEXT: s_lshr_b32 s18, s33, 6
+; GFX8-NEXT: s_lshr_b32 s20, s33, 7
+; GFX8-NEXT: s_lshr_b32 s22, s33, 4
+; GFX8-NEXT: s_lshr_b32 s24, s33, 5
+; GFX8-NEXT: s_lshr_b32 s26, s33, 2
+; GFX8-NEXT: s_lshr_b32 s28, s33, 3
+; GFX8-NEXT: s_lshr_b32 s30, s33, 1
; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
; GFX8-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
; GFX8-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
@@ -7095,6 +7239,7 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v13, s25
; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s33
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[10:13]
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
@@ -7203,46 +7348,59 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v32, 0
+; GFX12-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-NEXT: ; implicit-def: $sgpr5
+; GFX12-NEXT: ; implicit-def: $sgpr9
+; GFX12-NEXT: ; implicit-def: $sgpr11
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: ; implicit-def: $sgpr7
+; GFX12-NEXT: ; implicit-def: $sgpr15
+; GFX12-NEXT: ; implicit-def: $sgpr17
+; GFX12-NEXT: ; implicit-def: $sgpr19
+; GFX12-NEXT: ; implicit-def: $sgpr21
+; GFX12-NEXT: ; implicit-def: $sgpr23
+; GFX12-NEXT: ; implicit-def: $sgpr25
+; GFX12-NEXT: ; implicit-def: $sgpr27
+; GFX12-NEXT: ; implicit-def: $sgpr29
+; GFX12-NEXT: ; implicit-def: $sgpr31
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_d16_b16 v0, v32, s[2:3]
+; GFX12-NEXT: ; implicit-def: $sgpr3
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s3, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_mov_b32_e32 v28, s3
-; GFX12-NEXT: s_lshr_b32 s2, s3, 14
-; GFX12-NEXT: s_lshr_b32 s4, s3, 15
-; GFX12-NEXT: s_lshr_b32 s8, s3, 13
-; GFX12-NEXT: s_lshr_b32 s10, s3, 10
-; GFX12-NEXT: s_lshr_b32 s12, s3, 11
-; GFX12-NEXT: s_lshr_b32 s6, s3, 12
-; GFX12-NEXT: s_lshr_b32 s14, s3, 8
-; GFX12-NEXT: s_lshr_b32 s16, s3, 9
-; GFX12-NEXT: s_lshr_b32 s18, s3, 6
-; GFX12-NEXT: s_lshr_b32 s20, s3, 7
-; GFX12-NEXT: s_lshr_b32 s22, s3, 4
-; GFX12-NEXT: s_lshr_b32 s24, s3, 5
-; GFX12-NEXT: s_lshr_b32 s26, s3, 2
-; GFX12-NEXT: s_lshr_b32 s28, s3, 3
-; GFX12-NEXT: s_lshr_b32 s30, s3, 1
+; GFX12-NEXT: v_readfirstlane_b32 s33, v0
+; GFX12-NEXT: s_lshr_b32 s2, s33, 14
+; GFX12-NEXT: s_lshr_b32 s4, s33, 15
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v28, s33 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: s_lshr_b32 s8, s33, 13
+; GFX12-NEXT: s_lshr_b32 s10, s33, 10
+; GFX12-NEXT: s_lshr_b32 s12, s33, 11
+; GFX12-NEXT: s_lshr_b32 s6, s33, 12
+; GFX12-NEXT: s_lshr_b32 s14, s33, 8
+; GFX12-NEXT: s_lshr_b32 s16, s33, 9
+; GFX12-NEXT: s_lshr_b32 s18, s33, 6
+; GFX12-NEXT: s_lshr_b32 s20, s33, 7
; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX12-NEXT: s_lshr_b32 s22, s33, 4
+; GFX12-NEXT: s_lshr_b32 s24, s33, 5
; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX12-NEXT: s_lshr_b32 s26, s33, 2
+; GFX12-NEXT: s_lshr_b32 s28, s33, 3
; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s5
-; GFX12-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
-; GFX12-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
-; GFX12-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v8, s10
-; GFX12-NEXT: v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v10, s12
-; GFX12-NEXT: v_mov_b32_e32 v13, s15
+; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v5, s7
+; GFX12-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v9, s11
+; GFX12-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v11, s13
+; GFX12-NEXT: v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
; GFX12-NEXT: v_bfe_i32 v28, v28, 0, 1
+; GFX12-NEXT: s_lshr_b32 s30, s33, 1
; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
; GFX12-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
; GFX12-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s9
@@ -7271,74 +7429,172 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v32, v[28:31], s[0:1]
; GFX12-NEXT: s_endpgm
;
-; GFX1250-LABEL: constant_sextload_v16i1_to_v16i64:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v32, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v0, v32, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s3, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_mov_b32_e32 v28, s3
-; GFX1250-NEXT: s_lshr_b32 s2, s3, 14
-; GFX1250-NEXT: s_lshr_b32 s4, s3, 15
-; GFX1250-NEXT: s_lshr_b32 s8, s3, 13
-; GFX1250-NEXT: s_lshr_b32 s10, s3, 10
-; GFX1250-NEXT: s_lshr_b32 s12, s3, 11
-; GFX1250-NEXT: s_lshr_b32 s6, s3, 12
-; GFX1250-NEXT: s_lshr_b32 s14, s3, 8
-; GFX1250-NEXT: s_lshr_b32 s16, s3, 9
-; GFX1250-NEXT: s_lshr_b32 s18, s3, 6
-; GFX1250-NEXT: s_lshr_b32 s20, s3, 7
-; GFX1250-NEXT: s_lshr_b32 s22, s3, 4
-; GFX1250-NEXT: s_lshr_b32 s24, s3, 5
-; GFX1250-NEXT: s_lshr_b32 s26, s3, 2
-; GFX1250-NEXT: s_lshr_b32 s28, s3, 3
-; GFX1250-NEXT: s_lshr_b32 s30, s3, 1
-; GFX1250-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX1250-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
-; GFX1250-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s9
-; GFX1250-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11
-; GFX1250-NEXT: v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
-; GFX1250-NEXT: v_mov_b32_e32 v12, s14
-; GFX1250-NEXT: v_bfe_i32 v28, v28, 0, 1
-; GFX1250-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
-; GFX1250-NEXT: v_dual_mov_b32 v13, s15 :: v_dual_mov_b32 v14, s16
-; GFX1250-NEXT: v_dual_mov_b32 v15, s17 :: v_dual_mov_b32 v16, s18
-; GFX1250-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v17, s19 :: v_dual_mov_b32 v18, s20
-; GFX1250-NEXT: v_dual_mov_b32 v19, s21 :: v_dual_mov_b32 v20, s22
-; GFX1250-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v21, s23 :: v_dual_mov_b32 v22, s24
-; GFX1250-NEXT: v_dual_mov_b32 v23, s25 :: v_dual_mov_b32 v24, s26
-; GFX1250-NEXT: v_dual_mov_b32 v25, s27 :: v_dual_mov_b32 v26, s28
-; GFX1250-NEXT: v_dual_mov_b32 v27, s29 :: v_dual_mov_b32 v30, s30
-; GFX1250-NEXT: v_dual_mov_b32 v31, s31 :: v_dual_ashrrev_i32 v29, 31, v28
-; GFX1250-NEXT: s_clause 0x7
-; GFX1250-NEXT: global_store_b128 v32, v[0:3], s[0:1] offset:112
-; GFX1250-NEXT: global_store_b128 v32, v[4:7], s[0:1] offset:96
-; GFX1250-NEXT: global_store_b128 v32, v[8:11], s[0:1] offset:80
-; GFX1250-NEXT: global_store_b128 v32, v[12:15], s[0:1] offset:64
-; GFX1250-NEXT: global_store_b128 v32, v[16:19], s[0:1] offset:48
-; GFX1250-NEXT: global_store_b128 v32, v[20:23], s[0:1] offset:32
-; GFX1250-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v32, v[28:31], s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: constant_sextload_v16i1_to_v16i64:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v32, 0
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr5
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr9
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr11
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr13
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr7
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr15
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr17
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr19
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr21
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr23
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr25
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr27
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr29
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr31
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: global_load_u16 v0, v32, s[2:3] nv
+; GFX1250-FAKE16-NEXT: ; implicit-def: $sgpr3
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-FAKE16-NEXT: v_readfirstlane_b32 s33, v0
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s2, s33, 14
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s4, s33, 15
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v28, s33 :: v_dual_mov_b32 v0, s2
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s8, s33, 13
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s10, s33, 10
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s12, s33, 11
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s6, s33, 12
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s14, s33, 8
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s16, s33, 9
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s18, s33, 6
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s20, s33, 7
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s22, s33, 4
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s24, s33, 5
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s26, s33, 2
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s28, s33, 3
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s6
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s12
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
+; GFX1250-FAKE16-NEXT: v_bfe_i32 v28, v28, 0, 1
+; GFX1250-FAKE16-NEXT: s_lshr_b32 s30, s33, 1
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v13, s15 :: v_dual_mov_b32 v14, s16
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v15, s17 :: v_dual_mov_b32 v16, s18
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v17, s19 :: v_dual_mov_b32 v18, s20
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v19, s21 :: v_dual_mov_b32 v20, s22
+; GFX1250-FAKE16-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v21, s23 :: v_dual_mov_b32 v22, s24
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v23, s25 :: v_dual_mov_b32 v24, s26
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v25, s27 :: v_dual_mov_b32 v26, s28
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v27, s29 :: v_dual_mov_b32 v30, s30
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v31, s31 :: v_dual_ashrrev_i32 v29, 31, v28
+; GFX1250-FAKE16-NEXT: s_clause 0x7
+; GFX1250-FAKE16-NEXT: global_store_b128 v32, v[0:3], s[0:1] offset:112
+; GFX1250-FAKE16-NEXT: global_store_b128 v32, v[4:7], s[0:1] offset:96
+; GFX1250-FAKE16-NEXT: global_store_b128 v32, v[8:11], s[0:1] offset:80
+; GFX1250-FAKE16-NEXT: global_store_b128 v32, v[12:15], s[0:1] offset:64
+; GFX1250-FAKE16-NEXT: global_store_b128 v32, v[16:19], s[0:1] offset:48
+; GFX1250-FAKE16-NEXT: global_store_b128 v32, v[20:23], s[0:1] offset:32
+; GFX1250-FAKE16-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
+; GFX1250-FAKE16-NEXT: global_store_b128 v32, v[28:31], s[0:1]
+; GFX1250-FAKE16-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: constant_sextload_v16i1_to_v16i64:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-REAL16-NEXT: v_mov_b32_e32 v32, 0
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr5
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr9
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr11
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr13
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr7
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr15
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr17
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr19
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr21
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr23
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr25
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr27
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr29
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr31
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: global_load_u16 v0, v32, s[2:3] nv
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $sgpr3
+; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
+; GFX1250-REAL16-NEXT: v_readfirstlane_b32 s33, v0
+; GFX1250-REAL16-NEXT: s_lshr_b32 s2, s33, 14
+; GFX1250-REAL16-NEXT: s_lshr_b32 s4, s33, 15
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v28, s33 :: v_dual_mov_b32 v0, s2
+; GFX1250-REAL16-NEXT: s_lshr_b32 s8, s33, 13
+; GFX1250-REAL16-NEXT: s_lshr_b32 s10, s33, 10
+; GFX1250-REAL16-NEXT: s_lshr_b32 s12, s33, 11
+; GFX1250-REAL16-NEXT: s_lshr_b32 s6, s33, 12
+; GFX1250-REAL16-NEXT: s_lshr_b32 s14, s33, 8
+; GFX1250-REAL16-NEXT: s_lshr_b32 s16, s33, 9
+; GFX1250-REAL16-NEXT: s_lshr_b32 s18, s33, 6
+; GFX1250-REAL16-NEXT: s_lshr_b32 s20, s33, 7
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX1250-REAL16-NEXT: s_lshr_b32 s22, s33, 4
+; GFX1250-REAL16-NEXT: s_lshr_b32 s24, s33, 5
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX1250-REAL16-NEXT: s_lshr_b32 s26, s33, 2
+; GFX1250-REAL16-NEXT: s_lshr_b32 s28, s33, 3
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s6
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, s10
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s12
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
+; GFX1250-REAL16-NEXT: v_bfe_i32 v28, v28, 0, 1
+; GFX1250-REAL16-NEXT: s_lshr_b32 s30, s33, 1
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s8
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v13, s15 :: v_dual_mov_b32 v14, s16
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v15, s17 :: v_dual_mov_b32 v16, s18
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v17, s19 :: v_dual_mov_b32 v18, s20
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v19, s21 :: v_dual_mov_b32 v20, s22
+; GFX1250-REAL16-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v21, s23 :: v_dual_mov_b32 v22, s24
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v23, s25 :: v_dual_mov_b32 v24, s26
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v25, s27 :: v_dual_mov_b32 v26, s28
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v27, s29 :: v_dual_mov_b32 v30, s30
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v31, s31 :: v_dual_ashrrev_i32 v29, 31, v28
+; GFX1250-REAL16-NEXT: s_clause 0x7
+; GFX1250-REAL16-NEXT: global_store_b128 v32, v[0:3], s[0:1] offset:112
+; GFX1250-REAL16-NEXT: global_store_b128 v32, v[4:7], s[0:1] offset:96
+; GFX1250-REAL16-NEXT: global_store_b128 v32, v[8:11], s[0:1] offset:80
+; GFX1250-REAL16-NEXT: global_store_b128 v32, v[12:15], s[0:1] offset:64
+; GFX1250-REAL16-NEXT: global_store_b128 v32, v[16:19], s[0:1] offset:48
+; GFX1250-REAL16-NEXT: global_store_b128 v32, v[20:23], s[0:1] offset:32
+; GFX1250-REAL16-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
+; GFX1250-REAL16-NEXT: global_store_b128 v32, v[28:31], s[0:1]
+; GFX1250-REAL16-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = sext <16 x i1> %load to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
@@ -7945,19 +8201,40 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-LABEL: constant_sextload_v32i1_to_v32i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-NEXT: ; implicit-def: $sgpr45
+; GFX6-NEXT: ; implicit-def: $sgpr43
+; GFX6-NEXT: ; implicit-def: $sgpr41
+; GFX6-NEXT: ; implicit-def: $sgpr39
+; GFX6-NEXT: ; implicit-def: $sgpr23
+; GFX6-NEXT: ; implicit-def: $sgpr19
+; GFX6-NEXT: ; implicit-def: $sgpr37
+; GFX6-NEXT: ; implicit-def: $sgpr35
+; GFX6-NEXT: ; implicit-def: $sgpr31
+; GFX6-NEXT: ; implicit-def: $sgpr29
+; GFX6-NEXT: ; implicit-def: $sgpr27
+; GFX6-NEXT: ; implicit-def: $sgpr25
+; GFX6-NEXT: ; implicit-def: $sgpr7
+; GFX6-NEXT: ; implicit-def: $sgpr9
+; GFX6-NEXT: ; implicit-def: $sgpr11
+; GFX6-NEXT: ; implicit-def: $sgpr13
+; GFX6-NEXT: ; implicit-def: $sgpr15
+; GFX6-NEXT: ; implicit-def: $sgpr17
+; GFX6-NEXT: ; implicit-def: $sgpr21
+; GFX6-NEXT: ; implicit-def: $sgpr5
+; GFX6-NEXT: ; implicit-def: $sgpr47
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s4, s[2:3], 0x0
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshr_b32 s42, s4, 30
-; GFX6-NEXT: s_lshr_b32 s44, s4, 31
+; GFX6-NEXT: s_lshr_b32 s44, s4, 30
+; GFX6-NEXT: s_lshr_b32 s42, s4, 31
; GFX6-NEXT: s_lshr_b32 s40, s4, 28
; GFX6-NEXT: s_lshr_b32 s38, s4, 29
; GFX6-NEXT: s_lshr_b32 s22, s4, 20
-; GFX6-NEXT: s_lshr_b32 s20, s4, 21
-; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX6-NEXT: s_lshr_b32 s18, s4, 21
; GFX6-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
; GFX6-NEXT: s_lshr_b32 s36, s4, 26
; GFX6-NEXT: s_lshr_b32 s34, s4, 27
; GFX6-NEXT: s_lshr_b32 s30, s4, 24
@@ -7966,14 +8243,14 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-NEXT: s_lshr_b32 s24, s4, 23
; GFX6-NEXT: s_lshr_b32 s6, s4, 18
; GFX6-NEXT: s_lshr_b32 s8, s4, 19
-; GFX6-NEXT: v_mov_b32_e32 v0, s42
-; GFX6-NEXT: v_mov_b32_e32 v1, s43
-; GFX6-NEXT: v_mov_b32_e32 v2, s44
-; GFX6-NEXT: v_mov_b32_e32 v3, s45
+; GFX6-NEXT: v_mov_b32_e32 v0, s44
+; GFX6-NEXT: v_mov_b32_e32 v1, s45
+; GFX6-NEXT: v_mov_b32_e32 v2, s42
+; GFX6-NEXT: v_mov_b32_e32 v3, s43
; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
; GFX6-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
; GFX6-NEXT: s_lshr_b32 s10, s4, 16
; GFX6-NEXT: s_lshr_b32 s12, s4, 17
; GFX6-NEXT: v_mov_b32_e32 v4, s40
@@ -7990,8 +8267,8 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s22
; GFX6-NEXT: v_mov_b32_e32 v1, s23
-; GFX6-NEXT: v_mov_b32_e32 v2, s20
-; GFX6-NEXT: v_mov_b32_e32 v3, s21
+; GFX6-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NEXT: v_mov_b32_e32 v3, s19
; GFX6-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
; GFX6-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
; GFX6-NEXT: s_lshr_b32 s14, s4, 14
@@ -8020,8 +8297,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NEXT: v_mov_b32_e32 v3, s9
-; GFX6-NEXT: s_lshr_b32 s18, s4, 12
-; GFX6-NEXT: s_lshr_b32 s42, s4, 13
+; GFX6-NEXT: s_lshr_b32 s20, s4, 12
+; GFX6-NEXT: s_lshr_b32 s44, s4, 13
+; GFX6-NEXT: ; implicit-def: $sgpr45
; GFX6-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
; GFX6-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
@@ -8030,10 +8308,12 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-NEXT: v_mov_b32_e32 v1, s11
; GFX6-NEXT: v_mov_b32_e32 v2, s12
; GFX6-NEXT: v_mov_b32_e32 v3, s13
-; GFX6-NEXT: s_lshr_b32 s44, s4, 10
+; GFX6-NEXT: s_lshr_b32 s42, s4, 10
+; GFX6-NEXT: ; implicit-def: $sgpr43
; GFX6-NEXT: s_lshr_b32 s40, s4, 11
-; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX6-NEXT: ; implicit-def: $sgpr41
+; GFX6-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s14
@@ -8041,27 +8321,33 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-NEXT: v_mov_b32_e32 v2, s16
; GFX6-NEXT: v_mov_b32_e32 v3, s17
; GFX6-NEXT: s_lshr_b32 s38, s4, 8
+; GFX6-NEXT: ; implicit-def: $sgpr39
; GFX6-NEXT: s_lshr_b32 s36, s4, 9
+; GFX6-NEXT: ; implicit-def: $sgpr37
; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s18
-; GFX6-NEXT: v_mov_b32_e32 v1, s19
-; GFX6-NEXT: v_mov_b32_e32 v2, s42
-; GFX6-NEXT: v_mov_b32_e32 v3, s43
+; GFX6-NEXT: v_mov_b32_e32 v0, s20
+; GFX6-NEXT: v_mov_b32_e32 v1, s21
+; GFX6-NEXT: v_mov_b32_e32 v2, s44
+; GFX6-NEXT: v_mov_b32_e32 v3, s45
; GFX6-NEXT: s_lshr_b32 s34, s4, 6
+; GFX6-NEXT: ; implicit-def: $sgpr35
; GFX6-NEXT: s_lshr_b32 s30, s4, 7
+; GFX6-NEXT: ; implicit-def: $sgpr31
; GFX6-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
; GFX6-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s44
-; GFX6-NEXT: v_mov_b32_e32 v1, s45
+; GFX6-NEXT: v_mov_b32_e32 v0, s42
+; GFX6-NEXT: v_mov_b32_e32 v1, s43
; GFX6-NEXT: v_mov_b32_e32 v2, s40
; GFX6-NEXT: v_mov_b32_e32 v3, s41
; GFX6-NEXT: s_lshr_b32 s28, s4, 4
+; GFX6-NEXT: ; implicit-def: $sgpr29
; GFX6-NEXT: s_lshr_b32 s26, s4, 5
+; GFX6-NEXT: ; implicit-def: $sgpr27
; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
; GFX6-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
@@ -8071,7 +8357,9 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-NEXT: v_mov_b32_e32 v2, s36
; GFX6-NEXT: v_mov_b32_e32 v3, s37
; GFX6-NEXT: s_lshr_b32 s24, s4, 2
+; GFX6-NEXT: ; implicit-def: $sgpr25
; GFX6-NEXT: s_lshr_b32 s22, s4, 3
+; GFX6-NEXT: ; implicit-def: $sgpr23
; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
; GFX6-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
@@ -8089,7 +8377,7 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-NEXT: v_mov_b32_e32 v1, s29
; GFX6-NEXT: v_mov_b32_e32 v2, s26
; GFX6-NEXT: v_mov_b32_e32 v3, s27
-; GFX6-NEXT: s_bfe_i64 s[20:21], s[4:5], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[18:19], s[4:5], 0x10000
; GFX6-NEXT: s_bfe_i64 s[4:5], s[46:47], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -8099,8 +8387,8 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX6-NEXT: v_mov_b32_e32 v3, s23
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s20
-; GFX6-NEXT: v_mov_b32_e32 v1, s21
+; GFX6-NEXT: v_mov_b32_e32 v0, s18
+; GFX6-NEXT: v_mov_b32_e32 v1, s19
; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
@@ -8109,27 +8397,59 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-LABEL: constant_sextload_v32i1_to_v32i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-NEXT: ; implicit-def: $sgpr31
+; GFX8-NEXT: ; implicit-def: $sgpr39
+; GFX8-NEXT: ; implicit-def: $sgpr41
+; GFX8-NEXT: ; implicit-def: $sgpr43
+; GFX8-NEXT: ; implicit-def: $sgpr45
+; GFX8-NEXT: ; implicit-def: $sgpr51
+; GFX8-NEXT: ; implicit-def: $sgpr53
+; GFX8-NEXT: ; implicit-def: $sgpr55
+; GFX8-NEXT: ; implicit-def: $sgpr57
+; GFX8-NEXT: ; implicit-def: $sgpr63
+; GFX8-NEXT: ; implicit-def: $sgpr65
+; GFX8-NEXT: ; implicit-def: $sgpr67
+; GFX8-NEXT: ; implicit-def: $sgpr61
+; GFX8-NEXT: ; implicit-def: $sgpr59
+; GFX8-NEXT: ; implicit-def: $sgpr49
+; GFX8-NEXT: ; implicit-def: $sgpr47
+; GFX8-NEXT: ; implicit-def: $sgpr37
+; GFX8-NEXT: ; implicit-def: $sgpr35
+; GFX8-NEXT: ; implicit-def: $sgpr29
+; GFX8-NEXT: ; implicit-def: $sgpr27
+; GFX8-NEXT: ; implicit-def: $sgpr25
+; GFX8-NEXT: ; implicit-def: $sgpr23
+; GFX8-NEXT: ; implicit-def: $sgpr21
+; GFX8-NEXT: ; implicit-def: $sgpr19
+; GFX8-NEXT: ; implicit-def: $sgpr17
+; GFX8-NEXT: ; implicit-def: $sgpr15
+; GFX8-NEXT: ; implicit-def: $sgpr13
+; GFX8-NEXT: ; implicit-def: $sgpr11
+; GFX8-NEXT: ; implicit-def: $sgpr9
+; GFX8-NEXT: ; implicit-def: $sgpr7
+; GFX8-NEXT: ; implicit-def: $sgpr69
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NEXT: ; implicit-def: $sgpr3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_lshr_b32 s44, s2, 30
-; GFX8-NEXT: s_lshr_b32 s46, s2, 31
-; GFX8-NEXT: s_lshr_b32 s48, s2, 28
-; GFX8-NEXT: s_lshr_b32 s50, s2, 29
-; GFX8-NEXT: s_lshr_b32 s52, s2, 26
-; GFX8-NEXT: s_lshr_b32 s54, s2, 27
-; GFX8-NEXT: s_lshr_b32 s56, s2, 24
-; GFX8-NEXT: s_lshr_b32 s58, s2, 25
-; GFX8-NEXT: s_lshr_b32 s60, s2, 22
+; GFX8-NEXT: s_lshr_b32 s30, s2, 30
+; GFX8-NEXT: s_lshr_b32 s38, s2, 31
+; GFX8-NEXT: s_lshr_b32 s40, s2, 28
+; GFX8-NEXT: s_lshr_b32 s42, s2, 29
+; GFX8-NEXT: s_lshr_b32 s44, s2, 26
+; GFX8-NEXT: s_lshr_b32 s50, s2, 27
+; GFX8-NEXT: s_lshr_b32 s52, s2, 24
+; GFX8-NEXT: s_lshr_b32 s54, s2, 25
+; GFX8-NEXT: s_lshr_b32 s56, s2, 22
; GFX8-NEXT: s_lshr_b32 s62, s2, 23
; GFX8-NEXT: s_lshr_b32 s64, s2, 20
; GFX8-NEXT: s_lshr_b32 s66, s2, 21
-; GFX8-NEXT: s_lshr_b32 s42, s2, 18
-; GFX8-NEXT: s_lshr_b32 s40, s2, 19
-; GFX8-NEXT: s_lshr_b32 s38, s2, 16
-; GFX8-NEXT: s_lshr_b32 s36, s2, 17
-; GFX8-NEXT: s_lshr_b32 s34, s2, 14
-; GFX8-NEXT: s_lshr_b32 s30, s2, 15
+; GFX8-NEXT: s_lshr_b32 s60, s2, 18
+; GFX8-NEXT: s_lshr_b32 s58, s2, 19
+; GFX8-NEXT: s_lshr_b32 s48, s2, 16
+; GFX8-NEXT: s_lshr_b32 s46, s2, 17
+; GFX8-NEXT: s_lshr_b32 s36, s2, 14
+; GFX8-NEXT: s_lshr_b32 s34, s2, 15
; GFX8-NEXT: s_lshr_b32 s28, s2, 12
; GFX8-NEXT: s_lshr_b32 s26, s2, 13
; GFX8-NEXT: s_lshr_b32 s24, s2, 10
@@ -8157,106 +8477,103 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX8-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
; GFX8-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
; GFX8-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
; GFX8-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
; GFX8-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
; GFX8-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
; GFX8-NEXT: s_bfe_i64 s[64:65], s[64:65], 0x10000
; GFX8-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x10000
; GFX8-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
; GFX8-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
; GFX8-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
; GFX8-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
; GFX8-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX8-NEXT: v_mov_b32_e32 v0, s30
+; GFX8-NEXT: s_add_u32 s30, s0, 0xf0
+; GFX8-NEXT: v_mov_b32_e32 v1, s31
+; GFX8-NEXT: s_addc_u32 s31, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
+; GFX8-NEXT: v_mov_b32_e32 v2, s38
+; GFX8-NEXT: v_mov_b32_e32 v3, s39
+; GFX8-NEXT: v_mov_b32_e32 v5, s31
+; GFX8-NEXT: s_add_u32 s30, s0, 0xe0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_addc_u32 s31, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
+; GFX8-NEXT: v_mov_b32_e32 v0, s40
+; GFX8-NEXT: v_mov_b32_e32 v1, s41
+; GFX8-NEXT: v_mov_b32_e32 v2, s42
+; GFX8-NEXT: v_mov_b32_e32 v3, s43
+; GFX8-NEXT: v_mov_b32_e32 v5, s31
+; GFX8-NEXT: s_add_u32 s30, s0, 0xd0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_addc_u32 s31, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NEXT: v_mov_b32_e32 v0, s44
-; GFX8-NEXT: s_add_u32 s44, s0, 0xf0
; GFX8-NEXT: v_mov_b32_e32 v1, s45
-; GFX8-NEXT: s_addc_u32 s45, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s44
-; GFX8-NEXT: v_mov_b32_e32 v2, s46
-; GFX8-NEXT: v_mov_b32_e32 v3, s47
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xe0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: s_addc_u32 s45, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s44
-; GFX8-NEXT: v_mov_b32_e32 v0, s48
-; GFX8-NEXT: v_mov_b32_e32 v1, s49
; GFX8-NEXT: v_mov_b32_e32 v2, s50
; GFX8-NEXT: v_mov_b32_e32 v3, s51
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xd0
+; GFX8-NEXT: v_mov_b32_e32 v5, s31
+; GFX8-NEXT: s_add_u32 s30, s0, 0xc0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: s_addc_u32 s45, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NEXT: s_addc_u32 s31, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NEXT: v_mov_b32_e32 v0, s52
; GFX8-NEXT: v_mov_b32_e32 v1, s53
; GFX8-NEXT: v_mov_b32_e32 v2, s54
; GFX8-NEXT: v_mov_b32_e32 v3, s55
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xc0
+; GFX8-NEXT: v_mov_b32_e32 v5, s31
+; GFX8-NEXT: s_add_u32 s30, s0, 0xb0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: s_addc_u32 s45, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NEXT: s_addc_u32 s31, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NEXT: v_mov_b32_e32 v0, s56
; GFX8-NEXT: v_mov_b32_e32 v1, s57
-; GFX8-NEXT: v_mov_b32_e32 v2, s58
-; GFX8-NEXT: v_mov_b32_e32 v3, s59
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xb0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: s_addc_u32 s45, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s44
-; GFX8-NEXT: v_mov_b32_e32 v0, s60
-; GFX8-NEXT: v_mov_b32_e32 v1, s61
; GFX8-NEXT: v_mov_b32_e32 v2, s62
; GFX8-NEXT: v_mov_b32_e32 v3, s63
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NEXT: s_add_u32 s44, s0, 0xa0
+; GFX8-NEXT: v_mov_b32_e32 v5, s31
+; GFX8-NEXT: s_add_u32 s30, s0, 0xa0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: s_addc_u32 s45, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NEXT: s_addc_u32 s31, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
; GFX8-NEXT: v_mov_b32_e32 v0, s64
; GFX8-NEXT: v_mov_b32_e32 v1, s65
; GFX8-NEXT: v_mov_b32_e32 v2, s66
; GFX8-NEXT: v_mov_b32_e32 v3, s67
-; GFX8-NEXT: v_mov_b32_e32 v5, s45
+; GFX8-NEXT: v_mov_b32_e32 v5, s31
+; GFX8-NEXT: s_add_u32 s30, s0, 0x90
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: s_nop 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s40
-; GFX8-NEXT: s_add_u32 s40, s0, 0x90
-; GFX8-NEXT: v_mov_b32_e32 v3, s41
-; GFX8-NEXT: s_addc_u32 s41, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s40
-; GFX8-NEXT: v_mov_b32_e32 v0, s42
-; GFX8-NEXT: v_mov_b32_e32 v1, s43
-; GFX8-NEXT: v_mov_b32_e32 v5, s41
+; GFX8-NEXT: s_addc_u32 s31, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
+; GFX8-NEXT: v_mov_b32_e32 v0, s60
+; GFX8-NEXT: v_mov_b32_e32 v1, s61
+; GFX8-NEXT: v_mov_b32_e32 v2, s58
+; GFX8-NEXT: v_mov_b32_e32 v3, s59
+; GFX8-NEXT: v_mov_b32_e32 v5, s31
+; GFX8-NEXT: s_add_u32 s30, s0, 0x80
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: s_nop 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s36
-; GFX8-NEXT: s_add_u32 s36, s0, 0x80
-; GFX8-NEXT: v_mov_b32_e32 v3, s37
-; GFX8-NEXT: s_addc_u32 s37, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v4, s36
-; GFX8-NEXT: v_mov_b32_e32 v0, s38
-; GFX8-NEXT: v_mov_b32_e32 v1, s39
-; GFX8-NEXT: v_mov_b32_e32 v5, s37
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: s_nop 0
-; GFX8-NEXT: v_mov_b32_e32 v2, s30
+; GFX8-NEXT: s_addc_u32 s31, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s30
+; GFX8-NEXT: v_mov_b32_e32 v0, s48
+; GFX8-NEXT: v_mov_b32_e32 v1, s49
+; GFX8-NEXT: v_mov_b32_e32 v2, s46
+; GFX8-NEXT: v_mov_b32_e32 v3, s47
+; GFX8-NEXT: v_mov_b32_e32 v5, s31
; GFX8-NEXT: s_add_u32 s30, s0, 0x70
-; GFX8-NEXT: v_mov_b32_e32 v3, s31
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s31, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s30
-; GFX8-NEXT: v_mov_b32_e32 v0, s34
-; GFX8-NEXT: v_mov_b32_e32 v1, s35
+; GFX8-NEXT: v_mov_b32_e32 v0, s36
+; GFX8-NEXT: v_mov_b32_e32 v1, s37
+; GFX8-NEXT: v_mov_b32_e32 v2, s34
+; GFX8-NEXT: v_mov_b32_e32 v3, s35
; GFX8-NEXT: v_mov_b32_e32 v5, s31
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_nop 0
@@ -8500,92 +8817,124 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX12-LABEL: constant_sextload_v32i1_to_v32i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: ; implicit-def: $sgpr15
+; GFX12-NEXT: ; implicit-def: $sgpr19
+; GFX12-NEXT: ; implicit-def: $sgpr21
+; GFX12-NEXT: ; implicit-def: $sgpr27
+; GFX12-NEXT: ; implicit-def: $sgpr29
+; GFX12-NEXT: ; implicit-def: $sgpr35
+; GFX12-NEXT: ; implicit-def: $sgpr39
+; GFX12-NEXT: ; implicit-def: $sgpr41
+; GFX12-NEXT: ; implicit-def: $sgpr11
+; GFX12-NEXT: ; implicit-def: $sgpr47
+; GFX12-NEXT: ; implicit-def: $sgpr49
+; GFX12-NEXT: ; implicit-def: $sgpr51
+; GFX12-NEXT: ; implicit-def: $sgpr55
+; GFX12-NEXT: ; implicit-def: $sgpr59
+; GFX12-NEXT: ; implicit-def: $sgpr61
+; GFX12-NEXT: ; implicit-def: $sgpr63
+; GFX12-NEXT: ; implicit-def: $sgpr65
+; GFX12-NEXT: ; implicit-def: $sgpr67
+; GFX12-NEXT: ; implicit-def: $sgpr57
+; GFX12-NEXT: ; implicit-def: $sgpr53
+; GFX12-NEXT: ; implicit-def: $sgpr45
+; GFX12-NEXT: ; implicit-def: $sgpr43
+; GFX12-NEXT: ; implicit-def: $sgpr37
+; GFX12-NEXT: ; implicit-def: $sgpr31
+; GFX12-NEXT: ; implicit-def: $sgpr25
+; GFX12-NEXT: ; implicit-def: $sgpr23
+; GFX12-NEXT: ; implicit-def: $sgpr17
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: ; implicit-def: $sgpr9
+; GFX12-NEXT: ; implicit-def: $sgpr7
+; GFX12-NEXT: ; implicit-def: $sgpr69
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX12-NEXT: ; implicit-def: $sgpr3
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s34, s2, 30
-; GFX12-NEXT: s_lshr_b32 s36, s2, 31
-; GFX12-NEXT: s_lshr_b32 s38, s2, 28
-; GFX12-NEXT: s_lshr_b32 s40, s2, 29
-; GFX12-NEXT: s_lshr_b32 s42, s2, 26
-; GFX12-NEXT: s_lshr_b32 s44, s2, 27
+; GFX12-NEXT: s_lshr_b32 s14, s2, 30
+; GFX12-NEXT: s_lshr_b32 s18, s2, 31
+; GFX12-NEXT: s_lshr_b32 s20, s2, 28
+; GFX12-NEXT: s_lshr_b32 s26, s2, 29
+; GFX12-NEXT: s_lshr_b32 s28, s2, 26
+; GFX12-NEXT: s_lshr_b32 s34, s2, 27
+; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX12-NEXT: s_lshr_b32 s38, s2, 24
+; GFX12-NEXT: s_lshr_b32 s40, s2, 25
+; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s15
; GFX12-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
-; GFX12-NEXT: s_lshr_b32 s46, s2, 24
-; GFX12-NEXT: s_lshr_b32 s48, s2, 25
+; GFX12-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v0, s14 :: v_dual_mov_b32 v3, s19
+; GFX12-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v5, s21
+; GFX12-NEXT: s_lshr_b32 s10, s2, 22
+; GFX12-NEXT: s_lshr_b32 s46, s2, 23
; GFX12-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
; GFX12-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s35
-; GFX12-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v0, s34 :: v_dual_mov_b32 v3, s37
-; GFX12-NEXT: v_dual_mov_b32 v2, s36 :: v_dual_mov_b32 v5, s39
-; GFX12-NEXT: s_lshr_b32 s26, s2, 22
-; GFX12-NEXT: s_lshr_b32 s50, s2, 23
-; GFX12-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v4, s38 :: v_dual_mov_b32 v7, s41
-; GFX12-NEXT: v_dual_mov_b32 v6, s40 :: v_dual_mov_b32 v9, s43
-; GFX12-NEXT: s_lshr_b32 s52, s2, 20
-; GFX12-NEXT: s_lshr_b32 s54, s2, 21
-; GFX12-NEXT: v_dual_mov_b32 v8, s42 :: v_dual_mov_b32 v11, s45
-; GFX12-NEXT: v_dual_mov_b32 v10, s44 :: v_dual_mov_b32 v13, s47
-; GFX12-NEXT: s_lshr_b32 s56, s2, 18
+; GFX12-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v7, s27
+; GFX12-NEXT: v_dual_mov_b32 v6, s26 :: v_dual_mov_b32 v9, s29
+; GFX12-NEXT: s_lshr_b32 s48, s2, 20
+; GFX12-NEXT: s_lshr_b32 s50, s2, 21
+; GFX12-NEXT: v_dual_mov_b32 v8, s28 :: v_dual_mov_b32 v11, s35
+; GFX12-NEXT: v_dual_mov_b32 v10, s34 :: v_dual_mov_b32 v13, s39
+; GFX12-NEXT: s_lshr_b32 s54, s2, 18
; GFX12-NEXT: s_lshr_b32 s58, s2, 19
-; GFX12-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v12, s46 :: v_dual_mov_b32 v15, s49
-; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX12-NEXT: v_mov_b32_e32 v14, s48
+; GFX12-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v12, s38 :: v_dual_mov_b32 v15, s41
+; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX12-NEXT: v_mov_b32_e32 v14, s40
; GFX12-NEXT: s_lshr_b32 s60, s2, 16
; GFX12-NEXT: s_lshr_b32 s62, s2, 17
-; GFX12-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
; GFX12-NEXT: s_lshr_b32 s64, s2, 14
; GFX12-NEXT: s_lshr_b32 s66, s2, 15
; GFX12-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
; GFX12-NEXT: s_clause 0x3
; GFX12-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:240
; GFX12-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:224
; GFX12-NEXT: global_store_b128 v24, v[8:11], s[0:1] offset:208
; GFX12-NEXT: global_store_b128 v24, v[12:15], s[0:1] offset:192
-; GFX12-NEXT: v_dual_mov_b32 v0, s26 :: v_dual_mov_b32 v3, s51
-; GFX12-NEXT: v_dual_mov_b32 v1, s27 :: v_dual_mov_b32 v2, s50
-; GFX12-NEXT: v_mov_b32_e32 v5, s53
-; GFX12-NEXT: s_lshr_b32 s30, s2, 12
-; GFX12-NEXT: s_lshr_b32 s28, s2, 13
-; GFX12-NEXT: s_lshr_b32 s24, s2, 10
-; GFX12-NEXT: s_lshr_b32 s22, s2, 11
+; GFX12-NEXT: v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v3, s47
+; GFX12-NEXT: v_dual_mov_b32 v1, s11 :: v_dual_mov_b32 v2, s46
+; GFX12-NEXT: v_mov_b32_e32 v5, s49
+; GFX12-NEXT: s_lshr_b32 s56, s2, 12
+; GFX12-NEXT: s_lshr_b32 s52, s2, 13
+; GFX12-NEXT: s_lshr_b32 s44, s2, 10
+; GFX12-NEXT: s_lshr_b32 s42, s2, 11
; GFX12-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
; GFX12-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v4, s52 :: v_dual_mov_b32 v7, s55
-; GFX12-NEXT: v_dual_mov_b32 v6, s54 :: v_dual_mov_b32 v9, s57
-; GFX12-NEXT: s_lshr_b32 s20, s2, 8
-; GFX12-NEXT: s_lshr_b32 s18, s2, 9
+; GFX12-NEXT: v_dual_mov_b32 v4, s48 :: v_dual_mov_b32 v7, s51
+; GFX12-NEXT: v_dual_mov_b32 v6, s50 :: v_dual_mov_b32 v9, s55
+; GFX12-NEXT: s_lshr_b32 s36, s2, 8
+; GFX12-NEXT: s_lshr_b32 s30, s2, 9
; GFX12-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
; GFX12-NEXT: s_bfe_i64 s[64:65], s[64:65], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v8, s56 :: v_dual_mov_b32 v11, s59
+; GFX12-NEXT: v_dual_mov_b32 v8, s54 :: v_dual_mov_b32 v11, s59
; GFX12-NEXT: v_dual_mov_b32 v10, s58 :: v_dual_mov_b32 v13, s61
-; GFX12-NEXT: s_lshr_b32 s16, s2, 6
-; GFX12-NEXT: s_lshr_b32 s14, s2, 7
-; GFX12-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX12-NEXT: s_lshr_b32 s24, s2, 6
+; GFX12-NEXT: s_lshr_b32 s22, s2, 7
+; GFX12-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
; GFX12-NEXT: v_dual_mov_b32 v12, s60 :: v_dual_mov_b32 v15, s63
; GFX12-NEXT: v_dual_mov_b32 v14, s62 :: v_dual_mov_b32 v17, s65
-; GFX12-NEXT: s_lshr_b32 s12, s2, 4
-; GFX12-NEXT: s_lshr_b32 s10, s2, 5
-; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX12-NEXT: s_lshr_b32 s16, s2, 4
+; GFX12-NEXT: s_lshr_b32 s12, s2, 5
+; GFX12-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
; GFX12-NEXT: v_dual_mov_b32 v16, s64 :: v_dual_mov_b32 v19, s67
-; GFX12-NEXT: v_dual_mov_b32 v18, s66 :: v_dual_mov_b32 v21, s31
+; GFX12-NEXT: v_dual_mov_b32 v18, s66 :: v_dual_mov_b32 v21, s57
; GFX12-NEXT: s_lshr_b32 s8, s2, 2
; GFX12-NEXT: s_lshr_b32 s6, s2, 3
-; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v20, s30 :: v_dual_mov_b32 v23, s29
-; GFX12-NEXT: v_mov_b32_e32 v22, s28
+; GFX12-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v20, s56 :: v_dual_mov_b32 v23, s53
+; GFX12-NEXT: v_mov_b32_e32 v22, s52
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:176
; GFX12-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:160
@@ -8593,22 +8942,22 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v24, v[12:15], s[0:1] offset:128
; GFX12-NEXT: global_store_b128 v24, v[16:19], s[0:1] offset:112
; GFX12-NEXT: global_store_b128 v24, v[20:23], s[0:1] offset:96
-; GFX12-NEXT: v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v3, s23
-; GFX12-NEXT: v_dual_mov_b32 v1, s25 :: v_dual_mov_b32 v2, s22
-; GFX12-NEXT: v_mov_b32_e32 v5, s21
+; GFX12-NEXT: v_dual_mov_b32 v0, s44 :: v_dual_mov_b32 v3, s43
+; GFX12-NEXT: v_dual_mov_b32 v1, s45 :: v_dual_mov_b32 v2, s42
+; GFX12-NEXT: v_mov_b32_e32 v5, s37
; GFX12-NEXT: s_lshr_b32 s68, s2, 1
-; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v7, s19
-; GFX12-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v9, s17
+; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v4, s36 :: v_dual_mov_b32 v7, s31
+; GFX12-NEXT: v_dual_mov_b32 v6, s30 :: v_dual_mov_b32 v9, s25
; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v11, s15
-; GFX12-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v13, s13
+; GFX12-NEXT: v_dual_mov_b32 v8, s24 :: v_dual_mov_b32 v11, s23
+; GFX12-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v13, s17
; GFX12-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
; GFX12-NEXT: s_bfe_i64 s[2:3], s[68:69], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v15, s11
-; GFX12-NEXT: v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v17, s9
+; GFX12-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v15, s13
+; GFX12-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v17, s9
; GFX12-NEXT: v_dual_mov_b32 v16, s8 :: v_dual_mov_b32 v19, s7
; GFX12-NEXT: v_dual_mov_b32 v18, s6 :: v_dual_mov_b32 v21, s5
; GFX12-NEXT: v_dual_mov_b32 v20, s4 :: v_dual_mov_b32 v23, s3
@@ -8626,136 +8975,168 @@ define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: ; implicit-def: $sgpr15
+; GFX1250-NEXT: ; implicit-def: $sgpr19
+; GFX1250-NEXT: ; implicit-def: $sgpr21
+; GFX1250-NEXT: ; implicit-def: $sgpr27
+; GFX1250-NEXT: ; implicit-def: $sgpr29
+; GFX1250-NEXT: ; implicit-def: $sgpr35
+; GFX1250-NEXT: ; implicit-def: $sgpr39
+; GFX1250-NEXT: ; implicit-def: $sgpr41
+; GFX1250-NEXT: ; implicit-def: $sgpr11
+; GFX1250-NEXT: ; implicit-def: $sgpr47
+; GFX1250-NEXT: ; implicit-def: $sgpr49
+; GFX1250-NEXT: ; implicit-def: $sgpr51
+; GFX1250-NEXT: ; implicit-def: $sgpr55
+; GFX1250-NEXT: ; implicit-def: $sgpr59
+; GFX1250-NEXT: ; implicit-def: $sgpr61
+; GFX1250-NEXT: ; implicit-def: $sgpr63
+; GFX1250-NEXT: ; implicit-def: $sgpr65
+; GFX1250-NEXT: ; implicit-def: $sgpr67
+; GFX1250-NEXT: ; implicit-def: $sgpr57
+; GFX1250-NEXT: ; implicit-def: $sgpr53
+; GFX1250-NEXT: ; implicit-def: $sgpr45
+; GFX1250-NEXT: ; implicit-def: $sgpr43
+; GFX1250-NEXT: ; implicit-def: $sgpr37
+; GFX1250-NEXT: ; implicit-def: $sgpr31
+; GFX1250-NEXT: ; implicit-def: $sgpr25
+; GFX1250-NEXT: ; implicit-def: $sgpr23
+; GFX1250-NEXT: ; implicit-def: $sgpr17
+; GFX1250-NEXT: ; implicit-def: $sgpr13
+; GFX1250-NEXT: ; implicit-def: $sgpr9
+; GFX1250-NEXT: ; implicit-def: $sgpr7
+; GFX1250-NEXT: ; implicit-def: $sgpr69
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0 nv
+; GFX1250-NEXT: ; implicit-def: $sgpr3
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s34, s2, 30
-; GFX1250-NEXT: s_lshr_b32 s36, s2, 31
-; GFX1250-NEXT: s_lshr_b32 s38, s2, 28
-; GFX1250-NEXT: s_lshr_b32 s40, s2, 29
-; GFX1250-NEXT: s_lshr_b32 s42, s2, 26
-; GFX1250-NEXT: s_lshr_b32 s44, s2, 27
+; GFX1250-NEXT: s_lshr_b32 s14, s2, 30
+; GFX1250-NEXT: s_lshr_b32 s18, s2, 31
+; GFX1250-NEXT: s_lshr_b32 s20, s2, 28
+; GFX1250-NEXT: s_lshr_b32 s26, s2, 29
+; GFX1250-NEXT: s_lshr_b32 s28, s2, 26
+; GFX1250-NEXT: s_lshr_b32 s34, s2, 27
+; GFX1250-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX1250-NEXT: s_lshr_b32 s38, s2, 24
+; GFX1250-NEXT: s_lshr_b32 s40, s2, 25
+; GFX1250-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v2, s14
; GFX1250-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s46, s2, 24
-; GFX1250-NEXT: s_lshr_b32 s48, s2, 25
+; GFX1250-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v3, s15 :: v_dual_mov_b32 v4, s18
+; GFX1250-NEXT: v_dual_mov_b32 v5, s19 :: v_dual_mov_b32 v6, s20
+; GFX1250-NEXT: s_lshr_b32 s10, s2, 22
+; GFX1250-NEXT: s_lshr_b32 s46, s2, 23
; GFX1250-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v0, s34
-; GFX1250-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v1, s35 :: v_dual_mov_b32 v2, s36
-; GFX1250-NEXT: v_dual_mov_b32 v3, s37 :: v_dual_mov_b32 v4, s38
-; GFX1250-NEXT: s_lshr_b32 s26, s2, 22
-; GFX1250-NEXT: s_lshr_b32 s50, s2, 23
-; GFX1250-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s39 :: v_dual_mov_b32 v6, s40
-; GFX1250-NEXT: v_dual_mov_b32 v7, s41 :: v_dual_mov_b32 v8, s42
-; GFX1250-NEXT: s_lshr_b32 s52, s2, 20
-; GFX1250-NEXT: s_lshr_b32 s54, s2, 21
-; GFX1250-NEXT: v_dual_mov_b32 v9, s43 :: v_dual_mov_b32 v10, s44
-; GFX1250-NEXT: v_dual_mov_b32 v11, s45 :: v_dual_mov_b32 v12, s46
-; GFX1250-NEXT: s_lshr_b32 s56, s2, 18
+; GFX1250-NEXT: v_dual_mov_b32 v7, s21 :: v_dual_mov_b32 v8, s26
+; GFX1250-NEXT: v_dual_mov_b32 v9, s27 :: v_dual_mov_b32 v10, s28
+; GFX1250-NEXT: s_lshr_b32 s48, s2, 20
+; GFX1250-NEXT: s_lshr_b32 s50, s2, 21
+; GFX1250-NEXT: v_dual_mov_b32 v11, s29 :: v_dual_mov_b32 v12, s34
+; GFX1250-NEXT: v_dual_mov_b32 v13, s35 :: v_dual_mov_b32 v14, s38
+; GFX1250-NEXT: s_lshr_b32 s54, s2, 18
; GFX1250-NEXT: s_lshr_b32 s58, s2, 19
-; GFX1250-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v13, s47 :: v_dual_mov_b32 v14, s48
-; GFX1250-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX1250-NEXT: v_mov_b32_e32 v15, s49
+; GFX1250-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v15, s39 :: v_dual_mov_b32 v16, s40
+; GFX1250-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX1250-NEXT: v_mov_b32_e32 v17, s41
; GFX1250-NEXT: s_lshr_b32 s60, s2, 16
; GFX1250-NEXT: s_lshr_b32 s62, s2, 17
-; GFX1250-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
; GFX1250-NEXT: s_lshr_b32 s64, s2, 14
; GFX1250-NEXT: s_lshr_b32 s66, s2, 15
; GFX1250-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
; GFX1250-NEXT: s_clause 0x3
-; GFX1250-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:240
-; GFX1250-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:224
-; GFX1250-NEXT: global_store_b128 v24, v[8:11], s[0:1] offset:208
-; GFX1250-NEXT: global_store_b128 v24, v[12:15], s[0:1] offset:192
+; GFX1250-NEXT: global_store_b128 v0, v[2:5], s[0:1] offset:240
+; GFX1250-NEXT: global_store_b128 v0, v[6:9], s[0:1] offset:224
+; GFX1250-NEXT: global_store_b128 v0, v[10:13], s[0:1] offset:208
+; GFX1250-NEXT: global_store_b128 v0, v[14:17], s[0:1] offset:192
; GFX1250-NEXT: s_wait_xcnt 0x3
-; GFX1250-NEXT: v_dual_mov_b32 v0, s26 :: v_dual_mov_b32 v1, s27
-; GFX1250-NEXT: v_dual_mov_b32 v2, s50 :: v_dual_mov_b32 v3, s51
+; GFX1250-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
+; GFX1250-NEXT: v_dual_mov_b32 v4, s46 :: v_dual_mov_b32 v5, s47
; GFX1250-NEXT: s_wait_xcnt 0x2
-; GFX1250-NEXT: v_mov_b32_e32 v4, s52
-; GFX1250-NEXT: s_lshr_b32 s30, s2, 12
-; GFX1250-NEXT: s_lshr_b32 s28, s2, 13
-; GFX1250-NEXT: s_lshr_b32 s24, s2, 10
-; GFX1250-NEXT: s_lshr_b32 s22, s2, 11
+; GFX1250-NEXT: v_mov_b32_e32 v6, s48
+; GFX1250-NEXT: s_lshr_b32 s56, s2, 12
+; GFX1250-NEXT: s_lshr_b32 s52, s2, 13
+; GFX1250-NEXT: s_lshr_b32 s44, s2, 10
+; GFX1250-NEXT: s_lshr_b32 s42, s2, 11
; GFX1250-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s53 :: v_dual_mov_b32 v6, s54
+; GFX1250-NEXT: v_dual_mov_b32 v7, s49 :: v_dual_mov_b32 v8, s50
; GFX1250-NEXT: s_wait_xcnt 0x1
-; GFX1250-NEXT: v_dual_mov_b32 v7, s55 :: v_dual_mov_b32 v8, s56
-; GFX1250-NEXT: s_lshr_b32 s20, s2, 8
-; GFX1250-NEXT: s_lshr_b32 s18, s2, 9
+; GFX1250-NEXT: v_dual_mov_b32 v9, s51 :: v_dual_mov_b32 v10, s54
+; GFX1250-NEXT: s_lshr_b32 s36, s2, 8
+; GFX1250-NEXT: s_lshr_b32 s30, s2, 9
; GFX1250-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[64:65], s[64:65], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v9, s57 :: v_dual_mov_b32 v10, s58
+; GFX1250-NEXT: v_dual_mov_b32 v11, s55 :: v_dual_mov_b32 v12, s58
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v11, s59 :: v_dual_mov_b32 v12, s60
-; GFX1250-NEXT: s_lshr_b32 s16, s2, 6
-; GFX1250-NEXT: s_lshr_b32 s14, s2, 7
-; GFX1250-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v13, s59 :: v_dual_mov_b32 v14, s60
+; GFX1250-NEXT: s_lshr_b32 s24, s2, 6
+; GFX1250-NEXT: s_lshr_b32 s22, s2, 7
+; GFX1250-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v15, s61 :: v_dual_mov_b32 v16, s62
+; GFX1250-NEXT: v_dual_mov_b32 v17, s63 :: v_dual_mov_b32 v18, s64
+; GFX1250-NEXT: s_lshr_b32 s16, s2, 4
+; GFX1250-NEXT: s_lshr_b32 s12, s2, 5
; GFX1250-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v13, s61 :: v_dual_mov_b32 v14, s62
-; GFX1250-NEXT: v_dual_mov_b32 v15, s63 :: v_dual_mov_b32 v16, s64
-; GFX1250-NEXT: s_lshr_b32 s12, s2, 4
-; GFX1250-NEXT: s_lshr_b32 s10, s2, 5
-; GFX1250-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v17, s65 :: v_dual_mov_b32 v18, s66
-; GFX1250-NEXT: v_dual_mov_b32 v19, s67 :: v_dual_mov_b32 v20, s30
+; GFX1250-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v19, s65 :: v_dual_mov_b32 v20, s66
+; GFX1250-NEXT: v_dual_mov_b32 v21, s67 :: v_dual_mov_b32 v22, s56
; GFX1250-NEXT: s_lshr_b32 s8, s2, 2
; GFX1250-NEXT: s_lshr_b32 s6, s2, 3
-; GFX1250-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v21, s31 :: v_dual_mov_b32 v22, s28
-; GFX1250-NEXT: v_mov_b32_e32 v23, s29
+; GFX1250-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v23, s57 :: v_dual_mov_b32 v24, s52
+; GFX1250-NEXT: v_mov_b32_e32 v25, s53
; GFX1250-NEXT: s_clause 0x5
-; GFX1250-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:176
-; GFX1250-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:160
-; GFX1250-NEXT: global_store_b128 v24, v[8:11], s[0:1] offset:144
-; GFX1250-NEXT: global_store_b128 v24, v[12:15], s[0:1] offset:128
-; GFX1250-NEXT: global_store_b128 v24, v[16:19], s[0:1] offset:112
-; GFX1250-NEXT: global_store_b128 v24, v[20:23], s[0:1] offset:96
+; GFX1250-NEXT: global_store_b128 v0, v[2:5], s[0:1] offset:176
+; GFX1250-NEXT: global_store_b128 v0, v[6:9], s[0:1] offset:160
+; GFX1250-NEXT: global_store_b128 v0, v[10:13], s[0:1] offset:144
+; GFX1250-NEXT: global_store_b128 v0, v[14:17], s[0:1] offset:128
+; GFX1250-NEXT: global_store_b128 v0, v[18:21], s[0:1] offset:112
+; GFX1250-NEXT: global_store_b128 v0, v[22:25], s[0:1] offset:96
; GFX1250-NEXT: s_wait_xcnt 0x5
-; GFX1250-NEXT: v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v1, s25
-; GFX1250-NEXT: v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v3, s23
+; GFX1250-NEXT: v_dual_mov_b32 v2, s44 :: v_dual_mov_b32 v3, s45
+; GFX1250-NEXT: v_dual_mov_b32 v4, s42 :: v_dual_mov_b32 v5, s43
; GFX1250-NEXT: s_wait_xcnt 0x4
-; GFX1250-NEXT: v_mov_b32_e32 v4, s20
+; GFX1250-NEXT: v_mov_b32_e32 v6, s36
; GFX1250-NEXT: s_lshr_b32 s68, s2, 1
-; GFX1250-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s21 :: v_dual_mov_b32 v6, s18
+; GFX1250-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v7, s37 :: v_dual_mov_b32 v8, s30
; GFX1250-NEXT: s_wait_xcnt 0x3
-; GFX1250-NEXT: v_dual_mov_b32 v7, s19 :: v_dual_mov_b32 v8, s16
+; GFX1250-NEXT: v_dual_mov_b32 v9, s31 :: v_dual_mov_b32 v10, s24
; GFX1250-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v9, s17 :: v_dual_mov_b32 v10, s14
+; GFX1250-NEXT: v_dual_mov_b32 v11, s25 :: v_dual_mov_b32 v12, s22
; GFX1250-NEXT: s_wait_xcnt 0x2
-; GFX1250-NEXT: v_dual_mov_b32 v11, s15 :: v_dual_mov_b32 v12, s12
+; GFX1250-NEXT: v_dual_mov_b32 v13, s23 :: v_dual_mov_b32 v14, s16
; GFX1250-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[2:3], s[68:69], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v14, s10
+; GFX1250-NEXT: v_dual_mov_b32 v15, s17 :: v_dual_mov_b32 v16, s12
; GFX1250-NEXT: s_wait_xcnt 0x1
-; GFX1250-NEXT: v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v16, s8
-; GFX1250-NEXT: v_dual_mov_b32 v17, s9 :: v_dual_mov_b32 v18, s6
+; GFX1250-NEXT: v_dual_mov_b32 v17, s13 :: v_dual_mov_b32 v18, s8
+; GFX1250-NEXT: v_dual_mov_b32 v19, s9 :: v_dual_mov_b32 v20, s6
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v19, s7 :: v_dual_mov_b32 v20, s4
-; GFX1250-NEXT: v_dual_mov_b32 v21, s5 :: v_dual_mov_b32 v22, s2
-; GFX1250-NEXT: v_mov_b32_e32 v23, s3
+; GFX1250-NEXT: v_dual_mov_b32 v21, s7 :: v_dual_mov_b32 v22, s4
+; GFX1250-NEXT: v_dual_mov_b32 v23, s5 :: v_dual_mov_b32 v24, s2
+; GFX1250-NEXT: v_mov_b32_e32 v25, s3
; GFX1250-NEXT: s_clause 0x5
-; GFX1250-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:80
-; GFX1250-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:64
-; GFX1250-NEXT: global_store_b128 v24, v[8:11], s[0:1] offset:48
-; GFX1250-NEXT: global_store_b128 v24, v[12:15], s[0:1] offset:32
-; GFX1250-NEXT: global_store_b128 v24, v[16:19], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v24, v[20:23], s[0:1]
+; GFX1250-NEXT: global_store_b128 v0, v[2:5], s[0:1] offset:80
+; GFX1250-NEXT: global_store_b128 v0, v[6:9], s[0:1] offset:64
+; GFX1250-NEXT: global_store_b128 v0, v[10:13], s[0:1] offset:48
+; GFX1250-NEXT: global_store_b128 v0, v[14:17], s[0:1] offset:32
+; GFX1250-NEXT: global_store_b128 v0, v[18:21], s[0:1] offset:16
+; GFX1250-NEXT: global_store_b128 v0, v[22:25], s[0:1]
; GFX1250-NEXT: s_endpgm
%load = load <32 x i1>, ptr addrspace(4) %in
%ext = sext <32 x i1> %load to <32 x i64>
@@ -9941,78 +10322,67 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[10:11], 0x0
; GFX6-NEXT: s_mov_b32 s37, s7
-; GFX6-NEXT: s_mov_b32 s31, s7
-; GFX6-NEXT: s_mov_b32 s27, s7
-; GFX6-NEXT: s_mov_b32 s23, s7
+; GFX6-NEXT: s_mov_b32 s21, s7
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshr_b32 s6, s5, 30
; GFX6-NEXT: s_lshr_b32 s42, s5, 28
; GFX6-NEXT: s_lshr_b32 s40, s5, 29
+; GFX6-NEXT: s_lshr_b32 s6, s5, 30
; GFX6-NEXT: s_lshr_b32 s38, s5, 26
; GFX6-NEXT: s_lshr_b32 s36, s5, 27
-; GFX6-NEXT: s_lshr_b32 s30, s5, 25
-; GFX6-NEXT: s_lshr_b32 s26, s5, 23
-; GFX6-NEXT: s_lshr_b32 s22, s5, 21
; GFX6-NEXT: s_lshr_b32 s20, s5, 18
-; GFX6-NEXT: s_mov_b32 s21, s7
-; GFX6-NEXT: s_bfe_i64 s[44:45], s[6:7], 0x10000
-; GFX6-NEXT: s_ashr_i32 s6, s5, 31
; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_mov_b32 s0, s8
; GFX6-NEXT: s_mov_b32 s1, s9
; GFX6-NEXT: s_lshr_b32 s18, s5, 19
; GFX6-NEXT: s_mov_b32 s19, s7
-; GFX6-NEXT: v_mov_b32_e32 v0, s44
-; GFX6-NEXT: v_mov_b32_e32 v1, s45
-; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: s_bfe_i64 s[44:45], s[6:7], 0x10000
+; GFX6-NEXT: s_ashr_i32 s6, s5, 31
; GFX6-NEXT: v_mov_b32_e32 v4, s42
; GFX6-NEXT: v_mov_b32_e32 v5, s43
; GFX6-NEXT: v_mov_b32_e32 v6, s40
; GFX6-NEXT: v_mov_b32_e32 v7, s41
; GFX6-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
; GFX6-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX6-NEXT: v_mov_b32_e32 v3, s6
-; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
; GFX6-NEXT: s_mov_b32 s35, s7
+; GFX6-NEXT: s_mov_b32 s31, s7
; GFX6-NEXT: s_mov_b32 s29, s7
+; GFX6-NEXT: s_mov_b32 s27, s7
; GFX6-NEXT: s_mov_b32 s25, s7
+; GFX6-NEXT: s_mov_b32 s23, s7
; GFX6-NEXT: s_lshr_b32 s16, s5, 16
; GFX6-NEXT: s_mov_b32 s17, s7
; GFX6-NEXT: s_mov_b32 s15, s7
; GFX6-NEXT: s_mov_b32 s13, s7
; GFX6-NEXT: s_mov_b32 s11, s7
; GFX6-NEXT: s_mov_b32 s9, s7
-; GFX6-NEXT: s_mov_b32 s45, s7
-; GFX6-NEXT: s_mov_b32 s43, s7
-; GFX6-NEXT: s_mov_b32 s41, s7
+; GFX6-NEXT: v_mov_b32_e32 v1, s45
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: s_mov_b32 s49, s7
+; GFX6-NEXT: s_mov_b32 s57, s7
+; GFX6-NEXT: s_mov_b32 s47, s7
; GFX6-NEXT: v_mov_b32_e32 v9, s39
-; GFX6-NEXT: s_mov_b32 s39, s7
+; GFX6-NEXT: s_mov_b32 s55, s7
; GFX6-NEXT: v_mov_b32_e32 v11, s37
; GFX6-NEXT: s_mov_b32 s37, s7
-; GFX6-NEXT: s_mov_b32 s47, s7
-; GFX6-NEXT: v_mov_b32_e32 v15, s31
-; GFX6-NEXT: s_mov_b32 s31, s7
-; GFX6-NEXT: s_mov_b32 s49, s7
-; GFX6-NEXT: v_mov_b32_e32 v19, s27
-; GFX6-NEXT: s_mov_b32 s27, s7
-; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:496
+; GFX6-NEXT: s_mov_b32 s39, s7
+; GFX6-NEXT: s_mov_b32 s43, s7
; GFX6-NEXT: s_mov_b32 s51, s7
-; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v3, s23
-; GFX6-NEXT: s_mov_b32 s23, s7
+; GFX6-NEXT: s_mov_b32 s41, s7
+; GFX6-NEXT: v_mov_b32_e32 v3, s6
+; GFX6-NEXT: s_mov_b32 s53, s7
+; GFX6-NEXT: s_mov_b32 s45, s7
; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:480
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v5, s21
; GFX6-NEXT: s_mov_b32 s21, s7
-; GFX6-NEXT: s_mov_b32 s53, s7
+; GFX6-NEXT: s_mov_b32 s59, s7
; GFX6-NEXT: s_bfe_i64 s[6:7], s[18:19], 0x10000
; GFX6-NEXT: s_lshr_b32 s34, s5, 24
+; GFX6-NEXT: s_lshr_b32 s30, s5, 25
; GFX6-NEXT: s_lshr_b32 s14, s5, 17
; GFX6-NEXT: v_mov_b32_e32 v8, s38
; GFX6-NEXT: v_mov_b32_e32 v10, s36
@@ -10021,86 +10391,99 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX6-NEXT: s_bfe_i64 s[6:7], s[16:17], 0x10000
; GFX6-NEXT: s_lshr_b32 s12, s5, 14
; GFX6-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:464
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v8, s6
; GFX6-NEXT: v_mov_b32_e32 v9, s7
; GFX6-NEXT: s_bfe_i64 s[6:7], s[14:15], 0x10000
; GFX6-NEXT: s_lshr_b32 s28, s5, 22
+; GFX6-NEXT: s_lshr_b32 s26, s5, 23
; GFX6-NEXT: s_lshr_b32 s10, s5, 15
; GFX6-NEXT: v_mov_b32_e32 v12, s34
; GFX6-NEXT: v_mov_b32_e32 v13, s35
; GFX6-NEXT: v_mov_b32_e32 v14, s30
+; GFX6-NEXT: v_mov_b32_e32 v15, s31
; GFX6-NEXT: v_mov_b32_e32 v10, s6
; GFX6-NEXT: v_mov_b32_e32 v11, s7
; GFX6-NEXT: s_bfe_i64 s[6:7], s[12:13], 0x10000
; GFX6-NEXT: s_lshr_b32 s8, s5, 12
; GFX6-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:448
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v12, s6
; GFX6-NEXT: v_mov_b32_e32 v13, s7
; GFX6-NEXT: s_bfe_i64 s[6:7], s[10:11], 0x10000
; GFX6-NEXT: s_lshr_b32 s24, s5, 20
-; GFX6-NEXT: s_lshr_b32 s44, s5, 13
+; GFX6-NEXT: s_lshr_b32 s22, s5, 21
+; GFX6-NEXT: s_lshr_b32 s48, s5, 13
; GFX6-NEXT: v_mov_b32_e32 v16, s28
; GFX6-NEXT: v_mov_b32_e32 v17, s29
; GFX6-NEXT: v_mov_b32_e32 v18, s26
+; GFX6-NEXT: v_mov_b32_e32 v19, s27
; GFX6-NEXT: v_mov_b32_e32 v14, s6
; GFX6-NEXT: v_mov_b32_e32 v15, s7
; GFX6-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x10000
-; GFX6-NEXT: s_lshr_b32 s42, s5, 10
+; GFX6-NEXT: v_mov_b32_e32 v0, s44
+; GFX6-NEXT: s_lshr_b32 s56, s5, 10
; GFX6-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:432
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v16, s6
; GFX6-NEXT: v_mov_b32_e32 v17, s7
-; GFX6-NEXT: s_bfe_i64 s[6:7], s[44:45], 0x10000
-; GFX6-NEXT: s_lshr_b32 s40, s5, 11
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[48:49], 0x10000
+; GFX6-NEXT: s_lshr_b32 s46, s5, 11
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:496
+; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s24
; GFX6-NEXT: v_mov_b32_e32 v1, s25
; GFX6-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NEXT: v_mov_b32_e32 v3, s23
; GFX6-NEXT: v_mov_b32_e32 v18, s6
; GFX6-NEXT: v_mov_b32_e32 v19, s7
-; GFX6-NEXT: s_bfe_i64 s[6:7], s[42:43], 0x10000
-; GFX6-NEXT: s_lshr_b32 s38, s5, 8
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[56:57], 0x10000
+; GFX6-NEXT: s_lshr_b32 s54, s5, 8
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:416
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: v_mov_b32_e32 v1, s7
-; GFX6-NEXT: s_bfe_i64 s[6:7], s[40:41], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[46:47], 0x10000
; GFX6-NEXT: s_lshr_b32 s36, s5, 9
; GFX6-NEXT: v_mov_b32_e32 v4, s20
; GFX6-NEXT: v_mov_b32_e32 v2, s6
; GFX6-NEXT: v_mov_b32_e32 v3, s7
-; GFX6-NEXT: s_bfe_i64 s[6:7], s[38:39], 0x10000
-; GFX6-NEXT: s_lshr_b32 s46, s5, 6
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[54:55], 0x10000
+; GFX6-NEXT: s_lshr_b32 s38, s5, 6
; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:400
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v4, s6
; GFX6-NEXT: v_mov_b32_e32 v5, s7
; GFX6-NEXT: s_bfe_i64 s[6:7], s[36:37], 0x10000
-; GFX6-NEXT: s_lshr_b32 s30, s5, 7
+; GFX6-NEXT: s_lshr_b32 s42, s5, 7
; GFX6-NEXT: v_mov_b32_e32 v6, s6
; GFX6-NEXT: v_mov_b32_e32 v7, s7
-; GFX6-NEXT: s_bfe_i64 s[6:7], s[46:47], 0x10000
-; GFX6-NEXT: s_lshr_b32 s48, s5, 4
-; GFX6-NEXT: s_lshr_b32 s26, s5, 5
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[38:39], 0x10000
+; GFX6-NEXT: s_lshr_b32 s50, s5, 4
+; GFX6-NEXT: s_lshr_b32 s40, s5, 5
; GFX6-NEXT: s_lshr_b32 s12, s4, 29
+; GFX6-NEXT: ; implicit-def: $sgpr13
; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:384
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v8, s6
; GFX6-NEXT: v_mov_b32_e32 v9, s7
-; GFX6-NEXT: s_bfe_i64 s[6:7], s[30:31], 0x10000
-; GFX6-NEXT: s_lshr_b32 s24, s4, 26
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[42:43], 0x10000
+; GFX6-NEXT: s_lshr_b32 s22, s4, 26
; GFX6-NEXT: v_mov_b32_e32 v10, s6
; GFX6-NEXT: v_mov_b32_e32 v11, s7
-; GFX6-NEXT: s_bfe_i64 s[8:9], s[48:49], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[10:11], s[26:27], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[8:9], s[50:51], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[10:11], s[40:41], 0x10000
; GFX6-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX6-NEXT: s_lshr_b32 s50, s5, 2
-; GFX6-NEXT: s_lshr_b32 s22, s5, 3
-; GFX6-NEXT: s_lshr_b32 s28, s4, 27
+; GFX6-NEXT: s_lshr_b32 s52, s5, 2
+; GFX6-NEXT: s_lshr_b32 s44, s5, 3
+; GFX6-NEXT: ; implicit-def: $sgpr23
+; GFX6-NEXT: s_lshr_b32 s24, s4, 27
; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:368
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v12, s8
@@ -10111,48 +10494,56 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v10, s12
; GFX6-NEXT: v_mov_b32_e32 v11, s13
-; GFX6-NEXT: s_bfe_i64 s[12:13], s[24:25], 0x10000
-; GFX6-NEXT: s_lshr_b32 s34, s4, 24
-; GFX6-NEXT: s_bfe_i64 s[26:27], s[50:51], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[22:23], 0x10000
+; GFX6-NEXT: ; implicit-def: $sgpr25
+; GFX6-NEXT: s_lshr_b32 s26, s4, 24
+; GFX6-NEXT: s_bfe_i64 s[40:41], s[52:53], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[44:45], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:288
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v12, s12
; GFX6-NEXT: v_mov_b32_e32 v13, s13
-; GFX6-NEXT: s_bfe_i64 s[12:13], s[28:29], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[24:25], 0x10000
; GFX6-NEXT: s_lshr_b32 s20, s5, 1
-; GFX6-NEXT: s_mov_b32 s52, s5
-; GFX6-NEXT: s_lshr_b32 s42, s4, 25
+; GFX6-NEXT: s_mov_b32 s58, s5
+; GFX6-NEXT: ; implicit-def: $sgpr27
+; GFX6-NEXT: s_lshr_b32 s28, s4, 25
; GFX6-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:352
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v16, s26
-; GFX6-NEXT: v_mov_b32_e32 v17, s27
-; GFX6-NEXT: v_mov_b32_e32 v18, s22
-; GFX6-NEXT: v_mov_b32_e32 v19, s23
+; GFX6-NEXT: v_mov_b32_e32 v16, s40
+; GFX6-NEXT: v_mov_b32_e32 v17, s41
+; GFX6-NEXT: v_mov_b32_e32 v18, s42
+; GFX6-NEXT: v_mov_b32_e32 v19, s43
; GFX6-NEXT: v_mov_b32_e32 v14, s12
; GFX6-NEXT: v_mov_b32_e32 v15, s13
-; GFX6-NEXT: s_bfe_i64 s[12:13], s[34:35], 0x10000
-; GFX6-NEXT: s_lshr_b32 s40, s4, 22
-; GFX6-NEXT: s_bfe_i64 s[30:31], s[52:53], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[26:27], 0x10000
+; GFX6-NEXT: ; implicit-def: $sgpr29
+; GFX6-NEXT: s_lshr_b32 s30, s4, 22
+; GFX6-NEXT: s_bfe_i64 s[44:45], s[58:59], 0x10000
; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:272
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v16, s12
; GFX6-NEXT: v_mov_b32_e32 v17, s13
-; GFX6-NEXT: s_bfe_i64 s[12:13], s[42:43], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[28:29], 0x10000
; GFX6-NEXT: s_lshr_b32 s18, s4, 30
+; GFX6-NEXT: ; implicit-def: $sgpr19
; GFX6-NEXT: s_lshr_b32 s16, s4, 31
-; GFX6-NEXT: s_lshr_b32 s38, s4, 23
+; GFX6-NEXT: ; implicit-def: $sgpr17
+; GFX6-NEXT: ; implicit-def: $sgpr31
+; GFX6-NEXT: s_lshr_b32 s34, s4, 23
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:336
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s30
-; GFX6-NEXT: v_mov_b32_e32 v1, s31
+; GFX6-NEXT: v_mov_b32_e32 v0, s44
+; GFX6-NEXT: v_mov_b32_e32 v1, s45
; GFX6-NEXT: v_mov_b32_e32 v2, s20
; GFX6-NEXT: v_mov_b32_e32 v3, s21
; GFX6-NEXT: v_mov_b32_e32 v18, s12
; GFX6-NEXT: v_mov_b32_e32 v19, s13
-; GFX6-NEXT: s_bfe_i64 s[12:13], s[40:41], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[30:31], 0x10000
; GFX6-NEXT: s_lshr_b32 s14, s4, 28
+; GFX6-NEXT: ; implicit-def: $sgpr15
+; GFX6-NEXT: ; implicit-def: $sgpr35
; GFX6-NEXT: s_lshr_b32 s36, s4, 20
; GFX6-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
; GFX6-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
@@ -10160,10 +10551,13 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s12
; GFX6-NEXT: v_mov_b32_e32 v1, s13
-; GFX6-NEXT: s_bfe_i64 s[12:13], s[38:39], 0x10000
-; GFX6-NEXT: s_lshr_b32 s44, s4, 21
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[34:35], 0x10000
+; GFX6-NEXT: ; implicit-def: $sgpr37
+; GFX6-NEXT: s_lshr_b32 s38, s4, 21
; GFX6-NEXT: s_lshr_b32 s6, s4, 18
+; GFX6-NEXT: ; implicit-def: $sgpr7
; GFX6-NEXT: s_lshr_b32 s8, s4, 19
+; GFX6-NEXT: ; implicit-def: $sgpr9
; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:320
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v4, s18
@@ -10174,22 +10568,27 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX6-NEXT: v_mov_b32_e32 v2, s12
; GFX6-NEXT: v_mov_b32_e32 v3, s13
; GFX6-NEXT: s_bfe_i64 s[12:13], s[36:37], 0x10000
+; GFX6-NEXT: ; implicit-def: $sgpr39
; GFX6-NEXT: s_lshr_b32 s10, s4, 16
-; GFX6-NEXT: s_lshr_b32 s26, s4, 17
+; GFX6-NEXT: ; implicit-def: $sgpr11
+; GFX6-NEXT: s_lshr_b32 s40, s4, 17
+; GFX6-NEXT: ; implicit-def: $sgpr41
; GFX6-NEXT: v_mov_b32_e32 v8, s14
; GFX6-NEXT: v_mov_b32_e32 v9, s15
; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:240
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v4, s12
; GFX6-NEXT: v_mov_b32_e32 v5, s13
-; GFX6-NEXT: s_bfe_i64 s[12:13], s[44:45], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[38:39], 0x10000
; GFX6-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
; GFX6-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX6-NEXT: s_lshr_b32 s22, s4, 14
-; GFX6-NEXT: s_lshr_b32 s30, s4, 15
+; GFX6-NEXT: s_lshr_b32 s42, s4, 14
+; GFX6-NEXT: ; implicit-def: $sgpr43
+; GFX6-NEXT: s_lshr_b32 s44, s4, 15
+; GFX6-NEXT: ; implicit-def: $sgpr45
; GFX6-NEXT: v_mov_b32_e32 v6, s12
; GFX6-NEXT: v_mov_b32_e32 v7, s13
-; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
; GFX6-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:224
; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:208
@@ -10202,76 +10601,89 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX6-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NEXT: v_mov_b32_e32 v3, s9
; GFX6-NEXT: s_lshr_b32 s20, s4, 12
+; GFX6-NEXT: ; implicit-def: $sgpr21
; GFX6-NEXT: s_lshr_b32 s18, s4, 13
-; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX6-NEXT: ; implicit-def: $sgpr19
+; GFX6-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s10
; GFX6-NEXT: v_mov_b32_e32 v1, s11
-; GFX6-NEXT: v_mov_b32_e32 v2, s26
-; GFX6-NEXT: v_mov_b32_e32 v3, s27
+; GFX6-NEXT: v_mov_b32_e32 v2, s40
+; GFX6-NEXT: v_mov_b32_e32 v3, s41
; GFX6-NEXT: s_lshr_b32 s46, s4, 10
; GFX6-NEXT: s_lshr_b32 s48, s4, 11
-; GFX6-NEXT: s_lshr_b32 s42, s4, 4
; GFX6-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s22
-; GFX6-NEXT: v_mov_b32_e32 v1, s23
-; GFX6-NEXT: v_mov_b32_e32 v2, s30
-; GFX6-NEXT: v_mov_b32_e32 v3, s31
+; GFX6-NEXT: v_mov_b32_e32 v0, s42
+; GFX6-NEXT: v_mov_b32_e32 v1, s43
+; GFX6-NEXT: v_mov_b32_e32 v2, s44
+; GFX6-NEXT: v_mov_b32_e32 v3, s45
+; GFX6-NEXT: ; implicit-def: $sgpr47
+; GFX6-NEXT: ; implicit-def: $sgpr49
; GFX6-NEXT: s_lshr_b32 s50, s4, 8
-; GFX6-NEXT: s_lshr_b32 s24, s4, 9
-; GFX6-NEXT: s_lshr_b32 s40, s4, 5
-; GFX6-NEXT: s_lshr_b32 s36, s4, 1
-; GFX6-NEXT: s_bfe_i64 s[38:39], s[42:43], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[42:43], s[48:49], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[44:45], s[46:47], 0x10000
+; GFX6-NEXT: s_lshr_b32 s22, s4, 9
+; GFX6-NEXT: ; implicit-def: $sgpr23
+; GFX6-NEXT: s_lshr_b32 s34, s4, 1
+; GFX6-NEXT: ; implicit-def: $sgpr35
+; GFX6-NEXT: s_bfe_i64 s[36:37], s[48:49], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[38:39], s[46:47], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s20
; GFX6-NEXT: v_mov_b32_e32 v1, s21
; GFX6-NEXT: v_mov_b32_e32 v2, s18
; GFX6-NEXT: v_mov_b32_e32 v3, s19
-; GFX6-NEXT: s_lshr_b32 s28, s4, 6
-; GFX6-NEXT: s_lshr_b32 s34, s4, 7
+; GFX6-NEXT: ; implicit-def: $sgpr51
+; GFX6-NEXT: s_lshr_b32 s24, s4, 6
+; GFX6-NEXT: ; implicit-def: $sgpr25
+; GFX6-NEXT: s_lshr_b32 s26, s4, 7
+; GFX6-NEXT: ; implicit-def: $sgpr27
+; GFX6-NEXT: s_lshr_b32 s28, s4, 4
+; GFX6-NEXT: s_lshr_b32 s30, s4, 5
; GFX6-NEXT: s_lshr_b32 s16, s4, 2
; GFX6-NEXT: s_lshr_b32 s14, s4, 3
; GFX6-NEXT: s_bfe_i64 s[12:13], s[4:5], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[4:5], s[36:37], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[36:37], s[40:41], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[40:41], s[50:51], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[4:5], s[34:35], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[34:35], s[50:51], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s44
-; GFX6-NEXT: v_mov_b32_e32 v1, s45
-; GFX6-NEXT: v_mov_b32_e32 v2, s42
-; GFX6-NEXT: v_mov_b32_e32 v3, s43
-; GFX6-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
-; GFX6-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v0, s38
+; GFX6-NEXT: v_mov_b32_e32 v1, s39
+; GFX6-NEXT: v_mov_b32_e32 v2, s36
+; GFX6-NEXT: v_mov_b32_e32 v3, s37
+; GFX6-NEXT: ; implicit-def: $sgpr29
+; GFX6-NEXT: ; implicit-def: $sgpr31
+; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s40
-; GFX6-NEXT: v_mov_b32_e32 v1, s41
-; GFX6-NEXT: v_mov_b32_e32 v2, s24
-; GFX6-NEXT: v_mov_b32_e32 v3, s25
+; GFX6-NEXT: v_mov_b32_e32 v0, s34
+; GFX6-NEXT: v_mov_b32_e32 v1, s35
+; GFX6-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NEXT: v_mov_b32_e32 v3, s23
+; GFX6-NEXT: ; implicit-def: $sgpr17
+; GFX6-NEXT: ; implicit-def: $sgpr15
+; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s28
-; GFX6-NEXT: v_mov_b32_e32 v1, s29
-; GFX6-NEXT: v_mov_b32_e32 v2, s34
-; GFX6-NEXT: v_mov_b32_e32 v3, s35
+; GFX6-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NEXT: v_mov_b32_e32 v2, s26
+; GFX6-NEXT: v_mov_b32_e32 v3, s27
; GFX6-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
; GFX6-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s38
-; GFX6-NEXT: v_mov_b32_e32 v1, s39
-; GFX6-NEXT: v_mov_b32_e32 v2, s36
-; GFX6-NEXT: v_mov_b32_e32 v3, s37
+; GFX6-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NEXT: v_mov_b32_e32 v1, s29
+; GFX6-NEXT: v_mov_b32_e32 v2, s30
+; GFX6-NEXT: v_mov_b32_e32 v3, s31
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s16
@@ -10290,190 +10702,239 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-LABEL: constant_sextload_v64i1_to_v64i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX8-NEXT: s_mov_b32 s69, 0
-; GFX8-NEXT: s_mov_b32 s39, s69
+; GFX8-NEXT: s_mov_b32 s71, 0
+; GFX8-NEXT: ; implicit-def: $sgpr5
; GFX8-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
-; GFX8-NEXT: s_mov_b32 s73, s69
-; GFX8-NEXT: s_mov_b32 s49, s69
+; GFX8-NEXT: s_mov_b32 s65, s71
+; GFX8-NEXT: s_mov_b32 s49, s71
+; GFX8-NEXT: s_mov_b32 s47, s71
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
-; GFX8-NEXT: s_mov_b32 s75, s69
-; GFX8-NEXT: s_mov_b32 s43, s69
-; GFX8-NEXT: s_mov_b32 s63, s69
-; GFX8-NEXT: s_mov_b32 s29, s69
+; GFX8-NEXT: s_mov_b32 s45, s71
+; GFX8-NEXT: ; implicit-def: $sgpr43
+; GFX8-NEXT: ; implicit-def: $sgpr41
+; GFX8-NEXT: ; implicit-def: $sgpr61
+; GFX8-NEXT: ; implicit-def: $sgpr59
+; GFX8-NEXT: ; implicit-def: $sgpr57
+; GFX8-NEXT: ; implicit-def: $sgpr55
+; GFX8-NEXT: s_mov_b32 s73, s71
+; GFX8-NEXT: s_mov_b32 s53, s71
+; GFX8-NEXT: s_mov_b32 s75, s71
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_lshr_b32 s38, s3, 19
; GFX8-NEXT: s_lshr_b32 s4, s3, 9
-; GFX8-NEXT: s_lshr_b32 s40, s3, 15
-; GFX8-NEXT: s_lshr_b32 s44, s3, 12
-; GFX8-NEXT: s_lshr_b32 s54, s3, 11
+; GFX8-NEXT: s_lshr_b32 s64, s3, 18
; GFX8-NEXT: v_writelane_b32 v62, s4, 0
-; GFX8-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
-; GFX8-NEXT: s_lshr_b32 s64, s3, 30
+; GFX8-NEXT: s_lshr_b32 s48, s3, 19
+; GFX8-NEXT: v_writelane_b32 v62, s5, 1
+; GFX8-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x10000
+; GFX8-NEXT: s_lshr_b32 s46, s3, 16
+; GFX8-NEXT: v_mov_b32_e32 v24, s4
+; GFX8-NEXT: v_mov_b32_e32 v25, s5
+; GFX8-NEXT: s_bfe_i64 s[4:5], s[48:49], 0x10000
+; GFX8-NEXT: s_lshr_b32 s44, s3, 17
+; GFX8-NEXT: v_mov_b32_e32 v26, s4
+; GFX8-NEXT: v_mov_b32_e32 v27, s5
+; GFX8-NEXT: s_bfe_i64 s[4:5], s[46:47], 0x10000
+; GFX8-NEXT: s_lshr_b32 s42, s3, 14
+; GFX8-NEXT: v_mov_b32_e32 v28, s4
+; GFX8-NEXT: v_mov_b32_e32 v29, s5
+; GFX8-NEXT: s_bfe_i64 s[4:5], s[44:45], 0x10000
+; GFX8-NEXT: s_lshr_b32 s40, s3, 15
+; GFX8-NEXT: v_mov_b32_e32 v30, s4
+; GFX8-NEXT: v_mov_b32_e32 v31, s5
+; GFX8-NEXT: s_bfe_i64 s[4:5], s[42:43], 0x10000
+; GFX8-NEXT: s_lshr_b32 s38, s3, 12
+; GFX8-NEXT: v_mov_b32_e32 v36, s4
+; GFX8-NEXT: v_mov_b32_e32 v37, s5
+; GFX8-NEXT: s_bfe_i64 s[4:5], s[40:41], 0x10000
+; GFX8-NEXT: s_lshr_b32 s62, s3, 30
; GFX8-NEXT: s_lshr_b32 s60, s3, 31
; GFX8-NEXT: s_lshr_b32 s66, s3, 28
; GFX8-NEXT: s_lshr_b32 s58, s3, 29
-; GFX8-NEXT: s_lshr_b32 s70, s3, 26
+; GFX8-NEXT: s_lshr_b32 s68, s3, 26
; GFX8-NEXT: s_lshr_b32 s56, s3, 27
-; GFX8-NEXT: s_lshr_b32 s68, s3, 24
-; GFX8-NEXT: s_lshr_b32 s52, s3, 25
+; GFX8-NEXT: s_lshr_b32 s70, s3, 24
+; GFX8-NEXT: s_lshr_b32 s54, s3, 25
; GFX8-NEXT: s_lshr_b32 s72, s3, 22
-; GFX8-NEXT: s_lshr_b32 s48, s3, 23
+; GFX8-NEXT: s_lshr_b32 s52, s3, 23
; GFX8-NEXT: s_lshr_b32 s74, s3, 20
-; GFX8-NEXT: s_lshr_b32 s42, s3, 21
-; GFX8-NEXT: s_lshr_b32 s62, s3, 18
-; GFX8-NEXT: s_lshr_b32 s28, s3, 16
-; GFX8-NEXT: s_lshr_b32 s34, s3, 17
-; GFX8-NEXT: s_mov_b32 s35, s69
-; GFX8-NEXT: s_lshr_b32 s36, s3, 14
-; GFX8-NEXT: s_lshr_b32 s18, s3, 8
-; GFX8-NEXT: v_writelane_b32 v62, s5, 1
-; GFX8-NEXT: v_mov_b32_e32 v26, s38
-; GFX8-NEXT: v_mov_b32_e32 v27, s39
-; GFX8-NEXT: s_bfe_i64 s[38:39], s[54:55], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[4:5], s[44:45], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
-; GFX8-NEXT: s_lshr_b32 s46, s3, 13
-; GFX8-NEXT: s_mov_b32 s23, s69
-; GFX8-NEXT: s_bfe_i64 s[74:75], s[74:75], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[72:73], s[72:73], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[68:69], s[68:69], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[70:71], s[70:71], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[64:65], s[64:65], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
+; GFX8-NEXT: s_lshr_b32 s50, s3, 21
+; GFX8-NEXT: s_mov_b32 s51, s71
+; GFX8-NEXT: ; implicit-def: $sgpr39
+; GFX8-NEXT: s_lshr_b32 s36, s3, 13
+; GFX8-NEXT: ; implicit-def: $sgpr37
+; GFX8-NEXT: s_lshr_b32 s34, s3, 10
+; GFX8-NEXT: ; implicit-def: $sgpr35
+; GFX8-NEXT: s_lshr_b32 s30, s3, 11
+; GFX8-NEXT: ; implicit-def: $sgpr31
+; GFX8-NEXT: s_lshr_b32 s28, s3, 8
+; GFX8-NEXT: ; implicit-def: $sgpr29
+; GFX8-NEXT: v_mov_b32_e32 v38, s4
+; GFX8-NEXT: v_mov_b32_e32 v39, s5
+; GFX8-NEXT: s_bfe_i64 s[4:5], s[38:39], 0x10000
+; GFX8-NEXT: ; implicit-def: $sgpr63
+; GFX8-NEXT: ; implicit-def: $sgpr67
+; GFX8-NEXT: ; implicit-def: $sgpr69
+; GFX8-NEXT: s_bfe_i64 s[86:87], s[74:75], 0x10000
+; GFX8-NEXT: s_bfe_i64 vcc, s[72:73], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[72:73], s[70:71], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[74:75], s[68:69], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[76:77], s[66:67], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[78:79], s[62:63], 0x10000
; GFX8-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
; GFX8-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x10000
; GFX8-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
; GFX8-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX8-NEXT: v_mov_b32_e32 v32, s4
+; GFX8-NEXT: v_mov_b32_e32 v33, s5
+; GFX8-NEXT: s_lshr_b32 s4, s2, 7
+; GFX8-NEXT: ; implicit-def: $sgpr5
; GFX8-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
; GFX8-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
; GFX8-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX8-NEXT: v_mov_b32_e32 v42, s40
-; GFX8-NEXT: v_mov_b32_e32 v28, s4
-; GFX8-NEXT: s_lshr_b32 s4, s2, 7
-; GFX8-NEXT: s_lshr_b32 s40, s2, 4
-; GFX8-NEXT: v_mov_b32_e32 v34, s38
-; GFX8-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX8-NEXT: s_lshr_b32 s38, s2, 1
-; GFX8-NEXT: s_lshr_b32 s50, s3, 10
+; GFX8-NEXT: s_lshr_b32 s40, s2, 1
+; GFX8-NEXT: ; implicit-def: $sgpr41
; GFX8-NEXT: s_lshr_b32 s6, s3, 6
; GFX8-NEXT: s_lshr_b32 s8, s3, 7
; GFX8-NEXT: s_lshr_b32 s10, s3, 4
; GFX8-NEXT: s_lshr_b32 s12, s3, 5
; GFX8-NEXT: s_lshr_b32 s14, s3, 2
; GFX8-NEXT: s_lshr_b32 s16, s3, 3
-; GFX8-NEXT: s_lshr_b32 s20, s3, 1
-; GFX8-NEXT: s_mov_b32 s22, s3
-; GFX8-NEXT: s_lshr_b32 s24, s2, 30
-; GFX8-NEXT: s_lshr_b32 s26, s2, 31
-; GFX8-NEXT: s_lshr_b32 s30, s2, 28
-; GFX8-NEXT: v_mov_b32_e32 v12, s64
-; GFX8-NEXT: v_mov_b32_e32 v4, s66
-; GFX8-NEXT: v_mov_b32_e32 v0, s70
-; GFX8-NEXT: v_mov_b32_e32 v8, s68
-; GFX8-NEXT: v_mov_b32_e32 v16, s72
-; GFX8-NEXT: v_mov_b32_e32 v20, s74
-; GFX8-NEXT: s_lshr_b32 s82, s2, 29
-; GFX8-NEXT: s_lshr_b32 s84, s2, 26
-; GFX8-NEXT: v_mov_b32_e32 v24, s62
-; GFX8-NEXT: s_lshr_b32 s80, s2, 27
-; GFX8-NEXT: s_lshr_b32 s78, s2, 24
-; GFX8-NEXT: s_lshr_b32 s76, s2, 25
+; GFX8-NEXT: s_lshr_b32 s18, s3, 1
+; GFX8-NEXT: s_mov_b32 s20, s3
+; GFX8-NEXT: s_lshr_b32 s22, s2, 30
+; GFX8-NEXT: s_lshr_b32 s24, s2, 31
+; GFX8-NEXT: s_lshr_b32 s26, s2, 28
+; GFX8-NEXT: v_mov_b32_e32 v12, s78
+; GFX8-NEXT: v_mov_b32_e32 v4, s76
+; GFX8-NEXT: v_mov_b32_e32 v0, s74
+; GFX8-NEXT: v_mov_b32_e32 v8, s72
+; GFX8-NEXT: s_lshr_b32 s62, s2, 29
+; GFX8-NEXT: s_lshr_b32 s66, s2, 26
+; GFX8-NEXT: s_lshr_b32 s68, s2, 27
+; GFX8-NEXT: s_lshr_b32 s70, s2, 24
+; GFX8-NEXT: s_lshr_b32 s80, s2, 25
; GFX8-NEXT: v_mov_b32_e32 v14, s60
-; GFX8-NEXT: s_lshr_b32 s74, s2, 22
-; GFX8-NEXT: s_lshr_b32 s72, s2, 23
+; GFX8-NEXT: s_lshr_b32 s84, s2, 22
+; GFX8-NEXT: s_lshr_b32 s82, s2, 23
; GFX8-NEXT: v_mov_b32_e32 v6, s58
-; GFX8-NEXT: s_lshr_b32 s70, s2, 20
-; GFX8-NEXT: s_lshr_b32 s68, s2, 21
+; GFX8-NEXT: s_lshr_b32 s78, s2, 20
+; GFX8-NEXT: s_lshr_b32 s76, s2, 21
; GFX8-NEXT: v_mov_b32_e32 v2, s56
-; GFX8-NEXT: s_lshr_b32 s66, s2, 18
-; GFX8-NEXT: s_lshr_b32 s64, s2, 19
-; GFX8-NEXT: v_mov_b32_e32 v10, s52
-; GFX8-NEXT: s_lshr_b32 s62, s2, 16
+; GFX8-NEXT: s_lshr_b32 s74, s2, 18
+; GFX8-NEXT: s_lshr_b32 s72, s2, 19
+; GFX8-NEXT: v_mov_b32_e32 v10, s54
+; GFX8-NEXT: s_lshr_b32 s64, s2, 16
; GFX8-NEXT: s_lshr_b32 s60, s2, 17
-; GFX8-NEXT: v_mov_b32_e32 v18, s48
+; GFX8-NEXT: v_mov_b32_e32 v18, s52
; GFX8-NEXT: s_lshr_b32 s58, s2, 14
; GFX8-NEXT: s_lshr_b32 s56, s2, 15
-; GFX8-NEXT: v_mov_b32_e32 v22, s42
-; GFX8-NEXT: s_lshr_b32 s86, s2, 12
+; GFX8-NEXT: v_mov_b32_e32 v22, s50
+; GFX8-NEXT: s_lshr_b32 s54, s2, 12
; GFX8-NEXT: s_lshr_b32 s52, s2, 13
-; GFX8-NEXT: s_lshr_b32 vcc_lo, s2, 10
-; GFX8-NEXT: s_bfe_i64 s[54:55], s[46:47], 0x10000
-; GFX8-NEXT: v_mov_b32_e32 v36, s28
+; GFX8-NEXT: s_lshr_b32 s50, s2, 10
; GFX8-NEXT: s_lshr_b32 s48, s2, 11
-; GFX8-NEXT: v_mov_b32_e32 v38, s34
; GFX8-NEXT: s_lshr_b32 s46, s2, 8
-; GFX8-NEXT: v_mov_b32_e32 v40, s36
; GFX8-NEXT: s_lshr_b32 s44, s2, 9
-; GFX8-NEXT: v_mov_b32_e32 v43, s41
; GFX8-NEXT: s_lshr_b32 s42, s2, 6
-; GFX8-NEXT: v_mov_b32_e32 v29, s5
+; GFX8-NEXT: v_mov_b32_e32 v34, s36
+; GFX8-NEXT: s_lshr_b32 s38, s2, 4
+; GFX8-NEXT: v_mov_b32_e32 v40, s34
; GFX8-NEXT: s_lshr_b32 s36, s2, 5
-; GFX8-NEXT: v_mov_b32_e32 v35, s39
+; GFX8-NEXT: v_mov_b32_e32 v42, s30
; GFX8-NEXT: s_lshr_b32 s34, s2, 2
-; GFX8-NEXT: v_mov_b32_e32 v44, s18
-; GFX8-NEXT: v_mov_b32_e32 v45, s19
-; GFX8-NEXT: s_lshr_b32 s28, s2, 3
-; GFX8-NEXT: s_bfe_i64 s[18:19], s[2:3], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[2:3], s[38:39], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[38:39], s[40:41], 0x10000
+; GFX8-NEXT: v_mov_b32_e32 v44, s28
+; GFX8-NEXT: v_mov_b32_e32 v45, s29
+; GFX8-NEXT: s_lshr_b32 s30, s2, 3
+; GFX8-NEXT: s_bfe_i64 s[28:29], s[2:3], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[2:3], s[40:41], 0x10000
; GFX8-NEXT: s_bfe_i64 s[40:41], s[4:5], 0x10000
; GFX8-NEXT: v_readlane_b32 s4, v62, 0
-; GFX8-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
-; GFX8-NEXT: v_readlane_b32 s5, v62, 1
-; GFX8-NEXT: v_mov_b32_e32 v13, s65
+; GFX8-NEXT: ; implicit-def: $sgpr7
+; GFX8-NEXT: ; implicit-def: $sgpr9
+; GFX8-NEXT: ; implicit-def: $sgpr11
+; GFX8-NEXT: ; implicit-def: $sgpr13
+; GFX8-NEXT: ; implicit-def: $sgpr15
+; GFX8-NEXT: ; implicit-def: $sgpr17
+; GFX8-NEXT: ; implicit-def: $sgpr19
+; GFX8-NEXT: s_mov_b32 s21, s71
+; GFX8-NEXT: ; implicit-def: $sgpr23
+; GFX8-NEXT: ; implicit-def: $sgpr25
+; GFX8-NEXT: ; implicit-def: $sgpr27
+; GFX8-NEXT: ; implicit-def: $sgpr63
+; GFX8-NEXT: ; implicit-def: $sgpr67
+; GFX8-NEXT: ; implicit-def: $sgpr69
+; GFX8-NEXT: ; implicit-def: $sgpr71
+; GFX8-NEXT: v_mov_b32_e32 v13, s79
+; GFX8-NEXT: ; implicit-def: $sgpr81
; GFX8-NEXT: v_mov_b32_e32 v15, s61
-; GFX8-NEXT: v_mov_b32_e32 v5, s67
+; GFX8-NEXT: ; implicit-def: $sgpr85
+; GFX8-NEXT: v_mov_b32_e32 v5, s77
+; GFX8-NEXT: ; implicit-def: $sgpr83
; GFX8-NEXT: v_mov_b32_e32 v7, s59
-; GFX8-NEXT: v_mov_b32_e32 v1, s71
+; GFX8-NEXT: ; implicit-def: $sgpr79
+; GFX8-NEXT: v_mov_b32_e32 v1, s75
+; GFX8-NEXT: ; implicit-def: $sgpr77
; GFX8-NEXT: v_mov_b32_e32 v3, s57
-; GFX8-NEXT: v_mov_b32_e32 v9, s69
-; GFX8-NEXT: v_mov_b32_e32 v11, s53
-; GFX8-NEXT: v_mov_b32_e32 v17, s73
-; GFX8-NEXT: v_mov_b32_e32 v19, s49
-; GFX8-NEXT: v_mov_b32_e32 v21, s75
-; GFX8-NEXT: v_mov_b32_e32 v23, s43
-; GFX8-NEXT: v_mov_b32_e32 v25, s63
-; GFX8-NEXT: v_mov_b32_e32 v37, s29
-; GFX8-NEXT: v_mov_b32_e32 v39, s35
-; GFX8-NEXT: v_mov_b32_e32 v41, s37
-; GFX8-NEXT: v_mov_b32_e32 v30, s54
-; GFX8-NEXT: v_mov_b32_e32 v31, s55
-; GFX8-NEXT: v_mov_b32_e32 v32, s50
-; GFX8-NEXT: v_mov_b32_e32 v33, s51
-; GFX8-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX8-NEXT: ; implicit-def: $sgpr75
+; GFX8-NEXT: v_mov_b32_e32 v9, s73
+; GFX8-NEXT: ; implicit-def: $sgpr73
+; GFX8-NEXT: v_mov_b32_e32 v11, s55
+; GFX8-NEXT: ; implicit-def: $sgpr65
+; GFX8-NEXT: ; implicit-def: $sgpr61
+; GFX8-NEXT: v_mov_b32_e32 v19, s53
+; GFX8-NEXT: ; implicit-def: $sgpr59
+; GFX8-NEXT: ; implicit-def: $sgpr57
+; GFX8-NEXT: v_mov_b32_e32 v23, s51
+; GFX8-NEXT: ; implicit-def: $sgpr55
+; GFX8-NEXT: ; implicit-def: $sgpr53
+; GFX8-NEXT: ; implicit-def: $sgpr51
+; GFX8-NEXT: ; implicit-def: $sgpr49
+; GFX8-NEXT: ; implicit-def: $sgpr47
+; GFX8-NEXT: ; implicit-def: $sgpr45
+; GFX8-NEXT: ; implicit-def: $sgpr43
+; GFX8-NEXT: v_mov_b32_e32 v35, s37
+; GFX8-NEXT: ; implicit-def: $sgpr39
+; GFX8-NEXT: v_mov_b32_e32 v41, s35
+; GFX8-NEXT: ; implicit-def: $sgpr37
+; GFX8-NEXT: v_mov_b32_e32 v43, s31
+; GFX8-NEXT: ; implicit-def: $sgpr35
+; GFX8-NEXT: ; implicit-def: $sgpr31
+; GFX8-NEXT: v_readlane_b32 s5, v62, 1
+; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
; GFX8-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
; GFX8-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
; GFX8-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
; GFX8-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
; GFX8-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
; GFX8-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[50:51], vcc, 0x10000
+; GFX8-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
; GFX8-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[54:55], s[86:87], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
; GFX8-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
; GFX8-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x10000
; GFX8-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
; GFX8-NEXT: s_bfe_i64 s[64:65], s[64:65], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[68:69], s[68:69], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[70:71], s[70:71], 0x10000
; GFX8-NEXT: s_bfe_i64 s[72:73], s[72:73], 0x10000
; GFX8-NEXT: s_bfe_i64 s[74:75], s[74:75], 0x10000
; GFX8-NEXT: s_bfe_i64 s[76:77], s[76:77], 0x10000
; GFX8-NEXT: s_bfe_i64 s[78:79], s[78:79], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[80:81], s[80:81], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[84:85], s[84:85], 0x10000
; GFX8-NEXT: s_bfe_i64 s[82:83], s[82:83], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[84:85], s[84:85], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[80:81], s[80:81], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[70:71], s[70:71], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[68:69], s[68:69], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
; GFX8-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
; GFX8-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
; GFX8-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
; GFX8-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
; GFX8-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
@@ -10481,7 +10942,9 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
; GFX8-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
; GFX8-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX8-NEXT: v_mov_b32_e32 v20, s86
; GFX8-NEXT: s_add_u32 s86, s0, 0x1f0
+; GFX8-NEXT: v_mov_b32_e32 v21, s87
; GFX8-NEXT: s_addc_u32 s87, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v46, s86
; GFX8-NEXT: v_mov_b32_e32 v47, s87
@@ -10533,6 +10996,8 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: s_add_u32 s4, s0, 0x130
; GFX8-NEXT: v_mov_b32_e32 v47, s5
; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, vcc_lo
+; GFX8-NEXT: v_mov_b32_e32 v17, vcc_hi
; GFX8-NEXT: flat_store_dwordx4 v[50:51], v[0:3]
; GFX8-NEXT: flat_store_dwordx4 v[52:53], v[8:11]
; GFX8-NEXT: flat_store_dwordx4 v[54:55], v[16:19]
@@ -10553,10 +11018,10 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NEXT: v_mov_b32_e32 v3, s9
-; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[28:31]
+; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[32:35]
; GFX8-NEXT: v_mov_b32_e32 v6, s12
; GFX8-NEXT: v_mov_b32_e32 v7, s13
-; GFX8-NEXT: flat_store_dwordx4 v[48:49], v[32:35]
+; GFX8-NEXT: flat_store_dwordx4 v[48:49], v[40:43]
; GFX8-NEXT: flat_store_dwordx4 v[60:61], v[44:47]
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
@@ -10571,80 +11036,80 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s22
-; GFX8-NEXT: v_mov_b32_e32 v1, s23
-; GFX8-NEXT: v_mov_b32_e32 v2, s20
-; GFX8-NEXT: v_mov_b32_e32 v3, s21
+; GFX8-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NEXT: v_mov_b32_e32 v1, s21
+; GFX8-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NEXT: v_mov_b32_e32 v3, s19
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xf0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s24
-; GFX8-NEXT: v_mov_b32_e32 v1, s25
-; GFX8-NEXT: v_mov_b32_e32 v2, s26
-; GFX8-NEXT: v_mov_b32_e32 v3, s27
+; GFX8-NEXT: v_mov_b32_e32 v0, s22
+; GFX8-NEXT: v_mov_b32_e32 v1, s23
+; GFX8-NEXT: v_mov_b32_e32 v2, s24
+; GFX8-NEXT: v_mov_b32_e32 v3, s25
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xe0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s30
-; GFX8-NEXT: v_mov_b32_e32 v1, s31
-; GFX8-NEXT: v_mov_b32_e32 v2, s82
-; GFX8-NEXT: v_mov_b32_e32 v3, s83
+; GFX8-NEXT: v_mov_b32_e32 v0, s26
+; GFX8-NEXT: v_mov_b32_e32 v1, s27
+; GFX8-NEXT: v_mov_b32_e32 v2, s62
+; GFX8-NEXT: v_mov_b32_e32 v3, s63
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xd0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s84
-; GFX8-NEXT: v_mov_b32_e32 v1, s85
-; GFX8-NEXT: v_mov_b32_e32 v2, s80
-; GFX8-NEXT: v_mov_b32_e32 v3, s81
+; GFX8-NEXT: v_mov_b32_e32 v0, s66
+; GFX8-NEXT: v_mov_b32_e32 v1, s67
+; GFX8-NEXT: v_mov_b32_e32 v2, s68
+; GFX8-NEXT: v_mov_b32_e32 v3, s69
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xc0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s78
-; GFX8-NEXT: v_mov_b32_e32 v1, s79
-; GFX8-NEXT: v_mov_b32_e32 v2, s76
-; GFX8-NEXT: v_mov_b32_e32 v3, s77
+; GFX8-NEXT: v_mov_b32_e32 v0, s70
+; GFX8-NEXT: v_mov_b32_e32 v1, s71
+; GFX8-NEXT: v_mov_b32_e32 v2, s80
+; GFX8-NEXT: v_mov_b32_e32 v3, s81
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xb0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s74
-; GFX8-NEXT: v_mov_b32_e32 v1, s75
-; GFX8-NEXT: v_mov_b32_e32 v2, s72
-; GFX8-NEXT: v_mov_b32_e32 v3, s73
+; GFX8-NEXT: v_mov_b32_e32 v0, s84
+; GFX8-NEXT: v_mov_b32_e32 v1, s85
+; GFX8-NEXT: v_mov_b32_e32 v2, s82
+; GFX8-NEXT: v_mov_b32_e32 v3, s83
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xa0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s70
-; GFX8-NEXT: v_mov_b32_e32 v1, s71
-; GFX8-NEXT: v_mov_b32_e32 v2, s68
-; GFX8-NEXT: v_mov_b32_e32 v3, s69
+; GFX8-NEXT: v_mov_b32_e32 v0, s78
+; GFX8-NEXT: v_mov_b32_e32 v1, s79
+; GFX8-NEXT: v_mov_b32_e32 v2, s76
+; GFX8-NEXT: v_mov_b32_e32 v3, s77
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0x90
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s66
-; GFX8-NEXT: v_mov_b32_e32 v1, s67
-; GFX8-NEXT: v_mov_b32_e32 v2, s64
-; GFX8-NEXT: v_mov_b32_e32 v3, s65
+; GFX8-NEXT: v_mov_b32_e32 v0, s74
+; GFX8-NEXT: v_mov_b32_e32 v1, s75
+; GFX8-NEXT: v_mov_b32_e32 v2, s72
+; GFX8-NEXT: v_mov_b32_e32 v3, s73
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0x80
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s62
-; GFX8-NEXT: v_mov_b32_e32 v1, s63
+; GFX8-NEXT: v_mov_b32_e32 v0, s64
+; GFX8-NEXT: v_mov_b32_e32 v1, s65
; GFX8-NEXT: v_mov_b32_e32 v2, s60
; GFX8-NEXT: v_mov_b32_e32 v3, s61
; GFX8-NEXT: v_mov_b32_e32 v5, s5
@@ -10708,18 +11173,18 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v0, s34
; GFX8-NEXT: v_mov_b32_e32 v1, s35
-; GFX8-NEXT: v_mov_b32_e32 v2, s28
-; GFX8-NEXT: v_mov_b32_e32 v3, s29
+; GFX8-NEXT: v_mov_b32_e32 v2, s30
+; GFX8-NEXT: v_mov_b32_e32 v3, s31
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v5, s1
-; GFX8-NEXT: v_mov_b32_e32 v0, s18
-; GFX8-NEXT: v_mov_b32_e32 v1, s19
+; GFX8-NEXT: v_mov_b32_e32 v0, s28
+; GFX8-NEXT: v_mov_b32_e32 v1, s29
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s0
-; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[36:39]
-; GFX8-NEXT: flat_store_dwordx4 v[58:59], v[40:43]
+; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[28:31]
+; GFX8-NEXT: flat_store_dwordx4 v[58:59], v[36:39]
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
;
@@ -11045,104 +11510,211 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-LABEL: constant_sextload_v64i1_to_v64i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT: s_mov_b32 s61, 0
+; GFX12-NEXT: ; implicit-def: $sgpr5
+; GFX12-NEXT: ; implicit-def: $vgpr33 : SGPR spill to VGPR lane
+; GFX12-NEXT: ; implicit-def: $sgpr7
+; GFX12-NEXT: s_mov_b32 s39, 0
+; GFX12-NEXT: ; implicit-def: $sgpr41
+; GFX12-NEXT: ; implicit-def: $sgpr37
+; GFX12-NEXT: ; implicit-def: $sgpr75
+; GFX12-NEXT: ; implicit-def: $sgpr65
+; GFX12-NEXT: ; implicit-def: $sgpr49
+; GFX12-NEXT: ; implicit-def: $sgpr51
+; GFX12-NEXT: ; implicit-def: $sgpr67
+; GFX12-NEXT: ; implicit-def: $sgpr43
+; GFX12-NEXT: ; implicit-def: $sgpr35
+; GFX12-NEXT: ; implicit-def: $sgpr9
+; GFX12-NEXT: ; implicit-def: $sgpr11
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: ; implicit-def: $sgpr15
+; GFX12-NEXT: ; implicit-def: $sgpr17
+; GFX12-NEXT: ; implicit-def: $sgpr19
+; GFX12-NEXT: ; implicit-def: $sgpr21
+; GFX12-NEXT: ; implicit-def: $sgpr23
+; GFX12-NEXT: ; implicit-def: $sgpr25
+; GFX12-NEXT: ; implicit-def: $sgpr27
+; GFX12-NEXT: ; implicit-def: $sgpr31
+; GFX12-NEXT: ; implicit-def: $sgpr47
+; GFX12-NEXT: ; implicit-def: $sgpr53
+; GFX12-NEXT: ; implicit-def: $sgpr59
+; GFX12-NEXT: ; implicit-def: $sgpr61
+; GFX12-NEXT: ; implicit-def: $sgpr63
+; GFX12-NEXT: ; implicit-def: $sgpr69
+; GFX12-NEXT: ; implicit-def: $sgpr77
+; GFX12-NEXT: ; implicit-def: $sgpr79
+; GFX12-NEXT: ; implicit-def: $sgpr81
+; GFX12-NEXT: ; implicit-def: $sgpr87
+; GFX12-NEXT: ; implicit-def: $sgpr89
+; GFX12-NEXT: ; implicit-def: $sgpr91
+; GFX12-NEXT: ; implicit-def: $sgpr95
+; GFX12-NEXT: ; implicit-def: $sgpr97
+; GFX12-NEXT: ; implicit-def: $sgpr99
+; GFX12-NEXT: ; implicit-def: $sgpr101
+; GFX12-NEXT: ; implicit-def: $sgpr103
+; GFX12-NEXT: ; implicit-def: $vcc_hi
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_mov_b32 s55, s61
-; GFX12-NEXT: s_mov_b32 s43, s61
-; GFX12-NEXT: s_mov_b32 s51, s61
-; GFX12-NEXT: s_mov_b32 s29, s61
-; GFX12-NEXT: s_mov_b32 s39, s61
-; GFX12-NEXT: s_mov_b32 s17, s61
-; GFX12-NEXT: s_mov_b32 s25, s61
-; GFX12-NEXT: s_mov_b32 s49, s61
+; GFX12-NEXT: s_mov_b32 s93, s39
+; GFX12-NEXT: s_mov_b32 s83, s39
+; GFX12-NEXT: s_mov_b32 s85, s39
+; GFX12-NEXT: s_mov_b32 s71, s39
+; GFX12-NEXT: s_mov_b32 s73, s39
+; GFX12-NEXT: s_mov_b32 s55, s39
+; GFX12-NEXT: s_mov_b32 s57, s39
+; GFX12-NEXT: s_mov_b32 s29, s39
+; GFX12-NEXT: s_mov_b32 s45, s39
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
-; GFX12-NEXT: s_mov_b32 s3, s61
+; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s98, s5, 30
-; GFX12-NEXT: s_lshr_b32 s90, s5, 31
-; GFX12-NEXT: s_lshr_b32 s96, s5, 28
-; GFX12-NEXT: s_lshr_b32 s76, s5, 29
-; GFX12-NEXT: s_lshr_b32 s72, s5, 27
-; GFX12-NEXT: s_lshr_b32 s60, s5, 24
-; GFX12-NEXT: s_lshr_b32 s86, s5, 26
-; GFX12-NEXT: s_bfe_i64 s[98:99], s[98:99], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[90:91], s[90:91], 0x10000
-; GFX12-NEXT: s_lshr_b32 s64, s5, 25
-; GFX12-NEXT: s_bfe_i64 s[96:97], s[96:97], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[76:77], s[76:77], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[72:73], s[72:73], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s98
-; GFX12-NEXT: s_lshr_b32 s54, s5, 22
-; GFX12-NEXT: s_lshr_b32 s42, s5, 23
-; GFX12-NEXT: v_dual_mov_b32 v2, s99 :: v_dual_mov_b32 v3, s90
-; GFX12-NEXT: v_dual_mov_b32 v4, s91 :: v_dual_mov_b32 v5, s96
-; GFX12-NEXT: s_bfe_i64 s[86:87], s[86:87], 0x10000
-; GFX12-NEXT: s_lshr_b32 s50, s5, 20
-; GFX12-NEXT: s_lshr_b32 s28, s5, 21
-; GFX12-NEXT: s_lshr_b32 s2, s5, 17
-; GFX12-NEXT: s_lshr_b32 s6, s5, 14
-; GFX12-NEXT: s_lshr_b32 s8, s5, 15
-; GFX12-NEXT: v_dual_mov_b32 v6, s97 :: v_dual_mov_b32 v7, s76
-; GFX12-NEXT: v_dual_mov_b32 v8, s77 :: v_dual_mov_b32 v9, s86
-; GFX12-NEXT: v_dual_mov_b32 v12, s73 :: v_dual_mov_b32 v13, s60
-; GFX12-NEXT: v_mov_b32_e32 v14, s61
-; GFX12-NEXT: s_bfe_i64 s[60:61], s[64:65], 0x10000
-; GFX12-NEXT: s_lshr_b32 s38, s5, 18
-; GFX12-NEXT: s_lshr_b32 s16, s5, 19
-; GFX12-NEXT: s_lshr_b32 s10, s5, 12
-; GFX12-NEXT: s_lshr_b32 s12, s5, 13
-; GFX12-NEXT: v_dual_mov_b32 v10, s87 :: v_dual_mov_b32 v11, s72
-; GFX12-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
-; GFX12-NEXT: s_lshr_b32 s24, s5, 16
-; GFX12-NEXT: s_lshr_b32 s14, s5, 10
-; GFX12-NEXT: s_lshr_b32 s18, s5, 11
+; GFX12-NEXT: s_lshr_b32 s4, s3, 14
+; GFX12-NEXT: s_lshr_b32 s6, s3, 15
+; GFX12-NEXT: v_writelane_b32 v33, s4, 0
+; GFX12-NEXT: s_lshr_b32 s40, s3, 27
+; GFX12-NEXT: s_lshr_b32 s38, s3, 24
+; GFX12-NEXT: s_lshr_b32 s36, s3, 25
+; GFX12-NEXT: s_lshr_b32 s92, s3, 22
+; GFX12-NEXT: v_writelane_b32 v33, s5, 1
+; GFX12-NEXT: s_lshr_b32 s4, s3, 1
+; GFX12-NEXT: ; implicit-def: $sgpr5
+; GFX12-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
+; GFX12-NEXT: s_lshr_b32 s82, s3, 23
+; GFX12-NEXT: v_writelane_b32 v33, s6, 2
+; GFX12-NEXT: s_lshr_b32 s84, s3, 20
+; GFX12-NEXT: v_dual_mov_b32 v12, s41 :: v_dual_mov_b32 v13, s38
+; GFX12-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX12-NEXT: v_writelane_b32 v33, s7, 3
+; GFX12-NEXT: v_dual_mov_b32 v14, s39 :: v_dual_mov_b32 v15, s36
+; GFX12-NEXT: s_bfe_i64 s[38:39], s[92:93], 0x10000
+; GFX12-NEXT: s_lshr_b32 s74, s3, 30
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_writelane_b32 v33, s4, 4
+; GFX12-NEXT: s_lshr_b32 s70, s3, 21
+; GFX12-NEXT: s_lshr_b32 s72, s3, 18
+; GFX12-NEXT: v_dual_mov_b32 v16, s37 :: v_dual_mov_b32 v17, s38
+; GFX12-NEXT: s_bfe_i64 s[36:37], s[82:83], 0x10000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v18, s39 :: v_dual_mov_b32 v19, s36
+; GFX12-NEXT: s_bfe_i64 s[38:39], s[84:85], 0x10000
+; GFX12-NEXT: s_lshr_b32 s64, s3, 31
+; GFX12-NEXT: s_lshr_b32 s54, s3, 19
+; GFX12-NEXT: s_lshr_b32 s56, s3, 16
+; GFX12-NEXT: v_writelane_b32 v33, s5, 5
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[74:75], 0x10000
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v15, s60 :: v_dual_mov_b32 v16, s61
-; GFX12-NEXT: v_mov_b32_e32 v17, s54
+; GFX12-NEXT: v_dual_mov_b32 v20, s37 :: v_dual_mov_b32 v21, s38
+; GFX12-NEXT: s_bfe_i64 s[36:37], s[70:71], 0x10000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v22, s39 :: v_dual_mov_b32 v23, s36
+; GFX12-NEXT: s_bfe_i64 s[38:39], s[72:73], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX12-NEXT: s_lshr_b32 s66, s3, 28
+; GFX12-NEXT: s_lshr_b32 s48, s3, 29
+; GFX12-NEXT: s_lshr_b32 s50, s3, 26
+; GFX12-NEXT: v_mov_b32_e32 v2, s5
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x10000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v24, s37 :: v_dual_mov_b32 v25, s38
+; GFX12-NEXT: s_bfe_i64 s[36:37], s[54:55], 0x10000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v26, s39 :: v_dual_mov_b32 v27, s36
+; GFX12-NEXT: s_bfe_i64 s[38:39], s[56:57], 0x10000
+; GFX12-NEXT: s_lshr_b32 s28, s3, 17
+; GFX12-NEXT: s_lshr_b32 s42, s3, 12
+; GFX12-NEXT: s_lshr_b32 s34, s3, 3
+; GFX12-NEXT: s_mov_b32 s44, s3
+; GFX12-NEXT: s_bfe_i64 s[64:65], s[66:67], 0x10000
+; GFX12-NEXT: v_mov_b32_e32 v3, s4
+; GFX12-NEXT: s_lshr_b32 s8, s2, 12
+; GFX12-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
; GFX12-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX12-NEXT: s_lshr_b32 s4, s2, 11
+; GFX12-NEXT: s_lshr_b32 s82, s2, 7
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v28, s37 :: v_dual_mov_b32 v29, s38
+; GFX12-NEXT: s_lshr_b32 s54, s2, 3
+; GFX12-NEXT: s_lshr_b32 s38, s2, 1
+; GFX12-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s64
+; GFX12-NEXT: ; implicit-def: $sgpr5
+; GFX12-NEXT: ; implicit-def: $sgpr83
+; GFX12-NEXT: ; implicit-def: $sgpr55
; GFX12-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-NEXT: s_lshr_b32 s20, s5, 8
-; GFX12-NEXT: s_lshr_b32 s22, s5, 9
-; GFX12-NEXT: v_dual_mov_b32 v18, s55 :: v_dual_mov_b32 v19, s42
-; GFX12-NEXT: v_dual_mov_b32 v20, s43 :: v_dual_mov_b32 v21, s50
-; GFX12-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v30, s39 :: v_dual_mov_b32 v31, s28
+; GFX12-NEXT: ; implicit-def: $sgpr39
+; GFX12-NEXT: s_lshr_b32 s10, s3, 13
+; GFX12-NEXT: s_lshr_b32 s12, s3, 10
+; GFX12-NEXT: s_lshr_b32 s14, s3, 11
+; GFX12-NEXT: s_lshr_b32 s16, s3, 8
+; GFX12-NEXT: s_lshr_b32 s18, s3, 9
+; GFX12-NEXT: s_lshr_b32 s20, s3, 6
+; GFX12-NEXT: s_lshr_b32 s22, s3, 7
+; GFX12-NEXT: s_lshr_b32 s24, s3, 4
+; GFX12-NEXT: s_lshr_b32 s26, s3, 5
+; GFX12-NEXT: s_lshr_b32 s30, s3, 2
+; GFX12-NEXT: s_lshr_b32 s46, s2, 30
+; GFX12-NEXT: s_lshr_b32 s52, s2, 31
+; GFX12-NEXT: s_lshr_b32 s58, s2, 28
+; GFX12-NEXT: s_lshr_b32 s60, s2, 29
+; GFX12-NEXT: s_lshr_b32 s62, s2, 26
+; GFX12-NEXT: s_lshr_b32 s68, s2, 27
+; GFX12-NEXT: s_lshr_b32 s76, s2, 24
+; GFX12-NEXT: s_lshr_b32 s78, s2, 25
+; GFX12-NEXT: s_lshr_b32 s80, s2, 22
+; GFX12-NEXT: s_lshr_b32 s86, s2, 23
+; GFX12-NEXT: s_lshr_b32 s88, s2, 20
+; GFX12-NEXT: s_lshr_b32 s90, s2, 21
+; GFX12-NEXT: s_lshr_b32 s94, s2, 18
+; GFX12-NEXT: s_lshr_b32 s96, s2, 19
+; GFX12-NEXT: s_lshr_b32 s98, s2, 16
+; GFX12-NEXT: s_lshr_b32 s100, s2, 17
+; GFX12-NEXT: s_lshr_b32 s102, s2, 14
+; GFX12-NEXT: s_lshr_b32 vcc_lo, s2, 15
+; GFX12-NEXT: v_dual_mov_b32 v6, s65 :: v_dual_mov_b32 v7, s48
+; GFX12-NEXT: v_dual_mov_b32 v8, s49 :: v_dual_mov_b32 v9, s50
+; GFX12-NEXT: s_lshr_b32 s74, s2, 13
+; GFX12-NEXT: v_dual_mov_b32 v10, s51 :: v_dual_mov_b32 v11, s40
+; GFX12-NEXT: s_lshr_b32 s6, s2, 10
+; GFX12-NEXT: s_lshr_b32 s66, s2, 8
+; GFX12-NEXT: s_lshr_b32 s64, s2, 9
+; GFX12-NEXT: s_lshr_b32 s92, s2, 6
+; GFX12-NEXT: s_lshr_b32 s50, s2, 4
+; GFX12-NEXT: s_lshr_b32 s48, s2, 5
+; GFX12-NEXT: s_lshr_b32 s40, s2, 2
+; GFX12-NEXT: s_bfe_i64 s[36:37], s[2:3], 0x10000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[38:39], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[38:39], s[54:55], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[54:55], s[82:83], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[70:71], s[4:5], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[82:83], s[8:9], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[44:45], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[8:9], s[34:35], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[34:35], s[42:43], 0x10000
+; GFX12-NEXT: v_readlane_b32 s42, v33, 2
+; GFX12-NEXT: v_readlane_b32 s44, v33, 0
+; GFX12-NEXT: v_readlane_b32 s43, v33, 3
+; GFX12-NEXT: v_readlane_b32 s45, v33, 1
+; GFX12-NEXT: ; implicit-def: $sgpr7
+; GFX12-NEXT: s_bfe_i64 s[72:73], s[6:7], 0x10000
+; GFX12-NEXT: v_readlane_b32 s6, v33, 4
+; GFX12-NEXT: v_readlane_b32 s7, v33, 5
+; GFX12-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX12-NEXT: s_lshr_b32 s26, s5, 6
-; GFX12-NEXT: s_lshr_b32 s30, s5, 7
-; GFX12-NEXT: v_dual_mov_b32 v22, s51 :: v_dual_mov_b32 v23, s28
-; GFX12-NEXT: v_dual_mov_b32 v24, s29 :: v_dual_mov_b32 v25, s38
-; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:496
; GFX12-NEXT: global_store_b128 v0, v[5:8], s[0:1] offset:480
-; GFX12-NEXT: v_dual_mov_b32 v32, s3 :: v_dual_mov_b32 v1, s6
-; GFX12-NEXT: v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v3, s8
-; GFX12-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
-; GFX12-NEXT: s_lshr_b32 s34, s5, 4
-; GFX12-NEXT: s_lshr_b32 s36, s5, 5
-; GFX12-NEXT: s_lshr_b32 s40, s5, 2
-; GFX12-NEXT: s_lshr_b32 s44, s5, 3
-; GFX12-NEXT: v_dual_mov_b32 v26, s39 :: v_dual_mov_b32 v27, s16
-; GFX12-NEXT: v_dual_mov_b32 v28, s17 :: v_dual_mov_b32 v29, s24
+; GFX12-NEXT: v_dual_mov_b32 v32, s29 :: v_dual_mov_b32 v1, s44
+; GFX12-NEXT: v_dual_mov_b32 v2, s45 :: v_dual_mov_b32 v3, s42
+; GFX12-NEXT: v_dual_mov_b32 v4, s43 :: v_dual_mov_b32 v5, s34
+; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v6, s35 :: v_dual_mov_b32 v7, s10
+; GFX12-NEXT: v_mov_b32_e32 v8, s11
; GFX12-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v6, s11 :: v_dual_mov_b32 v7, s12
-; GFX12-NEXT: v_mov_b32_e32 v8, s13
-; GFX12-NEXT: s_lshr_b32 s46, s5, 1
-; GFX12-NEXT: s_mov_b32 s48, s5
-; GFX12-NEXT: v_dual_mov_b32 v30, s25 :: v_dual_mov_b32 v31, s2
-; GFX12-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v0, v[9:12], s[0:1] offset:464
; GFX12-NEXT: global_store_b128 v0, v[13:16], s[0:1] offset:448
@@ -11150,29 +11722,21 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v0, v[21:24], s[0:1] offset:416
; GFX12-NEXT: global_store_b128 v0, v[25:28], s[0:1] offset:400
; GFX12-NEXT: global_store_b128 v0, v[29:32], s[0:1] offset:384
-; GFX12-NEXT: v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, s15
-; GFX12-NEXT: v_dual_mov_b32 v11, s18 :: v_dual_mov_b32 v12, s19
-; GFX12-NEXT: v_mov_b32_e32 v13, s20
-; GFX12-NEXT: s_lshr_b32 s52, s4, 30
-; GFX12-NEXT: s_lshr_b32 s56, s4, 31
-; GFX12-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v14, s21 :: v_dual_mov_b32 v15, s22
-; GFX12-NEXT: v_dual_mov_b32 v16, s23 :: v_dual_mov_b32 v17, s26
-; GFX12-NEXT: s_lshr_b32 s58, s4, 28
-; GFX12-NEXT: s_lshr_b32 s62, s4, 29
-; GFX12-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v18, s27 :: v_dual_mov_b32 v19, s30
-; GFX12-NEXT: v_dual_mov_b32 v20, s31 :: v_dual_mov_b32 v21, s34
-; GFX12-NEXT: s_lshr_b32 s66, s4, 26
-; GFX12-NEXT: s_lshr_b32 s68, s4, 27
-; GFX12-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
+; GFX12-NEXT: v_dual_mov_b32 v11, s14 :: v_dual_mov_b32 v12, s15
+; GFX12-NEXT: v_mov_b32_e32 v13, s16
+; GFX12-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v14, s17 :: v_dual_mov_b32 v15, s18
+; GFX12-NEXT: v_dual_mov_b32 v16, s19 :: v_dual_mov_b32 v17, s20
+; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v18, s21 :: v_dual_mov_b32 v19, s22
+; GFX12-NEXT: v_dual_mov_b32 v20, s23 :: v_dual_mov_b32 v21, s24
; GFX12-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v22, s35 :: v_dual_mov_b32 v23, s36
-; GFX12-NEXT: v_mov_b32_e32 v24, s37
+; GFX12-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v22, s25 :: v_dual_mov_b32 v23, s26
+; GFX12-NEXT: v_mov_b32_e32 v24, s27
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:368
; GFX12-NEXT: global_store_b128 v0, v[5:8], s[0:1] offset:352
@@ -11180,49 +11744,32 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v0, v[13:16], s[0:1] offset:320
; GFX12-NEXT: global_store_b128 v0, v[17:20], s[0:1] offset:304
; GFX12-NEXT: global_store_b128 v0, v[21:24], s[0:1] offset:288
-; GFX12-NEXT: v_dual_mov_b32 v1, s40 :: v_dual_mov_b32 v2, s41
-; GFX12-NEXT: v_dual_mov_b32 v3, s44 :: v_dual_mov_b32 v4, s45
-; GFX12-NEXT: v_mov_b32_e32 v5, s48
-; GFX12-NEXT: s_lshr_b32 s70, s4, 24
-; GFX12-NEXT: s_lshr_b32 s74, s4, 25
-; GFX12-NEXT: s_lshr_b32 s78, s4, 22
-; GFX12-NEXT: s_lshr_b32 s80, s4, 23
-; GFX12-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v1, s30 :: v_dual_mov_b32 v2, s31
+; GFX12-NEXT: v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s9
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v5, s4
+; GFX12-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
; GFX12-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v6, s49 :: v_dual_mov_b32 v7, s46
-; GFX12-NEXT: v_dual_mov_b32 v8, s47 :: v_dual_mov_b32 v9, s52
-; GFX12-NEXT: s_lshr_b32 s82, s4, 20
-; GFX12-NEXT: s_lshr_b32 s84, s4, 21
+; GFX12-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v7, s6
+; GFX12-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v9, s46
; GFX12-NEXT: s_bfe_i64 s[68:69], s[68:69], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v10, s53 :: v_dual_mov_b32 v11, s56
-; GFX12-NEXT: v_dual_mov_b32 v12, s57 :: v_dual_mov_b32 v13, s58
-; GFX12-NEXT: s_lshr_b32 s88, s4, 18
-; GFX12-NEXT: s_lshr_b32 s92, s4, 19
+; GFX12-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v10, s47 :: v_dual_mov_b32 v11, s52
+; GFX12-NEXT: v_dual_mov_b32 v12, s53 :: v_dual_mov_b32 v13, s58
+; GFX12-NEXT: s_bfe_i64 s[86:87], s[86:87], 0x10000
; GFX12-NEXT: s_bfe_i64 s[80:81], s[80:81], 0x10000
; GFX12-NEXT: s_bfe_i64 s[78:79], s[78:79], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[74:75], s[74:75], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[70:71], s[70:71], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v14, s59 :: v_dual_mov_b32 v15, s62
-; GFX12-NEXT: v_dual_mov_b32 v16, s63 :: v_dual_mov_b32 v17, s66
-; GFX12-NEXT: s_lshr_b32 s94, s4, 16
-; GFX12-NEXT: s_lshr_b32 s100, s4, 17
-; GFX12-NEXT: s_bfe_i64 s[84:85], s[84:85], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[82:83], s[82:83], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v18, s67 :: v_dual_mov_b32 v19, s68
-; GFX12-NEXT: v_dual_mov_b32 v20, s69 :: v_dual_mov_b32 v21, s70
-; GFX12-NEXT: s_lshr_b32 s98, s4, 14
-; GFX12-NEXT: s_lshr_b32 s102, s4, 15
-; GFX12-NEXT: s_lshr_b32 s96, s4, 13
-; GFX12-NEXT: s_lshr_b32 s86, s4, 8
-; GFX12-NEXT: s_lshr_b32 s64, s4, 7
-; GFX12-NEXT: s_lshr_b32 s50, s4, 5
-; GFX12-NEXT: s_lshr_b32 s38, s4, 3
-; GFX12-NEXT: s_lshr_b32 s24, s4, 1
-; GFX12-NEXT: s_bfe_i64 s[92:93], s[92:93], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[76:77], s[76:77], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v14, s59 :: v_dual_mov_b32 v15, s60
+; GFX12-NEXT: v_dual_mov_b32 v16, s61 :: v_dual_mov_b32 v17, s62
+; GFX12-NEXT: s_bfe_i64 s[90:91], s[90:91], 0x10000
; GFX12-NEXT: s_bfe_i64 s[88:89], s[88:89], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v22, s71 :: v_dual_mov_b32 v23, s74
-; GFX12-NEXT: v_mov_b32_e32 v24, s75
+; GFX12-NEXT: v_dual_mov_b32 v18, s63 :: v_dual_mov_b32 v19, s68
+; GFX12-NEXT: v_dual_mov_b32 v20, s69 :: v_dual_mov_b32 v21, s76
+; GFX12-NEXT: s_bfe_i64 s[96:97], s[96:97], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[94:95], s[94:95], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v22, s77 :: v_dual_mov_b32 v23, s78
+; GFX12-NEXT: v_mov_b32_e32 v24, s79
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:272
; GFX12-NEXT: global_store_b128 v0, v[5:8], s[0:1] offset:256
@@ -11230,44 +11777,33 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v0, v[13:16], s[0:1] offset:224
; GFX12-NEXT: global_store_b128 v0, v[17:20], s[0:1] offset:208
; GFX12-NEXT: global_store_b128 v0, v[21:24], s[0:1] offset:192
-; GFX12-NEXT: v_dual_mov_b32 v1, s78 :: v_dual_mov_b32 v2, s79
-; GFX12-NEXT: v_dual_mov_b32 v3, s80 :: v_dual_mov_b32 v4, s81
-; GFX12-NEXT: v_mov_b32_e32 v5, s82
-; GFX12-NEXT: s_lshr_b32 s90, s4, 12
-; GFX12-NEXT: s_lshr_b32 s76, s4, 10
-; GFX12-NEXT: s_lshr_b32 s72, s4, 11
+; GFX12-NEXT: v_dual_mov_b32 v1, s80 :: v_dual_mov_b32 v2, s81
+; GFX12-NEXT: v_dual_mov_b32 v3, s86 :: v_dual_mov_b32 v4, s87
+; GFX12-NEXT: v_mov_b32_e32 v5, s88
+; GFX12-NEXT: ; implicit-def: $sgpr93
; GFX12-NEXT: s_bfe_i64 s[100:101], s[100:101], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[94:95], s[94:95], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v6, s83 :: v_dual_mov_b32 v7, s84
-; GFX12-NEXT: v_dual_mov_b32 v8, s85 :: v_dual_mov_b32 v9, s88
-; GFX12-NEXT: s_lshr_b32 s60, s4, 9
-; GFX12-NEXT: s_lshr_b32 s54, s4, 6
-; GFX12-NEXT: s_lshr_b32 s42, s4, 4
-; GFX12-NEXT: s_lshr_b32 s28, s4, 2
-; GFX12-NEXT: s_bfe_i64 s[16:17], s[4:5], 0x10000
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[24:25], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[24:25], s[38:39], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[38:39], s[50:51], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[50:51], s[64:65], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[64:65], s[86:87], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[86:87], s[96:97], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[96:97], s[102:103], 0x10000
; GFX12-NEXT: s_bfe_i64 s[98:99], s[98:99], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v10, s89 :: v_dual_mov_b32 v11, s92
-; GFX12-NEXT: v_dual_mov_b32 v12, s93 :: v_dual_mov_b32 v13, s94
-; GFX12-NEXT: s_bfe_i64 s[72:73], s[72:73], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[76:77], s[76:77], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[90:91], s[90:91], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v14, s95 :: v_dual_mov_b32 v15, s100
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v16, s101 :: v_dual_mov_b32 v17, s98
-; GFX12-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v18, s99 :: v_dual_mov_b32 v19, s96
-; GFX12-NEXT: v_dual_mov_b32 v20, s97 :: v_dual_mov_b32 v21, s90
-; GFX12-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v22, s91 :: v_dual_mov_b32 v23, s86
-; GFX12-NEXT: v_mov_b32_e32 v24, s87
+; GFX12-NEXT: v_dual_mov_b32 v6, s89 :: v_dual_mov_b32 v7, s90
+; GFX12-NEXT: v_dual_mov_b32 v8, s91 :: v_dual_mov_b32 v9, s94
+; GFX12-NEXT: ; implicit-def: $sgpr75
+; GFX12-NEXT: s_bfe_i64 s[56:57], s[92:93], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[84:85], vcc, 0x10000
+; GFX12-NEXT: s_bfe_i64 s[92:93], s[102:103], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v10, s95 :: v_dual_mov_b32 v11, s96
+; GFX12-NEXT: v_dual_mov_b32 v12, s97 :: v_dual_mov_b32 v13, s98
+; GFX12-NEXT: ; implicit-def: $sgpr67
+; GFX12-NEXT: ; implicit-def: $sgpr65
+; GFX12-NEXT: s_bfe_i64 s[74:75], s[74:75], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v14, s99 :: v_dual_mov_b32 v15, s100
+; GFX12-NEXT: v_dual_mov_b32 v16, s101 :: v_dual_mov_b32 v17, s92
+; GFX12-NEXT: s_bfe_i64 s[64:65], s[64:65], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v18, s93 :: v_dual_mov_b32 v19, s84
+; GFX12-NEXT: v_dual_mov_b32 v20, s85 :: v_dual_mov_b32 v21, s82
+; GFX12-NEXT: ; implicit-def: $sgpr51
+; GFX12-NEXT: ; implicit-def: $sgpr49
+; GFX12-NEXT: v_dual_mov_b32 v22, s83 :: v_dual_mov_b32 v23, s74
+; GFX12-NEXT: v_mov_b32_e32 v24, s75
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:176
; GFX12-NEXT: global_store_b128 v0, v[5:8], s[0:1] offset:160
@@ -11275,23 +11811,25 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v0, v[13:16], s[0:1] offset:128
; GFX12-NEXT: global_store_b128 v0, v[17:20], s[0:1] offset:112
; GFX12-NEXT: global_store_b128 v0, v[21:24], s[0:1] offset:96
-; GFX12-NEXT: v_dual_mov_b32 v1, s76 :: v_dual_mov_b32 v2, s77
-; GFX12-NEXT: v_dual_mov_b32 v3, s72 :: v_dual_mov_b32 v4, s73
-; GFX12-NEXT: v_mov_b32_e32 v5, s64
-; GFX12-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v1, s72 :: v_dual_mov_b32 v2, s73
+; GFX12-NEXT: v_dual_mov_b32 v3, s70 :: v_dual_mov_b32 v4, s71
+; GFX12-NEXT: v_mov_b32_e32 v5, s66
+; GFX12-NEXT: ; implicit-def: $sgpr41
+; GFX12-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v6, s65 :: v_dual_mov_b32 v7, s60
-; GFX12-NEXT: v_dual_mov_b32 v8, s61 :: v_dual_mov_b32 v9, s54
-; GFX12-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v10, s55 :: v_dual_mov_b32 v11, s50
-; GFX12-NEXT: v_dual_mov_b32 v12, s51 :: v_dual_mov_b32 v13, s42
-; GFX12-NEXT: v_dual_mov_b32 v14, s43 :: v_dual_mov_b32 v15, s38
+; GFX12-NEXT: v_dual_mov_b32 v6, s67 :: v_dual_mov_b32 v7, s64
+; GFX12-NEXT: v_dual_mov_b32 v8, s65 :: v_dual_mov_b32 v9, s56
+; GFX12-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v10, s57 :: v_dual_mov_b32 v11, s54
+; GFX12-NEXT: v_dual_mov_b32 v12, s55 :: v_dual_mov_b32 v13, s50
+; GFX12-NEXT: v_dual_mov_b32 v14, s51 :: v_dual_mov_b32 v15, s48
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v16, s39 :: v_dual_mov_b32 v17, s28
-; GFX12-NEXT: v_dual_mov_b32 v18, s29 :: v_dual_mov_b32 v19, s24
-; GFX12-NEXT: v_dual_mov_b32 v20, s25 :: v_dual_mov_b32 v21, s16
-; GFX12-NEXT: v_dual_mov_b32 v22, s17 :: v_dual_mov_b32 v23, s4
-; GFX12-NEXT: v_mov_b32_e32 v24, s5
+; GFX12-NEXT: v_dual_mov_b32 v16, s49 :: v_dual_mov_b32 v17, s40
+; GFX12-NEXT: v_dual_mov_b32 v18, s41 :: v_dual_mov_b32 v19, s38
+; GFX12-NEXT: v_dual_mov_b32 v20, s39 :: v_dual_mov_b32 v21, s36
+; GFX12-NEXT: v_dual_mov_b32 v22, s37 :: v_dual_mov_b32 v23, s2
+; GFX12-NEXT: v_mov_b32_e32 v24, s3
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:80
; GFX12-NEXT: global_store_b128 v0, v[5:8], s[0:1] offset:64
@@ -11305,280 +11843,349 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: s_mov_b32 s61, 0
+; GFX1250-NEXT: ; implicit-def: $sgpr5
+; GFX1250-NEXT: ; implicit-def: $vgpr17 : SGPR spill to VGPR lane
+; GFX1250-NEXT: ; implicit-def: $sgpr7
+; GFX1250-NEXT: s_mov_b32 s39, 0
+; GFX1250-NEXT: ; implicit-def: $sgpr41
+; GFX1250-NEXT: ; implicit-def: $sgpr37
+; GFX1250-NEXT: ; implicit-def: $sgpr75
+; GFX1250-NEXT: ; implicit-def: $sgpr65
+; GFX1250-NEXT: ; implicit-def: $sgpr49
+; GFX1250-NEXT: ; implicit-def: $sgpr51
+; GFX1250-NEXT: ; implicit-def: $sgpr67
+; GFX1250-NEXT: ; implicit-def: $sgpr43
+; GFX1250-NEXT: ; implicit-def: $sgpr35
+; GFX1250-NEXT: ; implicit-def: $sgpr9
+; GFX1250-NEXT: ; implicit-def: $sgpr11
+; GFX1250-NEXT: ; implicit-def: $sgpr13
+; GFX1250-NEXT: ; implicit-def: $sgpr15
+; GFX1250-NEXT: ; implicit-def: $sgpr17
+; GFX1250-NEXT: ; implicit-def: $sgpr19
+; GFX1250-NEXT: ; implicit-def: $sgpr21
+; GFX1250-NEXT: ; implicit-def: $sgpr23
+; GFX1250-NEXT: ; implicit-def: $sgpr25
+; GFX1250-NEXT: ; implicit-def: $sgpr27
+; GFX1250-NEXT: ; implicit-def: $sgpr31
+; GFX1250-NEXT: ; implicit-def: $sgpr47
+; GFX1250-NEXT: ; implicit-def: $sgpr53
+; GFX1250-NEXT: ; implicit-def: $sgpr59
+; GFX1250-NEXT: ; implicit-def: $sgpr61
+; GFX1250-NEXT: ; implicit-def: $sgpr63
+; GFX1250-NEXT: ; implicit-def: $sgpr69
+; GFX1250-NEXT: ; implicit-def: $sgpr77
+; GFX1250-NEXT: ; implicit-def: $sgpr79
+; GFX1250-NEXT: ; implicit-def: $sgpr81
+; GFX1250-NEXT: ; implicit-def: $sgpr87
+; GFX1250-NEXT: ; implicit-def: $sgpr89
+; GFX1250-NEXT: ; implicit-def: $sgpr91
+; GFX1250-NEXT: ; implicit-def: $sgpr95
+; GFX1250-NEXT: ; implicit-def: $sgpr97
+; GFX1250-NEXT: ; implicit-def: $sgpr99
+; GFX1250-NEXT: ; implicit-def: $sgpr101
+; GFX1250-NEXT: ; implicit-def: $sgpr103
+; GFX1250-NEXT: ; implicit-def: $vcc_hi
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: s_mov_b32 s55, s61
-; GFX1250-NEXT: s_mov_b32 s43, s61
-; GFX1250-NEXT: s_mov_b32 s51, s61
-; GFX1250-NEXT: s_mov_b32 s29, s61
-; GFX1250-NEXT: s_mov_b32 s39, s61
-; GFX1250-NEXT: s_mov_b32 s17, s61
-; GFX1250-NEXT: s_mov_b32 s25, s61
-; GFX1250-NEXT: s_mov_b32 s49, s61
+; GFX1250-NEXT: s_mov_b32 s93, s39
+; GFX1250-NEXT: s_mov_b32 s83, s39
+; GFX1250-NEXT: s_mov_b32 s85, s39
+; GFX1250-NEXT: s_mov_b32 s71, s39
+; GFX1250-NEXT: s_mov_b32 s73, s39
+; GFX1250-NEXT: s_mov_b32 s55, s39
+; GFX1250-NEXT: s_mov_b32 s57, s39
+; GFX1250-NEXT: s_mov_b32 s29, s39
+; GFX1250-NEXT: s_mov_b32 s45, s39
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_load_b64 s[4:5], s[2:3], 0x0 nv
-; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s3, s61
+; GFX1250-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 nv
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s98, s5, 30
-; GFX1250-NEXT: s_lshr_b32 s90, s5, 31
-; GFX1250-NEXT: s_lshr_b32 s96, s5, 28
-; GFX1250-NEXT: s_lshr_b32 s76, s5, 29
-; GFX1250-NEXT: s_lshr_b32 s72, s5, 27
-; GFX1250-NEXT: s_lshr_b32 s60, s5, 24
-; GFX1250-NEXT: s_lshr_b32 s86, s5, 26
-; GFX1250-NEXT: s_bfe_i64 s[98:99], s[98:99], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[90:91], s[90:91], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s64, s5, 25
-; GFX1250-NEXT: s_bfe_i64 s[96:97], s[96:97], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[76:77], s[76:77], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[72:73], s[72:73], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v0, s98
-; GFX1250-NEXT: s_lshr_b32 s54, s5, 22
-; GFX1250-NEXT: s_lshr_b32 s42, s5, 23
-; GFX1250-NEXT: v_dual_mov_b32 v1, s99 :: v_dual_mov_b32 v2, s90
-; GFX1250-NEXT: v_dual_mov_b32 v3, s91 :: v_dual_mov_b32 v4, s96
-; GFX1250-NEXT: s_bfe_i64 s[86:87], s[86:87], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s50, s5, 20
-; GFX1250-NEXT: s_lshr_b32 s28, s5, 21
-; GFX1250-NEXT: s_lshr_b32 s2, s5, 17
-; GFX1250-NEXT: s_lshr_b32 s6, s5, 14
-; GFX1250-NEXT: s_lshr_b32 s8, s5, 15
-; GFX1250-NEXT: v_dual_mov_b32 v5, s97 :: v_dual_mov_b32 v6, s76
-; GFX1250-NEXT: v_dual_mov_b32 v7, s77 :: v_dual_mov_b32 v10, s86
-; GFX1250-NEXT: v_dual_mov_b32 v13, s73 :: v_dual_mov_b32 v14, s60
-; GFX1250-NEXT: v_mov_b32_e32 v15, s61
-; GFX1250-NEXT: s_bfe_i64 s[60:61], s[64:65], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s38, s5, 18
-; GFX1250-NEXT: s_lshr_b32 s16, s5, 19
-; GFX1250-NEXT: s_lshr_b32 s10, s5, 12
-; GFX1250-NEXT: s_lshr_b32 s12, s5, 13
-; GFX1250-NEXT: v_dual_mov_b32 v11, s87 :: v_dual_mov_b32 v12, s72
-; GFX1250-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s24, s5, 16
-; GFX1250-NEXT: s_lshr_b32 s14, s5, 10
-; GFX1250-NEXT: s_lshr_b32 s18, s5, 11
-; GFX1250-NEXT: v_dual_mov_b32 v16, s60 :: v_dual_mov_b32 v17, s61
-; GFX1250-NEXT: v_mov_b32_e32 v18, s54
+; GFX1250-NEXT: s_lshr_b32 s4, s3, 14
+; GFX1250-NEXT: s_lshr_b32 s6, s3, 15
+; GFX1250-NEXT: v_writelane_b32 v17, s4, 0
+; GFX1250-NEXT: s_lshr_b32 s40, s3, 27
+; GFX1250-NEXT: s_lshr_b32 s38, s3, 24
+; GFX1250-NEXT: s_lshr_b32 s36, s3, 25
+; GFX1250-NEXT: s_lshr_b32 s92, s3, 22
+; GFX1250-NEXT: v_writelane_b32 v17, s5, 1
+; GFX1250-NEXT: s_lshr_b32 s4, s3, 1
+; GFX1250-NEXT: ; implicit-def: $sgpr5
+; GFX1250-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
+; GFX1250-NEXT: s_lshr_b32 s82, s3, 23
+; GFX1250-NEXT: v_writelane_b32 v17, s6, 2
+; GFX1250-NEXT: s_lshr_b32 s84, s3, 20
+; GFX1250-NEXT: v_dual_mov_b32 v11, s41 :: v_dual_mov_b32 v12, s38
+; GFX1250-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX1250-NEXT: v_writelane_b32 v17, s7, 3
+; GFX1250-NEXT: v_dual_mov_b32 v13, s39 :: v_dual_mov_b32 v14, s36
+; GFX1250-NEXT: s_bfe_i64 s[38:39], s[92:93], 0x10000
+; GFX1250-NEXT: s_lshr_b32 s74, s3, 30
+; GFX1250-NEXT: v_writelane_b32 v17, s4, 4
+; GFX1250-NEXT: s_lshr_b32 s70, s3, 21
+; GFX1250-NEXT: s_lshr_b32 s72, s3, 18
+; GFX1250-NEXT: v_dual_mov_b32 v15, s37 :: v_dual_mov_b32 v18, s38
+; GFX1250-NEXT: s_bfe_i64 s[36:37], s[82:83], 0x10000
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v19, s39 :: v_dual_mov_b32 v20, s36
+; GFX1250-NEXT: s_bfe_i64 s[38:39], s[84:85], 0x10000
+; GFX1250-NEXT: s_lshr_b32 s64, s3, 31
+; GFX1250-NEXT: s_lshr_b32 s54, s3, 19
+; GFX1250-NEXT: s_lshr_b32 s56, s3, 16
+; GFX1250-NEXT: v_writelane_b32 v17, s5, 5
+; GFX1250-NEXT: s_bfe_i64 s[4:5], s[74:75], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v21, s37 :: v_dual_mov_b32 v22, s38
+; GFX1250-NEXT: s_bfe_i64 s[36:37], s[70:71], 0x10000
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v23, s39 :: v_dual_mov_b32 v24, s36
+; GFX1250-NEXT: s_bfe_i64 s[38:39], s[72:73], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v0, s4
+; GFX1250-NEXT: s_lshr_b32 s66, s3, 28
+; GFX1250-NEXT: s_lshr_b32 s48, s3, 29
+; GFX1250-NEXT: s_lshr_b32 s50, s3, 26
+; GFX1250-NEXT: v_mov_b32_e32 v1, s5
+; GFX1250-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v25, s37 :: v_dual_mov_b32 v26, s38
+; GFX1250-NEXT: s_bfe_i64 s[36:37], s[54:55], 0x10000
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v27, s39 :: v_dual_mov_b32 v28, s36
+; GFX1250-NEXT: s_bfe_i64 s[38:39], s[56:57], 0x10000
+; GFX1250-NEXT: s_lshr_b32 s28, s3, 17
+; GFX1250-NEXT: s_lshr_b32 s42, s3, 12
+; GFX1250-NEXT: s_lshr_b32 s34, s3, 3
+; GFX1250-NEXT: s_mov_b32 s44, s3
+; GFX1250-NEXT: s_bfe_i64 s[64:65], s[66:67], 0x10000
+; GFX1250-NEXT: v_mov_b32_e32 v2, s4
+; GFX1250-NEXT: s_lshr_b32 s8, s2, 12
+; GFX1250-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX1250-NEXT: s_lshr_b32 s4, s2, 11
+; GFX1250-NEXT: s_lshr_b32 s82, s2, 7
+; GFX1250-NEXT: v_dual_mov_b32 v29, s37 :: v_dual_mov_b32 v30, s38
+; GFX1250-NEXT: s_lshr_b32 s54, s2, 3
+; GFX1250-NEXT: s_lshr_b32 s38, s2, 1
+; GFX1250-NEXT: v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v4, s64
+; GFX1250-NEXT: ; implicit-def: $sgpr5
+; GFX1250-NEXT: ; implicit-def: $sgpr83
+; GFX1250-NEXT: ; implicit-def: $sgpr55
; GFX1250-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s20, s5, 8
-; GFX1250-NEXT: s_lshr_b32 s22, s5, 9
-; GFX1250-NEXT: v_dual_mov_b32 v19, s55 :: v_dual_mov_b32 v20, s42
-; GFX1250-NEXT: v_dual_mov_b32 v21, s43 :: v_dual_mov_b32 v22, s50
-; GFX1250-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v31, s39 :: v_dual_mov_b32 v32, s28
+; GFX1250-NEXT: ; implicit-def: $sgpr39
+; GFX1250-NEXT: s_lshr_b32 s10, s3, 13
+; GFX1250-NEXT: s_lshr_b32 s12, s3, 10
+; GFX1250-NEXT: s_lshr_b32 s14, s3, 11
+; GFX1250-NEXT: s_lshr_b32 s16, s3, 8
+; GFX1250-NEXT: s_lshr_b32 s18, s3, 9
+; GFX1250-NEXT: s_lshr_b32 s20, s3, 6
+; GFX1250-NEXT: s_lshr_b32 s22, s3, 7
+; GFX1250-NEXT: s_lshr_b32 s24, s3, 4
+; GFX1250-NEXT: s_lshr_b32 s26, s3, 5
+; GFX1250-NEXT: s_lshr_b32 s30, s3, 2
+; GFX1250-NEXT: s_lshr_b32 s46, s2, 30
+; GFX1250-NEXT: s_lshr_b32 s52, s2, 31
+; GFX1250-NEXT: s_lshr_b32 s58, s2, 28
+; GFX1250-NEXT: s_lshr_b32 s60, s2, 29
+; GFX1250-NEXT: s_lshr_b32 s62, s2, 26
+; GFX1250-NEXT: s_lshr_b32 s68, s2, 27
+; GFX1250-NEXT: s_lshr_b32 s76, s2, 24
+; GFX1250-NEXT: s_lshr_b32 s78, s2, 25
+; GFX1250-NEXT: s_lshr_b32 s80, s2, 22
+; GFX1250-NEXT: s_lshr_b32 s86, s2, 23
+; GFX1250-NEXT: s_lshr_b32 s88, s2, 20
+; GFX1250-NEXT: s_lshr_b32 s90, s2, 21
+; GFX1250-NEXT: s_lshr_b32 s94, s2, 18
+; GFX1250-NEXT: s_lshr_b32 s96, s2, 19
+; GFX1250-NEXT: s_lshr_b32 s98, s2, 16
+; GFX1250-NEXT: s_lshr_b32 s100, s2, 17
+; GFX1250-NEXT: s_lshr_b32 s102, s2, 14
+; GFX1250-NEXT: s_lshr_b32 vcc_lo, s2, 15
+; GFX1250-NEXT: v_dual_mov_b32 v5, s65 :: v_dual_mov_b32 v6, s48
+; GFX1250-NEXT: v_dual_mov_b32 v7, s49 :: v_dual_mov_b32 v8, s50
+; GFX1250-NEXT: s_lshr_b32 s74, s2, 13
+; GFX1250-NEXT: v_dual_mov_b32 v9, s51 :: v_dual_mov_b32 v10, s40
+; GFX1250-NEXT: s_lshr_b32 s6, s2, 10
+; GFX1250-NEXT: s_lshr_b32 s66, s2, 8
+; GFX1250-NEXT: s_lshr_b32 s64, s2, 9
+; GFX1250-NEXT: s_lshr_b32 s92, s2, 6
+; GFX1250-NEXT: s_lshr_b32 s50, s2, 4
+; GFX1250-NEXT: s_lshr_b32 s48, s2, 5
+; GFX1250-NEXT: s_lshr_b32 s40, s2, 2
+; GFX1250-NEXT: s_bfe_i64 s[36:37], s[2:3], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[2:3], s[38:39], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[38:39], s[54:55], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[54:55], s[82:83], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[70:71], s[4:5], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[82:83], s[8:9], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[4:5], s[44:45], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[8:9], s[34:35], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[34:35], s[42:43], 0x10000
+; GFX1250-NEXT: v_readlane_b32 s42, v17, 2
+; GFX1250-NEXT: v_readlane_b32 s44, v17, 0
+; GFX1250-NEXT: v_readlane_b32 s43, v17, 3
+; GFX1250-NEXT: v_readlane_b32 s45, v17, 1
+; GFX1250-NEXT: ; implicit-def: $sgpr7
+; GFX1250-NEXT: s_bfe_i64 s[72:73], s[6:7], 0x10000
+; GFX1250-NEXT: v_readlane_b32 s6, v17, 4
+; GFX1250-NEXT: v_readlane_b32 s7, v17, 5
+; GFX1250-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s26, s5, 6
-; GFX1250-NEXT: s_lshr_b32 s30, s5, 7
-; GFX1250-NEXT: v_dual_mov_b32 v23, s51 :: v_dual_mov_b32 v24, s28
-; GFX1250-NEXT: v_dual_mov_b32 v25, s29 :: v_dual_mov_b32 v26, s38
-; GFX1250-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:496
-; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:480
+; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:496
+; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:480
; GFX1250-NEXT: s_wait_xcnt 0x1
-; GFX1250-NEXT: v_dual_mov_b32 v33, s3 :: v_dual_mov_b32 v0, s6
-; GFX1250-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s8
+; GFX1250-NEXT: v_dual_mov_b32 v33, s29 :: v_dual_mov_b32 v0, s44
+; GFX1250-NEXT: v_dual_mov_b32 v1, s45 :: v_dual_mov_b32 v2, s42
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
-; GFX1250-NEXT: s_lshr_b32 s34, s5, 4
-; GFX1250-NEXT: s_lshr_b32 s36, s5, 5
-; GFX1250-NEXT: s_lshr_b32 s40, s5, 2
-; GFX1250-NEXT: s_lshr_b32 s44, s5, 3
-; GFX1250-NEXT: v_dual_mov_b32 v27, s39 :: v_dual_mov_b32 v28, s16
-; GFX1250-NEXT: v_dual_mov_b32 v29, s17 :: v_dual_mov_b32 v30, s24
+; GFX1250-NEXT: v_dual_mov_b32 v3, s43 :: v_dual_mov_b32 v4, s34
+; GFX1250-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v5, s35 :: v_dual_mov_b32 v6, s10
+; GFX1250-NEXT: v_mov_b32_e32 v7, s11
; GFX1250-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v6, s12
-; GFX1250-NEXT: v_mov_b32_e32 v7, s13
-; GFX1250-NEXT: s_lshr_b32 s46, s5, 1
-; GFX1250-NEXT: s_mov_b32 s48, s5
-; GFX1250-NEXT: v_dual_mov_b32 v31, s25 :: v_dual_mov_b32 v32, s2
-; GFX1250-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
; GFX1250-NEXT: s_clause 0x5
-; GFX1250-NEXT: global_store_b128 v8, v[10:13], s[0:1] offset:464
-; GFX1250-NEXT: global_store_b128 v8, v[14:17], s[0:1] offset:448
-; GFX1250-NEXT: global_store_b128 v8, v[18:21], s[0:1] offset:432
-; GFX1250-NEXT: global_store_b128 v8, v[22:25], s[0:1] offset:416
-; GFX1250-NEXT: global_store_b128 v8, v[26:29], s[0:1] offset:400
-; GFX1250-NEXT: global_store_b128 v8, v[30:33], s[0:1] offset:384
+; GFX1250-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:464
+; GFX1250-NEXT: global_store_b128 v16, v[12:15], s[0:1] offset:448
+; GFX1250-NEXT: global_store_b128 v16, v[18:21], s[0:1] offset:432
+; GFX1250-NEXT: global_store_b128 v16, v[22:25], s[0:1] offset:416
+; GFX1250-NEXT: global_store_b128 v16, v[26:29], s[0:1] offset:400
+; GFX1250-NEXT: global_store_b128 v16, v[30:33], s[0:1] offset:384
; GFX1250-NEXT: s_wait_xcnt 0x5
+; GFX1250-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
; GFX1250-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
-; GFX1250-NEXT: v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v13, s19
; GFX1250-NEXT: s_wait_xcnt 0x4
-; GFX1250-NEXT: v_mov_b32_e32 v14, s20
-; GFX1250-NEXT: s_lshr_b32 s52, s4, 30
-; GFX1250-NEXT: s_lshr_b32 s56, s4, 31
-; GFX1250-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v15, s21 :: v_dual_mov_b32 v16, s22
+; GFX1250-NEXT: v_mov_b32_e32 v12, s16
+; GFX1250-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v13, s17 :: v_dual_mov_b32 v14, s18
; GFX1250-NEXT: s_wait_xcnt 0x3
-; GFX1250-NEXT: v_dual_mov_b32 v17, s23 :: v_dual_mov_b32 v18, s26
-; GFX1250-NEXT: s_lshr_b32 s58, s4, 28
-; GFX1250-NEXT: s_lshr_b32 s62, s4, 29
-; GFX1250-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v19, s27 :: v_dual_mov_b32 v20, s30
+; GFX1250-NEXT: v_dual_mov_b32 v15, s19 :: v_dual_mov_b32 v18, s20
+; GFX1250-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v19, s21 :: v_dual_mov_b32 v20, s22
; GFX1250-NEXT: s_wait_xcnt 0x2
-; GFX1250-NEXT: v_dual_mov_b32 v21, s31 :: v_dual_mov_b32 v22, s34
-; GFX1250-NEXT: s_lshr_b32 s66, s4, 26
-; GFX1250-NEXT: s_lshr_b32 s68, s4, 27
-; GFX1250-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v21, s23 :: v_dual_mov_b32 v22, s24
; GFX1250-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v23, s35 :: v_dual_mov_b32 v24, s36
-; GFX1250-NEXT: v_mov_b32_e32 v25, s37
+; GFX1250-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v23, s25 :: v_dual_mov_b32 v24, s26
+; GFX1250-NEXT: v_mov_b32_e32 v25, s27
; GFX1250-NEXT: s_clause 0x5
-; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:368
-; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:352
-; GFX1250-NEXT: global_store_b128 v8, v[10:13], s[0:1] offset:336
-; GFX1250-NEXT: global_store_b128 v8, v[14:17], s[0:1] offset:320
-; GFX1250-NEXT: global_store_b128 v8, v[18:21], s[0:1] offset:304
-; GFX1250-NEXT: global_store_b128 v8, v[22:25], s[0:1] offset:288
+; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:368
+; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:352
+; GFX1250-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:336
+; GFX1250-NEXT: global_store_b128 v16, v[12:15], s[0:1] offset:320
+; GFX1250-NEXT: global_store_b128 v16, v[18:21], s[0:1] offset:304
+; GFX1250-NEXT: global_store_b128 v16, v[22:25], s[0:1] offset:288
; GFX1250-NEXT: s_wait_xcnt 0x5
-; GFX1250-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v1, s41
-; GFX1250-NEXT: v_dual_mov_b32 v2, s44 :: v_dual_mov_b32 v3, s45
+; GFX1250-NEXT: v_dual_mov_b32 v0, s30 :: v_dual_mov_b32 v1, s31
+; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
; GFX1250-NEXT: s_wait_xcnt 0x4
-; GFX1250-NEXT: v_mov_b32_e32 v4, s48
-; GFX1250-NEXT: s_lshr_b32 s70, s4, 24
-; GFX1250-NEXT: s_lshr_b32 s74, s4, 25
-; GFX1250-NEXT: s_lshr_b32 s78, s4, 22
-; GFX1250-NEXT: s_lshr_b32 s80, s4, 23
-; GFX1250-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
+; GFX1250-NEXT: v_mov_b32_e32 v4, s4
+; GFX1250-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s49 :: v_dual_mov_b32 v6, s46
+; GFX1250-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6
; GFX1250-NEXT: s_wait_xcnt 0x3
-; GFX1250-NEXT: v_dual_mov_b32 v7, s47 :: v_dual_mov_b32 v10, s52
-; GFX1250-NEXT: s_lshr_b32 s82, s4, 20
-; GFX1250-NEXT: s_lshr_b32 s84, s4, 21
+; GFX1250-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v8, s46
; GFX1250-NEXT: s_bfe_i64 s[68:69], s[68:69], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v11, s53 :: v_dual_mov_b32 v12, s56
+; GFX1250-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v9, s47 :: v_dual_mov_b32 v10, s52
; GFX1250-NEXT: s_wait_xcnt 0x2
-; GFX1250-NEXT: v_dual_mov_b32 v13, s57 :: v_dual_mov_b32 v14, s58
-; GFX1250-NEXT: s_lshr_b32 s88, s4, 18
-; GFX1250-NEXT: s_lshr_b32 s92, s4, 19
+; GFX1250-NEXT: v_dual_mov_b32 v11, s53 :: v_dual_mov_b32 v12, s58
+; GFX1250-NEXT: s_bfe_i64 s[86:87], s[86:87], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[80:81], s[80:81], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[78:79], s[78:79], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[74:75], s[74:75], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[70:71], s[70:71], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v15, s59 :: v_dual_mov_b32 v16, s62
+; GFX1250-NEXT: s_bfe_i64 s[76:77], s[76:77], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v13, s59 :: v_dual_mov_b32 v14, s60
; GFX1250-NEXT: s_wait_xcnt 0x1
-; GFX1250-NEXT: v_dual_mov_b32 v17, s63 :: v_dual_mov_b32 v18, s66
-; GFX1250-NEXT: s_lshr_b32 s94, s4, 16
-; GFX1250-NEXT: s_lshr_b32 s100, s4, 17
-; GFX1250-NEXT: s_bfe_i64 s[84:85], s[84:85], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[82:83], s[82:83], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v19, s67 :: v_dual_mov_b32 v20, s68
-; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v21, s69 :: v_dual_mov_b32 v22, s70
-; GFX1250-NEXT: s_lshr_b32 s98, s4, 14
-; GFX1250-NEXT: s_lshr_b32 s102, s4, 15
-; GFX1250-NEXT: s_lshr_b32 s96, s4, 13
-; GFX1250-NEXT: s_lshr_b32 s86, s4, 8
-; GFX1250-NEXT: s_lshr_b32 s64, s4, 7
-; GFX1250-NEXT: s_lshr_b32 s50, s4, 5
-; GFX1250-NEXT: s_lshr_b32 s38, s4, 3
-; GFX1250-NEXT: s_lshr_b32 s24, s4, 1
-; GFX1250-NEXT: s_bfe_i64 s[92:93], s[92:93], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v15, s61 :: v_dual_mov_b32 v18, s62
+; GFX1250-NEXT: s_bfe_i64 s[90:91], s[90:91], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[88:89], s[88:89], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v23, s71 :: v_dual_mov_b32 v24, s74
-; GFX1250-NEXT: v_mov_b32_e32 v25, s75
+; GFX1250-NEXT: v_dual_mov_b32 v19, s63 :: v_dual_mov_b32 v20, s68
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v21, s69 :: v_dual_mov_b32 v22, s76
+; GFX1250-NEXT: s_bfe_i64 s[96:97], s[96:97], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[94:95], s[94:95], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v23, s77 :: v_dual_mov_b32 v24, s78
+; GFX1250-NEXT: v_mov_b32_e32 v25, s79
; GFX1250-NEXT: s_clause 0x5
-; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:272
-; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:256
-; GFX1250-NEXT: global_store_b128 v8, v[10:13], s[0:1] offset:240
-; GFX1250-NEXT: global_store_b128 v8, v[14:17], s[0:1] offset:224
-; GFX1250-NEXT: global_store_b128 v8, v[18:21], s[0:1] offset:208
-; GFX1250-NEXT: global_store_b128 v8, v[22:25], s[0:1] offset:192
+; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:272
+; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:256
+; GFX1250-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:240
+; GFX1250-NEXT: global_store_b128 v16, v[12:15], s[0:1] offset:224
+; GFX1250-NEXT: global_store_b128 v16, v[18:21], s[0:1] offset:208
+; GFX1250-NEXT: global_store_b128 v16, v[22:25], s[0:1] offset:192
; GFX1250-NEXT: s_wait_xcnt 0x5
-; GFX1250-NEXT: v_dual_mov_b32 v0, s78 :: v_dual_mov_b32 v1, s79
-; GFX1250-NEXT: v_dual_mov_b32 v2, s80 :: v_dual_mov_b32 v3, s81
+; GFX1250-NEXT: v_dual_mov_b32 v0, s80 :: v_dual_mov_b32 v1, s81
+; GFX1250-NEXT: v_dual_mov_b32 v2, s86 :: v_dual_mov_b32 v3, s87
; GFX1250-NEXT: s_wait_xcnt 0x4
-; GFX1250-NEXT: v_mov_b32_e32 v4, s82
-; GFX1250-NEXT: s_lshr_b32 s90, s4, 12
-; GFX1250-NEXT: s_lshr_b32 s76, s4, 10
-; GFX1250-NEXT: s_lshr_b32 s72, s4, 11
+; GFX1250-NEXT: v_mov_b32_e32 v4, s88
+; GFX1250-NEXT: ; implicit-def: $sgpr93
; GFX1250-NEXT: s_bfe_i64 s[100:101], s[100:101], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[94:95], s[94:95], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s83 :: v_dual_mov_b32 v6, s84
-; GFX1250-NEXT: s_wait_xcnt 0x3
-; GFX1250-NEXT: v_dual_mov_b32 v7, s85 :: v_dual_mov_b32 v10, s88
-; GFX1250-NEXT: s_lshr_b32 s60, s4, 9
-; GFX1250-NEXT: s_lshr_b32 s54, s4, 6
-; GFX1250-NEXT: s_lshr_b32 s42, s4, 4
-; GFX1250-NEXT: s_lshr_b32 s28, s4, 2
-; GFX1250-NEXT: s_bfe_i64 s[16:17], s[4:5], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[4:5], s[24:25], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[24:25], s[38:39], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[38:39], s[50:51], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[50:51], s[64:65], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[64:65], s[86:87], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[86:87], s[96:97], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[96:97], s[102:103], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[98:99], s[98:99], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v11, s89 :: v_dual_mov_b32 v12, s92
+; GFX1250-NEXT: v_dual_mov_b32 v5, s89 :: v_dual_mov_b32 v6, s90
+; GFX1250-NEXT: s_wait_xcnt 0x3
+; GFX1250-NEXT: v_dual_mov_b32 v7, s91 :: v_dual_mov_b32 v8, s94
+; GFX1250-NEXT: ; implicit-def: $sgpr75
+; GFX1250-NEXT: s_bfe_i64 s[56:57], s[92:93], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[84:85], vcc, 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[92:93], s[102:103], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v9, s95 :: v_dual_mov_b32 v10, s96
; GFX1250-NEXT: s_wait_xcnt 0x2
-; GFX1250-NEXT: v_dual_mov_b32 v13, s93 :: v_dual_mov_b32 v14, s94
-; GFX1250-NEXT: s_bfe_i64 s[72:73], s[72:73], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[76:77], s[76:77], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[90:91], s[90:91], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v15, s95 :: v_dual_mov_b32 v16, s100
+; GFX1250-NEXT: v_dual_mov_b32 v11, s97 :: v_dual_mov_b32 v12, s98
+; GFX1250-NEXT: ; implicit-def: $sgpr67
+; GFX1250-NEXT: ; implicit-def: $sgpr65
+; GFX1250-NEXT: s_bfe_i64 s[74:75], s[74:75], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v13, s99 :: v_dual_mov_b32 v14, s100
; GFX1250-NEXT: s_wait_xcnt 0x1
-; GFX1250-NEXT: v_dual_mov_b32 v17, s101 :: v_dual_mov_b32 v18, s98
-; GFX1250-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v19, s99 :: v_dual_mov_b32 v20, s96
+; GFX1250-NEXT: v_dual_mov_b32 v15, s101 :: v_dual_mov_b32 v18, s92
+; GFX1250-NEXT: s_bfe_i64 s[64:65], s[64:65], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v19, s93 :: v_dual_mov_b32 v20, s84
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v21, s97 :: v_dual_mov_b32 v22, s90
-; GFX1250-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v23, s91 :: v_dual_mov_b32 v24, s86
-; GFX1250-NEXT: v_mov_b32_e32 v25, s87
+; GFX1250-NEXT: v_dual_mov_b32 v21, s85 :: v_dual_mov_b32 v22, s82
+; GFX1250-NEXT: ; implicit-def: $sgpr51
+; GFX1250-NEXT: ; implicit-def: $sgpr49
+; GFX1250-NEXT: v_dual_mov_b32 v23, s83 :: v_dual_mov_b32 v24, s74
+; GFX1250-NEXT: v_mov_b32_e32 v25, s75
; GFX1250-NEXT: s_clause 0x5
-; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:176
-; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:160
-; GFX1250-NEXT: global_store_b128 v8, v[10:13], s[0:1] offset:144
-; GFX1250-NEXT: global_store_b128 v8, v[14:17], s[0:1] offset:128
-; GFX1250-NEXT: global_store_b128 v8, v[18:21], s[0:1] offset:112
-; GFX1250-NEXT: global_store_b128 v8, v[22:25], s[0:1] offset:96
+; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:176
+; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:160
+; GFX1250-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:144
+; GFX1250-NEXT: global_store_b128 v16, v[12:15], s[0:1] offset:128
+; GFX1250-NEXT: global_store_b128 v16, v[18:21], s[0:1] offset:112
+; GFX1250-NEXT: global_store_b128 v16, v[22:25], s[0:1] offset:96
; GFX1250-NEXT: s_wait_xcnt 0x5
-; GFX1250-NEXT: v_dual_mov_b32 v0, s76 :: v_dual_mov_b32 v1, s77
-; GFX1250-NEXT: v_dual_mov_b32 v2, s72 :: v_dual_mov_b32 v3, s73
+; GFX1250-NEXT: v_dual_mov_b32 v0, s72 :: v_dual_mov_b32 v1, s73
+; GFX1250-NEXT: v_dual_mov_b32 v2, s70 :: v_dual_mov_b32 v3, s71
; GFX1250-NEXT: s_wait_xcnt 0x4
-; GFX1250-NEXT: v_mov_b32_e32 v4, s64
-; GFX1250-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s65 :: v_dual_mov_b32 v6, s60
+; GFX1250-NEXT: v_mov_b32_e32 v4, s66
+; GFX1250-NEXT: ; implicit-def: $sgpr41
+; GFX1250-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v5, s67 :: v_dual_mov_b32 v6, s64
; GFX1250-NEXT: s_wait_xcnt 0x3
-; GFX1250-NEXT: v_dual_mov_b32 v7, s61 :: v_dual_mov_b32 v10, s54
-; GFX1250-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v11, s55 :: v_dual_mov_b32 v12, s50
+; GFX1250-NEXT: v_dual_mov_b32 v7, s65 :: v_dual_mov_b32 v8, s56
+; GFX1250-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v9, s57 :: v_dual_mov_b32 v10, s54
; GFX1250-NEXT: s_wait_xcnt 0x2
-; GFX1250-NEXT: v_dual_mov_b32 v13, s51 :: v_dual_mov_b32 v14, s42
-; GFX1250-NEXT: v_dual_mov_b32 v15, s43 :: v_dual_mov_b32 v16, s38
+; GFX1250-NEXT: v_dual_mov_b32 v11, s55 :: v_dual_mov_b32 v12, s50
+; GFX1250-NEXT: v_dual_mov_b32 v13, s51 :: v_dual_mov_b32 v14, s48
; GFX1250-NEXT: s_wait_xcnt 0x1
-; GFX1250-NEXT: v_dual_mov_b32 v17, s39 :: v_dual_mov_b32 v18, s28
-; GFX1250-NEXT: v_dual_mov_b32 v19, s29 :: v_dual_mov_b32 v20, s24
+; GFX1250-NEXT: v_dual_mov_b32 v15, s49 :: v_dual_mov_b32 v18, s40
+; GFX1250-NEXT: v_dual_mov_b32 v19, s41 :: v_dual_mov_b32 v20, s38
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v21, s25 :: v_dual_mov_b32 v22, s16
-; GFX1250-NEXT: v_dual_mov_b32 v23, s17 :: v_dual_mov_b32 v24, s4
-; GFX1250-NEXT: v_mov_b32_e32 v25, s5
+; GFX1250-NEXT: v_dual_mov_b32 v21, s39 :: v_dual_mov_b32 v22, s36
+; GFX1250-NEXT: v_dual_mov_b32 v23, s37 :: v_dual_mov_b32 v24, s2
+; GFX1250-NEXT: v_mov_b32_e32 v25, s3
; GFX1250-NEXT: s_clause 0x5
-; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:80
-; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:64
-; GFX1250-NEXT: global_store_b128 v8, v[10:13], s[0:1] offset:48
-; GFX1250-NEXT: global_store_b128 v8, v[14:17], s[0:1] offset:32
-; GFX1250-NEXT: global_store_b128 v8, v[18:21], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v8, v[22:25], s[0:1]
+; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:80
+; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:64
+; GFX1250-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:48
+; GFX1250-NEXT: global_store_b128 v16, v[12:15], s[0:1] offset:32
+; GFX1250-NEXT: global_store_b128 v16, v[18:21], s[0:1] offset:16
+; GFX1250-NEXT: global_store_b128 v16, v[22:25], s[0:1]
; GFX1250-NEXT: s_endpgm
%load = load <64 x i1>, ptr addrspace(4) %in
%ext = sext <64 x i1> %load to <64 x i64>
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index 0021af9381335..e7db0492c7e67 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -769,6 +769,8 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v8, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_clause 0x7
; GFX12-TRUE16-NEXT: global_load_d16_b16 v3, v8, s[0:1] offset:12
@@ -5433,6 +5435,7 @@ define amdgpu_kernel void @constant_zextload_i16_to_i64(ptr addrspace(1) %out, p
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5535,6 +5538,7 @@ define amdgpu_kernel void @constant_sextload_i16_to_i64(ptr addrspace(1) %out, p
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5634,6 +5638,7 @@ define amdgpu_kernel void @constant_zextload_v1i16_to_v1i64(ptr addrspace(1) %ou
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5731,6 +5736,7 @@ define amdgpu_kernel void @constant_sextload_v1i16_to_v1i64(ptr addrspace(1) %ou
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5860,6 +5866,8 @@ define amdgpu_kernel void @constant_sextload_v2i16_to_v2i64(ptr addrspace(1) %ou
; GCN-NOHSA-SI-LABEL: constant_sextload_v2i16_to_v2i64:
; GCN-NOHSA-SI: ; %bb.0:
; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr5
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr7
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-SI-NEXT: s_load_dword s4, s[2:3], 0x0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s3, 0xf000
@@ -5879,20 +5887,22 @@ define amdgpu_kernel void @constant_sextload_v2i16_to_v2i64(ptr addrspace(1) %ou
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
+; GCN-HSA-NEXT: ; implicit-def: $sgpr5
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GCN-HSA-NEXT: ; implicit-def: $sgpr3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_lshr_b32 s0, s2, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GCN-HSA-NEXT: s_lshr_b32 s4, s2, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
;
@@ -5901,6 +5911,7 @@ define amdgpu_kernel void @constant_sextload_v2i16_to_v2i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dword s2, s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
@@ -5940,6 +5951,7 @@ define amdgpu_kernel void @constant_sextload_v2i16_to_v2i64(ptr addrspace(1) %ou
; GFX12-LABEL: constant_sextload_v2i16_to_v2i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: ; implicit-def: $sgpr5
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
@@ -6097,6 +6109,7 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-NOHSA-SI: ; %bb.0:
; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, 0
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr11
; GCN-NOHSA-SI-NEXT: s_mov_b32 s7, 0xf000
; GCN-NOHSA-SI-NEXT: s_mov_b32 s6, -1
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
@@ -6105,22 +6118,22 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-NOHSA-SI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s3
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s0, s2, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[2:3], 0x100000
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s10, s2, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x100000
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s12, s3, 31
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s13, s3, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[8:9], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s2
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s3
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s13
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s12
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s11
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s1
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s10
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s11
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
@@ -6130,15 +6143,16 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
; GCN-HSA-NEXT: s_mov_b32 s5, 0
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr7
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_mov_b32 s4, s3
; GCN-HSA-NEXT: s_lshr_b32 s6, s2, 16
-; GCN-HSA-NEXT: s_ashr_i32 s7, s3, 31
; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[2:3], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s10, s3, 16
+; GCN-HSA-NEXT: s_ashr_i32 s10, s3, 31
+; GCN-HSA-NEXT: s_ashr_i32 s11, s3, 16
; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
@@ -6146,8 +6160,8 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s10
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
@@ -6162,28 +6176,31 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-LABEL: constant_sextload_v4i16_to_v4i64:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr5
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr7
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr9
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s2, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s2, 16
; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, s3
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s3, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
-; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s9
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x100000
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
@@ -6223,20 +6240,23 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GFX12-LABEL: constant_sextload_v4i16_to_v4i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: ; implicit-def: $sgpr5
+; GFX12-NEXT: ; implicit-def: $sgpr7
+; GFX12-NEXT: ; implicit-def: $sgpr9
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_lshr_b32 s4, s2, 16
; GFX12-NEXT: s_mov_b32 s6, s3
; GFX12-NEXT: s_lshr_b32 s8, s3, 16
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x100000
-; GFX12-NEXT: s_lshr_b32 s2, s2, 16
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s5
-; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v5, s7
-; GFX12-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s9
-; GFX12-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v3, s3
+; GFX12-NEXT: s_bfe_i64 s[10:11], s[2:3], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[6:7], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x100000
+; GFX12-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s11
+; GFX12-NEXT: v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v5, s5
+; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
+; GFX12-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v3, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
@@ -6460,6 +6480,10 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-NOHSA-SI-LABEL: constant_sextload_v8i16_to_v8i64:
; GCN-NOHSA-SI: ; %bb.0:
; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr15
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s3, 0xf000
@@ -6467,27 +6491,27 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s7
; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s5
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s9, s5, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s11, s5, 16
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s12, s6, 16
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s14, s4, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[4:5], 0x100000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[6:7], 0x100000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s5, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s21, s5, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[10:11], 0x100000
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s10, s7, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s7, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s11, s7, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x100000
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s20
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s11
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s10
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s11
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s9
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s21
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s20
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
@@ -6508,21 +6532,25 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
-; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr9
+; GCN-HSA-NEXT: ; implicit-def: $sgpr11
+; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-HSA-NEXT: ; implicit-def: $sgpr13
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GCN-HSA-NEXT: ; implicit-def: $sgpr3
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_mov_b32 s2, s7
; GCN-HSA-NEXT: s_mov_b32 s8, s5
-; GCN-HSA-NEXT: s_lshr_b32 s10, s6, 16
-; GCN-HSA-NEXT: s_lshr_b32 s12, s4, 16
-; GCN-HSA-NEXT: s_ashr_i32 s13, s5, 16
+; GCN-HSA-NEXT: s_lshr_b32 s12, s6, 16
+; GCN-HSA-NEXT: s_lshr_b32 s10, s4, 16
; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[4:5], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[6:7], 0x100000
; GCN-HSA-NEXT: s_ashr_i32 s6, s5, 31
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s18, s5, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[10:11], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[12:13], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
; GCN-HSA-NEXT: s_ashr_i32 s12, s7, 31
; GCN-HSA-NEXT: s_ashr_i32 s7, s7, 16
@@ -6543,7 +6571,7 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s18
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s6
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -6566,22 +6594,28 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-LABEL: constant_sextload_v8i16_to_v8i64:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr17
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr3
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s6, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, s7
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s4, 16
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s5
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s5, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s6, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s16, s7
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s7, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr7
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 48
@@ -6591,30 +6625,31 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
-; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 32
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s13
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s15
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
-; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 16
+; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s0, 32
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s0, 16
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s15
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
@@ -6668,32 +6703,38 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GFX12-LABEL: constant_sextload_v8i16_to_v8i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: ; implicit-def: $sgpr9
+; GFX12-NEXT: ; implicit-def: $sgpr11
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: ; implicit-def: $sgpr15
+; GFX12-NEXT: ; implicit-def: $sgpr17
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
+; GFX12-NEXT: ; implicit-def: $sgpr3
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_mov_b32 s14, s7
-; GFX12-NEXT: s_lshr_b32 s16, s7, 16
-; GFX12-NEXT: s_bfe_i64 s[12:13], s[6:7], 0x100000
-; GFX12-NEXT: s_lshr_b32 s6, s6, 16
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
; GFX12-NEXT: s_mov_b32 s8, s5
; GFX12-NEXT: s_lshr_b32 s10, s5, 16
-; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
-; GFX12-NEXT: s_lshr_b32 s4, s4, 16
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s13
-; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v9, s15
-; GFX12-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v11, s17
-; GFX12-NEXT: v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v3, s7
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v5, s3
-; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v13, s9
-; GFX12-NEXT: v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v15, s11
-; GFX12-NEXT: v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v7, s5
-; GFX12-NEXT: v_mov_b32_e32 v6, s4
+; GFX12-NEXT: s_lshr_b32 s12, s6, 16
+; GFX12-NEXT: s_mov_b32 s14, s7
+; GFX12-NEXT: s_lshr_b32 s16, s7, 16
+; GFX12-NEXT: s_bfe_i64 s[18:19], s[4:5], 0x100000
+; GFX12-NEXT: s_lshr_b32 s2, s4, 16
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[6:7], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[8:9], s[10:11], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[10:11], s[12:13], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[12:13], s[14:15], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[14:15], s[16:17], 0x100000
+; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s5
+; GFX12-NEXT: v_dual_mov_b32 v4, s18 :: v_dual_mov_b32 v9, s13
+; GFX12-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
+; GFX12-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v3, s11
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v5, s19
+; GFX12-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v13, s7
+; GFX12-NEXT: v_dual_mov_b32 v12, s6 :: v_dual_mov_b32 v15, s9
+; GFX12-NEXT: v_dual_mov_b32 v14, s8 :: v_dual_mov_b32 v7, s3
+; GFX12-NEXT: v_mov_b32_e32 v6, s2
; GFX12-NEXT: s_clause 0x3
; GFX12-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:48
; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:32
@@ -7069,6 +7110,14 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-NOHSA-SI-LABEL: constant_sextload_v16i16_to_v16i64:
; GCN-NOHSA-SI: ; %bb.0:
; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr15
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr17
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr19
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr21
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr23
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr25
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr27
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-SI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, 0xf000
@@ -7078,9 +7127,6 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: s_mov_b32 s14, s5
; GCN-NOHSA-SI-NEXT: s_mov_b32 s16, s3
; GCN-NOHSA-SI-NEXT: s_mov_b32 s18, s1
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s13, s1, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s15, s1, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s17, s3, 31
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s20, s6, 16
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s22, s4, 16
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s24, s2, 16
@@ -7089,38 +7135,41 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[30:31], s[2:3], 0x100000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x100000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[6:7], 0x100000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s1, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s38, s1, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[0:1], s[18:19], 0x100000
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s18, s3, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s18, s3, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s19, s3, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[16:17], 0x100000
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s16, s5, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s19, s5, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s17, s5, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[14:15], 0x100000
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s14, s7, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s7, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s15, s7, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[12:13], 0x100000
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s33
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s15
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s14
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:112
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s19
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s17
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s16
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:80
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s2
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s3
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s18
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s17
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s19
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s18
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s0
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s15
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s13
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s38
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s33
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
@@ -7155,91 +7204,99 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
-; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr15
+; GCN-HSA-NEXT: ; implicit-def: $sgpr17
+; GCN-HSA-NEXT: ; implicit-def: $sgpr19
+; GCN-HSA-NEXT: ; implicit-def: $sgpr21
+; GCN-HSA-NEXT: ; implicit-def: $sgpr23
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr29
+; GCN-HSA-NEXT: ; implicit-def: $sgpr27
+; GCN-HSA-NEXT: ; implicit-def: $sgpr25
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-HSA-NEXT: s_mov_b32 s12, s7
-; GCN-HSA-NEXT: s_ashr_i32 s25, s1, 31
-; GCN-HSA-NEXT: s_ashr_i32 s27, s1, 16
-; GCN-HSA-NEXT: s_ashr_i32 s30, s3, 31
-; GCN-HSA-NEXT: s_ashr_i32 s31, s3, 16
-; GCN-HSA-NEXT: s_mov_b32 s14, s5
-; GCN-HSA-NEXT: s_mov_b32 s16, s3
-; GCN-HSA-NEXT: s_mov_b32 s18, s1
-; GCN-HSA-NEXT: s_lshr_b32 s20, s6, 16
-; GCN-HSA-NEXT: s_lshr_b32 s22, s4, 16
-; GCN-HSA-NEXT: s_lshr_b32 s24, s2, 16
-; GCN-HSA-NEXT: s_lshr_b32 s26, s0, 16
+; GCN-HSA-NEXT: s_mov_b32 s14, s7
+; GCN-HSA-NEXT: s_ashr_i32 s33, s3, 31
+; GCN-HSA-NEXT: s_ashr_i32 s34, s3, 16
+; GCN-HSA-NEXT: s_mov_b32 s16, s5
+; GCN-HSA-NEXT: s_mov_b32 s18, s3
+; GCN-HSA-NEXT: s_mov_b32 s20, s1
+; GCN-HSA-NEXT: s_lshr_b32 s22, s6, 16
+; GCN-HSA-NEXT: s_lshr_b32 s24, s4, 16
+; GCN-HSA-NEXT: s_lshr_b32 s26, s2, 16
+; GCN-HSA-NEXT: s_lshr_b32 s28, s0, 16
; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[2:3], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s33, s5, 31
-; GCN-HSA-NEXT: s_ashr_i32 s34, s5, 16
-; GCN-HSA-NEXT: s_ashr_i32 s35, s7, 31
-; GCN-HSA-NEXT: s_ashr_i32 s36, s7, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[14:15], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s30, s1, 31
+; GCN-HSA-NEXT: s_ashr_i32 s31, s1, 16
+; GCN-HSA-NEXT: s_ashr_i32 s35, s5, 31
+; GCN-HSA-NEXT: s_ashr_i32 s36, s5, 16
+; GCN-HSA-NEXT: s_ashr_i32 s37, s7, 31
+; GCN-HSA-NEXT: s_ashr_i32 s38, s7, 16
; GCN-HSA-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[4:5], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[4:5], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[26:27], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[24:25], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[22:23], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[28:29], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[26:27], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[24:25], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
-; GCN-HSA-NEXT: s_add_u32 s22, s8, 0x70
-; GCN-HSA-NEXT: s_addc_u32 s23, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
-; GCN-HSA-NEXT: s_add_u32 s14, s8, 0x50
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
-; GCN-HSA-NEXT: s_addc_u32 s15, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s14
-; GCN-HSA-NEXT: s_add_u32 s14, s8, 48
-; GCN-HSA-NEXT: s_addc_u32 s15, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s23
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
-; GCN-HSA-NEXT: s_add_u32 s14, s8, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s34
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s33
+; GCN-HSA-NEXT: s_add_u32 s24, s8, 0x70
+; GCN-HSA-NEXT: s_addc_u32 s25, s9, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GCN-HSA-NEXT: s_add_u32 s16, s8, 0x50
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GCN-HSA-NEXT: s_addc_u32 s17, s9, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s17
+; GCN-HSA-NEXT: s_add_u32 s16, s8, 48
+; GCN-HSA-NEXT: s_addc_u32 s17, s9, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s25
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s37
+; GCN-HSA-NEXT: s_add_u32 s16, s8, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s35
; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
-; GCN-HSA-NEXT: s_addc_u32 s15, s9, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s31
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s30
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s27
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s15
+; GCN-HSA-NEXT: s_addc_u32 s17, s9, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s33
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s17
; GCN-HSA-NEXT: flat_store_dwordx4 v[15:16], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[17:18], v[8:11]
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s25
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s30
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
; GCN-HSA-NEXT: s_add_u32 s6, s8, 0x60
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
; GCN-HSA-NEXT: s_addc_u32 s7, s9, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s23
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: s_add_u32 s6, s8, 64
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s7, s9, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -7264,36 +7321,48 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-NOHSA-VI-LABEL: constant_sextload_v16i16_to_v16i64:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr19
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr21
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr15
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr25
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr27
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr31
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr35
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s12, s1
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s0, 16
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s1, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s20, s2, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x100000
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s14, s1
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[2:3], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s2, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s6, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[12:13], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[0:1], s[12:13], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[18:19], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[2:3], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, s3
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, s7
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s5
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s0, s0, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[20:21], 0x100000
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s20, s3
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr21
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s3, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr3
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s6, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s26, s7
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s7, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr7
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s4, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s34, s5
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s5, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr5
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 0x50
@@ -7447,65 +7516,77 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
;
; GFX12-LABEL: constant_sextload_v16i16_to_v16i64:
; GFX12: ; %bb.0:
-; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: ; implicit-def: $sgpr15
+; GFX12-NEXT: ; implicit-def: $sgpr17
+; GFX12-NEXT: ; implicit-def: $sgpr19
+; GFX12-NEXT: ; implicit-def: $sgpr21
+; GFX12-NEXT: ; implicit-def: $sgpr23
+; GFX12-NEXT: ; implicit-def: $sgpr25
+; GFX12-NEXT: ; implicit-def: $sgpr27
+; GFX12-NEXT: ; implicit-def: $sgpr29
+; GFX12-NEXT: ; implicit-def: $sgpr31
+; GFX12-NEXT: ; implicit-def: $sgpr35
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_load_b256 s[4:11], s[2:3], 0x0
+; GFX12-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
+; GFX12-NEXT: ; implicit-def: $sgpr11
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_mov_b32 s30, s9
-; GFX12-NEXT: s_lshr_b32 s34, s9, 16
-; GFX12-NEXT: s_bfe_i64 s[28:29], s[8:9], 0x100000
-; GFX12-NEXT: s_lshr_b32 s8, s8, 16
-; GFX12-NEXT: s_bfe_i64 s[22:23], s[10:11], 0x100000
-; GFX12-NEXT: s_mov_b32 s24, s11
-; GFX12-NEXT: s_lshr_b32 s26, s11, 16
-; GFX12-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x100000
-; GFX12-NEXT: s_lshr_b32 s10, s10, 16
-; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s29
-; GFX12-NEXT: s_mov_b32 s18, s7
-; GFX12-NEXT: s_lshr_b32 s20, s7, 16
-; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v9, s31
-; GFX12-NEXT: v_dual_mov_b32 v8, s30 :: v_dual_mov_b32 v11, s35
-; GFX12-NEXT: v_dual_mov_b32 v10, s34 :: v_dual_mov_b32 v3, s9
-; GFX12-NEXT: s_bfe_i64 s[16:17], s[6:7], 0x100000
-; GFX12-NEXT: s_lshr_b32 s6, s6, 16
-; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v5, s23
-; GFX12-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v13, s25
-; GFX12-NEXT: s_mov_b32 s12, s5
-; GFX12-NEXT: s_lshr_b32 s14, s5, 16
-; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v15, s27
-; GFX12-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v7, s11
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
-; GFX12-NEXT: s_lshr_b32 s4, s4, 16
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v17, s19
-; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v19, s21
-; GFX12-NEXT: v_mov_b32_e32 v18, s20
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
+; GFX12-NEXT: s_lshr_b32 s10, s0, 16
+; GFX12-NEXT: s_mov_b32 s12, s1
+; GFX12-NEXT: s_lshr_b32 s14, s1, 16
+; GFX12-NEXT: s_lshr_b32 s16, s2, 16
+; GFX12-NEXT: s_mov_b32 s18, s3
+; GFX12-NEXT: s_lshr_b32 s20, s3, 16
+; GFX12-NEXT: s_lshr_b32 s22, s6, 16
+; GFX12-NEXT: s_mov_b32 s24, s7
+; GFX12-NEXT: s_lshr_b32 s26, s7, 16
+; GFX12-NEXT: s_lshr_b32 s28, s4, 16
+; GFX12-NEXT: s_mov_b32 s30, s5
+; GFX12-NEXT: s_lshr_b32 s34, s5, 16
+; GFX12-NEXT: s_bfe_i64 s[36:37], s[0:1], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[10:11], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[10:11], s[12:13], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[12:13], s[14:15], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[14:15], s[16:17], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[16:17], s[18:19], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[18:19], s[20:21], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[20:21], s[22:23], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[22:23], s[24:25], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[24:25], s[26:27], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[26:27], s[28:29], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[28:29], s[30:31], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[30:31], s[34:35], 0x100000
+; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s7
+; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v9, s29
+; GFX12-NEXT: v_dual_mov_b32 v8, s28 :: v_dual_mov_b32 v11, s31
+; GFX12-NEXT: v_dual_mov_b32 v10, s30 :: v_dual_mov_b32 v3, s27
+; GFX12-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v5, s3
+; GFX12-NEXT: v_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v13, s23
+; GFX12-NEXT: v_dual_mov_b32 v12, s22 :: v_dual_mov_b32 v15, s25
+; GFX12-NEXT: v_dual_mov_b32 v14, s24 :: v_dual_mov_b32 v7, s21
+; GFX12-NEXT: v_dual_mov_b32 v6, s20 :: v_dual_mov_b32 v17, s17
+; GFX12-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v19, s19
+; GFX12-NEXT: v_mov_b32_e32 v18, s18
; GFX12-NEXT: s_clause 0x1
-; GFX12-NEXT: global_store_b128 v24, v[8:11], s[0:1] offset:80
-; GFX12-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:64
-; GFX12-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v3, s7
-; GFX12-NEXT: v_dual_mov_b32 v1, s17 :: v_dual_mov_b32 v2, s6
-; GFX12-NEXT: v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v8, s12
-; GFX12-NEXT: v_dual_mov_b32 v11, s15 :: v_dual_mov_b32 v10, s14
-; GFX12-NEXT: v_dual_mov_b32 v21, s3 :: v_dual_mov_b32 v20, s2
+; GFX12-NEXT: global_store_b128 v24, v[8:11], s[8:9] offset:80
+; GFX12-NEXT: global_store_b128 v24, v[0:3], s[8:9] offset:64
+; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s15
+; GFX12-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s14
+; GFX12-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v8, s10
+; GFX12-NEXT: v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v10, s12
+; GFX12-NEXT: v_dual_mov_b32 v21, s37 :: v_dual_mov_b32 v20, s36
; GFX12-NEXT: v_dual_mov_b32 v23, s5 :: v_dual_mov_b32 v22, s4
; GFX12-NEXT: s_clause 0x5
-; GFX12-NEXT: global_store_b128 v24, v[12:15], s[0:1] offset:112
-; GFX12-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:96
-; GFX12-NEXT: global_store_b128 v24, v[16:19], s[0:1] offset:48
-; GFX12-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:32
-; GFX12-NEXT: global_store_b128 v24, v[8:11], s[0:1] offset:16
-; GFX12-NEXT: global_store_b128 v24, v[20:23], s[0:1]
+; GFX12-NEXT: global_store_b128 v24, v[12:15], s[8:9] offset:112
+; GFX12-NEXT: global_store_b128 v24, v[4:7], s[8:9] offset:96
+; GFX12-NEXT: global_store_b128 v24, v[16:19], s[8:9] offset:48
+; GFX12-NEXT: global_store_b128 v24, v[0:3], s[8:9] offset:32
+; GFX12-NEXT: global_store_b128 v24, v[8:11], s[8:9] offset:16
+; GFX12-NEXT: global_store_b128 v24, v[20:23], s[8:9]
; GFX12-NEXT: s_endpgm
%load = load <16 x i16>, ptr addrspace(4) %in
%ext = sext <16 x i16> %load to <16 x i64>
@@ -8188,61 +8269,74 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-LABEL: constant_sextload_v32i16_to_v32i64:
; GCN-NOHSA-SI: ; %bb.0:
; GCN-NOHSA-SI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x9
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr45
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr47
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr49
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr51
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr53
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-SI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s42, s15
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s43, s11, 31
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s44, s15
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s25, s3, 31
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s27, s3, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s45, s11, 16
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s44, s13
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s54, s3
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s46, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s42, s3
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s36, s2, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[2:3], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[42:43], 0x100000
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s47, s13, 31
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s46, s11
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[44:45], 0x100000
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s48, s11
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s2
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s3
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[44:45], 0x100000
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s49, s13, 16
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s48, s9
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[46:47], 0x100000
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s50, s9
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s2
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s3
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[46:47], 0x100000
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s51, s15, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s53, s15, 16
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s50, s7
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s52, s5
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[48:49], 0x100000
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s52, s7
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s2
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s3
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[48:49], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[50:51], 0x100000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s55, s11, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s56, s13, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s57, s13, 16
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s54, s5
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s2
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s3
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[52:53], 0x100000
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s1, 31
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s23, s1, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s43, s11, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s58, s15, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s59, s15, 16
; GCN-NOHSA-SI-NEXT: s_mov_b32 s40, s1
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s38, s0, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[0:1], 0x100000
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s16
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s17
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s2
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s3
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[2:3], s[50:51], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[52:53], 0x100000
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s29, s5, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s31, s5, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s22, s14, 16
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s2
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s3
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s53
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s51
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s49
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s47
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v20, s16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s57
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s56
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s55
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr55
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[54:55], 0x100000
; GCN-NOHSA-SI-NEXT: s_mov_b32 s3, 0xf000
; GCN-NOHSA-SI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s29, s5, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s31, s5, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s22, s14, 16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s59
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s58
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s43
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v20, s16
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v21, s17
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[54:55], 0x100000
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr43
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[42:43], 0x100000
+; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:208
+; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s23
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr23
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s24, s12, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v22, s31
@@ -8250,15 +8344,14 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s16
-; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:208
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s17
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s27
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s25
-; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s23
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr25
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x100000
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s26, s10, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr27
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:80
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
@@ -8269,6 +8362,7 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s23
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s28, s8, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr29
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:224
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
@@ -8276,10 +8370,12 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s13
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s24
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s25
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s35, s7, 31
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s39, s9, 31
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s41, s9, 16
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s30, s6, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr31
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:192
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
@@ -8287,10 +8383,11 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s11
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s26
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s27
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s35, s7, 31
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s37, s7, 16
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s34, s4, 16
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v19, s35
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr35
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
@@ -8299,7 +8396,8 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s28
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s29
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v19, s35
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v18, s37
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr37
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
@@ -8307,7 +8405,8 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s30
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s31
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v18, s37
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s41
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr41
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[40:41], 0x100000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
@@ -8316,8 +8415,10 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s5
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s34
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s35
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s39
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s16
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s17
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr39
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[38:39], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
@@ -8325,10 +8426,6 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s21
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s36
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s37
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s45
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s43
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s41
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s39
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s33
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
@@ -8349,210 +8446,225 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-HSA-NEXT: s_load_dwordx4 s[16:19], s[8:9], 0x0
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr31
+; GCN-HSA-NEXT: ; implicit-def: $sgpr47
+; GCN-HSA-NEXT: ; implicit-def: $sgpr49
+; GCN-HSA-NEXT: ; implicit-def: $sgpr51
+; GCN-HSA-NEXT: ; implicit-def: $sgpr53
+; GCN-HSA-NEXT: ; implicit-def: $sgpr55
+; GCN-HSA-NEXT: ; implicit-def: $sgpr39
+; GCN-HSA-NEXT: ; implicit-def: $sgpr37
+; GCN-HSA-NEXT: ; implicit-def: $sgpr35
+; GCN-HSA-NEXT: ; implicit-def: $sgpr69
+; GCN-HSA-NEXT: ; implicit-def: $sgpr67
+; GCN-HSA-NEXT: ; implicit-def: $sgpr65
+; GCN-HSA-NEXT: ; implicit-def: $sgpr63
+; GCN-HSA-NEXT: ; implicit-def: $sgpr61
+; GCN-HSA-NEXT: ; implicit-def: $sgpr59
+; GCN-HSA-NEXT: ; implicit-def: $sgpr57
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: s_mov_b32 s30, s15
-; GCN-HSA-NEXT: s_ashr_i32 s41, s3, 31
-; GCN-HSA-NEXT: s_ashr_i32 s55, s3, 16
-; GCN-HSA-NEXT: s_ashr_i32 s57, s5, 31
-; GCN-HSA-NEXT: s_ashr_i32 s59, s5, 16
-; GCN-HSA-NEXT: s_ashr_i32 s61, s7, 31
-; GCN-HSA-NEXT: s_ashr_i32 s63, s7, 16
-; GCN-HSA-NEXT: s_ashr_i32 s65, s9, 31
-; GCN-HSA-NEXT: s_ashr_i32 s67, s9, 16
-; GCN-HSA-NEXT: s_mov_b32 s42, s13
-; GCN-HSA-NEXT: s_mov_b32 s44, s11
-; GCN-HSA-NEXT: s_mov_b32 s46, s9
-; GCN-HSA-NEXT: s_mov_b32 s48, s7
-; GCN-HSA-NEXT: s_mov_b32 s50, s5
+; GCN-HSA-NEXT: s_ashr_i32 s43, s5, 31
+; GCN-HSA-NEXT: s_ashr_i32 s44, s5, 16
+; GCN-HSA-NEXT: s_mov_b32 s46, s13
+; GCN-HSA-NEXT: s_mov_b32 s48, s11
+; GCN-HSA-NEXT: s_mov_b32 s50, s9
+; GCN-HSA-NEXT: s_mov_b32 s52, s7
+; GCN-HSA-NEXT: s_mov_b32 s54, s5
; GCN-HSA-NEXT: s_mov_b32 s38, s3
; GCN-HSA-NEXT: s_mov_b32 s36, s1
-; GCN-HSA-NEXT: s_lshr_b32 s52, s14, 16
-; GCN-HSA-NEXT: s_lshr_b32 s54, s12, 16
-; GCN-HSA-NEXT: s_lshr_b32 s56, s10, 16
-; GCN-HSA-NEXT: s_lshr_b32 s58, s8, 16
-; GCN-HSA-NEXT: s_lshr_b32 s60, s6, 16
-; GCN-HSA-NEXT: s_lshr_b32 s62, s4, 16
-; GCN-HSA-NEXT: s_lshr_b32 s64, s2, 16
-; GCN-HSA-NEXT: s_lshr_b32 s66, s0, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[2:3], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[30:31], 0x100000
+; GCN-HSA-NEXT: s_lshr_b32 s34, s14, 16
+; GCN-HSA-NEXT: s_lshr_b32 s56, s12, 16
+; GCN-HSA-NEXT: s_lshr_b32 s58, s10, 16
+; GCN-HSA-NEXT: s_lshr_b32 s60, s8, 16
+; GCN-HSA-NEXT: s_lshr_b32 s62, s6, 16
+; GCN-HSA-NEXT: s_lshr_b32 s64, s4, 16
+; GCN-HSA-NEXT: s_lshr_b32 s66, s2, 16
+; GCN-HSA-NEXT: s_lshr_b32 s68, s0, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[4:5], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[30:31], 0x100000
; GCN-HSA-NEXT: s_ashr_i32 s33, s1, 31
; GCN-HSA-NEXT: s_ashr_i32 s40, s1, 16
-; GCN-HSA-NEXT: s_ashr_i32 s68, s11, 31
-; GCN-HSA-NEXT: s_ashr_i32 s69, s11, 16
-; GCN-HSA-NEXT: s_ashr_i32 s70, s13, 31
-; GCN-HSA-NEXT: s_ashr_i32 s71, s13, 16
-; GCN-HSA-NEXT: s_ashr_i32 s72, s15, 31
-; GCN-HSA-NEXT: s_ashr_i32 s73, s15, 16
+; GCN-HSA-NEXT: s_ashr_i32 s41, s3, 31
+; GCN-HSA-NEXT: s_ashr_i32 s42, s3, 16
+; GCN-HSA-NEXT: s_ashr_i32 s45, s7, 31
+; GCN-HSA-NEXT: s_ashr_i32 s70, s7, 16
+; GCN-HSA-NEXT: s_ashr_i32 s71, s9, 31
+; GCN-HSA-NEXT: s_ashr_i32 s72, s9, 16
+; GCN-HSA-NEXT: s_ashr_i32 s73, s11, 31
+; GCN-HSA-NEXT: s_ashr_i32 s74, s11, 16
+; GCN-HSA-NEXT: s_ashr_i32 s75, s13, 31
+; GCN-HSA-NEXT: s_ashr_i32 s76, s13, 16
+; GCN-HSA-NEXT: s_ashr_i32 s77, s15, 31
+; GCN-HSA-NEXT: s_ashr_i32 s78, s15, 16
; GCN-HSA-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[4:5], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[6:7], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[8:9], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[10:11], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[14:15], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[66:67], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[62:63], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[60:61], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[58:59], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[56:57], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[54:55], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[52:53], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[6:7], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[8:9], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[10:11], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[12:13], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[14:15], 0x100000
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[68:69], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[66:67], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[64:65], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[62:63], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[60:61], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[58:59], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[56:57], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x100000
-; GCN-HSA-NEXT: s_add_u32 s52, s16, 0xf0
-; GCN-HSA-NEXT: s_addc_u32 s53, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s42
-; GCN-HSA-NEXT: s_add_u32 s42, s16, 0xd0
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s43
-; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s43
-; GCN-HSA-NEXT: s_add_u32 s42, s16, 0xb0
-; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s43
-; GCN-HSA-NEXT: s_add_u32 s42, s16, 0x90
-; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s43
-; GCN-HSA-NEXT: s_add_u32 s42, s16, 0x70
-; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s52
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s43
-; GCN-HSA-NEXT: s_add_u32 s42, s16, 0x50
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s73
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s72
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s71
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s70
-; GCN-HSA-NEXT: s_addc_u32 s43, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s44
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s45
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[2:5]
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s69
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s68
-; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[6:9]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[10:13]
+; GCN-HSA-NEXT: s_add_u32 s56, s16, 0xf0
+; GCN-HSA-NEXT: s_addc_u32 s57, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s46
+; GCN-HSA-NEXT: s_add_u32 s46, s16, 0xd0
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s47
+; GCN-HSA-NEXT: s_addc_u32 s47, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s47
+; GCN-HSA-NEXT: s_add_u32 s46, s16, 0xb0
+; GCN-HSA-NEXT: s_addc_u32 s47, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s47
+; GCN-HSA-NEXT: s_add_u32 s46, s16, 0x90
+; GCN-HSA-NEXT: s_addc_u32 s47, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s47
+; GCN-HSA-NEXT: s_add_u32 s46, s16, 0x70
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s56
+; GCN-HSA-NEXT: s_addc_u32 s47, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s76
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s75
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s57
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s78
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s77
+; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s44
+; GCN-HSA-NEXT: s_add_u32 s44, s16, 0x50
+; GCN-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s45
+; GCN-HSA-NEXT: s_addc_u32 s45, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s48
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s49
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s74
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s73
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s36
; GCN-HSA-NEXT: s_add_u32 s36, s16, 48
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s37
; GCN-HSA-NEXT: s_addc_u32 s37, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s37
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s36
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s37
; GCN-HSA-NEXT: s_add_u32 s36, s16, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s47
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s67
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s65
; GCN-HSA-NEXT: s_addc_u32 s37, s17, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[14:17]
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s30
-; GCN-HSA-NEXT: s_add_u32 s30, s16, 0xe0
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s49
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s63
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s61
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s31
-; GCN-HSA-NEXT: s_addc_u32 s31, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s42
-; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s50
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
-; GCN-HSA-NEXT: s_add_u32 s14, s16, 0xc0
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s51
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s59
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s57
-; GCN-HSA-NEXT: v_mov_b32_e32 v29, s43
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
-; GCN-HSA-NEXT: s_addc_u32 s15, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s39
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s55
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v28, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s28
+; GCN-HSA-NEXT: s_add_u32 s28, s16, 0xe0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s53
+; GCN-HSA-NEXT: v_mov_b32_e32 v29, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s70
+; GCN-HSA-NEXT: v_mov_b32_e32 v30, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s29
+; GCN-HSA-NEXT: s_addc_u32 s29, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s50
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s51
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s54
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s55
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s72
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s71
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v31, s45
+; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[4:7]
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s26
+; GCN-HSA-NEXT: s_add_u32 s26, s16, 0xc0
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s41
+; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s27
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s30
-; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[18:21]
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s28
+; GCN-HSA-NEXT: flat_store_dwordx4 v[30:31], v[20:23]
+; GCN-HSA-NEXT: s_addc_u32 s27, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s26
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s37
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s15
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s33
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s34
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s35
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s31
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s14
-; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s29
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s30
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s27
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GCN-HSA-NEXT: s_add_u32 s14, s16, 0xa0
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GCN-HSA-NEXT: s_addc_u32 s15, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s12
-; GCN-HSA-NEXT: s_add_u32 s12, s16, 0xa0
+; GCN-HSA-NEXT: s_add_u32 s12, s16, 0x80
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s13
; GCN-HSA-NEXT: s_addc_u32 s13, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s26
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s27
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s13
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s10
-; GCN-HSA-NEXT: s_add_u32 s10, s16, 0x80
+; GCN-HSA-NEXT: s_add_u32 s10, s16, 0x60
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s11
; GCN-HSA-NEXT: s_addc_u32 s11, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s24
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s21
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s11
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s8
-; GCN-HSA-NEXT: s_add_u32 s8, s16, 0x60
+; GCN-HSA-NEXT: s_add_u32 s8, s16, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s9
; GCN-HSA-NEXT: s_addc_u32 s9, s17, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s19
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s16, 32
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCN-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s6
-; GCN-HSA-NEXT: s_add_u32 s6, s16, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s7
-; GCN-HSA-NEXT: s_addc_u32 s7, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s21
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: s_nop 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s4
-; GCN-HSA-NEXT: s_add_u32 s4, s16, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s5
-; GCN-HSA-NEXT: s_addc_u32 s5, s17, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s17
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
@@ -8560,27 +8672,51 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-LABEL: constant_sextload_v32i16_to_v32i64:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x24
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr25
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr27
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr29
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr35
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr37
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr39
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr41
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr45
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr47
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr49
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr51
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr53
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr55
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr57
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr59
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr61
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr63
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr65
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr67
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr69
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr71
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr75
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr77
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr79
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s22, s0, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s0, 16
; GCN-NOHSA-VI-NEXT: s_mov_b32 s26, s1
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s1, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s2, 16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s34, s3
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s36, s3, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s2, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s36, s3
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s38, s3, 16
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s40, s4, 16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s42, s5
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s44, s5, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s46, s6, 16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s48, s7
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s50, s7, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s52, s8, 16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s54, s9
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s56, s9, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s58, s10, 16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s60, s11
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s62, s11, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s44, s5
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s46, s5, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s48, s6, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s50, s7
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s52, s7, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s54, s8, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s56, s9
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s58, s9, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s60, s10, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s62, s11
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s64, s11, 16
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s66, s12, 16
; GCN-NOHSA-VI-NEXT: s_mov_b32 s68, s13
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s70, s13, 16
@@ -8591,120 +8727,119 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[8:9], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[38:39], s[10:11], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[64:65], s[12:13], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[8:9], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[10:11], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[42:43], s[12:13], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[72:73], s[14:15], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[22:23], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[26:27], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[28:29], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[30:31], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[34:35], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[24:25], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[26:27], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[28:29], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[34:35], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[36:37], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[40:41], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[42:43], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[38:39], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[40:41], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[44:45], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[46:47], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[36:37], s[48:49], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[50:51], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[40:41], s[52:53], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[44:45], s[54:55], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[42:43], s[56:57], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[46:47], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[48:49], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[36:37], s[50:51], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[38:39], s[52:53], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[40:41], s[54:55], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[44:45], s[56:57], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[46:47], s[58:59], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[48:49], s[60:61], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[50:51], s[62:63], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[52:53], s[66:67], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[54:55], s[68:69], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[56:57], s[70:71], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[58:59], s[74:75], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[60:61], s[76:77], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[62:63], s[78:79], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s60
-; GCN-NOHSA-VI-NEXT: s_add_u32 s60, s16, 0xf0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s61
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[52:53], s[64:65], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[54:55], s[66:67], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[56:57], s[68:69], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[58:59], s[70:71], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[60:61], s[74:75], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[62:63], s[76:77], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[64:65], s[78:79], 0x100000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s62
+; GCN-NOHSA-VI-NEXT: s_add_u32 s62, s16, 0xf0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s63
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s63, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s62
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s64
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s65
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s63
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s60
+; GCN-NOHSA-VI-NEXT: s_add_u32 s60, s16, 0xe0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s61
; GCN-NOHSA-VI-NEXT: s_addc_u32 s61, s17, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s60
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s62
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s63
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s72
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s73
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s61
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s56
+; GCN-NOHSA-VI-NEXT: s_add_u32 s56, s16, 0xd0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s57
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s57, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s56
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s58
-; GCN-NOHSA-VI-NEXT: s_add_u32 s58, s16, 0xe0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s59
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s59, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s58
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s72
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s73
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s59
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s57
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s54
-; GCN-NOHSA-VI-NEXT: s_add_u32 s54, s16, 0xd0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s55
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s55, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s54
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s56
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s57
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s55
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s42
+; GCN-NOHSA-VI-NEXT: s_add_u32 s42, s16, 0xc0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s43
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s43, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s42
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s54
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s55
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s43
+; GCN-NOHSA-VI-NEXT: s_add_u32 s42, s16, 0xb0
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s43, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s42
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s50
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s51
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s52
-; GCN-NOHSA-VI-NEXT: s_add_u32 s52, s16, 0xc0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s53
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s53, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s52
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s64
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s65
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s53
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s43
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s48
-; GCN-NOHSA-VI-NEXT: s_add_u32 s48, s16, 0xb0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s49
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s49, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s48
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s50
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s51
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s49
-; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s38
-; GCN-NOHSA-VI-NEXT: s_add_u32 s38, s16, 0xa0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s39
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s39, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s38
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s46
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s47
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s39
-; GCN-NOHSA-VI-NEXT: s_add_u32 s38, s16, 0x90
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s30
+; GCN-NOHSA-VI-NEXT: s_add_u32 s30, s16, 0xa0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s31
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s31, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s30
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s48
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s49
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s31
+; GCN-NOHSA-VI-NEXT: s_add_u32 s30, s16, 0x90
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s39, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s38
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s31, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s30
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s44
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s45
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s42
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s43
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s39
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s46
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s47
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s31
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
-; GCN-NOHSA-VI-NEXT: s_add_u32 s24, s16, 0x80
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s25
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s25, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s24
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
+; GCN-NOHSA-VI-NEXT: s_add_u32 s22, s16, 0x80
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s23
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s23, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s40
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s41
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s25
-; GCN-NOHSA-VI-NEXT: s_add_u32 s24, s16, 0x70
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s23
+; GCN-NOHSA-VI-NEXT: s_add_u32 s22, s16, 0x70
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-NOHSA-VI-NEXT: s_addc_u32 s25, s17, 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s24
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s23, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s36
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s37
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s34
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s25
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s38
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s39
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s23
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
@@ -8712,17 +8847,17 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s21
; GCN-NOHSA-VI-NEXT: s_addc_u32 s21, s17, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s20
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s31
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s34
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s21
; GCN-NOHSA-VI-NEXT: s_add_u32 s20, s16, 0x50
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_addc_u32 s21, s17, 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s20
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s29
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s26
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s27
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s27
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s28
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s29
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s21
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
@@ -8733,15 +8868,15 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s16, 48
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s22
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s23
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s24
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s25
; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s17, 0
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s15
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s15
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
@@ -8757,10 +8892,10 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s16
@@ -8919,92 +9054,116 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GFX12-LABEL: constant_sextload_v32i16_to_v32i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[16:19], s[4:5], 0x24
+; GFX12-NEXT: ; implicit-def: $sgpr29
+; GFX12-NEXT: ; implicit-def: $sgpr35
+; GFX12-NEXT: ; implicit-def: $sgpr41
+; GFX12-NEXT: ; implicit-def: $sgpr51
+; GFX12-NEXT: ; implicit-def: $sgpr53
+; GFX12-NEXT: ; implicit-def: $sgpr55
+; GFX12-NEXT: ; implicit-def: $sgpr65
+; GFX12-NEXT: ; implicit-def: $sgpr63
+; GFX12-NEXT: ; implicit-def: $sgpr67
+; GFX12-NEXT: ; implicit-def: $sgpr25
+; GFX12-NEXT: ; implicit-def: $sgpr31
+; GFX12-NEXT: ; implicit-def: $sgpr39
+; GFX12-NEXT: ; implicit-def: $sgpr43
+; GFX12-NEXT: ; implicit-def: $sgpr49
+; GFX12-NEXT: ; implicit-def: $sgpr59
+; GFX12-NEXT: ; implicit-def: $sgpr57
+; GFX12-NEXT: ; implicit-def: $sgpr61
+; GFX12-NEXT: ; implicit-def: $sgpr45
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b512 s[0:15], s[18:19], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s28, s2, 16
-; GFX12-NEXT: s_lshr_b32 s42, s5, 16
-; GFX12-NEXT: s_lshr_b32 s50, s8, 16
-; GFX12-NEXT: s_mov_b32 s60, s11
-; GFX12-NEXT: s_lshr_b32 s22, s0, 16
-; GFX12-NEXT: s_mov_b32 s24, s1
-; GFX12-NEXT: s_lshr_b32 s26, s1, 16
-; GFX12-NEXT: s_mov_b32 s30, s3
-; GFX12-NEXT: s_lshr_b32 s36, s3, 16
-; GFX12-NEXT: s_lshr_b32 s38, s4, 16
-; GFX12-NEXT: s_mov_b32 s40, s5
-; GFX12-NEXT: s_lshr_b32 s44, s6, 16
-; GFX12-NEXT: s_mov_b32 s46, s7
-; GFX12-NEXT: s_lshr_b32 s48, s7, 16
-; GFX12-NEXT: s_mov_b32 s52, s9
-; GFX12-NEXT: s_lshr_b32 s54, s9, 16
-; GFX12-NEXT: s_bfe_i64 s[56:57], s[10:11], 0x100000
-; GFX12-NEXT: s_lshr_b32 s58, s10, 16
-; GFX12-NEXT: s_lshr_b32 s62, s11, 16
-; GFX12-NEXT: s_bfe_i64 s[10:11], s[28:29], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[28:29], s[42:43], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[42:43], s[50:51], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[50:51], s[60:61], 0x100000
-; GFX12-NEXT: s_lshr_b32 s60, s14, 16
+; GFX12-NEXT: s_mov_b32 s28, s1
+; GFX12-NEXT: s_lshr_b32 s34, s2, 16
+; GFX12-NEXT: s_lshr_b32 s40, s3, 16
+; GFX12-NEXT: s_lshr_b32 s50, s5, 16
+; GFX12-NEXT: s_lshr_b32 s52, s6, 16
+; GFX12-NEXT: s_mov_b32 s54, s7
+; GFX12-NEXT: s_lshr_b32 s62, s9, 16
+; GFX12-NEXT: s_lshr_b32 s64, s10, 16
+; GFX12-NEXT: s_mov_b32 s66, s11
+; GFX12-NEXT: s_lshr_b32 s24, s0, 16
+; GFX12-NEXT: s_lshr_b32 s30, s1, 16
+; GFX12-NEXT: s_mov_b32 s38, s3
+; GFX12-NEXT: s_bfe_i64 s[22:23], s[4:5], 0x100000
+; GFX12-NEXT: s_lshr_b32 s42, s4, 16
+; GFX12-NEXT: s_mov_b32 s48, s5
+; GFX12-NEXT: s_bfe_i64 s[26:27], s[6:7], 0x100000
+; GFX12-NEXT: s_lshr_b32 s56, s7, 16
+; GFX12-NEXT: s_bfe_i64 s[36:37], s[8:9], 0x100000
+; GFX12-NEXT: s_lshr_b32 s58, s8, 16
+; GFX12-NEXT: s_mov_b32 s60, s9
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[28:29], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[6:7], s[34:35], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[8:9], s[40:41], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[28:29], s[50:51], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[34:35], s[52:53], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[40:41], s[54:55], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[50:51], s[62:63], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[52:53], s[64:65], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[54:55], s[66:67], 0x100000
+; GFX12-NEXT: s_lshr_b32 s62, s14, 16
; GFX12-NEXT: s_bfe_i64 s[64:65], s[14:15], 0x100000
-; GFX12-NEXT: s_mov_b32 s14, s15
-; GFX12-NEXT: s_lshr_b32 s66, s15, 16
+; GFX12-NEXT: s_mov_b32 s66, s15
+; GFX12-NEXT: s_lshr_b32 s14, s15, 16
+; GFX12-NEXT: ; implicit-def: $sgpr67
+; GFX12-NEXT: ; implicit-def: $sgpr15
; GFX12-NEXT: s_bfe_i64 s[18:19], s[0:1], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[20:21], s[6:7], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[34:35], s[8:9], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[22:23], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[8:9], s[24:25], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[26:27], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[24:25], s[30:31], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[22:23], s[36:37], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[26:27], s[38:39], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[30:31], s[40:41], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[36:37], s[44:45], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[40:41], s[46:47], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[38:39], s[48:49], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[44:45], s[52:53], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[46:47], s[54:55], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[48:49], s[58:59], 0x100000
-; GFX12-NEXT: s_lshr_b32 s52, s12, 16
-; GFX12-NEXT: s_bfe_i64 s[54:55], s[12:13], 0x100000
-; GFX12-NEXT: s_mov_b32 s12, s13
-; GFX12-NEXT: s_lshr_b32 s58, s13, 16
-; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[20:21], s[2:3], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[46:47], s[10:11], 0x100000
+; GFX12-NEXT: s_lshr_b32 s44, s11, 16
+; GFX12-NEXT: s_bfe_i64 s[0:1], s[24:25], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[30:31], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[10:11], s[38:39], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[24:25], s[42:43], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[30:31], s[48:49], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[38:39], s[56:57], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[42:43], s[58:59], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[48:49], s[60:61], 0x100000
+; GFX12-NEXT: s_lshr_b32 s56, s12, 16
+; GFX12-NEXT: s_bfe_i64 s[58:59], s[12:13], 0x100000
+; GFX12-NEXT: s_mov_b32 s60, s13
+; GFX12-NEXT: s_lshr_b32 s12, s13, 16
+; GFX12-NEXT: ; implicit-def: $sgpr63
; GFX12-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x100000
+; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
+; GFX12-NEXT: ; implicit-def: $sgpr61
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x100000
+; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s67
+; GFX12-NEXT: ; implicit-def: $sgpr57
; GFX12-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s15
; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
-; GFX12-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v0, s14 :: v_dual_mov_b32 v3, s67
-; GFX12-NEXT: v_dual_mov_b32 v2, s66 :: v_dual_mov_b32 v5, s65
-; GFX12-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x100000
-; GFX12-NEXT: v_dual_mov_b32 v4, s64 :: v_dual_mov_b32 v7, s61
-; GFX12-NEXT: v_dual_mov_b32 v6, s60 :: v_dual_mov_b32 v9, s13
-; GFX12-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s59
-; GFX12-NEXT: v_dual_mov_b32 v10, s58 :: v_dual_mov_b32 v13, s55
-; GFX12-NEXT: v_dual_mov_b32 v12, s54 :: v_dual_mov_b32 v15, s53
-; GFX12-NEXT: v_mov_b32_e32 v14, s52
-; GFX12-NEXT: s_bfe_i64 s[12:13], s[62:63], 0x100000
+; GFX12-NEXT: v_dual_mov_b32 v0, s66 :: v_dual_mov_b32 v3, s15
+; GFX12-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v5, s65
+; GFX12-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x100000
+; GFX12-NEXT: v_dual_mov_b32 v4, s64 :: v_dual_mov_b32 v7, s63
+; GFX12-NEXT: v_dual_mov_b32 v6, s62 :: v_dual_mov_b32 v9, s61
+; GFX12-NEXT: v_dual_mov_b32 v8, s60 :: v_dual_mov_b32 v11, s13
+; GFX12-NEXT: v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s59
+; GFX12-NEXT: v_dual_mov_b32 v12, s58 :: v_dual_mov_b32 v15, s57
+; GFX12-NEXT: v_mov_b32_e32 v14, s56
+; GFX12-NEXT: s_bfe_i64 s[12:13], s[44:45], 0x100000
; GFX12-NEXT: s_clause 0x3
; GFX12-NEXT: global_store_b128 v24, v[0:3], s[16:17] offset:240
; GFX12-NEXT: global_store_b128 v24, v[4:7], s[16:17] offset:224
; GFX12-NEXT: global_store_b128 v24, v[8:11], s[16:17] offset:208
; GFX12-NEXT: global_store_b128 v24, v[12:15], s[16:17] offset:192
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v0, s50 :: v_dual_mov_b32 v3, s13
-; GFX12-NEXT: v_dual_mov_b32 v1, s51 :: v_dual_mov_b32 v2, s12
-; GFX12-NEXT: v_dual_mov_b32 v5, s57 :: v_dual_mov_b32 v4, s56
-; GFX12-NEXT: v_dual_mov_b32 v7, s49 :: v_dual_mov_b32 v6, s48
-; GFX12-NEXT: v_dual_mov_b32 v9, s45 :: v_dual_mov_b32 v8, s44
-; GFX12-NEXT: v_dual_mov_b32 v11, s47 :: v_dual_mov_b32 v10, s46
-; GFX12-NEXT: v_dual_mov_b32 v13, s35 :: v_dual_mov_b32 v12, s34
+; GFX12-NEXT: v_dual_mov_b32 v0, s54 :: v_dual_mov_b32 v3, s13
+; GFX12-NEXT: v_dual_mov_b32 v1, s55 :: v_dual_mov_b32 v2, s12
+; GFX12-NEXT: v_dual_mov_b32 v5, s47 :: v_dual_mov_b32 v4, s46
+; GFX12-NEXT: v_dual_mov_b32 v7, s53 :: v_dual_mov_b32 v6, s52
+; GFX12-NEXT: v_dual_mov_b32 v9, s49 :: v_dual_mov_b32 v8, s48
+; GFX12-NEXT: v_dual_mov_b32 v11, s51 :: v_dual_mov_b32 v10, s50
+; GFX12-NEXT: v_dual_mov_b32 v13, s37 :: v_dual_mov_b32 v12, s36
; GFX12-NEXT: v_dual_mov_b32 v15, s43 :: v_dual_mov_b32 v14, s42
; GFX12-NEXT: v_dual_mov_b32 v17, s41 :: v_dual_mov_b32 v16, s40
; GFX12-NEXT: v_dual_mov_b32 v19, s39 :: v_dual_mov_b32 v18, s38
-; GFX12-NEXT: v_dual_mov_b32 v21, s21 :: v_dual_mov_b32 v20, s20
-; GFX12-NEXT: v_dual_mov_b32 v23, s37 :: v_dual_mov_b32 v22, s36
+; GFX12-NEXT: v_dual_mov_b32 v21, s27 :: v_dual_mov_b32 v20, s26
+; GFX12-NEXT: v_dual_mov_b32 v23, s35 :: v_dual_mov_b32 v22, s34
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v24, v[0:3], s[16:17] offset:176
; GFX12-NEXT: global_store_b128 v24, v[4:7], s[16:17] offset:160
@@ -9014,16 +9173,16 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GFX12-NEXT: global_store_b128 v24, v[20:23], s[16:17] offset:96
; GFX12-NEXT: v_dual_mov_b32 v0, s30 :: v_dual_mov_b32 v3, s29
; GFX12-NEXT: v_dual_mov_b32 v1, s31 :: v_dual_mov_b32 v2, s28
-; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
-; GFX12-NEXT: v_dual_mov_b32 v7, s27 :: v_dual_mov_b32 v6, s26
-; GFX12-NEXT: v_dual_mov_b32 v9, s25 :: v_dual_mov_b32 v8, s24
-; GFX12-NEXT: v_dual_mov_b32 v11, s23 :: v_dual_mov_b32 v10, s22
-; GFX12-NEXT: v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
-; GFX12-NEXT: v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v14, s10
-; GFX12-NEXT: v_dual_mov_b32 v17, s9 :: v_dual_mov_b32 v16, s8
-; GFX12-NEXT: v_dual_mov_b32 v19, s7 :: v_dual_mov_b32 v18, s6
+; GFX12-NEXT: v_dual_mov_b32 v5, s23 :: v_dual_mov_b32 v4, s22
+; GFX12-NEXT: v_dual_mov_b32 v7, s25 :: v_dual_mov_b32 v6, s24
+; GFX12-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v8, s10
+; GFX12-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
+; GFX12-NEXT: v_dual_mov_b32 v13, s21 :: v_dual_mov_b32 v12, s20
+; GFX12-NEXT: v_dual_mov_b32 v15, s7 :: v_dual_mov_b32 v14, s6
+; GFX12-NEXT: v_dual_mov_b32 v17, s5 :: v_dual_mov_b32 v16, s4
+; GFX12-NEXT: v_dual_mov_b32 v19, s3 :: v_dual_mov_b32 v18, s2
; GFX12-NEXT: v_dual_mov_b32 v21, s19 :: v_dual_mov_b32 v20, s18
-; GFX12-NEXT: v_dual_mov_b32 v23, s5 :: v_dual_mov_b32 v22, s4
+; GFX12-NEXT: v_dual_mov_b32 v23, s1 :: v_dual_mov_b32 v22, s0
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v24, v[0:3], s[16:17] offset:80
; GFX12-NEXT: global_store_b128 v24, v[4:7], s[16:17] offset:64
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 14c1e04776561..557c698f0a57d 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -952,6 +952,7 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i32(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
@@ -5233,6 +5234,7 @@ define amdgpu_kernel void @constant_zextload_i8_to_i64(ptr addrspace(1) %out, pt
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_u8 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5331,6 +5333,7 @@ define amdgpu_kernel void @constant_sextload_i8_to_i64(ptr addrspace(1) %out, pt
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_i8 v0, v2, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5515,6 +5518,7 @@ define amdgpu_kernel void @constant_sextload_v1i8_to_v1i64(ptr addrspace(1) %out
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_i8 v0, v2, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5642,6 +5646,7 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i64(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
@@ -5766,6 +5771,7 @@ define amdgpu_kernel void @constant_sextload_v2i8_to_v2i64(ptr addrspace(1) %out
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v4, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -5942,28 +5948,32 @@ define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(ptr addrspace(1) %out
; GFX6-NOHSA-LABEL: constant_sextload_v4i8_to_v4i64:
; GFX6-NOHSA: ; %bb.0:
; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr9
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr11
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr5
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr7
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT: s_lshr_b32 s6, s4, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s4, 16
; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s4, 24
-; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s4, 8
+; GFX6-NOHSA-NEXT: s_lshr_b32 s6, s4, 8
; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
; GFX6-NOHSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s11
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s9
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s10
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NOHSA-NEXT: s_endpgm
;
@@ -5971,32 +5981,36 @@ define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(ptr addrspace(1) %out
; GFX7-HSA: ; %bb.0:
; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX7-HSA-NEXT: s_add_i32 s12, s12, s17
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr5
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr7
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr9
; GFX7-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr3
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT: s_lshr_b32 s4, s2, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s8, s2, 16
; GFX7-HSA-NEXT: s_lshr_b32 s6, s2, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s8, s2, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s4, s2, 8
; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT: s_add_u32 s4, s0, 16
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s0, 16
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s8
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s5
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_endpgm
@@ -6004,30 +6018,34 @@ define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(ptr addrspace(1) %out
; GFX8-NOHSA-LABEL: constant_sextload_v4i8_to_v4i64:
; GFX8-NOHSA: ; %bb.0:
; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr5
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr7
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr9
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr3
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT: s_lshr_b32 s4, s2, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s2, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s6, s2, 24
-; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s2, 8
+; GFX8-NOHSA-NEXT: s_lshr_b32 s4, s2, 8
; GFX8-NOHSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
-; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 16
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s8
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_endpgm
@@ -6068,21 +6086,25 @@ define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(ptr addrspace(1) %out
; GFX12-LABEL: constant_sextload_v4i8_to_v4i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: ; implicit-def: $sgpr7
+; GFX12-NEXT: ; implicit-def: $sgpr9
+; GFX12-NEXT: ; implicit-def: $sgpr5
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x0
+; GFX12-NEXT: ; implicit-def: $sgpr3
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s4, s2, 16
+; GFX12-NEXT: s_lshr_b32 s8, s2, 16
; GFX12-NEXT: s_lshr_b32 s6, s2, 24
-; GFX12-NEXT: s_lshr_b32 s8, s2, 8
+; GFX12-NEXT: s_lshr_b32 s4, s2, 8
; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
; GFX12-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s3
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s5
-; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7
-; GFX12-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v3, s9
-; GFX12-NEXT: v_mov_b32_e32 v2, s8
+; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s9
+; GFX12-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v7, s7
+; GFX12-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v3, s5
+; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
; GFX12-NEXT: global_store_b128 v8, v[0:3], s[0:1]
@@ -6317,6 +6339,9 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i64(ptr addrspace(1) %out
; GFX6-NOHSA-NEXT: s_mov_b32 s0, s4
; GFX6-NOHSA-NEXT: s_mov_b32 s1, s5
; GFX6-NOHSA-NEXT: s_mov_b32 s5, s9
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr15
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr13
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr17
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s7, 16
; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s7, 8
@@ -6363,12 +6388,15 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i64(ptr addrspace(1) %out
; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX7-HSA-NEXT: s_add_i32 s12, s12, s17
; GFX7-HSA-NEXT: s_mov_b32 s5, 0
+; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX7-HSA-NEXT: s_mov_b32 s7, s5
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_mov_b32 s7, s5
; GFX7-HSA-NEXT: s_mov_b32 s9, s5
-; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr15
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr13
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr11
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_lshr_b32 s4, s3, 16
; GFX7-HSA-NEXT: s_lshr_b32 s6, s3, 8
@@ -6425,22 +6453,26 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i64(ptr addrspace(1) %out
; GFX8-NOHSA: ; %bb.0:
; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NOHSA-NEXT: s_mov_b32 s5, 0
-; GFX8-NOHSA-NEXT: s_mov_b32 s7, s5
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr7
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr9
+; GFX8-NOHSA-NEXT: s_mov_b32 s11, s5
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr15
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr13
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_lshr_b32 s4, s3, 16
-; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s3, 8
-; GFX8-NOHSA-NEXT: s_mov_b32 s6, s3
-; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s2, 16
-; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s2, 24
-; GFX8-NOHSA-NEXT: s_lshr_b32 s14, s2, 8
+; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s3, 8
+; GFX8-NOHSA-NEXT: s_mov_b32 s10, s3
+; GFX8-NOHSA-NEXT: s_lshr_b32 s14, s2, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s2, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s6, s2, 8
; GFX8-NOHSA-NEXT: s_bfe_i64 s[16:17], s[2:3], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
; GFX8-NOHSA-NEXT: s_ashr_i32 s18, s3, 31
; GFX8-NOHSA-NEXT: s_ashr_i32 s19, s3, 24
; GFX8-NOHSA-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x80000
@@ -6458,24 +6490,24 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i64(ptr addrspace(1) %out
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s7
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s8
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s9
-; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s11
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s12
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s9
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s17
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_endpgm
@@ -6535,34 +6567,38 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i64(ptr addrspace(1) %out
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_mov_b32 s5, 0
+; GFX12-NEXT: ; implicit-def: $sgpr7
+; GFX12-NEXT: ; implicit-def: $sgpr9
+; GFX12-NEXT: ; implicit-def: $sgpr11
+; GFX12-NEXT: ; implicit-def: $sgpr13
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_mov_b32 s7, s5
+; GFX12-NEXT: s_mov_b32 s15, s5
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_lshr_b32 s4, s3, 16
-; GFX12-NEXT: s_lshr_b32 s8, s3, 8
-; GFX12-NEXT: s_mov_b32 s6, s3
+; GFX12-NEXT: s_lshr_b32 s12, s3, 8
+; GFX12-NEXT: s_mov_b32 s14, s3
; GFX12-NEXT: s_lshr_b32 s10, s2, 16
-; GFX12-NEXT: s_lshr_b32 s12, s2, 24
+; GFX12-NEXT: s_lshr_b32 s8, s2, 24
+; GFX12-NEXT: s_lshr_b32 s6, s2, 8
; GFX12-NEXT: s_bfe_i64 s[16:17], s[2:3], 0x80000
-; GFX12-NEXT: s_ashr_i32 s15, s3, 31
-; GFX12-NEXT: s_ashr_i32 s18, s3, 24
+; GFX12-NEXT: s_ashr_i32 s18, s3, 31
+; GFX12-NEXT: s_ashr_i32 s19, s3, 24
; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
-; GFX12-NEXT: s_lshr_b32 s14, s2, 8
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v3, s15
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[8:9], s[10:11], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[10:11], s[14:15], 0x80000
; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v5, s17
+; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v3, s18
+; GFX12-NEXT: v_dual_mov_b32 v2, s19 :: v_dual_mov_b32 v5, s17
; GFX12-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v1, s5
-; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v9, s7
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[14:15], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v11, s9
-; GFX12-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v13, s11
-; GFX12-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v15, s13
-; GFX12-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v7, s3
+; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v9, s11
+; GFX12-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v11, s13
+; GFX12-NEXT: v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s9
+; GFX12-NEXT: v_dual_mov_b32 v12, s8 :: v_dual_mov_b32 v15, s7
+; GFX12-NEXT: v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v7, s3
; GFX12-NEXT: v_mov_b32_e32 v6, s2
; GFX12-NEXT: s_clause 0x3
; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
@@ -6944,20 +6980,27 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX6-NOHSA-LABEL: constant_sextload_v16i8_to_v16i64:
; GFX6-NOHSA: ; %bb.0:
; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr13
; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr17
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr19
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr25
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr29
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr27
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr31
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[10:11], 0x0
; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0
; GFX6-NOHSA-NEXT: s_mov_b32 s21, s11
-; GFX6-NOHSA-NEXT: s_mov_b32 s13, s11
+; GFX6-NOHSA-NEXT: s_mov_b32 s15, s11
; GFX6-NOHSA-NEXT: s_mov_b32 s0, s8
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s7, 16
; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s5, 16
-; GFX6-NOHSA-NEXT: s_lshr_b32 s12, s7, 8
-; GFX6-NOHSA-NEXT: s_mov_b32 s8, s7
-; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s6, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s7, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s12, s7
+; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s6, 16
; GFX6-NOHSA-NEXT: s_lshr_b32 s16, s6, 24
; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s6, 8
; GFX6-NOHSA-NEXT: s_lshr_b32 s22, s5, 8
@@ -6974,25 +7017,26 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX6-NOHSA-NEXT: s_ashr_i32 s21, s7, 24
; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[10:11], 0x80000
; GFX6-NOHSA-NEXT: s_mov_b32 s1, s9
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr9
; GFX6-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s21
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s20
; GFX6-NOHSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s12
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s15
; GFX6-NOHSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s14
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s16
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s17
; GFX6-NOHSA-NEXT: s_mov_b32 s23, s11
@@ -7039,32 +7083,40 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX7-HSA-NEXT: s_add_i32 s12, s12, s17
; GFX7-HSA-NEXT: s_mov_b32 s9, 0
+; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX7-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; GFX7-HSA-NEXT: s_mov_b32 s11, s9
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GFX7-HSA-NEXT: s_mov_b32 s21, s9
+; GFX7-HSA-NEXT: s_mov_b32 s13, s9
; GFX7-HSA-NEXT: s_mov_b32 s23, s9
-; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX7-HSA-NEXT: s_mov_b32 s11, s9
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr15
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr25
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr21
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr19
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr17
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr31
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr29
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr27
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_lshr_b32 s8, s7, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s10, s7, 8
-; GFX7-HSA-NEXT: s_mov_b32 s12, s7
-; GFX7-HSA-NEXT: s_lshr_b32 s14, s6, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s16, s6, 24
-; GFX7-HSA-NEXT: s_ashr_i32 s29, s5, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s31, s5, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s18, s6, 8
-; GFX7-HSA-NEXT: s_lshr_b32 s20, s5, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s22, s5, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s12, s7, 8
+; GFX7-HSA-NEXT: s_mov_b32 s14, s7
+; GFX7-HSA-NEXT: s_lshr_b32 s16, s6, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s18, s6, 24
+; GFX7-HSA-NEXT: s_ashr_i32 s33, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s36, s5, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s20, s6, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s22, s5, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s10, s5, 8
; GFX7-HSA-NEXT: s_mov_b32 s24, s5
; GFX7-HSA-NEXT: s_lshr_b32 s26, s4, 16
; GFX7-HSA-NEXT: s_lshr_b32 s28, s4, 24
; GFX7-HSA-NEXT: s_lshr_b32 s30, s4, 8
; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[8:9], 0x80000
-; GFX7-HSA-NEXT: s_ashr_i32 s33, s7, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s36, s7, 24
+; GFX7-HSA-NEXT: s_ashr_i32 s37, s7, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s38, s7, 24
; GFX7-HSA-NEXT: s_bfe_i64 s[34:35], s[6:7], 0x80000
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
@@ -7072,63 +7124,64 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[28:29], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[8:9], s[26:27], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
; GFX7-HSA-NEXT: s_add_u32 s26, s0, 0x70
; GFX7-HSA-NEXT: s_addc_u32 s27, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
-; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s11
-; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s13
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s26
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s13
; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s27
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s36
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s33
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s10
-; GFX7-HSA-NEXT: s_add_u32 s10, s0, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 0x50
; GFX7-HSA-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
-; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s11
-; GFX7-HSA-NEXT: s_add_u32 s10, s0, 64
-; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
-; GFX7-HSA-NEXT: s_add_u32 s10, s0, 48
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s14
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s15
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 64
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s13
+; GFX7-HSA-NEXT: s_add_u32 s12, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s17
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s34
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s16
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s19
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s35
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s18
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s21
; GFX7-HSA-NEXT: flat_store_dwordx4 v[16:17], v[4:7]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX7-HSA-NEXT: flat_store_dwordx4 v[2:3], v[12:15]
-; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
-; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s20
-; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s31
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s29
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
-; GFX7-HSA-NEXT: s_add_u32 s10, s0, 32
+; GFX7-HSA-NEXT: s_addc_u32 s13, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-HSA-NEXT: s_add_u32 s10, s0, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
; GFX7-HSA-NEXT: s_addc_u32 s11, s1, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s23
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_nop 0
@@ -7154,23 +7207,32 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX8-NOHSA: ; %bb.0:
; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NOHSA-NEXT: s_mov_b32 s19, 0
-; GFX8-NOHSA-NEXT: s_mov_b32 s21, s19
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr21
+; GFX8-NOHSA-NEXT: s_mov_b32 s23, s19
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr15
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr9
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr11
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr13
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr17
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr31
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr29
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr27
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr25
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_lshr_b32 s18, s7, 16
-; GFX8-NOHSA-NEXT: s_lshr_b32 s22, s7, 8
-; GFX8-NOHSA-NEXT: s_mov_b32 s24, s7
+; GFX8-NOHSA-NEXT: s_lshr_b32 s24, s7, 8
+; GFX8-NOHSA-NEXT: s_mov_b32 s20, s7
; GFX8-NOHSA-NEXT: s_lshr_b32 s26, s6, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s28, s6, 24
; GFX8-NOHSA-NEXT: s_lshr_b32 s30, s6, 8
-; GFX8-NOHSA-NEXT: s_lshr_b32 s20, s5, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s22, s5, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s16, s5, 8
; GFX8-NOHSA-NEXT: s_mov_b32 s14, s5
; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s4, 24
; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s4, 8
-; GFX8-NOHSA-NEXT: s_ashr_i32 s31, s5, 31
; GFX8-NOHSA-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[34:35], s[6:7], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
@@ -7178,32 +7240,33 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
-; GFX8-NOHSA-NEXT: s_ashr_i32 s33, s5, 24
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[4:5], s[20:21], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[20:21], s[30:31], 0x80000
+; GFX8-NOHSA-NEXT: s_ashr_i32 s33, s5, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s36, s5, 24
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[4:5], s[22:23], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[22:23], s[30:31], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
; GFX8-NOHSA-NEXT: s_ashr_i32 s30, s7, 31
-; GFX8-NOHSA-NEXT: s_ashr_i32 s36, s7, 24
+; GFX8-NOHSA-NEXT: s_ashr_i32 s31, s7, 24
; GFX8-NOHSA-NEXT: s_bfe_i64 s[6:7], s[18:19], 0x80000
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x70
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s31
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s30
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x60
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s24
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s25
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s25
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 0x50
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -7220,8 +7283,8 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s34
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s35
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s20
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s23
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
@@ -7230,8 +7293,8 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s33
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s33
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 32
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -7352,63 +7415,73 @@ define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX12-LABEL: constant_sextload_v16i8_to_v16i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT: s_mov_b32 s9, 0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_mov_b32 s11, s9
+; GFX12-NEXT: ; implicit-def: $sgpr9
+; GFX12-NEXT: ; implicit-def: $sgpr15
+; GFX12-NEXT: ; implicit-def: $sgpr19
+; GFX12-NEXT: ; implicit-def: $sgpr21
+; GFX12-NEXT: ; implicit-def: $sgpr23
+; GFX12-NEXT: ; implicit-def: $sgpr25
+; GFX12-NEXT: ; implicit-def: $sgpr27
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: ; implicit-def: $sgpr17
+; GFX12-NEXT: ; implicit-def: $sgpr11
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
+; GFX12-NEXT: s_mov_b32 s3, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: s_mov_b32 s29, s3
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s8, s7, 16
-; GFX12-NEXT: s_lshr_b32 s12, s7, 8
-; GFX12-NEXT: s_mov_b32 s14, s7
+; GFX12-NEXT: s_lshr_b32 s2, s7, 16
+; GFX12-NEXT: s_lshr_b32 s26, s7, 8
+; GFX12-NEXT: s_mov_b32 s8, s7
+; GFX12-NEXT: s_lshr_b32 s24, s6, 16
+; GFX12-NEXT: s_lshr_b32 s22, s6, 24
+; GFX12-NEXT: s_lshr_b32 s20, s6, 8
+; GFX12-NEXT: s_lshr_b32 s18, s5, 8
+; GFX12-NEXT: s_lshr_b32 s14, s4, 24
; GFX12-NEXT: s_bfe_i64 s[34:35], s[6:7], 0x80000
-; GFX12-NEXT: s_ashr_i32 s33, s7, 31
-; GFX12-NEXT: s_ashr_i32 s36, s7, 24
+; GFX12-NEXT: s_ashr_i32 s37, s7, 31
+; GFX12-NEXT: s_ashr_i32 s38, s7, 24
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[6:7], s[14:15], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[14:15], s[18:19], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[18:19], s[20:21], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[20:21], s[22:23], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[22:23], s[24:25], 0x80000
; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GFX12-NEXT: s_lshr_b32 s16, s6, 16
-; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v3, s33
-; GFX12-NEXT: s_lshr_b32 s18, s6, 24
-; GFX12-NEXT: v_dual_mov_b32 v2, s36 :: v_dual_mov_b32 v5, s35
-; GFX12-NEXT: v_dual_mov_b32 v4, s34 :: v_dual_mov_b32 v1, s9
-; GFX12-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v7, s15
-; GFX12-NEXT: s_lshr_b32 s20, s6, 8
-; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v9, s13
-; GFX12-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s17
-; GFX12-NEXT: s_lshr_b32 s10, s5, 16
-; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
-; GFX12-NEXT: s_lshr_b32 s22, s5, 8
-; GFX12-NEXT: s_mov_b32 s24, s5
-; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
-; GFX12-NEXT: s_lshr_b32 s26, s4, 16
-; GFX12-NEXT: s_lshr_b32 s28, s4, 24
-; GFX12-NEXT: s_ashr_i32 s29, s5, 31
-; GFX12-NEXT: s_ashr_i32 s31, s5, 24
+; GFX12-NEXT: s_bfe_i64 s[24:25], s[26:27], 0x80000
+; GFX12-NEXT: v_dual_mov_b32 v26, 0 :: v_dual_mov_b32 v3, s37
+; GFX12-NEXT: v_dual_mov_b32 v2, s38 :: v_dual_mov_b32 v5, s35
+; GFX12-NEXT: v_dual_mov_b32 v4, s34 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v7, s9
+; GFX12-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v9, s25
+; GFX12-NEXT: v_dual_mov_b32 v8, s24 :: v_dual_mov_b32 v11, s23
+; GFX12-NEXT: s_lshr_b32 s28, s5, 16
+; GFX12-NEXT: s_lshr_b32 s16, s4, 16
+; GFX12-NEXT: s_lshr_b32 s12, s4, 8
+; GFX12-NEXT: s_mov_b32 s10, s5
+; GFX12-NEXT: s_bfe_i64 s[30:31], s[4:5], 0x80000
+; GFX12-NEXT: s_ashr_i32 s33, s5, 31
+; GFX12-NEXT: s_ashr_i32 s36, s5, 24
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[12:13], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[12:13], s[16:17], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[16:17], s[28:29], 0x80000
+; GFX12-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v13, s21
+; GFX12-NEXT: v_mov_b32_e32 v12, s20
; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v13, s19
-; GFX12-NEXT: v_mov_b32_e32 v12, s18
-; GFX12-NEXT: s_lshr_b32 s30, s4, 8
-; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: global_store_b128 v26, v[0:3], s[0:1] offset:112
; GFX12-NEXT: global_store_b128 v26, v[6:9], s[0:1] offset:96
-; GFX12-NEXT: v_dual_mov_b32 v6, s20 :: v_dual_mov_b32 v1, s11
-; GFX12-NEXT: v_mov_b32_e32 v7, s21
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[28:29], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v3, s29
-; GFX12-NEXT: v_dual_mov_b32 v2, s31 :: v_dual_mov_b32 v15, s25
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[30:31], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v14, s24 :: v_dual_mov_b32 v17, s23
-; GFX12-NEXT: v_dual_mov_b32 v16, s22 :: v_dual_mov_b32 v19, s27
-; GFX12-NEXT: v_dual_mov_b32 v18, s26 :: v_dual_mov_b32 v21, s7
-; GFX12-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v23, s3
-; GFX12-NEXT: v_dual_mov_b32 v22, s2 :: v_dual_mov_b32 v25, s5
-; GFX12-NEXT: v_mov_b32_e32 v24, s4
+; GFX12-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v1, s17
+; GFX12-NEXT: v_dual_mov_b32 v7, s19 :: v_dual_mov_b32 v0, s16
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v3, s33 :: v_dual_mov_b32 v2, s36
+; GFX12-NEXT: v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v14, s10
+; GFX12-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
+; GFX12-NEXT: v_dual_mov_b32 v19, s13 :: v_dual_mov_b32 v18, s12
+; GFX12-NEXT: v_dual_mov_b32 v21, s7 :: v_dual_mov_b32 v20, s6
+; GFX12-NEXT: v_dual_mov_b32 v23, s31 :: v_dual_mov_b32 v22, s30
+; GFX12-NEXT: v_dual_mov_b32 v25, s5 :: v_dual_mov_b32 v24, s4
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v26, v[10:13], s[0:1] offset:80
; GFX12-NEXT: global_store_b128 v26, v[4:7], s[0:1] offset:64
@@ -8106,64 +8179,73 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX6-NOHSA-LABEL: constant_sextload_v32i8_to_v32i64:
; GFX6-NOHSA: ; %bb.0:
; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
-; GFX6-NOHSA-NEXT: s_mov_b32 s57, 0
-; GFX6-NOHSA-NEXT: s_mov_b32 s47, s57
-; GFX6-NOHSA-NEXT: s_mov_b32 s19, s57
-; GFX6-NOHSA-NEXT: s_mov_b32 s15, s57
+; GFX6-NOHSA-NEXT: s_mov_b32 s59, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s51, s59
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr61
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr55
+; GFX6-NOHSA-NEXT: s_mov_b32 s27, s59
+; GFX6-NOHSA-NEXT: s_mov_b32 s15, s59
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
-; GFX6-NOHSA-NEXT: s_mov_b32 s21, s57
-; GFX6-NOHSA-NEXT: s_mov_b32 s23, s57
-; GFX6-NOHSA-NEXT: s_mov_b32 s39, s57
-; GFX6-NOHSA-NEXT: s_mov_b32 s41, s57
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr43
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr31
+; GFX6-NOHSA-NEXT: s_mov_b32 s19, s59
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr63
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr57
+; GFX6-NOHSA-NEXT: s_mov_b32 s21, s59
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr47
+; GFX6-NOHSA-NEXT: s_mov_b32 s37, s59
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr35
+; GFX6-NOHSA-NEXT: s_mov_b32 s39, s59
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT: s_lshr_b32 s56, s7, 16
-; GFX6-NOHSA-NEXT: s_lshr_b32 s46, s7, 8
+; GFX6-NOHSA-NEXT: s_lshr_b32 s58, s7, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s50, s7, 8
; GFX6-NOHSA-NEXT: s_mov_b32 s60, s7
-; GFX6-NOHSA-NEXT: s_lshr_b32 s50, s6, 16
-; GFX6-NOHSA-NEXT: s_lshr_b32 s36, s6, 24
-; GFX6-NOHSA-NEXT: s_lshr_b32 s24, s6, 8
-; GFX6-NOHSA-NEXT: s_ashr_i32 s33, s3, 31
-; GFX6-NOHSA-NEXT: s_ashr_i32 s43, s3, 24
-; GFX6-NOHSA-NEXT: s_ashr_i32 s31, s7, 31
-; GFX6-NOHSA-NEXT: s_ashr_i32 s35, s7, 24
-; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s3, 16
-; GFX6-NOHSA-NEXT: s_lshr_b32 s22, s3, 8
-; GFX6-NOHSA-NEXT: s_mov_b32 s26, s3
-; GFX6-NOHSA-NEXT: s_lshr_b32 s28, s2, 16
-; GFX6-NOHSA-NEXT: s_lshr_b32 s30, s2, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s54, s6, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s42, s6, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s30, s6, 8
+; GFX6-NOHSA-NEXT: s_ashr_i32 s65, s3, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s66, s3, 24
+; GFX6-NOHSA-NEXT: s_ashr_i32 s25, s7, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s29, s7, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s3, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s3, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s22, s3
+; GFX6-NOHSA-NEXT: s_lshr_b32 s24, s2, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s28, s2, 24
; GFX6-NOHSA-NEXT: s_lshr_b32 s34, s2, 8
; GFX6-NOHSA-NEXT: s_bfe_i64 s[12:13], s[2:3], 0x80000
; GFX6-NOHSA-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x80000
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[56:57], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[58:59], 0x80000
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[60:61], 0x80000
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s7
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[46:47], 0x80000
-; GFX6-NOHSA-NEXT: s_ashr_i32 s25, s1, 24
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[50:51], 0x80000
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s6
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s7
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[50:51], 0x80000
-; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s5, 16
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[54:55], 0x80000
+; GFX6-NOHSA-NEXT: s_lshr_b32 s26, s5, 16
; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s5, 8
; GFX6-NOHSA-NEXT: s_mov_b32 s16, s5
-; GFX6-NOHSA-NEXT: s_ashr_i32 s17, s1, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s17, s5, 31
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s6
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s7
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[36:37], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[42:43], 0x80000
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s2
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s3
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[2:3], s[24:25], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[2:3], s[30:31], 0x80000
+; GFX6-NOHSA-NEXT: s_ashr_i32 s33, s1, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s64, s1, 24
; GFX6-NOHSA-NEXT: s_lshr_b32 s62, s4, 16
-; GFX6-NOHSA-NEXT: s_lshr_b32 s58, s4, 24
-; GFX6-NOHSA-NEXT: s_lshr_b32 s38, s1, 16
-; GFX6-NOHSA-NEXT: s_lshr_b32 s40, s1, 8
-; GFX6-NOHSA-NEXT: s_mov_b32 s44, s1
-; GFX6-NOHSA-NEXT: s_lshr_b32 s48, s0, 16
-; GFX6-NOHSA-NEXT: s_lshr_b32 s52, s0, 24
-; GFX6-NOHSA-NEXT: s_lshr_b32 s54, s0, 8
+; GFX6-NOHSA-NEXT: s_lshr_b32 s56, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s36, s1, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s38, s1, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s40, s1
+; GFX6-NOHSA-NEXT: s_lshr_b32 s44, s0, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s48, s0, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s52, s0, 8
; GFX6-NOHSA-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x80000
; GFX6-NOHSA-NEXT: s_mov_b32 s0, s8
; GFX6-NOHSA-NEXT: s_mov_b32 s1, s9
@@ -8171,14 +8253,17 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s7
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s2
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s3
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[2:3], s[18:19], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[2:3], s[26:27], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v19, s17
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr17
; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[16:17], 0x80000
; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[14:15], 0x80000
-; GFX6-NOHSA-NEXT: s_lshr_b32 s42, s4, 8
+; GFX6-NOHSA-NEXT: s_ashr_i32 s23, s5, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s46, s4, 8
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v16, s2
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v17, s3
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s35
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s25
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v20, s6
; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
@@ -8186,75 +8271,79 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v22, s8
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v23, s9
; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[62:63], 0x80000
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[58:59], 0x80000
-; GFX6-NOHSA-NEXT: s_ashr_i32 s27, s5, 31
-; GFX6-NOHSA-NEXT: s_ashr_i32 s29, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[56:57], 0x80000
; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v18, s23
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s9
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[42:43], 0x80000
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v19, s27
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[46:47], 0x80000
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr23
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:224
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s4
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s5
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s6
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s7
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr29
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr25
; GFX6-NOHSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:160
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:128
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(1)
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s20
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s21
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s43
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s33
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v18, s29
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s66
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s65
; GFX6-NOHSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s26
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s27
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s22
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s23
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[30:31], s[34:35], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s28
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s29
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s30
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s31
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[36:37], s[38:39], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s29
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[26:27], s[36:37], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s34
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s35
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[14:15], s[44:45], 0x80000
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[18:19], s[40:41], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s30
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr41
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[14:15], s[40:41], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[16:17], s[38:39], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s36
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s37
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s25
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s17
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[52:53], 0x80000
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[48:49], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s27
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s64
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr49
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[48:49], 0x80000
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr45
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[44:45], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s14
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s15
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s18
-; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s19
-; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[54:55], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NOHSA-NEXT: ; implicit-def: $sgpr53
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[52:53], 0x80000
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
@@ -8277,31 +8366,45 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA: ; %bb.0:
; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
; GFX7-HSA-NEXT: s_add_i32 s12, s12, s17
-; GFX7-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX7-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GFX7-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr39
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr49
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr27
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr13
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr19
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr21
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr23
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr37
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr43
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr45
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr57
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr55
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr41
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr67
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr65
+; GFX7-HSA-NEXT: ; implicit-def: $sgpr63
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
; GFX7-HSA-NEXT: s_mov_b32 s11, 0
-; GFX7-HSA-NEXT: s_mov_b32 s37, s11
-; GFX7-HSA-NEXT: s_mov_b32 s57, s11
+; GFX7-HSA-NEXT: s_mov_b32 s35, s11
+; GFX7-HSA-NEXT: s_mov_b32 s59, s11
; GFX7-HSA-NEXT: s_mov_b32 s47, s11
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_lshr_b32 s10, s7, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s36, s7, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s34, s7, 8
; GFX7-HSA-NEXT: s_mov_b32 s38, s7
; GFX7-HSA-NEXT: s_lshr_b32 s40, s6, 16
-; GFX7-HSA-NEXT: s_ashr_i32 s39, s1, 24
-; GFX7-HSA-NEXT: s_ashr_i32 s41, s3, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s50, s3, 24
-; GFX7-HSA-NEXT: s_ashr_i32 s65, s5, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s52, s6, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s54, s6, 8
-; GFX7-HSA-NEXT: s_lshr_b32 s56, s5, 16
+; GFX7-HSA-NEXT: s_ashr_i32 s51, s3, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s52, s3, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s54, s6, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s56, s6, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s58, s5, 16
; GFX7-HSA-NEXT: s_lshr_b32 s46, s5, 8
; GFX7-HSA-NEXT: s_mov_b32 s48, s5
; GFX7-HSA-NEXT: s_lshr_b32 s44, s4, 16
; GFX7-HSA-NEXT: s_lshr_b32 s42, s4, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s34, s4, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s36, s4, 8
; GFX7-HSA-NEXT: s_lshr_b32 s30, s3, 16
; GFX7-HSA-NEXT: s_lshr_b32 s24, s3, 8
; GFX7-HSA-NEXT: s_mov_b32 s26, s3
@@ -8309,31 +8412,33 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_lshr_b32 s20, s2, 24
; GFX7-HSA-NEXT: s_lshr_b32 s18, s2, 8
; GFX7-HSA-NEXT: s_lshr_b32 s16, s1, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s58, s1, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s60, s1, 8
; GFX7-HSA-NEXT: s_mov_b32 s12, s1
-; GFX7-HSA-NEXT: s_lshr_b32 s60, s0, 16
-; GFX7-HSA-NEXT: s_lshr_b32 s62, s0, 24
-; GFX7-HSA-NEXT: s_lshr_b32 s64, s0, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s62, s0, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s64, s0, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s66, s0, 8
; GFX7-HSA-NEXT: s_bfe_i64 s[14:15], s[2:3], 0x80000
; GFX7-HSA-NEXT: s_mov_b32 s31, s11
; GFX7-HSA-NEXT: s_mov_b32 s25, s11
; GFX7-HSA-NEXT: s_mov_b32 s17, s11
-; GFX7-HSA-NEXT: s_mov_b32 s59, s11
+; GFX7-HSA-NEXT: s_mov_b32 s61, s11
; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[10:11], 0x80000
; GFX7-HSA-NEXT: s_ashr_i32 s33, s1, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s51, s5, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s68, s7, 31
-; GFX7-HSA-NEXT: s_ashr_i32 s69, s7, 24
+; GFX7-HSA-NEXT: s_ashr_i32 s50, s1, 24
+; GFX7-HSA-NEXT: s_ashr_i32 s53, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s70, s5, 24
+; GFX7-HSA-NEXT: s_ashr_i32 s71, s7, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s72, s7, 24
; GFX7-HSA-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[28:29], s[4:5], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[66:67], s[6:7], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[68:69], s[6:7], 0x80000
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[64:65], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[62:63], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[60:61], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[66:67], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[62:63], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[10:11], s[58:59], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[10:11], s[60:61], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
@@ -8341,74 +8446,74 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
; GFX7-HSA-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[58:59], s[40:41], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[60:61], s[38:39], 0x80000
-; GFX7-HSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
-; GFX7-HSA-NEXT: s_add_u32 s62, s8, 0xf0
-; GFX7-HSA-NEXT: s_addc_u32 s63, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s36
-; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xe0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s37
-; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s36
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s37
-; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xd0
-; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s36
-; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s37
-; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xc0
-; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s36
-; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s37
-; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xb0
-; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s36
-; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s37
-; GFX7-HSA-NEXT: s_add_u32 s36, s8, 0xa0
-; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s58
-; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s59
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s52
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s53
-; GFX7-HSA-NEXT: s_addc_u32 s37, s9, 0
+; GFX7-HSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
+; GFX7-HSA-NEXT: s_add_u32 s60, s8, 0xf0
+; GFX7-HSA-NEXT: s_addc_u32 s61, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s34
+; GFX7-HSA-NEXT: s_add_u32 s34, s8, 0xe0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s35
+; GFX7-HSA-NEXT: s_addc_u32 s35, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s35
+; GFX7-HSA-NEXT: s_add_u32 s34, s8, 0xd0
+; GFX7-HSA-NEXT: s_addc_u32 s35, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s35
+; GFX7-HSA-NEXT: s_add_u32 s34, s8, 0xc0
+; GFX7-HSA-NEXT: s_addc_u32 s35, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s35
+; GFX7-HSA-NEXT: s_add_u32 s34, s8, 0xb0
+; GFX7-HSA-NEXT: s_addc_u32 s35, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s35
+; GFX7-HSA-NEXT: s_add_u32 s34, s8, 0xa0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s40
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s54
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s55
+; GFX7-HSA-NEXT: s_addc_u32 s35, s9, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s66
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s68
; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s28
; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x90
; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s29
; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s28
-; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s67
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s54
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s55
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s69
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s56
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s57
; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s29
; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x80
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s62
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s60
; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[12:15]
; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s28
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s63
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s69
-; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s68
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s61
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s72
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s71
; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s29
; GFX7-HSA-NEXT: s_add_u32 s28, s8, 0x70
-; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s60
-; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s61
-; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s56
-; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s57
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s39
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s58
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s59
; GFX7-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s65
-; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s51
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s53
; GFX7-HSA-NEXT: s_addc_u32 s29, s9, 0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s34
; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s48
; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s24
@@ -8416,7 +8521,7 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s49
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s46
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s47
-; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s35
; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s25
; GFX7-HSA-NEXT: s_addc_u32 s25, s9, 0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s44
@@ -8425,16 +8530,16 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s43
; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s28
; GFX7-HSA-NEXT: flat_store_dwordx4 v[20:21], v[0:3]
-; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s36
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
; GFX7-HSA-NEXT: s_add_u32 s20, s8, 0x50
-; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s37
; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s30
; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s31
; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s26
-; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s50
-; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s52
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s51
; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s27
; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s29
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
@@ -8464,7 +8569,7 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
-; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s39
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s50
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s33
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -8500,27 +8605,47 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-LABEL: constant_sextload_v32i8_to_v32i64:
; GFX8-NOHSA: ; %bb.0:
; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GFX8-NOHSA-NEXT: s_mov_b32 s47, 0
-; GFX8-NOHSA-NEXT: s_mov_b32 s53, s47
-; GFX8-NOHSA-NEXT: s_mov_b32 s65, s47
-; GFX8-NOHSA-NEXT: s_mov_b32 s67, s47
+; GFX8-NOHSA-NEXT: s_mov_b32 s43, 0
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr49
+; GFX8-NOHSA-NEXT: s_mov_b32 s57, s43
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr51
+; GFX8-NOHSA-NEXT: s_mov_b32 s65, s43
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr31
+; GFX8-NOHSA-NEXT: s_mov_b32 s67, s43
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr19
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr13
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr15
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr17
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr21
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr25
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr27
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr29
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr37
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr39
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr41
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr45
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr55
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr63
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr61
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr59
+; GFX8-NOHSA-NEXT: ; implicit-def: $sgpr53
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT: s_lshr_b32 s46, s7, 16
-; GFX8-NOHSA-NEXT: s_lshr_b32 s54, s7, 8
-; GFX8-NOHSA-NEXT: s_mov_b32 s56, s7
+; GFX8-NOHSA-NEXT: s_lshr_b32 s42, s7, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s52, s7, 8
+; GFX8-NOHSA-NEXT: s_mov_b32 s48, s7
; GFX8-NOHSA-NEXT: s_lshr_b32 s58, s6, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s60, s6, 24
; GFX8-NOHSA-NEXT: s_lshr_b32 s62, s6, 8
-; GFX8-NOHSA-NEXT: s_lshr_b32 s52, s5, 16
-; GFX8-NOHSA-NEXT: s_lshr_b32 s50, s5, 8
-; GFX8-NOHSA-NEXT: s_mov_b32 s48, s5
-; GFX8-NOHSA-NEXT: s_lshr_b32 s42, s4, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s56, s5, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s54, s5, 8
+; GFX8-NOHSA-NEXT: s_mov_b32 s50, s5
+; GFX8-NOHSA-NEXT: s_lshr_b32 s44, s4, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s40, s4, 24
; GFX8-NOHSA-NEXT: s_lshr_b32 s38, s4, 8
; GFX8-NOHSA-NEXT: s_lshr_b32 s64, s3, 16
-; GFX8-NOHSA-NEXT: s_lshr_b32 s34, s3, 8
+; GFX8-NOHSA-NEXT: s_lshr_b32 s36, s3, 8
; GFX8-NOHSA-NEXT: s_mov_b32 s30, s3
; GFX8-NOHSA-NEXT: s_lshr_b32 s28, s2, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s26, s2, 24
@@ -8533,8 +8658,8 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s0, 8
; GFX8-NOHSA-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[22:23], s[2:3], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[36:37], s[4:5], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[44:45], s[6:7], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[46:47], s[6:7], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
@@ -8547,80 +8672,79 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
; GFX8-NOHSA-NEXT: s_ashr_i32 s33, s3, 31
; GFX8-NOHSA-NEXT: s_ashr_i32 s66, s3, 24
; GFX8-NOHSA-NEXT: s_bfe_i64 s[2:3], s[64:65], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x80000
; GFX8-NOHSA-NEXT: s_ashr_i32 s64, s5, 31
; GFX8-NOHSA-NEXT: s_ashr_i32 s5, s5, 24
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[62:63], s[62:63], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x80000
; GFX8-NOHSA-NEXT: s_ashr_i32 s65, s7, 31
; GFX8-NOHSA-NEXT: s_ashr_i32 s7, s7, 24
-; GFX8-NOHSA-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s46
-; GFX8-NOHSA-NEXT: s_add_u32 s46, s8, 0xf0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s47
-; GFX8-NOHSA-NEXT: s_addc_u32 s47, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s46
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s42
+; GFX8-NOHSA-NEXT: s_add_u32 s42, s8, 0xf0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s43
+; GFX8-NOHSA-NEXT: s_addc_u32 s43, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s42
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s65
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s47
-; GFX8-NOHSA-NEXT: s_add_u32 s46, s8, 0xe0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s43
+; GFX8-NOHSA-NEXT: s_add_u32 s42, s8, 0xe0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s47, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s46
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s56
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s57
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s54
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s55
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s47
-; GFX8-NOHSA-NEXT: s_add_u32 s46, s8, 0xd0
+; GFX8-NOHSA-NEXT: s_addc_u32 s43, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s42
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s49
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s52
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s53
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s43
+; GFX8-NOHSA-NEXT: s_add_u32 s42, s8, 0xd0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s47, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s46
+; GFX8-NOHSA-NEXT: s_addc_u32 s43, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s42
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s58
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s59
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s60
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s61
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s47
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s43
+; GFX8-NOHSA-NEXT: s_add_u32 s42, s8, 0xc0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_nop 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s44
-; GFX8-NOHSA-NEXT: s_add_u32 s44, s8, 0xc0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s45
-; GFX8-NOHSA-NEXT: s_addc_u32 s45, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s44
+; GFX8-NOHSA-NEXT: s_addc_u32 s43, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s42
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s46
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s47
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s62
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s63
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NOHSA-NEXT: s_add_u32 s44, s8, 0xb0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s43
+; GFX8-NOHSA-NEXT: s_add_u32 s42, s8, 0xb0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s45, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s44
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s52
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s53
+; GFX8-NOHSA-NEXT: s_addc_u32 s43, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s42
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s56
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s57
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s64
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s45
-; GFX8-NOHSA-NEXT: s_add_u32 s44, s8, 0xa0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s43
+; GFX8-NOHSA-NEXT: s_add_u32 s42, s8, 0xa0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NOHSA-NEXT: s_addc_u32 s45, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s44
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s48
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s49
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s50
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s51
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s45
+; GFX8-NOHSA-NEXT: s_addc_u32 s43, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s42
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s51
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s54
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s55
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s43
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s40
@@ -8628,19 +8752,19 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s41
; GFX8-NOHSA-NEXT: s_addc_u32 s41, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s40
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s42
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s43
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s44
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s45
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s41
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s36
-; GFX8-NOHSA-NEXT: s_add_u32 s36, s8, 0x80
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s37
-; GFX8-NOHSA-NEXT: s_addc_u32 s37, s9, 0
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s34
+; GFX8-NOHSA-NEXT: s_add_u32 s34, s8, 0x80
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s35
+; GFX8-NOHSA-NEXT: s_addc_u32 s35, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s34
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s38
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s39
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s37
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s35
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_nop 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
@@ -8659,8 +8783,8 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX8-NOHSA-NEXT: s_add_u32 s2, s8, 0x50
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s30
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s31
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s34
-; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s37
; GFX8-NOHSA-NEXT: s_addc_u32 s3, s9, 0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
@@ -8886,71 +9010,97 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX12-LABEL: constant_sextload_v32i8_to_v32i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
-; GFX12-NEXT: s_mov_b32 s41, 0
+; GFX12-NEXT: s_mov_b32 s29, 0
+; GFX12-NEXT: ; implicit-def: $sgpr17
+; GFX12-NEXT: ; implicit-def: $sgpr13
+; GFX12-NEXT: ; implicit-def: $sgpr15
+; GFX12-NEXT: ; implicit-def: $sgpr19
+; GFX12-NEXT: ; implicit-def: $sgpr23
+; GFX12-NEXT: ; implicit-def: $sgpr65
+; GFX12-NEXT: ; implicit-def: $sgpr63
+; GFX12-NEXT: ; implicit-def: $sgpr35
+; GFX12-NEXT: ; implicit-def: $sgpr55
+; GFX12-NEXT: ; implicit-def: $sgpr49
+; GFX12-NEXT: ; implicit-def: $sgpr53
+; GFX12-NEXT: ; implicit-def: $sgpr51
+; GFX12-NEXT: ; implicit-def: $sgpr45
+; GFX12-NEXT: ; implicit-def: $sgpr57
+; GFX12-NEXT: ; implicit-def: $sgpr61
+; GFX12-NEXT: ; implicit-def: $sgpr59
+; GFX12-NEXT: ; implicit-def: $sgpr37
+; GFX12-NEXT: ; implicit-def: $sgpr27
+; GFX12-NEXT: ; implicit-def: $sgpr39
+; GFX12-NEXT: ; implicit-def: $sgpr25
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_mov_b32 s43, s41
-; GFX12-NEXT: s_mov_b32 s31, s41
-; GFX12-NEXT: s_mov_b32 s23, s41
+; GFX12-NEXT: s_mov_b32 s47, s29
+; GFX12-NEXT: s_mov_b32 s31, s29
+; GFX12-NEXT: s_mov_b32 s43, s29
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_lshr_b32 s40, s7, 16
-; GFX12-NEXT: s_lshr_b32 s52, s6, 8
+; GFX12-NEXT: s_lshr_b32 s28, s7, 16
+; GFX12-NEXT: s_lshr_b32 s54, s6, 8
; GFX12-NEXT: s_lshr_b32 s62, s4, 8
-; GFX12-NEXT: s_lshr_b32 s42, s3, 16
-; GFX12-NEXT: s_lshr_b32 s64, s0, 8
-; GFX12-NEXT: s_ashr_i32 s53, s3, 31
-; GFX12-NEXT: s_ashr_i32 s63, s3, 24
-; GFX12-NEXT: s_lshr_b32 s44, s7, 8
-; GFX12-NEXT: s_mov_b32 s46, s7
-; GFX12-NEXT: s_lshr_b32 s48, s6, 16
-; GFX12-NEXT: s_lshr_b32 s50, s6, 24
-; GFX12-NEXT: s_lshr_b32 s30, s5, 16
-; GFX12-NEXT: s_lshr_b32 s54, s5, 8
-; GFX12-NEXT: s_mov_b32 s56, s5
+; GFX12-NEXT: s_lshr_b32 s46, s3, 16
+; GFX12-NEXT: s_lshr_b32 s64, s2, 16
+; GFX12-NEXT: s_lshr_b32 s30, s1, 16
+; GFX12-NEXT: s_lshr_b32 s22, s1, 8
+; GFX12-NEXT: s_mov_b32 s16, s1
+; GFX12-NEXT: s_lshr_b32 s18, s0, 16
+; GFX12-NEXT: s_lshr_b32 s14, s0, 24
+; GFX12-NEXT: s_lshr_b32 s12, s0, 8
+; GFX12-NEXT: s_lshr_b32 s48, s7, 8
+; GFX12-NEXT: s_mov_b32 s34, s7
+; GFX12-NEXT: s_lshr_b32 s50, s6, 16
+; GFX12-NEXT: s_lshr_b32 s52, s6, 24
+; GFX12-NEXT: s_lshr_b32 s42, s5, 16
+; GFX12-NEXT: s_lshr_b32 s56, s5, 8
+; GFX12-NEXT: s_mov_b32 s44, s5
; GFX12-NEXT: s_lshr_b32 s58, s4, 16
; GFX12-NEXT: s_lshr_b32 s60, s4, 24
; GFX12-NEXT: s_lshr_b32 s38, s3, 8
; GFX12-NEXT: s_mov_b32 s36, s3
-; GFX12-NEXT: s_lshr_b32 s28, s2, 16
; GFX12-NEXT: s_lshr_b32 s26, s2, 24
; GFX12-NEXT: s_lshr_b32 s24, s2, 8
-; GFX12-NEXT: s_lshr_b32 s22, s1, 16
-; GFX12-NEXT: s_lshr_b32 s16, s1, 8
-; GFX12-NEXT: s_mov_b32 s18, s1
-; GFX12-NEXT: s_lshr_b32 s14, s0, 16
-; GFX12-NEXT: s_lshr_b32 s12, s0, 24
; GFX12-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x80000
; GFX12-NEXT: s_bfe_i64 s[20:21], s[2:3], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[40:41], s[4:5], 0x80000
; GFX12-NEXT: s_bfe_i64 s[66:67], s[6:7], 0x80000
; GFX12-NEXT: s_ashr_i32 s6, s1, 31
; GFX12-NEXT: s_ashr_i32 s33, s1, 24
-; GFX12-NEXT: s_bfe_i64 s[0:1], s[64:65], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[42:43], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[42:43], s[62:63], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[0:1], s[12:13], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[12:13], s[14:15], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[14:15], s[18:19], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[18:19], s[16:17], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[16:17], s[22:23], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[22:23], s[30:31], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[30:31], s[64:65], 0x80000
+; GFX12-NEXT: s_ashr_i32 s64, s3, 31
+; GFX12-NEXT: s_ashr_i32 s65, s3, 24
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[46:47], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[46:47], s[62:63], 0x80000
; GFX12-NEXT: s_ashr_i32 s62, s5, 31
-; GFX12-NEXT: s_ashr_i32 s64, s5, 24
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[52:53], 0x80000
-; GFX12-NEXT: s_ashr_i32 s52, s7, 31
-; GFX12-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
+; GFX12-NEXT: s_ashr_i32 s63, s5, 24
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[54:55], 0x80000
+; GFX12-NEXT: s_ashr_i32 s54, s7, 31
+; GFX12-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
; GFX12-NEXT: s_ashr_i32 s7, s7, 24
-; GFX12-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s41
-; GFX12-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
; GFX12-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v3, s52
-; GFX12-NEXT: v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s47
-; GFX12-NEXT: v_dual_mov_b32 v4, s46 :: v_dual_mov_b32 v7, s45
-; GFX12-NEXT: v_dual_mov_b32 v6, s44 :: v_dual_mov_b32 v9, s49
-; GFX12-NEXT: v_dual_mov_b32 v8, s48 :: v_dual_mov_b32 v11, s51
-; GFX12-NEXT: v_dual_mov_b32 v10, s50 :: v_dual_mov_b32 v13, s67
+; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s29
+; GFX12-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x80000
+; GFX12-NEXT: v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v3, s54
+; GFX12-NEXT: v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s35
+; GFX12-NEXT: v_dual_mov_b32 v4, s34 :: v_dual_mov_b32 v7, s49
+; GFX12-NEXT: v_dual_mov_b32 v6, s48 :: v_dual_mov_b32 v9, s51
+; GFX12-NEXT: v_dual_mov_b32 v8, s50 :: v_dual_mov_b32 v11, s53
+; GFX12-NEXT: v_dual_mov_b32 v10, s52 :: v_dual_mov_b32 v13, s67
; GFX12-NEXT: v_dual_mov_b32 v12, s66 :: v_dual_mov_b32 v15, s5
; GFX12-NEXT: v_mov_b32_e32 v14, s4
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[30:31], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[42:43], 0x80000
+; GFX12-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
; GFX12-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x80000
; GFX12-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x80000
; GFX12-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x80000
; GFX12-NEXT: s_clause 0x3
@@ -8960,22 +9110,20 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v24, v[12:15], s[8:9] offset:192
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s62
-; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s64
-; GFX12-NEXT: v_dual_mov_b32 v5, s57 :: v_dual_mov_b32 v4, s56
-; GFX12-NEXT: v_dual_mov_b32 v7, s55 :: v_dual_mov_b32 v6, s54
+; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s63
+; GFX12-NEXT: v_dual_mov_b32 v5, s45 :: v_dual_mov_b32 v4, s44
+; GFX12-NEXT: v_dual_mov_b32 v7, s57 :: v_dual_mov_b32 v6, s56
; GFX12-NEXT: v_dual_mov_b32 v9, s59 :: v_dual_mov_b32 v8, s58
; GFX12-NEXT: v_dual_mov_b32 v11, s61 :: v_dual_mov_b32 v10, s60
-; GFX12-NEXT: v_mov_b32_e32 v13, s35
+; GFX12-NEXT: v_mov_b32_e32 v13, s41
; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
; GFX12-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
; GFX12-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v12, s34 :: v_dual_mov_b32 v15, s43
-; GFX12-NEXT: v_dual_mov_b32 v14, s42 :: v_dual_mov_b32 v17, s3
+; GFX12-NEXT: v_dual_mov_b32 v12, s40 :: v_dual_mov_b32 v15, s47
+; GFX12-NEXT: v_dual_mov_b32 v14, s46 :: v_dual_mov_b32 v17, s3
; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v16, s2 :: v_dual_mov_b32 v19, s53
-; GFX12-NEXT: v_dual_mov_b32 v18, s63 :: v_dual_mov_b32 v21, s37
-; GFX12-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GFX12-NEXT: v_dual_mov_b32 v16, s2 :: v_dual_mov_b32 v19, s64
+; GFX12-NEXT: v_dual_mov_b32 v18, s65 :: v_dual_mov_b32 v21, s37
; GFX12-NEXT: v_dual_mov_b32 v20, s36 :: v_dual_mov_b32 v23, s39
; GFX12-NEXT: v_mov_b32_e32 v22, s38
; GFX12-NEXT: s_clause 0x5
@@ -8985,23 +9133,18 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v24, v[12:15], s[8:9] offset:128
; GFX12-NEXT: global_store_b128 v24, v[16:19], s[8:9] offset:112
; GFX12-NEXT: global_store_b128 v24, v[20:23], s[8:9] offset:96
-; GFX12-NEXT: v_dual_mov_b32 v0, s28 :: v_dual_mov_b32 v3, s27
-; GFX12-NEXT: v_dual_mov_b32 v1, s29 :: v_dual_mov_b32 v2, s26
-; GFX12-NEXT: v_mov_b32_e32 v5, s21
-; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v7, s25
-; GFX12-NEXT: v_dual_mov_b32 v6, s24 :: v_dual_mov_b32 v9, s23
-; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
-; GFX12-NEXT: v_dual_mov_b32 v8, s22 :: v_dual_mov_b32 v11, s6
-; GFX12-NEXT: v_dual_mov_b32 v10, s33 :: v_dual_mov_b32 v13, s19
-; GFX12-NEXT: v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v15, s17
-; GFX12-NEXT: v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v17, s15
-; GFX12-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v19, s13
-; GFX12-NEXT: v_dual_mov_b32 v18, s12 :: v_dual_mov_b32 v21, s11
-; GFX12-NEXT: v_dual_mov_b32 v20, s10 :: v_dual_mov_b32 v23, s1
-; GFX12-NEXT: v_mov_b32_e32 v22, s0
+; GFX12-NEXT: v_dual_mov_b32 v0, s30 :: v_dual_mov_b32 v3, s27
+; GFX12-NEXT: v_dual_mov_b32 v1, s31 :: v_dual_mov_b32 v2, s26
+; GFX12-NEXT: v_dual_mov_b32 v5, s21 :: v_dual_mov_b32 v4, s20
+; GFX12-NEXT: v_dual_mov_b32 v7, s25 :: v_dual_mov_b32 v6, s24
+; GFX12-NEXT: v_dual_mov_b32 v9, s23 :: v_dual_mov_b32 v8, s22
+; GFX12-NEXT: v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v10, s33
+; GFX12-NEXT: v_dual_mov_b32 v13, s19 :: v_dual_mov_b32 v12, s18
+; GFX12-NEXT: v_dual_mov_b32 v15, s17 :: v_dual_mov_b32 v14, s16
+; GFX12-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
+; GFX12-NEXT: v_dual_mov_b32 v19, s13 :: v_dual_mov_b32 v18, s12
+; GFX12-NEXT: v_dual_mov_b32 v21, s11 :: v_dual_mov_b32 v20, s10
+; GFX12-NEXT: v_dual_mov_b32 v23, s1 :: v_dual_mov_b32 v22, s0
; GFX12-NEXT: s_clause 0x5
; GFX12-NEXT: global_store_b128 v24, v[0:3], s[8:9] offset:80
; GFX12-NEXT: global_store_b128 v24, v[4:7], s[8:9] offset:64
@@ -9510,6 +9653,7 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i16(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v1
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
@@ -9641,12 +9785,13 @@ define amdgpu_kernel void @constant_sextload_v2i8_to_v2i16(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v1, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v1, 0, 8
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
+; GFX12-TRUE16-NEXT: global_store_b32 v0, v2, s[0:1]
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_sextload_v2i8_to_v2i16:
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
index f8c8be01f2d35..b03b19a963b02 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
@@ -6169,41 +6169,45 @@ define amdgpu_kernel void @global_sextload_v8i16_to_v8i64(ptr addrspace(1) %out,
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr7
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr13
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s7, v3
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s15, v3
; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s4, v0
; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s6, v2
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s7
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s5
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s12, s6, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s14, s4, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s13, s5, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s15, s5, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s7, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s21, s7, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s14, v2
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s6, s15
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s5
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s12, s14, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s10, s4, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[14:15], 0x100000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s21, s15, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s15, s15, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[4:5], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[6:7], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[14:15], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[12:13], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s21
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s20
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s8
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s9
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s15
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s13
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s14, s5, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s5, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[10:11], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[12:13], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s21
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s20
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s14
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s18
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s19
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s16
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s17
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s10
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s11
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s6
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s7
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s10
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s11
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s4
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s5
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
@@ -6218,49 +6222,51 @@ define amdgpu_kernel void @global_sextload_v8i16_to_v8i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr5
+; GCN-HSA-NEXT: ; implicit-def: $sgpr7
+; GCN-HSA-NEXT: ; implicit-def: $sgpr9
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: ; implicit-def: $sgpr3
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-HSA-NEXT: v_readfirstlane_b32 s3, v1
-; GCN-HSA-NEXT: v_readfirstlane_b32 s4, v2
-; GCN-HSA-NEXT: v_readfirstlane_b32 s5, v3
-; GCN-HSA-NEXT: s_mov_b32 s6, s5
-; GCN-HSA-NEXT: s_mov_b32 s8, s3
-; GCN-HSA-NEXT: s_lshr_b32 s10, s4, 16
-; GCN-HSA-NEXT: s_lshr_b32 s12, s2, 16
-; GCN-HSA-NEXT: s_ashr_i32 s11, s3, 31
-; GCN-HSA-NEXT: s_ashr_i32 s13, s3, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[2:3], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[4:5], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s18, s5, 31
-; GCN-HSA-NEXT: s_ashr_i32 s19, s5, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[10:11], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-HSA-NEXT: v_readfirstlane_b32 s10, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s11, v1
+; GCN-HSA-NEXT: v_readfirstlane_b32 s12, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s13, v3
+; GCN-HSA-NEXT: s_mov_b32 s2, s13
+; GCN-HSA-NEXT: s_mov_b32 s4, s11
+; GCN-HSA-NEXT: s_lshr_b32 s8, s12, 16
+; GCN-HSA-NEXT: s_lshr_b32 s6, s10, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[10:11], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[12:13], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s10, s11, 31
+; GCN-HSA-NEXT: s_ashr_i32 s11, s11, 16
+; GCN-HSA-NEXT: s_ashr_i32 s12, s13, 31
+; GCN-HSA-NEXT: s_ashr_i32 s13, s13, 16
; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GCN-HSA-NEXT: s_add_u32 s6, s0, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
-; GCN-HSA-NEXT: s_addc_u32 s7, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s7
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s6
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s13
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 32
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
@@ -6268,11 +6274,13 @@ define amdgpu_kernel void @global_sextload_v8i16_to_v8i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
; GCN-HSA-NEXT: s_endpgm
@@ -6789,80 +6797,88 @@ define amdgpu_kernel void @global_sextload_v16i16_to_v16i64(ptr addrspace(1) %ou
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr7
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr15
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr17
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr19
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr21
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s9, v3
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s7, v1
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s14, s9
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s6, v0
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s8, v2
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s23, v3
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s5, v1
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s22, v2
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s6, s23
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s4, v0
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s10, v4
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s11, v5
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s12, v6
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s13, v7
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s16, s7
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s39, s9, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s40, s9, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s18, s13
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s20, s11
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s22, s8, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s24, s6, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s26, s12, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s28, s10, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s23, s11, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s25, s11, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s27, s13, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s29, s13, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s7, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s38, s7, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s40
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s39
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s14
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s15
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[10:11], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[30:31], s[12:13], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[6:7], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[8:9], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[28:29], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[26:27], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[24:25], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[22:23], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x100000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s38
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s33
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s24, v4
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s25, v5
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s26, v6
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s27, v7
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s5
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[22:23], 0x100000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s38, s23, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s23, s23, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s27
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s12, s25
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s20, s22, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s18, s4, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s16, s26, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s14, s24, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[28:29], s[24:25], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[30:31], s[26:27], 0x100000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s22, s25, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s24, s25, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s25, s27, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s26, s27, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s27, s5, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s5, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s23
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s38
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[14:15], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[16:17], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[18:19], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[20:21], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s33
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s27
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s16
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s17
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s29
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s27
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s25
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s23
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s9
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s26
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s25
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s24
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s22
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s36
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s37
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v18, s34
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v19, s35
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v22, s30
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v23, s31
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v26, s4
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v27, s5
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s18
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s19
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s20
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s21
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s12
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s13
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v20, s10
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v21, s11
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v24, s8
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v25, s9
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v28, s6
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v29, s7
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v26, s28
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v27, s29
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s10
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s11
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s13
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s18
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s19
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v20, s16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v21, s17
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v24, s14
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v25, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v28, s4
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v29, s5
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:80
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:16
@@ -6878,6 +6894,13 @@ define amdgpu_kernel void @global_sextload_v16i16_to_v16i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-HSA-NEXT: ; implicit-def: $sgpr11
+; GCN-HSA-NEXT: ; implicit-def: $sgpr13
+; GCN-HSA-NEXT: ; implicit-def: $sgpr5
+; GCN-HSA-NEXT: ; implicit-def: $sgpr7
+; GCN-HSA-NEXT: ; implicit-def: $sgpr9
+; GCN-HSA-NEXT: ; implicit-def: $sgpr15
+; GCN-HSA-NEXT: ; implicit-def: $sgpr17
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
@@ -6887,112 +6910,113 @@ define amdgpu_kernel void @global_sextload_v16i16_to_v16i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
+; GCN-HSA-NEXT: ; implicit-def: $sgpr3
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-HSA-NEXT: v_readfirstlane_b32 s3, v1
-; GCN-HSA-NEXT: v_readfirstlane_b32 s4, v2
-; GCN-HSA-NEXT: v_readfirstlane_b32 s5, v3
-; GCN-HSA-NEXT: s_mov_b32 s6, s5
-; GCN-HSA-NEXT: s_mov_b32 s8, s3
-; GCN-HSA-NEXT: s_lshr_b32 s10, s4, 16
-; GCN-HSA-NEXT: s_lshr_b32 s12, s2, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[2:3], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[4:5], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s18, s3, 31
-; GCN-HSA-NEXT: s_ashr_i32 s19, s3, 16
-; GCN-HSA-NEXT: s_ashr_i32 s20, s5, 31
-; GCN-HSA-NEXT: s_ashr_i32 s21, s5, 16
+; GCN-HSA-NEXT: v_readfirstlane_b32 s18, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s19, v1
+; GCN-HSA-NEXT: v_readfirstlane_b32 s20, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s21, v3
+; GCN-HSA-NEXT: s_mov_b32 s10, s21
+; GCN-HSA-NEXT: s_mov_b32 s12, s19
+; GCN-HSA-NEXT: s_lshr_b32 s16, s20, 16
+; GCN-HSA-NEXT: s_lshr_b32 s14, s18, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[18:19], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[20:21], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s2, s19, 31
+; GCN-HSA-NEXT: s_ashr_i32 s4, s19, 16
+; GCN-HSA-NEXT: s_ashr_i32 s6, s21, 31
+; GCN-HSA-NEXT: s_ashr_i32 s8, s21, 16
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s2, v4
-; GCN-HSA-NEXT: v_readfirstlane_b32 s3, v5
-; GCN-HSA-NEXT: v_readfirstlane_b32 s4, v6
-; GCN-HSA-NEXT: v_readfirstlane_b32 s5, v7
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s21
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s15
-; GCN-HSA-NEXT: s_mov_b32 s14, s5
-; GCN-HSA-NEXT: s_mov_b32 s16, s3
-; GCN-HSA-NEXT: s_lshr_b32 s18, s4, 16
-; GCN-HSA-NEXT: s_lshr_b32 s20, s2, 16
-; GCN-HSA-NEXT: s_ashr_i32 s15, s3, 31
-; GCN-HSA-NEXT: s_ashr_i32 s17, s3, 16
-; GCN-HSA-NEXT: s_ashr_i32 s19, s5, 31
-; GCN-HSA-NEXT: s_ashr_i32 s21, s5, 16
+; GCN-HSA-NEXT: v_readfirstlane_b32 s18, v4
+; GCN-HSA-NEXT: v_readfirstlane_b32 s19, v5
+; GCN-HSA-NEXT: v_readfirstlane_b32 s20, v6
+; GCN-HSA-NEXT: v_readfirstlane_b32 s21, v7
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s2
+; GCN-HSA-NEXT: s_mov_b32 s2, s21
+; GCN-HSA-NEXT: s_mov_b32 s4, s19
+; GCN-HSA-NEXT: s_lshr_b32 s8, s20, 16
+; GCN-HSA-NEXT: s_lshr_b32 s6, s18, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[2:3], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[4:5], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[20:21], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[18:19], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[16:17], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[14:15], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s25
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s23
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[18:19], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[20:21], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s18, s19, 31
+; GCN-HSA-NEXT: s_ashr_i32 s19, s19, 16
+; GCN-HSA-NEXT: s_ashr_i32 s20, s21, 31
+; GCN-HSA-NEXT: s_ashr_i32 s21, s21, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
; GCN-HSA-NEXT: s_add_u32 s10, s0, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s15
; GCN-HSA-NEXT: s_addc_u32 s11, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s10
-; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s19
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x70
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s13
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[4:7]
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s21
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x50
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s20
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[14:17]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s5
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[18:21]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s17
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s25
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s9
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[22:25]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
@@ -7901,176 +7925,193 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:32
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:16
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr23
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr27
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr15
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr17
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr19
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr21
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr25
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr35
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr39
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr43
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr31
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr37
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr41
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr47
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr45
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(3)
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s15, v3
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s13, v1
-; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s10, v8
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s11, v9
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s20, v10
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s21, v11
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s36, s15
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s38, s13
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s26, s21
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s30, s11
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s52, s20, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s54, s10, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[10:11], 0x100000
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s57, s11, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s59, s11, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s60, s21, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s61, s21, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[20:21], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[36:37], 0x100000
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s12, v0
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s20
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s21
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[38:39], 0x100000
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s16, v4
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s20
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s15, 16
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s14, v2
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s19, v7
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s20
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s15, 31
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s17, v5
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s22, s19
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s20
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s13, 16
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s18, v6
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s24, s17
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s64, s19, 31
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s20
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s13, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s65, s19, 16
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s49, v1
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s22, s49
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s51, v3
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x100000
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s62, s17, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s63, s17, 16
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s21
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s20
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x100000
+; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(2)
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s28, v4
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s22
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s22, s51, 16
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s50, v2
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s53, v7
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s26, s51
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s22
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s22, s51, 31
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s29, v5
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s53
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s22
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s22, s49, 16
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s48, v0
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s52, v6
+; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s12, v8
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s13, v9
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s54, v10
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s55, v11
+; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s56, v12
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s57, v13
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s58, v14
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s59, v15
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s14, s29
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s26
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s27
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s63, s53, 31
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s22
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s22, s49, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s64, s53, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s16, s55
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s18, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s20, s59
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s24, s57
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s38, s54, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s36, s12, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s34, s58, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s30, s56, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[56:57], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[58:59], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[12:13], 0x100000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s57, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s56, s57, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s57, s59, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s58, s59, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s59, s13, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s60, s13, 16
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s61, s55, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s62, s55, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[54:55], 0x100000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s54, s29, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s55, s29, 16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s23
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s22
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:208
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(1)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s22
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s23
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s65
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s64
-; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(2)
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s35, v15
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s11
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s64
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s63
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s24
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s25
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s63
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s62
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s29, v13
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s40, s35
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s55
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s54
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s26
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s27
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s61
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s60
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s42, s29
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s53, s35, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s55, s35, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s17
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s62
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s61
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s30
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s31
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s59
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s57
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s44, s14, 16
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s29, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s51, s29, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s18
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s19
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s60
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s59
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s46, s50, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s42, s52, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s40
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s41
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s55
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s53
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s46, s12, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[38:39], s[14:15], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s20
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s21
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s58
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s57
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s44, s48, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s40, s28, 16
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[34:35], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[38:39], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[38:39], s[42:43], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[42:43], s[46:47], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s42
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s43
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s51
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s24
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s25
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s56
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s33
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s34, v14
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s48, s18, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[12:13], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[30:31], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[30:31], s[36:37], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[40:41], 0x100000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[40:41], s[44:45], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s38
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s39
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s44
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s45
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s28, v12
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s50, s16, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s56, s34, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[34:35], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[18:19], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s50
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s51
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s42
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s43
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:224
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s36
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s37
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s46
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s47
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s58, s28, 16
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[28:29], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x100000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[28:29], s[50:51], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s48
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s49
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s40
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s41
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x100000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:192
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s34
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s35
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s48
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s49
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[52:53], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s52
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s53
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s38
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s39
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s16
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s17
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s28
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s29
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[54:55], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s28
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s29
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s36
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s37
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s11
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s20
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s21
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[56:57], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s13
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s34
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s35
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s9
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s18
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s19
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[58:59], 0x100000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s30
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s31
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s26
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s27
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s12
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s13
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s22
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s23
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
@@ -8080,162 +8121,178 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GCN-HSA-NEXT: ; implicit-def: $sgpr9
+; GCN-HSA-NEXT: ; implicit-def: $sgpr19
+; GCN-HSA-NEXT: ; implicit-def: $sgpr23
+; GCN-HSA-NEXT: ; implicit-def: $sgpr25
+; GCN-HSA-NEXT: ; implicit-def: $sgpr7
+; GCN-HSA-NEXT: ; implicit-def: $sgpr11
+; GCN-HSA-NEXT: ; implicit-def: $sgpr13
+; GCN-HSA-NEXT: ; implicit-def: $sgpr15
+; GCN-HSA-NEXT: ; implicit-def: $sgpr27
+; GCN-HSA-NEXT: ; implicit-def: $sgpr21
+; GCN-HSA-NEXT: ; implicit-def: $sgpr41
+; GCN-HSA-NEXT: ; implicit-def: $sgpr37
+; GCN-HSA-NEXT: ; implicit-def: $sgpr43
+; GCN-HSA-NEXT: ; implicit-def: $sgpr45
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s4, s2, 48
-; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s4, s2, 32
-; GCN-HSA-NEXT: flat_load_dwordx4 v[16:19], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s5, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
-; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: flat_load_dwordx4 v[2:5], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: ; implicit-def: $sgpr3
+; GCN-HSA-NEXT: ; implicit-def: $sgpr5
; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s7, v13
-; GCN-HSA-NEXT: v_readfirstlane_b32 s9, v15
-; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v14
-; GCN-HSA-NEXT: s_mov_b32 s10, s9
-; GCN-HSA-NEXT: s_mov_b32 s12, s7
+; GCN-HSA-NEXT: v_readfirstlane_b32 s35, v11
+; GCN-HSA-NEXT: v_readfirstlane_b32 s30, v8
+; GCN-HSA-NEXT: v_readfirstlane_b32 s31, v9
+; GCN-HSA-NEXT: s_mov_b32 s8, s35
+; GCN-HSA-NEXT: v_readfirstlane_b32 s34, v10
+; GCN-HSA-NEXT: s_mov_b32 s18, s31
+; GCN-HSA-NEXT: s_lshr_b32 s20, s30, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[30:31], 0x100000
; GCN-HSA-NEXT: s_waitcnt vmcnt(2)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s19, v19
-; GCN-HSA-NEXT: v_readfirstlane_b32 s6, v12
-; GCN-HSA-NEXT: s_lshr_b32 s16, s8, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[8:9], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s49, s9, 31
-; GCN-HSA-NEXT: s_ashr_i32 s50, s9, 16
-; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v16
-; GCN-HSA-NEXT: v_readfirstlane_b32 s9, v17
-; GCN-HSA-NEXT: v_readfirstlane_b32 s18, v18
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
-; GCN-HSA-NEXT: s_mov_b32 s20, s19
-; GCN-HSA-NEXT: s_lshr_b32 s14, s6, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s33, s7, 31
-; GCN-HSA-NEXT: s_ashr_i32 s48, s7, 16
-; GCN-HSA-NEXT: s_mov_b32 s22, s9
-; GCN-HSA-NEXT: s_lshr_b32 s24, s18, 16
-; GCN-HSA-NEXT: s_lshr_b32 s28, s8, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s51, s9, 31
-; GCN-HSA-NEXT: s_ashr_i32 s52, s9, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s13
+; GCN-HSA-NEXT: v_readfirstlane_b32 s30, v12
+; GCN-HSA-NEXT: s_bfe_i64 s[46:47], s[8:9], 0x100000
+; GCN-HSA-NEXT: s_lshr_b32 s24, s34, 16
+; GCN-HSA-NEXT: s_ashr_i32 s33, s31, 31
+; GCN-HSA-NEXT: s_ashr_i32 s54, s31, 16
+; GCN-HSA-NEXT: v_readfirstlane_b32 s31, v13
+; GCN-HSA-NEXT: v_readfirstlane_b32 s38, v14
+; GCN-HSA-NEXT: v_readfirstlane_b32 s39, v15
+; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x100000
+; GCN-HSA-NEXT: s_lshr_b32 s22, s30, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s46
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s47
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s9, v9
-; GCN-HSA-NEXT: v_readfirstlane_b32 s10, v10
-; GCN-HSA-NEXT: v_readfirstlane_b32 s11, v11
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[20:21], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[16:17], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[18:19], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s53, s19, 31
-; GCN-HSA-NEXT: s_ashr_i32 s54, s19, 16
-; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v8
-; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[28:29], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[24:25], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[40:41], s[22:23], 0x100000
-; GCN-HSA-NEXT: s_mov_b32 s22, s11
-; GCN-HSA-NEXT: s_mov_b32 s24, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s12
-; GCN-HSA-NEXT: s_ashr_i32 s57, s11, 31
-; GCN-HSA-NEXT: s_ashr_i32 s58, s11, 16
-; GCN-HSA-NEXT: s_lshr_b32 s12, s10, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[10:11], 0x100000
+; GCN-HSA-NEXT: v_readfirstlane_b32 s46, v6
+; GCN-HSA-NEXT: v_readfirstlane_b32 s47, v7
+; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[34:35], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s55, s35, 31
+; GCN-HSA-NEXT: s_ashr_i32 s56, s35, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[24:25], 0x100000
+; GCN-HSA-NEXT: s_mov_b32 s6, s39
+; GCN-HSA-NEXT: s_lshr_b32 s26, s38, 16
+; GCN-HSA-NEXT: s_ashr_i32 s59, s39, 31
+; GCN-HSA-NEXT: s_ashr_i32 s60, s39, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[38:39], 0x100000
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s19
+; GCN-HSA-NEXT: v_readfirstlane_b32 s38, v4
+; GCN-HSA-NEXT: v_readfirstlane_b32 s39, v5
+; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[22:23], 0x100000
+; GCN-HSA-NEXT: s_mov_b32 s2, s47
+; GCN-HSA-NEXT: s_lshr_b32 s14, s46, 16
+; GCN-HSA-NEXT: s_ashr_i32 s63, s47, 31
+; GCN-HSA-NEXT: s_ashr_i32 s64, s47, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[46:47], 0x100000
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s10, v2
-; GCN-HSA-NEXT: v_readfirstlane_b32 s11, v3
-; GCN-HSA-NEXT: v_readfirstlane_b32 s36, v4
-; GCN-HSA-NEXT: v_readfirstlane_b32 s37, v5
-; GCN-HSA-NEXT: s_lshr_b32 s20, s8, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[24:25], 0x100000
-; GCN-HSA-NEXT: s_mov_b32 s44, s11
-; GCN-HSA-NEXT: s_lshr_b32 s12, s10, 16
-; GCN-HSA-NEXT: s_mov_b32 s46, s37
-; GCN-HSA-NEXT: s_lshr_b32 s24, s36, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s55, s9, 31
-; GCN-HSA-NEXT: s_ashr_i32 s56, s9, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s13
+; GCN-HSA-NEXT: v_readfirstlane_b32 s46, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s47, v1
+; GCN-HSA-NEXT: v_readfirstlane_b32 s50, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s51, v3
+; GCN-HSA-NEXT: s_mov_b32 s10, s31
+; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
+; GCN-HSA-NEXT: s_mov_b32 s4, s39
+; GCN-HSA-NEXT: s_lshr_b32 s12, s38, 16
+; GCN-HSA-NEXT: s_mov_b32 s40, s51
+; GCN-HSA-NEXT: s_mov_b32 s36, s47
+; GCN-HSA-NEXT: s_lshr_b32 s42, s50, 16
+; GCN-HSA-NEXT: s_lshr_b32 s44, s46, 16
; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[42:43], s[22:23], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s59, s11, 31
-; GCN-HSA-NEXT: s_ashr_i32 s60, s11, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
-; GCN-HSA-NEXT: s_ashr_i32 s61, s37, 31
-; GCN-HSA-NEXT: s_ashr_i32 s62, s37, 16
-; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[36:37], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[36:37], s[44:45], 0x100000
-; GCN-HSA-NEXT: s_bfe_i64 s[44:45], s[46:47], 0x100000
-; GCN-HSA-NEXT: s_add_u32 s46, s0, 48
-; GCN-HSA-NEXT: s_addc_u32 s47, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s47
-; GCN-HSA-NEXT: s_add_u32 s46, s0, 16
-; GCN-HSA-NEXT: s_addc_u32 s47, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s47
-; GCN-HSA-NEXT: s_add_u32 s46, s0, 0xf0
-; GCN-HSA-NEXT: s_addc_u32 s47, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s40
-; GCN-HSA-NEXT: s_add_u32 s40, s0, 0xd0
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s41
-; GCN-HSA-NEXT: s_addc_u32 s41, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v29, s40
-; GCN-HSA-NEXT: v_mov_b32_e32 v30, s41
-; GCN-HSA-NEXT: s_add_u32 s40, s0, 0xb0
-; GCN-HSA-NEXT: s_addc_u32 s41, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s50
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s49
-; GCN-HSA-NEXT: v_mov_b32_e32 v22, s38
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[30:31], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s57, s31, 31
+; GCN-HSA-NEXT: s_ashr_i32 s58, s31, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[26:27], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[48:49], s[10:11], 0x100000
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GCN-HSA-NEXT: s_ashr_i32 s61, s39, 31
+; GCN-HSA-NEXT: s_ashr_i32 s62, s39, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[38:39], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[12:13], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[14:15], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[4:5], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[52:53], s[2:3], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s65, s47, 31
+; GCN-HSA-NEXT: s_ashr_i32 s66, s47, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[46:47], 0x100000
+; GCN-HSA-NEXT: s_ashr_i32 s46, s51, 31
+; GCN-HSA-NEXT: s_ashr_i32 s47, s51, 16
+; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[50:51], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[44:45], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[42:43], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x100000
+; GCN-HSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x100000
+; GCN-HSA-NEXT: s_add_u32 s42, s0, 48
+; GCN-HSA-NEXT: s_addc_u32 s43, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s43
+; GCN-HSA-NEXT: s_add_u32 s42, s0, 16
+; GCN-HSA-NEXT: s_addc_u32 s43, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s43
+; GCN-HSA-NEXT: s_add_u32 s42, s0, 0xf0
+; GCN-HSA-NEXT: s_addc_u32 s43, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s43
+; GCN-HSA-NEXT: s_add_u32 s42, s0, 0xd0
+; GCN-HSA-NEXT: s_addc_u32 s43, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v28, s43
+; GCN-HSA-NEXT: s_add_u32 s42, s0, 0xb0
+; GCN-HSA-NEXT: s_addc_u32 s43, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s56
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s55
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s38
; GCN-HSA-NEXT: s_add_u32 s38, s0, 0x90
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v23, s39
+; GCN-HSA-NEXT: flat_store_dwordx4 v[21:22], v[12:15]
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s39
; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s46
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v29, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s54
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s33
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s60
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s59
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s39
; GCN-HSA-NEXT: s_add_u32 s38, s0, 0x70
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s47
-; GCN-HSA-NEXT: v_mov_b32_e32 v31, s40
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s33
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s54
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s53
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s48
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s49
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s52
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s53
+; GCN-HSA-NEXT: v_mov_b32_e32 v30, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s58
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s57
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s64
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s63
+; GCN-HSA-NEXT: v_mov_b32_e32 v22, s62
+; GCN-HSA-NEXT: flat_store_dwordx4 v[23:24], v[8:11]
+; GCN-HSA-NEXT: v_mov_b32_e32 v23, s61
+; GCN-HSA-NEXT: flat_store_dwordx4 v[25:26], v[4:7]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[27:28], v[0:3]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[29:30], v[16:19]
+; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[20:23]
; GCN-HSA-NEXT: s_addc_u32 s39, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s42
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s43
-; GCN-HSA-NEXT: v_mov_b32_e32 v32, s41
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s52
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s51
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s58
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s57
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s56
-; GCN-HSA-NEXT: flat_store_dwordx4 v[25:26], v[6:9]
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s55
-; GCN-HSA-NEXT: flat_store_dwordx4 v[27:28], v[10:13]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[29:30], v[14:17]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[31:32], v[18:21]
-; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[22:25]
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s44
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s45
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s62
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s61
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s40
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s41
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s46
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s39
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8244,79 +8301,81 @@ define amdgpu_kernel void @global_sextload_v32i16_to_v32i64(ptr addrspace(1) %ou
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s37
; GCN-HSA-NEXT: s_addc_u32 s37, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s60
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s59
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s66
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s65
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s37
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s4
-; GCN-HSA-NEXT: s_add_u32 s4, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s5
-; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s27
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GCN-HSA-NEXT: s_add_u32 s28, s0, 32
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GCN-HSA-NEXT: s_addc_u32 s29, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s28
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s29
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xe0
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
-; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xc0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GCN-HSA-NEXT: s_add_u32 s16, s0, 0xe0
+; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-HSA-NEXT: s_addc_u32 s17, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s31
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s17
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xa0
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GCN-HSA-NEXT: s_add_u32 s8, s0, 0xc0
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GCN-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s18
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s19
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GCN-HSA-NEXT: s_add_u32 s8, s0, 0xa0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s28
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s26
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s27
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
-; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s9
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
-; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GCN-HSA-NEXT: s_nop 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GCN-HSA-NEXT: s_add_u32 s6, s0, 0x80
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GCN-HSA-NEXT: s_addc_u32 s7, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GCN-HSA-NEXT: s_add_u32 s6, s0, 0x60
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GCN-HSA-NEXT: s_addc_u32 s7, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s24
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s25
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
index f074770ad6e92..80212f4fc5df9 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll
@@ -6068,40 +6068,43 @@ define amdgpu_kernel void @global_sextload_v8i8_to_v8i64(ptr addrspace(1) %out,
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-SI-NEXT: s_mov_b32 s7, 0
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, s7
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s15, s7
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s17, s7
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s5, v1
; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s4, v0
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s6, s5, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s8, s5, 8
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s5
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s14, s5, 8
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s16, s5
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s12, s4, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s14, s4, 24
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s16, s4, 8
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s17, s5, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s5, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s10, s4, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s8, s4, 8
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s20, s5, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s21, s5, 24
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[4:5], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[16:17], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[8:9], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[10:11], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[12:13], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[16:17], 0x80000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s20
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s17
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s21
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s20
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s18
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s19
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s10
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s11
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s8
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s9
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s12
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s13
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s14
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s13
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s14
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s10
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s11
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s9
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s4
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s5
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
@@ -6116,63 +6119,66 @@ define amdgpu_kernel void @global_sextload_v8i8_to_v8i64(ptr addrspace(1) %out,
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr5
+; GCN-HSA-NEXT: ; implicit-def: $sgpr7
+; GCN-HSA-NEXT: ; implicit-def: $sgpr9
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; GCN-HSA-NEXT: s_mov_b32 s3, 0
-; GCN-HSA-NEXT: s_mov_b32 s5, s3
-; GCN-HSA-NEXT: s_mov_b32 s7, s3
+; GCN-HSA-NEXT: s_mov_b32 s11, s3
+; GCN-HSA-NEXT: s_mov_b32 s13, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s8, v0
-; GCN-HSA-NEXT: v_readfirstlane_b32 s9, v1
-; GCN-HSA-NEXT: s_lshr_b32 s2, s9, 16
-; GCN-HSA-NEXT: s_lshr_b32 s4, s9, 8
-; GCN-HSA-NEXT: s_mov_b32 s6, s9
-; GCN-HSA-NEXT: s_lshr_b32 s10, s8, 16
-; GCN-HSA-NEXT: s_lshr_b32 s12, s8, 24
-; GCN-HSA-NEXT: s_lshr_b32 s14, s8, 8
-; GCN-HSA-NEXT: s_ashr_i32 s15, s9, 31
-; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[8:9], 0x80000
-; GCN-HSA-NEXT: s_ashr_i32 s18, s9, 24
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[14:15], 0x80000
+; GCN-HSA-NEXT: v_readfirstlane_b32 s14, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s15, v1
+; GCN-HSA-NEXT: s_lshr_b32 s2, s15, 16
+; GCN-HSA-NEXT: s_lshr_b32 s10, s15, 8
+; GCN-HSA-NEXT: s_mov_b32 s12, s15
+; GCN-HSA-NEXT: s_lshr_b32 s8, s14, 16
+; GCN-HSA-NEXT: s_lshr_b32 s6, s14, 24
+; GCN-HSA-NEXT: s_lshr_b32 s4, s14, 8
+; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[14:15], 0x80000
+; GCN-HSA-NEXT: s_ashr_i32 s14, s15, 31
+; GCN-HSA-NEXT: s_ashr_i32 s15, s15, 24
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s14
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s6
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s7
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s12
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s11
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s13
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s16
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s5
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[4:7]
; GCN-HSA-NEXT: s_endpgm
@@ -6191,39 +6197,43 @@ define amdgpu_kernel void @global_sextload_v8i8_to_v8i64(ptr addrspace(1) %out,
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr15
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s17, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s5, v1
; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s4, v0
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s5, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s5, 8
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s5
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s5, 8
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s16, s5
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s4, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s4, 24
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s16, s4, 8
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s17, s5, 31
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s20, s5, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s4, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s4, 8
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s20, s5, 31
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s21, s5, 24
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[4:5], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[16:17], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[8:9], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[10:11], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[12:13], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[16:17], 0x80000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s20
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s17
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s21
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s20
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s18
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s19
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v8, s8
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, s9
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v10, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v12, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, s13
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s15
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v8, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v10, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, s15
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v12, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, s11
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s5
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
@@ -6713,81 +6723,89 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s13, 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s15, s13
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s17, s13
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s19, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, 0
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr19
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr21
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr23
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s25, s11
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s27, s11
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s29, s11
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr15
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr7
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr17
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s7, v3
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s6, v2
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s12, s7, 16
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s31, v3
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s30, v2
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s10, s31, 16
; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s4, v0
; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s14, s7, 8
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s20, s7
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s22, s6, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s24, s6, 24
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s26, s6, 8
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s35, s7, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s38, s7, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s24, s31, 8
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s12, s31
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s22, s30, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s20, s30, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s18, s30, 8
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[30:31], 0x80000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s38, s31, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s31, s31, 24
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s26, s5, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s28, s5, 8
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s14, s5
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s16, s4, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s8, s4, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s6, s4, 8
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s16, s5, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s18, s5, 8
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s28, s5
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s10, s4, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s30, s4, 24
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s34, s4, 8
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[6:7], 0x80000
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s31, s5, 31
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s38
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s35
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s12
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s13
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[4:5], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s31
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s38
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s11
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x80000
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s30, s5, 31
; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s5, 24
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[34:35], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[30:31], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[6:7], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[16:17], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[28:29], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s36
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s37
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s20
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s21
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s14
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s13
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s24
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s25
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s22
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s23
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s24
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s25
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s26
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s27
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s20
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s21
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s18
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s19
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s33
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s31
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s8
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s9
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s16
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s17
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s30
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s34
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s35
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s26
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s27
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:96
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s28
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s29
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v18, s18
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v19, s19
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s14
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v18, s16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v19, s17
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s11
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s9
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s6
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s7
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s4
@@ -6805,58 +6823,66 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr5
+; GCN-HSA-NEXT: ; implicit-def: $sgpr7
+; GCN-HSA-NEXT: ; implicit-def: $sgpr9
+; GCN-HSA-NEXT: ; implicit-def: $sgpr11
+; GCN-HSA-NEXT: ; implicit-def: $sgpr13
+; GCN-HSA-NEXT: ; implicit-def: $sgpr15
+; GCN-HSA-NEXT: ; implicit-def: $sgpr17
+; GCN-HSA-NEXT: ; implicit-def: $sgpr21
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; GCN-HSA-NEXT: flat_load_dwordx4 v[2:5], v[0:1]
; GCN-HSA-NEXT: s_mov_b32 s3, 0
-; GCN-HSA-NEXT: s_mov_b32 s5, s3
-; GCN-HSA-NEXT: s_mov_b32 s7, s3
-; GCN-HSA-NEXT: s_mov_b32 s9, s3
+; GCN-HSA-NEXT: s_mov_b32 s19, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s10, v0
-; GCN-HSA-NEXT: v_readfirstlane_b32 s11, v1
-; GCN-HSA-NEXT: v_readfirstlane_b32 s12, v2
-; GCN-HSA-NEXT: v_readfirstlane_b32 s13, v3
-; GCN-HSA-NEXT: s_lshr_b32 s2, s13, 16
-; GCN-HSA-NEXT: s_lshr_b32 s4, s13, 8
-; GCN-HSA-NEXT: s_mov_b32 s14, s13
-; GCN-HSA-NEXT: s_lshr_b32 s16, s12, 16
-; GCN-HSA-NEXT: s_lshr_b32 s18, s12, 24
-; GCN-HSA-NEXT: s_lshr_b32 s20, s12, 8
-; GCN-HSA-NEXT: s_ashr_i32 s15, s13, 31
-; GCN-HSA-NEXT: s_ashr_i32 s17, s13, 24
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[10:11], 0x80000
-; GCN-HSA-NEXT: s_lshr_b32 s6, s11, 16
-; GCN-HSA-NEXT: s_lshr_b32 s8, s11, 8
-; GCN-HSA-NEXT: s_mov_b32 s22, s11
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
-; GCN-HSA-NEXT: s_lshr_b32 s12, s10, 16
-; GCN-HSA-NEXT: s_ashr_i32 s13, s11, 31
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
-; GCN-HSA-NEXT: s_ashr_i32 s15, s11, 24
+; GCN-HSA-NEXT: v_readfirstlane_b32 s22, v4
+; GCN-HSA-NEXT: v_readfirstlane_b32 s23, v5
+; GCN-HSA-NEXT: s_lshr_b32 s2, s23, 16
+; GCN-HSA-NEXT: s_lshr_b32 s18, s23, 8
+; GCN-HSA-NEXT: s_mov_b32 s4, s23
+; GCN-HSA-NEXT: s_lshr_b32 s20, s22, 16
+; GCN-HSA-NEXT: s_lshr_b32 s16, s22, 24
+; GCN-HSA-NEXT: s_lshr_b32 s14, s22, 8
+; GCN-HSA-NEXT: s_ashr_i32 s6, s23, 31
+; GCN-HSA-NEXT: s_ashr_i32 s8, s23, 24
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GCN-HSA-NEXT: v_readfirstlane_b32 s22, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s23, v3
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GCN-HSA-NEXT: s_ashr_i32 s8, s23, 31
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s6
+; GCN-HSA-NEXT: s_ashr_i32 s6, s23, 24
+; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[22:23], 0x80000
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s8
; GCN-HSA-NEXT: v_mov_b32_e32 v8, s24
-; GCN-HSA-NEXT: s_lshr_b32 s24, s10, 24
-; GCN-HSA-NEXT: s_lshr_b32 s10, s10, 8
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s13
; GCN-HSA-NEXT: v_mov_b32_e32 v9, s25
+; GCN-HSA-NEXT: s_mov_b32 s25, s3
+; GCN-HSA-NEXT: s_lshr_b32 s24, s23, 16
+; GCN-HSA-NEXT: s_mov_b32 s6, s23
+; GCN-HSA-NEXT: s_lshr_b32 s12, s22, 16
+; GCN-HSA-NEXT: s_lshr_b32 s10, s22, 24
+; GCN-HSA-NEXT: s_lshr_b32 s8, s22, 8
+; GCN-HSA-NEXT: s_lshr_b32 s22, s23, 8
+; GCN-HSA-NEXT: s_mov_b32 s23, s3
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
; GCN-HSA-NEXT: v_mov_b32_e32 v2, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x70
@@ -6872,20 +6898,20 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x50
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s5
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s18
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s19
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 64
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[2:5]
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s18
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s19
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s16
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s17
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s24
; GCN-HSA-NEXT: v_mov_b32_e32 v11, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v10, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
@@ -6893,29 +6919,29 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s25
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
; GCN-HSA-NEXT: s_add_u32 s0, s0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s23
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s8
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s9
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s7
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s23
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s15
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[12:15]
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s12
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s13
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s24
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s25
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s10
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s8
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s9
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
; GCN-HSA-NEXT: s_endpgm
@@ -6931,79 +6957,89 @@ define amdgpu_kernel void @global_sextload_v16i8_to_v16i64(ptr addrspace(1) %out
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s17, 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s19, s17
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s15, 0
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr17
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr21
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr23
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr25
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr27
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s29, s15
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr7
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr19
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s9, v3
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s8, v2
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s16, s9, 16
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s31, v3
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s30, v2
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s31, 16
; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s4, v0
; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s20, s9, 8
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s22, s9
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s8, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s26, s8, 24
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s8, 8
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s35, s9, 31
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s38, s9, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s26, s31, 8
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s16, s31
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s30, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s22, s30, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s20, s30, 8
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[36:37], s[30:31], 0x80000
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s38, s31, 31
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s31, s31, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s5, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s5, 8
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s5
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s4, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s4, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s4, 8
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s5, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s5, 8
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s14, s5
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s4, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s4, 24
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s4, 8
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[36:37], s[8:9], 0x80000
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s31, s5, 31
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s38
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x80000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s31
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s38
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s15
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x80000
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s30, s5, 31
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s33, s5, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[34:35], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[30:31], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[6:7], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[8:9], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[12:13], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[10:11], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[18:19], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[28:29], 0x80000
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s36
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s37
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s22
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s23
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v16, s20
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v17, s21
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s17
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v16, s26
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v17, s27
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s28
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s20
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s25
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s26
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s27
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s29
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s22
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s23
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s21
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v10, s33
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, s31
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v12, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, s30
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v12, s34
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, s35
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v8, s18
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, s19
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:96
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v18, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v16, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v17, s15
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v19, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v18, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v16, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v17, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v19, s11
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s5
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48
@@ -7857,178 +7893,194 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-NOHSA-SI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
-; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16
-; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s29, 0
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s27, s29
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s23, s29
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s11, s29
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s7, s29
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s29
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s13, s29
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s15, s29
+; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s13, 0
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s41, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s43, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s27, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s17, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s19, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s21, s13
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s23, s13
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr15
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr39
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr35
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr37
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr29
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr47
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr7
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr49
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr9
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s43, v3
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s28, s43, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s22, s5, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s10, s5, 8
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s6, s43, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s8, s43, 24
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s45, v7
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s12, s45, 16
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s14, s45
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s25, v5
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s44, v6
+; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s4, v0
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s42, v2
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s26, s43, 8
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s12, s43
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s30, s5
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s5, v1
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s40, s45, 8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s13
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[14:15], 0x80000
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s38, s44, 16
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s10, s25
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s6, s45, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s8, s45, 24
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s13
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[40:41], 0x80000
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s30, v2
+; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s31, v3
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s36, s44, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s26, s25, 8
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s8
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s6
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s28
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s29
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s13
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[38:39], 0x80000
; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s38, s42, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s36, s42, 24
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s34, s42, 8
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s16, s4, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s18, s4, 24
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[44:45], s[12:13], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s22
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s23
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[30:31], 0x80000
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s34, s44, 8
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s42, s25, 16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s13
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[36:37], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s10
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s10, s5, 24
-; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(1)
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s11
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[26:27], 0x80000
; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s24, v4
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s25, v5
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s21, v7
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s40, s4, 8
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v8, s44
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, s45
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, s26
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v11, s27
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s22
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s23
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s11
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s13
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[34:35], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[42:43], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s10
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s10, s25, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s28, s24, 16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s44
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s44, s24, 24
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s40, s30, 24
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v16, s34
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, s35
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s34, s4, 8
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v18, s10
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s10, s5, 31
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
-; GCN-NOHSA-SI-NEXT: v_readfirstlane_b32 s20, v6
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s6, s21, 16
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v4, s42
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s43
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s12, s25, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s14, s25, 8
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v12, s38
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v13, s39
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s38, s25
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v14, s36
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v15, s37
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s36, s24, 16
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s34
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s35
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s34, s24, 24
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s10, s25, 31
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr35
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr41
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v5, s45
; GCN-NOHSA-SI-NEXT: s_lshr_b32 s46, s24, 8
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s25, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s43, s25, 24
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[24:25], 0x80000
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s38, s30, 8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s11
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v19, s10
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[24:25], s[4:5], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[34:35], 0x80000
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr39
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[40:41], 0x80000
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr45
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[40:41], s[44:45], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s16, s31, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s18, s31, 8
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s6, s31
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s48, s30, 16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v6, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v7, s13
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s43, s31, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s50, s31, 24
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[30:31], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[30:31], s[38:39], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[38:39], s[46:47], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:224
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:208
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:192
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:176
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s16
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s17
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s18
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s19
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s8, s21, 8
-; GCN-NOHSA-SI-NEXT: s_mov_b32 s42, s21
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s45, s21, 31
-; GCN-NOHSA-SI-NEXT: s_ashr_i32 s47, s21, 24
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s28
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s29
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s40
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s41
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s24
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s25
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s40
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s41
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s28, s20, 16
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s44, s20, 24
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[10:11], s[34:35], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[34:35], s[38:39], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[38:39], s[42:43], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s38
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s39
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s6
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s47
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s45
-; GCN-NOHSA-SI-NEXT: s_lshr_b32 s26, s20, 8
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[30:31], s[36:37], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[44:45], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s16
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s17
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s50
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s43
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[36:37], s[48:49], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s38
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s39
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s8
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s9
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s18
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s19
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s20, s5, 16
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s28
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s29
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s36
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s37
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s36
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s37
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s34
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s35
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s22, s5, 8
+; GCN-NOHSA-SI-NEXT: s_mov_b32 s8, s5
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s33, s5, 31
+; GCN-NOHSA-SI-NEXT: s_ashr_i32 s42, s5, 24
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s20
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s21
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s26
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s27
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s26
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s27
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s30
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s31
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s14, s4, 16
+; GCN-NOHSA-SI-NEXT: s_lshr_b32 s12, s4, 24
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-SI-NEXT: ; implicit-def: $sgpr15
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s12
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s13
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s43
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s20
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s21
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s42
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s33
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s34
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s35
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s15
-; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[46:47], 0x80000
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s9
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s22
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s23
+; GCN-NOHSA-SI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s30
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s31
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s10
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s11
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s15
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s12
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s13
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s22
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s23
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s4
-; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v2, s10
+; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v3, s11
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NOHSA-SI-NEXT: s_endpgm
;
@@ -8036,190 +8088,206 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GCN-HSA-NEXT: s_add_i32 s12, s12, s17
-; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-HSA-NEXT: s_mov_b32 flat_scratch_lo, s13
-; GCN-HSA-NEXT: s_mov_b32 s5, 0
+; GCN-HSA-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GCN-HSA-NEXT: ; implicit-def: $sgpr7
+; GCN-HSA-NEXT: ; implicit-def: $sgpr5
+; GCN-HSA-NEXT: ; implicit-def: $sgpr9
+; GCN-HSA-NEXT: ; implicit-def: $sgpr11
+; GCN-HSA-NEXT: ; implicit-def: $sgpr13
+; GCN-HSA-NEXT: ; implicit-def: $sgpr15
+; GCN-HSA-NEXT: ; implicit-def: $sgpr17
+; GCN-HSA-NEXT: ; implicit-def: $sgpr19
+; GCN-HSA-NEXT: ; implicit-def: $sgpr27
+; GCN-HSA-NEXT: ; implicit-def: $sgpr23
+; GCN-HSA-NEXT: ; implicit-def: $sgpr21
+; GCN-HSA-NEXT: ; implicit-def: $sgpr35
+; GCN-HSA-NEXT: ; implicit-def: $sgpr39
+; GCN-HSA-NEXT: ; implicit-def: $sgpr45
+; GCN-HSA-NEXT: ; implicit-def: $sgpr47
+; GCN-HSA-NEXT: ; implicit-def: $sgpr49
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
-; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
+; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
-; GCN-HSA-NEXT: s_mov_b32 s9, s5
-; GCN-HSA-NEXT: s_mov_b32 s3, s5
-; GCN-HSA-NEXT: s_mov_b32 s7, s5
-; GCN-HSA-NEXT: s_mov_b32 s31, s5
-; GCN-HSA-NEXT: s_mov_b32 s27, s5
-; GCN-HSA-NEXT: s_mov_b32 s15, s5
-; GCN-HSA-NEXT: s_mov_b32 s11, s5
+; GCN-HSA-NEXT: s_mov_b32 s3, 0
+; GCN-HSA-NEXT: s_mov_b32 s29, s3
+; GCN-HSA-NEXT: s_mov_b32 s43, s3
+; GCN-HSA-NEXT: s_mov_b32 s41, s3
+; GCN-HSA-NEXT: s_mov_b32 s51, s3
+; GCN-HSA-NEXT: s_mov_b32 s53, s3
+; GCN-HSA-NEXT: s_mov_b32 s55, s3
+; GCN-HSA-NEXT: s_mov_b32 s57, s3
; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s17, v7
-; GCN-HSA-NEXT: v_readfirstlane_b32 s12, v4
-; GCN-HSA-NEXT: v_readfirstlane_b32 s13, v5
-; GCN-HSA-NEXT: v_readfirstlane_b32 s16, v6
-; GCN-HSA-NEXT: s_lshr_b32 s4, s17, 16
-; GCN-HSA-NEXT: s_lshr_b32 s8, s17, 8
-; GCN-HSA-NEXT: s_mov_b32 s14, s17
-; GCN-HSA-NEXT: s_lshr_b32 s2, s13, 16
-; GCN-HSA-NEXT: s_lshr_b32 s6, s13, 8
-; GCN-HSA-NEXT: s_mov_b32 s10, s13
-; GCN-HSA-NEXT: s_lshr_b32 s18, s12, 16
-; GCN-HSA-NEXT: s_lshr_b32 s22, s12, 24
-; GCN-HSA-NEXT: s_lshr_b32 s24, s12, 8
-; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[12:13], 0x80000
-; GCN-HSA-NEXT: s_lshr_b32 s12, s16, 16
-; GCN-HSA-NEXT: s_lshr_b32 s26, s16, 24
-; GCN-HSA-NEXT: s_lshr_b32 s30, s16, 8
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
-; GCN-HSA-NEXT: v_readfirstlane_b32 s38, v0
-; GCN-HSA-NEXT: v_readfirstlane_b32 s39, v1
-; GCN-HSA-NEXT: v_readfirstlane_b32 s48, v2
-; GCN-HSA-NEXT: v_readfirstlane_b32 s49, v3
-; GCN-HSA-NEXT: s_ashr_i32 s59, s17, 31
-; GCN-HSA-NEXT: s_ashr_i32 s60, s17, 24
-; GCN-HSA-NEXT: s_bfe_i64 s[46:47], s[16:17], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[14:15], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[24:25], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[22:23], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[36:37], s[18:19], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[42:43], s[10:11], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[40:41], s[6:7], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[50:51], s[2:3], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[52:53], s[30:31], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[54:55], s[26:27], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[56:57], s[12:13], 0x80000
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s4
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s8
-; GCN-HSA-NEXT: s_lshr_b32 s30, s49, 16
-; GCN-HSA-NEXT: s_lshr_b32 s26, s49, 8
-; GCN-HSA-NEXT: s_lshr_b32 s14, s39, 16
-; GCN-HSA-NEXT: s_lshr_b32 s10, s39, 8
-; GCN-HSA-NEXT: s_mov_b32 s12, s39
-; GCN-HSA-NEXT: s_lshr_b32 s8, s38, 16
-; GCN-HSA-NEXT: s_lshr_b32 s6, s38, 24
-; GCN-HSA-NEXT: s_lshr_b32 s4, s38, 8
-; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[38:39], 0x80000
-; GCN-HSA-NEXT: s_mov_b32 s38, s49
-; GCN-HSA-NEXT: s_lshr_b32 s24, s48, 16
-; GCN-HSA-NEXT: s_lshr_b32 s22, s48, 24
-; GCN-HSA-NEXT: s_lshr_b32 s18, s48, 8
-; GCN-HSA-NEXT: s_ashr_i32 s45, s13, 31
-; GCN-HSA-NEXT: s_ashr_i32 s58, s13, 24
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s5
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s16
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s17
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s9
-; GCN-HSA-NEXT: s_ashr_i32 s33, s39, 31
-; GCN-HSA-NEXT: s_ashr_i32 s44, s39, 24
-; GCN-HSA-NEXT: s_ashr_i32 s61, s49, 31
-; GCN-HSA-NEXT: s_ashr_i32 s62, s49, 24
-; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[48:49], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GCN-HSA-NEXT: v_readfirstlane_b32 s31, v7
+; GCN-HSA-NEXT: s_lshr_b32 s2, s31, 16
+; GCN-HSA-NEXT: s_mov_b32 s6, s31
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GCN-HSA-NEXT: v_readfirstlane_b32 s24, v4
+; GCN-HSA-NEXT: v_readfirstlane_b32 s25, v5
+; GCN-HSA-NEXT: v_readfirstlane_b32 s30, v6
+; GCN-HSA-NEXT: s_lshr_b32 s28, s31, 8
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
+; GCN-HSA-NEXT: v_readfirstlane_b32 s2, v0
+; GCN-HSA-NEXT: v_readfirstlane_b32 s3, v1
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GCN-HSA-NEXT: v_readfirstlane_b32 s6, v2
+; GCN-HSA-NEXT: v_readfirstlane_b32 s7, v3
+; GCN-HSA-NEXT: s_lshr_b32 s12, s30, 16
+; GCN-HSA-NEXT: s_lshr_b32 s10, s30, 24
+; GCN-HSA-NEXT: s_lshr_b32 s8, s30, 8
+; GCN-HSA-NEXT: s_lshr_b32 s42, s25, 16
+; GCN-HSA-NEXT: s_lshr_b32 s40, s25, 8
+; GCN-HSA-NEXT: s_mov_b32 s4, s25
+; GCN-HSA-NEXT: s_lshr_b32 s14, s24, 16
+; GCN-HSA-NEXT: s_lshr_b32 s16, s24, 24
+; GCN-HSA-NEXT: s_lshr_b32 s18, s24, 8
+; GCN-HSA-NEXT: s_bfe_i64 s[60:61], s[28:29], 0x80000
+; GCN-HSA-NEXT: s_lshr_b32 s50, s7, 16
+; GCN-HSA-NEXT: s_lshr_b32 s52, s7, 8
+; GCN-HSA-NEXT: s_mov_b32 s26, s7
+; GCN-HSA-NEXT: s_lshr_b32 s22, s6, 16
+; GCN-HSA-NEXT: s_lshr_b32 s20, s6, 24
+; GCN-HSA-NEXT: s_lshr_b32 s34, s6, 8
+; GCN-HSA-NEXT: s_lshr_b32 s54, s3, 16
+; GCN-HSA-NEXT: s_lshr_b32 s56, s3, 8
+; GCN-HSA-NEXT: s_mov_b32 s38, s3
+; GCN-HSA-NEXT: s_lshr_b32 s44, s2, 16
+; GCN-HSA-NEXT: s_lshr_b32 s46, s2, 24
+; GCN-HSA-NEXT: s_lshr_b32 s48, s2, 8
+; GCN-HSA-NEXT: s_ashr_i32 s72, s25, 31
+; GCN-HSA-NEXT: s_ashr_i32 s73, s25, 24
; GCN-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
-; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
-; GCN-HSA-NEXT: s_add_u32 s48, s0, 0x70
-; GCN-HSA-NEXT: s_addc_u32 s49, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s49
-; GCN-HSA-NEXT: s_add_u32 s48, s0, 0x60
-; GCN-HSA-NEXT: s_addc_u32 s49, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v24, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v25, s49
-; GCN-HSA-NEXT: s_add_u32 s48, s0, 0x50
-; GCN-HSA-NEXT: s_addc_u32 s49, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s46
-; GCN-HSA-NEXT: s_add_u32 s46, s0, 64
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s47
-; GCN-HSA-NEXT: s_addc_u32 s47, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s42
-; GCN-HSA-NEXT: s_add_u32 s42, s0, 48
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s43
-; GCN-HSA-NEXT: s_addc_u32 s43, s1, 0
+; GCN-HSA-NEXT: s_ashr_i32 s74, s31, 31
+; GCN-HSA-NEXT: s_ashr_i32 s75, s31, 24
+; GCN-HSA-NEXT: s_bfe_i64 s[58:59], s[30:31], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[28:29], s[18:19], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[30:31], s[16:17], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[36:37], s[14:15], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[62:63], s[4:5], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[64:65], s[42:43], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[66:67], s[8:9], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[68:69], s[10:11], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[70:71], s[12:13], 0x80000
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s60
+; GCN-HSA-NEXT: s_ashr_i32 s33, s3, 31
+; GCN-HSA-NEXT: s_ashr_i32 s42, s3, 24
+; GCN-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
+; GCN-HSA-NEXT: s_ashr_i32 s43, s7, 31
+; GCN-HSA-NEXT: s_ashr_i32 s60, s7, 24
+; GCN-HSA-NEXT: s_bfe_i64 s[16:17], s[6:7], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[4:5], s[48:49], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[6:7], s[46:47], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[8:9], s[44:45], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[12:13], s[38:39], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[10:11], s[56:57], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[14:15], s[54:55], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[18:19], s[34:35], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[34:35], s[26:27], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[26:27], s[52:53], 0x80000
+; GCN-HSA-NEXT: s_bfe_i64 s[38:39], s[50:51], 0x80000
+; GCN-HSA-NEXT: s_add_u32 s44, s0, 0x70
+; GCN-HSA-NEXT: s_addc_u32 s45, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s45
+; GCN-HSA-NEXT: s_add_u32 s44, s0, 0x60
+; GCN-HSA-NEXT: s_addc_u32 s45, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v24, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v25, s45
+; GCN-HSA-NEXT: s_add_u32 s44, s0, 0x50
+; GCN-HSA-NEXT: s_addc_u32 s45, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v26, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v27, s45
+; GCN-HSA-NEXT: s_add_u32 s44, s0, 64
+; GCN-HSA-NEXT: s_addc_u32 s45, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v28, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v29, s45
+; GCN-HSA-NEXT: s_add_u32 s44, s0, 48
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s61
+; GCN-HSA-NEXT: s_addc_u32 s45, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v6, s60
+; GCN-HSA-NEXT: v_mov_b32_e32 v6, s75
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s36
; GCN-HSA-NEXT: s_add_u32 s36, s0, 32
-; GCN-HSA-NEXT: v_mov_b32_e32 v7, s59
-; GCN-HSA-NEXT: v_mov_b32_e32 v30, s42
+; GCN-HSA-NEXT: v_mov_b32_e32 v7, s74
+; GCN-HSA-NEXT: v_mov_b32_e32 v30, s44
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s37
; GCN-HSA-NEXT: s_addc_u32 s37, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s50
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s51
-; GCN-HSA-NEXT: v_mov_b32_e32 v31, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s64
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s65
+; GCN-HSA-NEXT: v_mov_b32_e32 v31, s45
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s58
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s45
-; GCN-HSA-NEXT: v_mov_b32_e32 v4, s20
-; GCN-HSA-NEXT: s_add_u32 s20, s0, 16
-; GCN-HSA-NEXT: v_mov_b32_e32 v5, s21
-; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s73
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s72
+; GCN-HSA-NEXT: v_mov_b32_e32 v4, s24
+; GCN-HSA-NEXT: s_add_u32 s24, s0, 16
+; GCN-HSA-NEXT: v_mov_b32_e32 v5, s25
+; GCN-HSA-NEXT: s_addc_u32 s25, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[30:31], v[16:19]
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s36
-; GCN-HSA-NEXT: v_mov_b32_e32 v16, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v17, s21
-; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xf0
-; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v18, s20
+; GCN-HSA-NEXT: v_mov_b32_e32 v16, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v17, s25
+; GCN-HSA-NEXT: s_add_u32 s24, s0, 0xf0
+; GCN-HSA-NEXT: s_addc_u32 s25, s1, 0
+; GCN-HSA-NEXT: v_mov_b32_e32 v18, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s30
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s31
+; GCN-HSA-NEXT: v_mov_b32_e32 v19, s25
+; GCN-HSA-NEXT: s_add_u32 s24, s0, 0xe0
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s62
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s63
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s40
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s41
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s37
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s34
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
-; GCN-HSA-NEXT: v_mov_b32_e32 v19, s21
-; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xe0
-; GCN-HSA-NEXT: v_mov_b32_e32 v26, s48
-; GCN-HSA-NEXT: v_mov_b32_e32 v28, s46
-; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[20:23]
-; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
-; GCN-HSA-NEXT: v_mov_b32_e32 v20, s20
+; GCN-HSA-NEXT: s_addc_u32 s25, s1, 0
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s56
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s70
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s57
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s54
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s55
-; GCN-HSA-NEXT: v_mov_b32_e32 v27, s49
-; GCN-HSA-NEXT: v_mov_b32_e32 v14, s52
-; GCN-HSA-NEXT: v_mov_b32_e32 v15, s53
-; GCN-HSA-NEXT: v_mov_b32_e32 v29, s47
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s71
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s68
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s69
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s58
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s59
+; GCN-HSA-NEXT: v_mov_b32_e32 v14, s66
+; GCN-HSA-NEXT: v_mov_b32_e32 v15, s67
; GCN-HSA-NEXT: v_mov_b32_e32 v6, s28
; GCN-HSA-NEXT: v_mov_b32_e32 v7, s29
-; GCN-HSA-NEXT: v_mov_b32_e32 v21, s21
+; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[20:23]
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GCN-HSA-NEXT: v_mov_b32_e32 v20, s24
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s20
; GCN-HSA-NEXT: s_add_u32 s20, s0, 0xd0
; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11]
; GCN-HSA-NEXT: flat_store_dwordx4 v[28:29], v[12:15]
-; GCN-HSA-NEXT: v_mov_b32_e32 v8, s30
-; GCN-HSA-NEXT: v_mov_b32_e32 v9, s31
-; GCN-HSA-NEXT: v_mov_b32_e32 v10, s62
-; GCN-HSA-NEXT: v_mov_b32_e32 v11, s61
-; GCN-HSA-NEXT: v_mov_b32_e32 v12, s38
-; GCN-HSA-NEXT: v_mov_b32_e32 v13, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v8, s38
+; GCN-HSA-NEXT: v_mov_b32_e32 v9, s39
+; GCN-HSA-NEXT: v_mov_b32_e32 v10, s60
+; GCN-HSA-NEXT: v_mov_b32_e32 v11, s43
+; GCN-HSA-NEXT: v_mov_b32_e32 v12, s34
+; GCN-HSA-NEXT: v_mov_b32_e32 v13, s35
+; GCN-HSA-NEXT: v_mov_b32_e32 v21, s25
; GCN-HSA-NEXT: v_mov_b32_e32 v14, s26
; GCN-HSA-NEXT: v_mov_b32_e32 v15, s27
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[8:11]
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[12:15]
+; GCN-HSA-NEXT: v_mov_b32_e32 v3, s21
; GCN-HSA-NEXT: s_addc_u32 s21, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s20
-; GCN-HSA-NEXT: v_mov_b32_e32 v0, s24
-; GCN-HSA-NEXT: v_mov_b32_e32 v1, s25
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s22
-; GCN-HSA-NEXT: v_mov_b32_e32 v3, s23
+; GCN-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GCN-HSA-NEXT: v_mov_b32_e32 v1, s23
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s21
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-HSA-NEXT: s_nop 0
@@ -8238,7 +8306,7 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s15
; GCN-HSA-NEXT: s_addc_u32 s15, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v4, s14
-; GCN-HSA-NEXT: v_mov_b32_e32 v2, s44
+; GCN-HSA-NEXT: v_mov_b32_e32 v2, s42
; GCN-HSA-NEXT: v_mov_b32_e32 v3, s33
; GCN-HSA-NEXT: v_mov_b32_e32 v5, s15
; GCN-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -8283,163 +8351,183 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
-; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16
-; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s21, 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s27, s21
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s35, s21
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s23, s21
+; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr53
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr55
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s59, s7
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s61, s7
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s39, s7
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr51
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr17
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr49
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr45
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr47
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr43
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr25
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr19
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr27
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr41
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr31
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr35
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr29
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr13
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr15
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr9
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr11
+; GCN-NOHSA-VI-NEXT: ; implicit-def: $sgpr57
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s11, v3
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s10, v2
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s20, s11, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s46, s10, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s48, s10, 24
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s71, s11, 31
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s72, s11, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s8, v0
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s9, v1
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s50, s10, 8
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s72
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s71
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s21
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s26, s9, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[36:37], s[10:11], 0x80000
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s63, v7
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s62, v6
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s63, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s56, s63, 8
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s63
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s54, s62, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s52, s62, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[68:69], s[62:63], 0x80000
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s70, s63, 31
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s63, s63, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s21, v5
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s64, v0
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s65, v1
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s66, v2
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s67, v3
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s50, s62, 8
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x80000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s63
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s70
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s58, s21, 16
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x80000
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s52, s9, 8
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s46
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s47
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s48
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s49
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s54, s9
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s69, s9, 31
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s70, s9, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s20, v4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s54
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s55
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s52
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s53
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s48, s21, 8
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s16, s21
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s60, s67, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s40, s67, 8
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s24, s67
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s66, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s66, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s66, 8
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s38, s65, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s26, s65, 8
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s18, s65
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s64, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s64, 24
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s64, 8
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[66:67], 0x80000
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s33, s65, 31
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s62, s65, 24
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s64, s67, 31
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s65, s67, 24
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s66, s21, 31
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s67, s21, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x80000
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:208
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s56, s8, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s36
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s37
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s46, s20, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s68
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s69
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s50
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s51
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s58, s8, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x80000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s44, s20, 24
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x80000
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:192
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s15, v7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s27
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s70
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s69
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s60, s8, 8
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s42, s20, 8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s58
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s59
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s67
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s66
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s15, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s54
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s55
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s52
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s53
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[8:9], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[60:61], s[60:61], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[36:37], s[20:21], 0x80000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s48
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s49
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s14, v6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s56
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s57
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s58
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s59
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s38, s15, 8
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s40, s15
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s65, s15, 31
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s67, s15, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[18:19], 0x80000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s46
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s47
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s44
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s45
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[26:27], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[38:39], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[38:39], s[24:25], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[40:41], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[40:41], s[60:61], 0x80000
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s14, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s19
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s60
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s61
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s14, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s13, v5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s34
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s35
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s67
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s65
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s14, 8
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s22, s13, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s36
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s37
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s42
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s43
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s40
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s41
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s38
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s39
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[14:15], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
-; GCN-NOHSA-VI-NEXT: v_readfirstlane_b32 s12, v4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s30
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s31
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s28
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s29
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s62, s13, 8
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s16, s13
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s33, s13, 31
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s63, s13, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s64, s12, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s65
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s64
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s38
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s39
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s25
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s66, s12, 24
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[62:63], 0x80000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s42, s11, 8
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s34
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s35
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s31
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s23
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s63
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s28
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s29
+; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s27
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s62
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s33
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s44, s11
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s68, s12, 8
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[12:13], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[66:67], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[64:65], 0x80000
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[68:69], 0x80000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s15
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s21
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s19
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s44
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s13
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s45
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s42
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s43
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s15
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s56
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s57
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:224
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s11
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NOHSA-VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/lrint.ll b/llvm/test/CodeGen/AMDGPU/lrint.ll
index 737ca214d2258..5894d0f7c035a 100644
--- a/llvm/test/CodeGen/AMDGPU/lrint.ll
+++ b/llvm/test/CodeGen/AMDGPU/lrint.ll
@@ -521,6 +521,7 @@ define half @intrinsic_frint_half(half %arg) {
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_rndne_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: intrinsic_frint_half:
diff --git a/llvm/test/CodeGen/AMDGPU/lround.ll b/llvm/test/CodeGen/AMDGPU/lround.ll
index 1fe0499cf2630..fafd320b56f4f 100644
--- a/llvm/test/CodeGen/AMDGPU/lround.ll
+++ b/llvm/test/CodeGen/AMDGPU/lround.ll
@@ -822,14 +822,16 @@ define half @intrinsic_fround_half(half %arg) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_trunc_f16_e32 v1.h, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0, 0x3c00, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX11-SDAG-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v1.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -860,6 +862,7 @@ define half @intrinsic_fround_half(half %arg) {
; GFX11-GISEL-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: intrinsic_fround_half:
@@ -943,14 +946,16 @@ define i32 @intrinsic_lround_i32_f16(half %arg) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_trunc_f16_e32 v1.h, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0, 0x3c00, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX11-SDAG-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v1.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
index a1e78bdc3b27f..f4c6c9155bff7 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
@@ -3,12 +3,22 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -85,6 +95,7 @@ define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x bfloat> %src0, <2 x bfloat> %sr
; GFX1250-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
; GFX1250-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
+; GFX1250-NEXT: ; implicit-def: $vgpr1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_pk_fma_f32 v[0:1], v[4:5], v[6:7], v[0:1] op_sel_hi:[1,1,0]
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
@@ -99,12 +110,22 @@ define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x bfloat> %src0, <2 x bfloat> %sr
}
define float @v_mad_mix_f32_negbf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_negbf16lo_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negbf16lo_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negbf16lo_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -114,12 +135,22 @@ define float @v_mad_mix_f32_negbf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src1,
}
define float @v_mad_mix_f32_absbf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_absbf16lo_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_absbf16lo_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_absbf16lo_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -129,12 +160,22 @@ define float @v_mad_mix_f32_absbf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src1,
}
define float @v_mad_mix_f32_negabsbf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_negabsbf16lo_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negabsbf16lo_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negabsbf16lo_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -145,12 +186,21 @@ define float @v_mad_mix_f32_negabsbf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src
}
define float @v_mad_mix_f32_bf16lo_bf16lo_f32(bfloat %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -158,12 +208,21 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_f32(bfloat %src0, bfloat %src1, float
}
define float @v_mad_mix_f32_bf16lo_bf16lo_negf32(bfloat %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_negf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_negf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_negf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.neg = fneg float %src2
@@ -172,12 +231,21 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_negf32(bfloat %src0, bfloat %src1, flo
}
define float @v_mad_mix_f32_bf16lo_bf16lo_absf32(bfloat %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_absf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, |v2| op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_absf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, |v2| op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_absf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, |v2| op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.abs = call float @llvm.fabs.f32(float %src2)
@@ -186,12 +254,21 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_absf32(bfloat %src0, bfloat %src1, flo
}
define float @v_mad_mix_f32_bf16lo_bf16lo_negabsf32(bfloat %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_negabsf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, -|v2| op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_negabsf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, -|v2| op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_negabsf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, -|v2| op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.abs = call float @llvm.fabs.f32(float %src2)
@@ -201,14 +278,25 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_negabsf32(bfloat %src0, bfloat %src1,
}
define float @v_mad_mix_f32_bf16lo_bf16lo_f32imm1(bfloat %src0, bfloat %src1) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32imm1:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s0, 1.0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32imm1:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 1.0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32imm1:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: s_mov_b32 s0, 1.0
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float 1.0)
@@ -216,14 +304,25 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_f32imm1(bfloat %src0, bfloat %src1) #0
}
define float @v_mad_mix_f32_bf16lo_bf16lo_f32imminv2pi(bfloat %src0, bfloat %src1) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32imminv2pi:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s0, 0.15915494
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32imminv2pi:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0.15915494
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32imminv2pi:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: s_mov_b32 s0, 0.15915494
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float 0x3FC45F3060000000)
@@ -231,14 +330,25 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_f32imminv2pi(bfloat %src0, bfloat %src
}
define float @v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imminv2pi(bfloat %src0, bfloat %src1) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imminv2pi:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s0, 0x3e230000
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imminv2pi:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0x3e230000
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imminv2pi:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: s_mov_b32 s0, 0x3e230000
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2 = fpext bfloat 0xR3e23 to float
@@ -247,14 +357,25 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imminv2pi(bfloat %src0, bfloat
}
define float @v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imm63(bfloat %src0, bfloat %src1) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imm63:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_mov_b32 s0, 0x367c0000
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imm63:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0x367c0000
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_cvtbf16imm63:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: s_mov_b32 s0, 0x367c0000
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2 = fpext bfloat 0xR367c to float
@@ -288,6 +409,7 @@ define <2 x float> @v_mad_mix_v2f32_cvtbf16imminv2pi(<2 x bfloat> %src0, <2 x bf
; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v0 :: v_dual_lshlrev_b32 v4, 16, v1
; GFX1250-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX1250-NEXT: s_mov_b32 s0, 0x3e230000
+; GFX1250-NEXT: ; implicit-def: $sgpr1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT: v_pk_fma_f32 v[0:1], v[2:3], v[4:5], s[0:1] op_sel_hi:[1,1,0]
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
@@ -359,12 +481,22 @@ define float @no_mix_simple_fabs(float %src0, float %src1, float %src2) #0 {
}
define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals(bfloat %src0, bfloat %src1, bfloat %src2) #1 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -373,12 +505,21 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals(bfloat %src0, bfl
}
define float @v_mad_mix_f32_bf16lo_bf16lo_f32_denormals(bfloat %src0, bfloat %src1, float %src2) #1 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_denormals:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_denormals:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_denormals:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -386,14 +527,26 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_f32_denormals(bfloat %src0, bfloat %sr
}
define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals_fmulfadd(bfloat %src0, bfloat %src1, bfloat %src2) #1 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals_fmulfadd:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v2, 1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals_fmulfadd:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v2, 1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals_fmulfadd:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v2, 1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -403,14 +556,25 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals_fmulfadd(bfloat %
}
define float @v_mad_mix_f32_bf16lo_bf16lo_f32_denormals_fmulfadd(bfloat %src0, bfloat %src1, float %src2) #1 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_denormals_fmulfadd:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_denormals_fmulfadd:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_denormals_fmulfadd:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%mul = fmul float %src0.ext, %src1.ext
@@ -419,12 +583,22 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_f32_denormals_fmulfadd(bfloat %src0, b
}
define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_flush_fmulfadd(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_flush_fmulfadd:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_flush_fmulfadd:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_flush_fmulfadd:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -434,12 +608,21 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_flush_fmulfadd(bfloat %src0
}
define float @v_mad_mix_f32_bf16lo_bf16lo_f32_flush_fmulfadd(bfloat %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_flush_fmulfadd:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_flush_fmulfadd:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_bf16lo_f32_flush_fmulfadd:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%mul = fmul contract float %src0.ext, %src1.ext
@@ -448,12 +631,22 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_f32_flush_fmulfadd(bfloat %src0, bfloa
}
define float @v_mad_mix_f32_negprecvtbf16lo_bf16lo_bf16lo(i32 %src0.arg, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_negprecvtbf16lo_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negprecvtbf16lo_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negprecvtbf16lo_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0
%src0.neg = fneg bfloat %src0
@@ -481,6 +674,9 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_bf16lo_bf16lo(i32 %src0.arg, bfl
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, v2.l
; GFX1250-REAL16-NEXT: v_xor_b16 v2.l, 0x8000, v0.h
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v2|, v1, v0 op_sel_hi:[1,1,1]
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
@@ -496,12 +692,21 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_bf16lo_bf16lo(i32 %src0.arg, bfl
}
define float @v_mad_mix_f32_precvtabsbf16hi_bf16lo_bf16lo(i32 %src0.arg, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_precvtabsbf16hi_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_precvtabsbf16hi_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_precvtabsbf16hi_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1
%src0.abs = call bfloat @llvm.fabs.bf16(bfloat %src0)
@@ -513,12 +718,21 @@ define float @v_mad_mix_f32_precvtabsbf16hi_bf16lo_bf16lo(i32 %src0.arg, bfloat
}
define float @v_mad_mix_f32_preextractfneg_bf16hi_bf16lo_bf16lo(i32 %src0.arg, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fneg = fneg <2 x bfloat> %src0.arg.bc
%src0 = extractelement <2 x bfloat> %fneg, i32 1
@@ -530,12 +744,21 @@ define float @v_mad_mix_f32_preextractfneg_bf16hi_bf16lo_bf16lo(i32 %src0.arg, b
}
define float @v_mad_mix_f32_preextractfabs_bf16hi_bf16lo_bf16lo(i32 %src0.arg, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc)
%src0 = extractelement <2 x bfloat> %fabs, i32 1
@@ -547,12 +770,21 @@ define float @v_mad_mix_f32_preextractfabs_bf16hi_bf16lo_bf16lo(i32 %src0.arg, b
}
define float @v_mad_mix_f32_preextractfabsfneg_bf16hi_bf16lo_bf16lo(i32 %src0.arg, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc)
%fneg.fabs = fneg <2 x bfloat> %fabs
@@ -585,14 +817,25 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo_all_cast_from_half(half %src0,
}
define float @v_mad_mix_f32_bf16lo_cast_from_half_bf16lo_bf16lo(half %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_cast_from_half_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_cast_from_half_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_cast_from_half_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.bf16 = bitcast half %src0 to bfloat
%src0.ext = fpext bfloat %src0.bf16 to float
%src1.ext = fpext bfloat %src1 to float
@@ -627,12 +870,21 @@ entry:
}
define float @v_mad_mix_f32_bf16lo_add_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = fadd float %src0.ext, %src1.ext
@@ -710,12 +962,21 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x bfloat> %src0, <2 x bfl
}
define float @v_mad_mix_f32_negbf16lo_add_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_negbf16lo_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negbf16lo_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negbf16lo_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src0.ext.neg = fneg float %src0.ext
@@ -724,12 +985,21 @@ define float @v_mad_mix_f32_negbf16lo_add_bf16lo(bfloat %src0, bfloat %src1) {
}
define float @v_mad_mix_f32_absbf16lo_add_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_absbf16lo_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_absbf16lo_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_absbf16lo_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext)
@@ -738,12 +1008,21 @@ define float @v_mad_mix_f32_absbf16lo_add_bf16lo(bfloat %src0, bfloat %src1) {
}
define float @v_mad_mix_f32_negabsbf16lo_add_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_negabsbf16lo_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negabsbf16lo_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negabsbf16lo_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext)
@@ -753,24 +1032,40 @@ define float @v_mad_mix_f32_negabsbf16lo_add_bf16lo(bfloat %src0, bfloat %src1)
}
define float @v_mad_mix_f32_bf16lo_add_f32(bfloat %src0, float %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_f32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_add_f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_add_f32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%result = fadd float %src0.ext, %src1
ret float %result
}
define float @v_mad_mix_f32_bf16lo_add_negf32(bfloat %src0, float %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_negf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_add_negf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_add_negf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.neg = fneg float %src1
%result = fadd float %src0.ext, %src1.neg
@@ -778,12 +1073,20 @@ define float @v_mad_mix_f32_bf16lo_add_negf32(bfloat %src0, float %src1) {
}
define float @v_mad_mix_f32_bf16lo_add_absf32(bfloat %src0, float %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_absf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, |v1| op_sel:[0,1,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_add_absf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, |v1| op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_add_absf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, |v1| op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.abs = call float @llvm.fabs.f32(float %src1)
%result = fadd float %src0.ext, %src1.abs
@@ -791,12 +1094,20 @@ define float @v_mad_mix_f32_bf16lo_add_absf32(bfloat %src0, float %src1) {
}
define float @v_mad_mix_f32_bf16lo_add_negabsf32(bfloat %src0, float %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_negabsf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v1|, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_add_negabsf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v1|, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_add_negabsf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v1|, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[0,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.abs = call float @llvm.fabs.f32(float %src1)
%src1.neg.abs = fneg float %src1.abs
@@ -845,12 +1156,20 @@ define float @v_mad_mix_clamp_f32_bf16hi_add_bf16hi_elt(<2 x bfloat> %src0, <2 x
}
define float @v_mad_mix_f32_negprecvtbf16lo_add_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_negprecvtbf16lo_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negprecvtbf16lo_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negprecvtbf16lo_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0
%src0.neg = fneg bfloat %src0
@@ -861,12 +1180,21 @@ define float @v_mad_mix_f32_negprecvtbf16lo_add_bf16lo(i32 %src0.arg, bfloat %sr
}
define float @v_mad_mix_f32_absprecvtbf16lo_add_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_absprecvtbf16lo_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_absprecvtbf16lo_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_absprecvtbf16lo_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0
%src0.fabs = call bfloat @llvm.fabs.bf16(bfloat %src0)
@@ -877,12 +1205,21 @@ define float @v_mad_mix_f32_absprecvtbf16lo_add_bf16lo(i32 %src0.arg, bfloat %sr
}
define float @v_mad_mix_f32_negabsprecvtbf16lo_add_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_negabsprecvtbf16lo_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negabsprecvtbf16lo_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negabsprecvtbf16lo_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, -1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0
%src0.fabs = call bfloat @llvm.fabs.bf16(bfloat %src0)
@@ -910,6 +1247,8 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_add_bf16lo(i32 %src0.arg, bfloat
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX1250-REAL16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v1|, 1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,1]
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
@@ -924,12 +1263,20 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_add_bf16lo(i32 %src0.arg, bfloat
}
define float @v_mad_mix_f32_precvtabsbf16hi_add_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_precvtabsbf16hi_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_precvtabsbf16hi_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_precvtabsbf16hi_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1
%src0.abs = call bfloat @llvm.fabs.bf16(bfloat %src0)
@@ -940,12 +1287,20 @@ define float @v_mad_mix_f32_precvtabsbf16hi_add_bf16lo(i32 %src0.arg, bfloat %sr
}
define float @v_mad_mix_f32_preextractfneg_bf16hi_add_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -v0, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -v0, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fneg = fneg <2 x bfloat> %src0.arg.bc
%src0 = extractelement <2 x bfloat> %fneg, i32 1
@@ -956,12 +1311,20 @@ define float @v_mad_mix_f32_preextractfneg_bf16hi_add_bf16lo(i32 %src0.arg, bflo
}
define float @v_mad_mix_f32_preextractfabs_bf16hi_add_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc)
%src0 = extractelement <2 x bfloat> %fabs, i32 1
@@ -972,12 +1335,20 @@ define float @v_mad_mix_f32_preextractfabs_bf16hi_add_bf16lo(i32 %src0.arg, bflo
}
define float @v_mad_mix_f32_preextractfabsfneg_bf16hi_add_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_add_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_add_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_add_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, 1.0, v1 op_sel:[1,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc)
%fneg.fabs = fneg <2 x bfloat> %fabs
@@ -989,12 +1360,21 @@ define float @v_mad_mix_f32_preextractfabsfneg_bf16hi_add_bf16lo(i32 %src0.arg,
}
define float @v_mad_mix_f32_bf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = fmul float %src0.ext, %src1.ext
@@ -1072,12 +1452,21 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_mul(<2 x bfloat> %src0, <2 x bfl
}
define float @v_mad_mix_f32_negbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_negbf16lo_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negbf16lo_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negbf16lo_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src0.ext.neg = fneg float %src0.ext
@@ -1086,12 +1475,21 @@ define float @v_mad_mix_f32_negbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) {
}
define float @v_mad_mix_f32_absbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_absbf16lo_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_absbf16lo_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_absbf16lo_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext)
@@ -1100,12 +1498,21 @@ define float @v_mad_mix_f32_absbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) {
}
define float @v_mad_mix_f32_negabsbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_negabsbf16lo_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negabsbf16lo_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negabsbf16lo_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext)
@@ -1115,24 +1522,40 @@ define float @v_mad_mix_f32_negabsbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1)
}
define float @v_mad_mix_f32_bf16lo_mul_f32(bfloat %src0, float %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_f32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,0,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_mul_f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,0,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_mul_f32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,0,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%result = fmul float %src0.ext, %src1
ret float %result
}
define float @v_mad_mix_f32_bf16lo_mul_negf32(bfloat %src0, float %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_negf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_mul_negf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_mul_negf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.neg = fneg float %src1
%result = fmul float %src0.ext, %src1.neg
@@ -1140,12 +1563,20 @@ define float @v_mad_mix_f32_bf16lo_mul_negf32(bfloat %src0, float %src1) {
}
define float @v_mad_mix_f32_bf16lo_mul_absf32(bfloat %src0, float %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_absf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_mul_absf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_mul_absf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.abs = call float @llvm.fabs.f32(float %src1)
%result = fmul float %src0.ext, %src1.abs
@@ -1153,12 +1584,20 @@ define float @v_mad_mix_f32_bf16lo_mul_absf32(bfloat %src0, float %src1) {
}
define float @v_mad_mix_f32_bf16lo_mul_negabsf32(bfloat %src0, float %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_negabsf32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_mul_negabsf32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_mul_negabsf32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.abs = call float @llvm.fabs.f32(float %src1)
%src1.neg.abs = fneg float %src1.abs
@@ -1207,12 +1646,21 @@ define float @v_mad_mix_clamp_f32_bf16hi_mul_bf16hi_elt(<2 x bfloat> %src0, <2 x
}
define float @v_mad_mix_f32_negprecvtbf16lo_mul_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_negprecvtbf16lo_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negprecvtbf16lo_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negprecvtbf16lo_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0
%src0.neg = fneg bfloat %src0
@@ -1223,12 +1671,21 @@ define float @v_mad_mix_f32_negprecvtbf16lo_mul_bf16lo(i32 %src0.arg, bfloat %sr
}
define float @v_mad_mix_f32_absprecvtbf16lo_mul_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_absprecvtbf16lo_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_absprecvtbf16lo_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_absprecvtbf16lo_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0
%src0.fabs = call bfloat @llvm.fabs.bf16(bfloat %src0)
@@ -1239,12 +1696,21 @@ define float @v_mad_mix_f32_absprecvtbf16lo_mul_bf16lo(i32 %src0.arg, bfloat %sr
}
define float @v_mad_mix_f32_negabsprecvtbf16lo_mul_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_negabsprecvtbf16lo_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_negabsprecvtbf16lo_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_negabsprecvtbf16lo_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0
%src0.fabs = call bfloat @llvm.fabs.bf16(bfloat %src0)
@@ -1272,6 +1738,8 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_mul_bf16lo(i32 %src0.arg, bfloat
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX1250-REAL16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v1|, v0, neg(0) op_sel_hi:[1,1,0]
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
@@ -1286,12 +1754,20 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_mul_bf16lo(i32 %src0.arg, bfloat
}
define float @v_mad_mix_f32_precvtabsbf16hi_mul_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_precvtabsbf16hi_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_precvtabsbf16hi_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_precvtabsbf16hi_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1
%src0.abs = call bfloat @llvm.fabs.bf16(bfloat %src0)
@@ -1302,12 +1778,20 @@ define float @v_mad_mix_f32_precvtabsbf16hi_mul_bf16lo(i32 %src0.arg, bfloat %sr
}
define float @v_mad_mix_f32_preextractfneg_bf16hi_mul_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fneg = fneg <2 x bfloat> %src0.arg.bc
%src0 = extractelement <2 x bfloat> %fneg, i32 1
@@ -1318,12 +1802,20 @@ define float @v_mad_mix_f32_preextractfneg_bf16hi_mul_bf16lo(i32 %src0.arg, bflo
}
define float @v_mad_mix_f32_preextractfabs_bf16hi_mul_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc)
%src0 = extractelement <2 x bfloat> %fabs, i32 1
@@ -1334,12 +1826,20 @@ define float @v_mad_mix_f32_preextractfabs_bf16hi_mul_bf16lo(i32 %src0.arg, bflo
}
define float @v_mad_mix_f32_preextractfabsfneg_bf16hi_mul_bf16lo(i32 %src0.arg, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_mul_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_mul_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_mul_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc)
%fneg.fabs = fneg <2 x bfloat> %fabs
@@ -1351,12 +1851,21 @@ define float @v_mad_mix_f32_preextractfabsfneg_bf16hi_mul_bf16lo(i32 %src0.arg,
}
define float @v_mad_mix_f32_bf16lo_sub_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_bf16lo_sub_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_bf16lo_sub_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_bf16lo_sub_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = fsub float %src0.ext, %src1.ext
@@ -1364,12 +1873,21 @@ define float @v_mad_mix_f32_bf16lo_sub_bf16lo(bfloat %src0, bfloat %src1) {
}
define float @v_mad_mix_f32_absbf16lo_sub_bf16lo(bfloat %src0, bfloat %src1) {
-; GFX1250-LABEL: v_mad_mix_f32_absbf16lo_sub_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, |v0| op_sel:[0,1,0] op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mix_f32_absbf16lo_sub_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, |v0| op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mix_f32_absbf16lo_sub_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, |v0| op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext)
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
index 67a85c6d53b24..f381d80d6e61b 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
@@ -3,12 +3,22 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -31,6 +41,9 @@ define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_constlo(bfloat %src0,
;
; GFX1250-REAL16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_constlo:
; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
@@ -57,6 +70,9 @@ define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_reglo(bfloat %src0, b
;
; GFX1250-REAL16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_reglo:
; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
@@ -73,14 +89,26 @@ define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_reglo(bfloat %src0, b
}
define i32 @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -93,14 +121,26 @@ define i32 @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack(bfloat %src0, bfloat %
}
define i32 @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack_sext(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack_sext:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack_sext:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_intpack_sext:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -125,12 +165,16 @@ define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo_clamp_precvt(
;
; GFX1250-REAL16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo_clamp_precvt:
; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_lo16
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
@@ -144,12 +188,22 @@ define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo_clamp_precvt(
}
define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo_clamp_postcvt(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo_clamp_postcvt:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo_clamp_postcvt:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo_clamp_postcvt:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -177,6 +231,9 @@ define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo_clamp_postcvt
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v3, v1, v2 op_sel_hi:[1,1,1]
; GFX1250-REAL16-NEXT: v_fma_mixhi_bf16 v0, v3, v1, v2 op_sel_hi:[1,1,1] clamp
@@ -204,3 +261,5 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone speculatable }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1250: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index 4deb6a7f578e3..a2b16e2019099 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -13,11 +13,20 @@
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo(half %src0, half %src1, half %src2) #0 {
-; GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
+; SDAG-GFX11-TRUE16: ; %bb.0:
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
+; SDAG-GFX11-FAKE16: ; %bb.0:
+; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
; GFX9: ; %bb.0:
@@ -46,6 +55,12 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo(half %src0, half %s
; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
+; GISEL-GFX11: ; %bb.0:
+; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -68,6 +83,9 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo(half %src0, half %s
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo(half %src0, half %src1, half %src2) #0 {
; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
; SDAG-GFX11-TRUE16: ; %bb.0:
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3c00
@@ -145,6 +163,9 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo(half %src0, half %s
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo(half %src0, half %src1, half %src2, half %lo) #0 {
; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:
; SDAG-GFX11-TRUE16: ; %bb.0:
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
@@ -220,13 +241,24 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo(half %src0, half %src
}
define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, half %src2) #0 {
-; SDAG-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
+; SDAG-GFX11-TRUE16: ; %bb.0:
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
+; SDAG-GFX11-FAKE16: ; %bb.0:
+; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
; SDAG-GFX9: ; %bb.0:
@@ -295,13 +327,24 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha
}
define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src1, half %src2) #0 {
-; SDAG-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
+; SDAG-GFX11-TRUE16: ; %bb.0:
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
+; SDAG-GFX11-FAKE16: ; %bb.0:
+; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
; SDAG-GFX9: ; %bb.0:
@@ -385,6 +428,9 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %src0, half %src1, half %src2) #0 {
; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; SDAG-GFX11-TRUE16: ; %bb.0:
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -470,11 +516,20 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
}
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half %src0, half %src1, half %src2) #0 {
-; GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
+; SDAG-GFX11-TRUE16: ; %bb.0:
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
+; SDAG-GFX11-FAKE16: ; %bb.0:
+; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
; GFX9: ; %bb.0:
@@ -509,6 +564,12 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half
; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
+; GISEL-GFX11: ; %bb.0:
+; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -541,6 +602,9 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi
; SDAG-GFX11-TRUE16: ; %bb.0:
; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v3, v1, v2 op_sel_hi:[1,1,1]
; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, v1, v2 op_sel_hi:[1,1,1] clamp
@@ -651,4 +715,6 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
; GISEL-GFX11-FAKE16: {{.*}}
+; SDAG-GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
index 1a5b6daf2bdd0..5503bbf641ad7 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
@@ -27,12 +27,22 @@ define bfloat @mixlo_simpl_no_flush(float %src0, float %src1, float %src2) {
}
define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -42,12 +52,22 @@ define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo(bfloat %src0, bfloat %src1,
}
define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo_no_flush(bfloat %src0, bfloat %src1, bfloat %src2) {
-; GFX1250-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo_no_flush:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo_no_flush:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo_no_flush:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
@@ -57,12 +77,21 @@ define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_bf16lo_no_flush(bfloat %src0, bflo
}
define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_f32(bfloat %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -71,12 +100,21 @@ define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_f32(bfloat %src0, bfloat %src1, fl
}
define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_post_cvt(bfloat %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_post_cvt:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_post_cvt:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_post_cvt:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -87,14 +125,25 @@ define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_post_cvt(bfloat %src0, b
}
define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_pre_cvt(bfloat %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_pre_cvt:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_pre_cvt:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixlo_bf16_bf16lo_bf16lo_f32_clamp_pre_cvt:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -145,6 +194,7 @@ define <3 x bfloat> @v_mad_mix_v3f32(<3 x bfloat> %src0, <3 x bfloat> %src1, <3
; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v2, v4 op_sel_hi:[1,1,1]
; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v6
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
@@ -232,6 +282,7 @@ define <3 x bfloat> @v_mad_mix_v3f32_clamp_postcvt(<3 x bfloat> %src0, <3 x bflo
; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; GFX1250-REAL16-NEXT: v_fma_mixhi_bf16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-REAL16-NEXT: v_pk_max_num_bf16 v1, v1, v1 clamp
; GFX1250-REAL16-NEXT: v_mov_b32_e32 v0, v3
@@ -355,6 +406,7 @@ define <2 x bfloat> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x bfloat> %src0, <2 x b
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_pk_fma_f32 v[0:1], v[4:5], v[6:7], v[0:1]
; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX1250-REAL16-NEXT: v_pk_max_num_bf16 v1, v1, v1 op_sel_hi:[0,0] clamp
@@ -422,6 +474,7 @@ define <3 x bfloat> @v_mad_mix_v3f32_clamp_precvt(<3 x bfloat> %src0, <3 x bfloa
; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0
+; GFX1250-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v0, v3, v0
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext <3 x bfloat> %src0 to <3 x float>
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index d338967abe34f..a0dc16196ddeb 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -105,11 +105,20 @@ define half @mixlo_simpl_no_flush(float %src0, float %src1, float %src2) {
}
define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -143,6 +152,12 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo(half %src0, half %src1, half %src
; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -161,11 +176,20 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo(half %src0, half %src1, half %src
}
define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush(half %src0, half %src1, half %src2) {
-; GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush:
; GFX900: ; %bb.0:
@@ -204,6 +228,12 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush(half %src0, half %src1,
; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -222,11 +252,19 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo_no_flush(half %src0, half %src1,
}
define half @v_mad_mixlo_f16_f16lo_f16lo_f32(half %src0, half %src1, float %src2) #0 {
-; GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32:
; GFX900: ; %bb.0:
@@ -258,6 +296,12 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f32(half %src0, half %src1, float %src2
; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -274,11 +318,19 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f32(half %src0, half %src1, float %src2
}
define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt(half %src0, half %src1, float %src2) #0 {
-; GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt:
; GFX900: ; %bb.0:
@@ -316,6 +368,12 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt(half %src0, half %sr
; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -342,6 +400,8 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_post_cvt(half %src0, half %sr
define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt(half %src0, half %src1, float %src2) #0 {
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -546,6 +606,7 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v6
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1083,6 +1144,7 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
@@ -2066,6 +2128,7 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v2
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_precvt:
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index ee5de5fb697a8..bc5883b4b157e 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -17,11 +17,20 @@
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI,GISEL-CI %s
define float @v_mad_mix_f32_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -61,6 +70,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2
; CI-NEXT: v_cvt_f32_f16_e32 v0, v2
; CI-NEXT: v_mac_f32_e32 v0, v3, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%src2.ext = fpext half %src2 to float
@@ -410,11 +425,20 @@ define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x half> %src0, <2 x half> %src1,
}
define float @v_mad_mix_f32_negf16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -455,6 +479,12 @@ define float @v_mad_mix_f32_negf16lo_f16lo_f16lo(half %src0, half %src1, half %s
; SDAG-CI-NEXT: v_mad_f32 v0, -v0, v1, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_f16lo_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -490,11 +520,20 @@ define float @v_mad_mix_f32_negf16lo_f16lo_f16lo(half %src0, half %src1, half %s
}
define float @v_mad_mix_f32_absf16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_absf16lo_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_absf16lo_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_absf16lo_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_absf16lo_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -536,6 +575,12 @@ define float @v_mad_mix_f32_absf16lo_f16lo_f16lo(half %src0, half %src1, half %s
; SDAG-CI-NEXT: v_mov_b32_e32 v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_absf16lo_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_absf16lo_f16lo_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -553,11 +598,20 @@ define float @v_mad_mix_f32_absf16lo_f16lo_f16lo(half %src0, half %src1, half %s
}
define float @v_mad_mix_f32_negabsf16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -598,6 +652,12 @@ define float @v_mad_mix_f32_negabsf16lo_f16lo_f16lo(half %src0, half %src1, half
; SDAG-CI-NEXT: v_mad_f32 v0, -v0, v1, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -616,11 +676,19 @@ define float @v_mad_mix_f32_negabsf16lo_f16lo_f16lo(half %src0, half %src1, half
}
define float @v_mad_mix_f32_f16lo_f16lo_f32(half %src0, half %src1, float %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32:
; GFX900: ; %bb.0:
@@ -657,6 +725,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32(half %src0, half %src1, float %src2)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mad_f32 v0, v0, v1, v2
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -664,11 +738,19 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32(half %src0, half %src1, float %src2)
}
define float @v_mad_mix_f32_f16lo_f16lo_negf32(half %src0, half %src1, float %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_negf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_negf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_negf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_negf32:
; GFX900: ; %bb.0:
@@ -705,6 +787,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_negf32(half %src0, half %src1, float %sr
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mad_f32 v0, v0, v1, -v2
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_negf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%src2.neg = fneg float %src2
@@ -713,11 +801,19 @@ define float @v_mad_mix_f32_f16lo_f16lo_negf32(half %src0, half %src1, float %sr
}
define float @v_mad_mix_f32_f16lo_f16lo_absf32(half %src0, half %src1, float %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_absf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, |v2| op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_absf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, |v2| op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_absf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, |v2| op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_absf32:
; GFX900: ; %bb.0:
@@ -754,6 +850,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_absf32(half %src0, half %src1, float %sr
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mad_f32 v0, v0, v1, |v2|
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_absf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, |v2| op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%src2.abs = call float @llvm.fabs.f32(float %src2)
@@ -762,11 +864,19 @@ define float @v_mad_mix_f32_f16lo_f16lo_absf32(half %src0, half %src1, float %sr
}
define float @v_mad_mix_f32_f16lo_f16lo_negabsf32(half %src0, half %src1, float %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_negabsf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, -|v2| op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_negabsf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, -|v2| op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_negabsf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, -|v2| op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_negabsf32:
; GFX900: ; %bb.0:
@@ -803,6 +913,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_negabsf32(half %src0, half %src1, float
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mad_f32 v0, v0, v1, -|v2|
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_negabsf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, -|v2| op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%src2.abs = call float @llvm.fabs.f32(float %src2)
@@ -816,13 +932,23 @@ define float @v_mad_mix_f32_f16lo_f16lo_negabsf32(half %src0, half %src1, float
; inline immediate.
define float @v_mad_mix_f32_f16lo_f16lo_f32imm1(half %src0, half %src1) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: s_mov_b32 s0, 1.0
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: s_mov_b32 s0, 1.0
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 1.0
+; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
; SDAG-GFX900: ; %bb.0:
@@ -890,13 +1016,23 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imm1(half %src0, half %src1) #0 {
}
define float @v_mad_mix_f32_f16lo_f16lo_f32imminv2pi(half %src0, half %src1) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0.15915494
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: s_mov_b32 s0, 0.15915494
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 0.15915494
+; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
; SDAG-GFX900: ; %bb.0:
@@ -979,13 +1115,23 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imminv2pi(half %src0, half %src1) #0
; f32 1/2pi = 0x3e22f983
define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi(half %src0, half %src1) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0x3e230000
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: s_mov_b32 s0, 0x3e230000
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 0x3e230000
+; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
; SDAG-GFX900: ; %bb.0:
@@ -1082,13 +1228,23 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi(half %src0, half %src1)
define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imm63(half %src0, half %src1) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0x367c0000
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: s_mov_b32 s0, 0x367c0000
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 0x367c0000
+; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
; SDAG-GFX900: ; %bb.0:
@@ -1747,11 +1903,20 @@ define float @no_mix_simple_fabs(float %src0, float %src1, float %src2) #0 {
; v_mad_mix_f32 flushes.
define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals(half %src0, half %src1, half %src2) #1 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals:
; GFX900: ; %bb.0:
@@ -1795,6 +1960,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals(half %src0, half %sr
; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; CI-NEXT: v_fma_f32 v0, v0, v1, v2
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%src2.ext = fpext half %src2 to float
@@ -1803,11 +1974,19 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals(half %src0, half %sr
}
define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals(half %src0, half %src1, float %src2) #1 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals:
; GFX900: ; %bb.0:
@@ -1847,6 +2026,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals(half %src0, half %src1, fl
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_fma_f32 v0, v0, v1, v2
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -1854,13 +2039,24 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals(half %src0, half %src1, fl
}
define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half %src1, half %src2) #1 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v2, 1.0, v0 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v2, 1.0, v0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v2, 1.0, v0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd:
; GFX900: ; %bb.0:
@@ -1908,6 +2104,14 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd(half %src0,
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v2
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v2, 1.0, v0 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%src2.ext = fpext half %src2 to float
@@ -1917,13 +2121,23 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd(half %src0,
}
define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half %src1, float %src2) #1 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd:
; GFX900: ; %bb.0:
@@ -1967,6 +2181,14 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v2
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-NEXT: v_add_f32_e32 v0, v0, v2
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%mul = fmul float %src0.ext, %src1.ext
@@ -1975,11 +2197,20 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half
}
define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd:
; GFX900: ; %bb.0:
@@ -2019,6 +2250,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd(half %src0, hal
; CI-NEXT: v_cvt_f32_f16_e32 v0, v2
; CI-NEXT: v_mac_f32_e32 v0, v3, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%src2.ext = fpext half %src2 to float
@@ -2028,11 +2265,19 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd(half %src0, hal
}
define float @v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src1, float %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd:
; GFX900: ; %bb.0:
@@ -2069,6 +2314,12 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mad_f32 v0, v0, v1, v2
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%mul = fmul contract float %src0.ext, %src1.ext
@@ -2077,14 +2328,23 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src
}
define float @v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
-; GFX900: ; %bb.0:
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
+; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2122,6 +2382,12 @@ define float @v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo(i32 %src0.arg, half %src1
; SDAG-CI-NEXT: v_mad_f32 v0, -v0, v1, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2167,6 +2433,9 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo(i32 %src0.arg, half %
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v2.l, 0x8000, v0.h
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v2|, v1, v0 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2254,11 +2523,19 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -2299,6 +2576,12 @@ define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1
; CI-NEXT: v_cvt_f32_f16_e32 v0, v2
; CI-NEXT: v_mac_f32_e32 v0, v3, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.abs = call half @llvm.fabs.f16(half %src0)
@@ -2310,11 +2593,19 @@ define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1
}
define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -2356,6 +2647,12 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half
; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2397,11 +2694,19 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half
}
define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -2443,6 +2748,12 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half
; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2484,11 +2795,19 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half
}
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
; GFX900: ; %bb.0:
@@ -2530,6 +2849,12 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg,
; SDAG-CI-NEXT: v_mac_f32_e32 v0, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
; GISEL-GFX9GEN: ; %bb.0:
; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2572,11 +2897,19 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg,
}
define float @v_mad_mix_f32_f16lo_add_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_add_f16lo:
; GFX900: ; %bb.0:
@@ -2615,6 +2948,12 @@ define float @v_mad_mix_f32_f16lo_add_f16lo(half %src0, half %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_add_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%result = fadd float %src0.ext, %src1.ext
@@ -2943,11 +3282,19 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x half> %src0, <2 x half>
}
define float @v_mad_mix_f32_negf16lo_add_f16lo(half %src0, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -3038,11 +3385,19 @@ define float @v_mad_mix_f32_negf16lo_add_f16lo(half %src0, half %src1) {
}
define float @v_mad_mix_f32_absf16lo_add_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_absf16lo_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_absf16lo_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_absf16lo_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_absf16lo_add_f16lo:
; GFX900: ; %bb.0:
@@ -3082,6 +3437,12 @@ define float @v_mad_mix_f32_absf16lo_add_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_absf16lo_add_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_absf16lo_add_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3097,11 +3458,19 @@ define float @v_mad_mix_f32_absf16lo_add_f16lo(half %src0, half %src1) {
}
define float @v_mad_mix_f32_negabsf16lo_add_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo:
; GFX900: ; %bb.0:
@@ -3141,6 +3510,12 @@ define float @v_mad_mix_f32_negabsf16lo_add_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3157,11 +3532,18 @@ define float @v_mad_mix_f32_negabsf16lo_add_f16lo(half %src0, half %src1) {
}
define float @v_mad_mix_f32_f16lo_add_f32(half %src0, float %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_add_f32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_add_f32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_add_f32:
; GFX900: ; %bb.0:
@@ -3196,17 +3578,30 @@ define float @v_mad_mix_f32_f16lo_add_f32(half %src0, float %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_add_f32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%result = fadd float %src0.ext, %src1
ret float %result
}
define float @v_mad_mix_f32_f16lo_add_negf32(half %src0, float %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_negf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[0,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_add_negf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[0,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_add_negf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[0,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_add_negf32:
; GFX900: ; %bb.0:
@@ -3241,6 +3636,12 @@ define float @v_mad_mix_f32_f16lo_add_negf32(half %src0, float %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_sub_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_add_negf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[0,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.neg = fneg float %src1
%result = fadd float %src0.ext, %src1.neg
@@ -3248,11 +3649,18 @@ define float @v_mad_mix_f32_f16lo_add_negf32(half %src0, float %src1) {
}
define float @v_mad_mix_f32_f16lo_add_absf32(half %src0, float %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_absf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, |v1| op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_add_absf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, |v1| op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_add_absf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, |v1| op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_add_absf32:
; GFX900: ; %bb.0:
@@ -3287,6 +3695,12 @@ define float @v_mad_mix_f32_f16lo_add_absf32(half %src0, float %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_add_f32_e64 v0, v0, |v1|
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_add_absf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, |v1| op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.abs = call float @llvm.fabs.f32(float %src1)
%result = fadd float %src0.ext, %src1.abs
@@ -3294,11 +3708,18 @@ define float @v_mad_mix_f32_f16lo_add_absf32(half %src0, float %src1) {
}
define float @v_mad_mix_f32_f16lo_add_negabsf32(half %src0, float %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_negabsf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v1|, -1.0, v0 op_sel_hi:[0,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_add_negabsf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, -1.0, v0 op_sel_hi:[0,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_add_negabsf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v1|, -1.0, v0 op_sel_hi:[0,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_add_negabsf32:
; GFX900: ; %bb.0:
@@ -3333,6 +3754,12 @@ define float @v_mad_mix_f32_f16lo_add_negabsf32(half %src0, float %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_sub_f32_e64 v0, v0, |v1|
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_add_negabsf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v1|, -1.0, v0 op_sel_hi:[0,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.abs = call float @llvm.fabs.f32(float %src1)
%src1.neg.abs = fneg float %src1.abs
@@ -3488,11 +3915,18 @@ define float @v_mad_mix_clamp_f32_f16hi_add_f16hi(<2 x half> %src0, <2 x half> %
}
define float @v_mad_mix_f32_negprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -3585,11 +4019,19 @@ define float @v_mad_mix_f32_negprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_absprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo:
; GFX900: ; %bb.0:
@@ -3628,6 +4070,12 @@ define float @v_mad_mix_f32_absprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 0
%src0.fabs = call half @llvm.fabs.f16(half %src0)
@@ -3638,11 +4086,19 @@ define float @v_mad_mix_f32_absprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_negabsprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -3741,6 +4197,8 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo(i32 %src0.arg, half %sr
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, 1.0, v0 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -3823,11 +4281,18 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo(i32 %src0.arg, half %sr
}
define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
; GFX900: ; %bb.0:
@@ -3867,6 +4332,12 @@ define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.abs = call half @llvm.fabs.f16(half %src0)
@@ -3877,11 +4348,18 @@ define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -3980,11 +4458,18 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -4025,6 +4510,12 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %
; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4071,11 +4562,18 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -4175,11 +4673,19 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, ha
}
define float @v_mad_mix_f32_f16lo_mul_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_f16lo:
; GFX900: ; %bb.0:
@@ -4218,6 +4724,12 @@ define float @v_mad_mix_f32_f16lo_mul_f16lo(half %src0, half %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%result = fmul float %src0.ext, %src1.ext
@@ -4546,11 +5058,19 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_mul(<2 x half> %src0, <2 x half>
}
define float @v_mad_mix_f32_negf16lo_mul_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -4590,6 +5110,12 @@ define float @v_mad_mix_f32_negf16lo_mul_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4629,11 +5155,19 @@ define float @v_mad_mix_f32_negf16lo_mul_f16lo(half %src0, half %src1) {
}
define float @v_mad_mix_f32_absf16lo_mul_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo:
; GFX900: ; %bb.0:
@@ -4673,6 +5207,12 @@ define float @v_mad_mix_f32_absf16lo_mul_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4688,11 +5228,19 @@ define float @v_mad_mix_f32_absf16lo_mul_f16lo(half %src0, half %src1) {
}
define float @v_mad_mix_f32_negabsf16lo_mul_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo:
; GFX900: ; %bb.0:
@@ -4733,6 +5281,12 @@ define float @v_mad_mix_f32_negabsf16lo_mul_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4749,11 +5303,18 @@ define float @v_mad_mix_f32_negabsf16lo_mul_f16lo(half %src0, half %src1) {
}
define float @v_mad_mix_f32_f16lo_mul_f32(half %src0, float %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,0,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_mul_f32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,0,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_mul_f32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,0,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_f32:
; GFX900: ; %bb.0:
@@ -4788,17 +5349,30 @@ define float @v_mad_mix_f32_f16lo_mul_f32(half %src0, float %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_f32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,0,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%result = fmul float %src0.ext, %src1
ret float %result
}
define float @v_mad_mix_f32_f16lo_mul_negf32(half %src0, float %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_negf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_mul_negf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_mul_negf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_negf32:
; GFX900: ; %bb.0:
@@ -4833,6 +5407,12 @@ define float @v_mad_mix_f32_f16lo_mul_negf32(half %src0, float %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_mul_f32_e64 v0, v0, -v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_negf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.neg = fneg float %src1
%result = fmul float %src0.ext, %src1.neg
@@ -4840,11 +5420,18 @@ define float @v_mad_mix_f32_f16lo_mul_negf32(half %src0, float %src1) {
}
define float @v_mad_mix_f32_f16lo_mul_absf32(half %src0, float %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_absf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_mul_absf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_mul_absf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_absf32:
; GFX900: ; %bb.0:
@@ -4879,6 +5466,12 @@ define float @v_mad_mix_f32_f16lo_mul_absf32(half %src0, float %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_mul_f32_e64 v0, v0, |v1|
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_absf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.abs = call float @llvm.fabs.f32(float %src1)
%result = fmul float %src0.ext, %src1.abs
@@ -4886,11 +5479,18 @@ define float @v_mad_mix_f32_f16lo_mul_absf32(half %src0, float %src1) {
}
define float @v_mad_mix_f32_f16lo_mul_negabsf32(half %src0, float %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32:
; GFX900: ; %bb.0:
@@ -4925,6 +5525,12 @@ define float @v_mad_mix_f32_f16lo_mul_negabsf32(half %src0, float %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_mul_f32_e64 v0, v0, -|v1|
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.abs = call float @llvm.fabs.f32(float %src1)
%src1.neg.abs = fneg float %src1.abs
@@ -5080,11 +5686,19 @@ define float @v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt(<2 x half> %src0, <2 x hal
}
define float @v_mad_mix_f32_negprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo:
; GFX900: ; %bb.0:
@@ -5123,6 +5737,12 @@ define float @v_mad_mix_f32_negprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 0
%src0.neg = fneg half %src0
@@ -5133,11 +5753,19 @@ define float @v_mad_mix_f32_negprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_absprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo:
; GFX900: ; %bb.0:
@@ -5176,6 +5804,12 @@ define float @v_mad_mix_f32_absprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 0
%src0.fabs = call half @llvm.fabs.f16(half %src0)
@@ -5186,11 +5820,19 @@ define float @v_mad_mix_f32_absprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo:
; GFX900: ; %bb.0:
@@ -5229,6 +5871,12 @@ define float @v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 0
%src0.fabs = call half @llvm.fabs.f16(half %src0)
@@ -5245,6 +5893,8 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo(i32 %src0.arg, half %sr
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, v0, neg(0) op_sel_hi:[1,1,0]
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -5327,11 +5977,18 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo(i32 %src0.arg, half %sr
}
define float @v_mad_mix_f32_precvtabsf16hi_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
; GFX900: ; %bb.0:
@@ -5371,6 +6028,12 @@ define float @v_mad_mix_f32_precvtabsf16hi_mul_f16lo(i32 %src0.arg, half %src1)
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.abs = call half @llvm.fabs.f16(half %src0)
@@ -5381,11 +6044,18 @@ define float @v_mad_mix_f32_precvtabsf16hi_mul_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -5426,6 +6096,12 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo(i32 %src0.arg, half %
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5472,11 +6148,18 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -5517,6 +6200,12 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5563,11 +6252,18 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
; SDAG-GFX900: ; %bb.0:
@@ -5608,6 +6304,12 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo(i32 %src0.arg, ha
; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -5655,11 +6357,19 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo(i32 %src0.arg, ha
}
define float @v_mad_mix_f32_f16lo_sub_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_sub_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_sub_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_sub_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_sub_f16lo:
; GFX900: ; %bb.0:
@@ -5698,6 +6408,12 @@ define float @v_mad_mix_f32_f16lo_sub_f16lo(half %src0, half %src1) {
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_sub_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_sub_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%result = fsub float %src0.ext, %src1.ext
@@ -5705,11 +6421,19 @@ define float @v_mad_mix_f32_f16lo_sub_f16lo(half %src0, half %src1) {
}
define float @v_mad_mix_f32_absf16lo_sub_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, |v0| op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo:
+; SDAG-GFX1100-TRUE16: ; %bb.0:
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; SDAG-GFX1100-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, |v0| op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo:
+; SDAG-GFX1100-FAKE16: ; %bb.0:
+; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, |v0| op_sel_hi:[1,1,1]
+; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo:
; GFX900: ; %bb.0:
@@ -5749,6 +6473,12 @@ define float @v_mad_mix_f32_absf16lo_sub_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_sub_f32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, |v0| op_sel_hi:[1,1,1]
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
index 4e24b02a9b15e..30e0a9a892868 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
@@ -623,6 +623,7 @@ define i64 @mad_i64_i32_extops_i32_i64(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v0
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v4, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v2, v1
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, v4, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -767,6 +768,7 @@ define i64 @mad_u64_u32_bitops_lhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #
; GFX9-NEXT: v_and_b32_e32 v3, 1, v1
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[4:5]
; GFX9-NEXT: v_mov_b32_e32 v4, v1
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v2, v[4:5]
; GFX9-NEXT: v_mov_b32_e32 v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -852,9 +854,10 @@ define i64 @mad_u64_u32_bitops_rhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v6, v0
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v2, v[4:5]
-; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_and_b32_e32 v7, 1, v3
; GFX9-NEXT: v_mov_b32_e32 v2, v1
-; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v3, v[2:3]
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v7, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1798,6 +1801,7 @@ define i64 @lshr_mad_i64_4(i32 %arg0, i64 %arg1) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v0, 0
; GFX9-NEXT: v_mov_b32_e32 v6, v5
+; GFX9-NEXT: ; implicit-def: $vgpr7
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, v[6:7]
; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_movk_i32 s4, 0xfc88
@@ -2115,9 +2119,10 @@ define i64 @lshr_mad_i64_negative_4(i64 %arg0) #0 {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v0, v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, v3
-; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v1, v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v4, v3
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: v_mov_b32_e32 v0, v2
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v1, v[4:5]
; GFX9-NEXT: v_mov_b32_e32 v1, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll b/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
index 577fe2f54e551..d99208343cc50 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
@@ -9,19 +9,22 @@
define amdgpu_ps float @mad_i32_vvv(i32 %a, i32 %b, i32 %c) {
; GFX9-LABEL: mad_i32_vvv:
; GFX9: ; %bb.0:
+; GFX9-NEXT: ; implicit-def: $vgpr3
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: mad_i32_vvv:
; GFX10: ; %bb.0:
+; GFX10-NEXT: ; implicit-def: $vgpr3
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[2:3]
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mad_i32_vvv:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_mov_b32_e32 v3, v1
-; GFX11-NEXT: v_mov_b32_e32 v4, v0
-; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v3, v[2:3]
+; GFX11-NEXT: v_mov_b32_e32 v4, v1
+; GFX11-NEXT: v_mov_b32_e32 v5, v0
+; GFX11-NEXT: ; implicit-def: $vgpr3
+; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v5, v4, v[2:3]
; GFX11-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: mad_i32_vvv:
@@ -164,18 +167,21 @@ define amdgpu_ps float @mad_i32_vvi_neg(i32 %a, i32 %b) {
define amdgpu_ps float @mad_i32_vcv(i32 %a, i32 %c) {
; GFX9-LABEL: mad_i32_vcv:
; GFX9: ; %bb.0:
+; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 42, v[1:2]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: mad_i32_vcv:
; GFX10: ; %bb.0:
+; GFX10-NEXT: ; implicit-def: $vgpr2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 42, v[1:2]
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mad_i32_vcv:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v0, 42, v[1:2]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: ; implicit-def: $vgpr2
+; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v0, 42, v[1:2]
+; GFX11-NEXT: v_mov_b32_e32 v0, v3
; GFX11-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: mad_i32_vcv:
@@ -220,11 +226,13 @@ define amdgpu_ps float @mad_i32_vcc(i32 %a) {
define amdgpu_ps float @mad_i32_vvs(i32 %a, i32 %b, i32 inreg %c) {
; GFX9-LABEL: mad_i32_vvs:
; GFX9: ; %bb.0:
+; GFX9-NEXT: ; implicit-def: $sgpr1
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, s[0:1]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: mad_i32_vvs:
; GFX10: ; %bb.0:
+; GFX10-NEXT: ; implicit-def: $sgpr1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, s[0:1]
; GFX10-NEXT: ; return to shader part epilog
;
@@ -232,6 +240,7 @@ define amdgpu_ps float @mad_i32_vvs(i32 %a, i32 %b, i32 inreg %c) {
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mov_b32_e32 v2, v1
; GFX11-NEXT: v_mov_b32_e32 v3, v0
+; GFX11-NEXT: ; implicit-def: $sgpr1
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, s[0:1]
; GFX11-NEXT: ; return to shader part epilog
;
@@ -249,18 +258,21 @@ define amdgpu_ps float @mad_i32_vvs(i32 %a, i32 %b, i32 inreg %c) {
define amdgpu_ps float @mad_i32_vsv(i32 %a, i32 inreg %b, i32 %c) {
; GFX9-LABEL: mad_i32_vsv:
; GFX9: ; %bb.0:
+; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, s0, v[1:2]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: mad_i32_vsv:
; GFX10: ; %bb.0:
+; GFX10-NEXT: ; implicit-def: $vgpr2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s0, v[1:2]
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mad_i32_vsv:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: ; implicit-def: $vgpr2
+; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v0, s0, v[1:2]
+; GFX11-NEXT: v_mov_b32_e32 v0, v3
; GFX11-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: mad_i32_vsv:
@@ -277,18 +289,21 @@ define amdgpu_ps float @mad_i32_vsv(i32 %a, i32 inreg %b, i32 %c) {
define amdgpu_ps float @mad_i32_svv(i32 inreg %a, i32 %b, i32 %c) {
; GFX9-LABEL: mad_i32_svv:
; GFX9: ; %bb.0:
+; GFX9-NEXT: ; implicit-def: $vgpr2
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s0, v0, v[1:2]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: mad_i32_svv:
; GFX10: ; %bb.0:
+; GFX10-NEXT: ; implicit-def: $vgpr2
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, v0, v[1:2]
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mad_i32_svv:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, s0, v0, v[1:2]
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: ; implicit-def: $vgpr2
+; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, s0, v0, v[1:2]
+; GFX11-NEXT: v_mov_b32_e32 v0, v3
; GFX11-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: mad_i32_svv:
@@ -312,6 +327,7 @@ define amdgpu_ps float @mad_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c) {
; GFX10-LABEL: mad_i32_vss:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b32 s2, s1
+; GFX10-NEXT: ; implicit-def: $sgpr3
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s0, s[2:3]
; GFX10-NEXT: ; return to shader part epilog
;
@@ -319,6 +335,7 @@ define amdgpu_ps float @mad_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c) {
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mov_b32_e32 v2, v0
; GFX11-NEXT: s_mov_b32 s2, s1
+; GFX11-NEXT: ; implicit-def: $sgpr3
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, s0, s[2:3]
; GFX11-NEXT: ; return to shader part epilog
;
@@ -343,6 +360,7 @@ define amdgpu_ps float @mad_i32_svs(i32 inreg %a, i32 %b, i32 inreg %c) {
; GFX10-LABEL: mad_i32_svs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b32 s2, s1
+; GFX10-NEXT: ; implicit-def: $sgpr3
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, v0, s[2:3]
; GFX10-NEXT: ; return to shader part epilog
;
@@ -350,6 +368,7 @@ define amdgpu_ps float @mad_i32_svs(i32 inreg %a, i32 %b, i32 inreg %c) {
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mov_b32_e32 v2, v0
; GFX11-NEXT: s_mov_b32 s2, s1
+; GFX11-NEXT: ; implicit-def: $sgpr3
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, s0, v2, s[2:3]
; GFX11-NEXT: ; return to shader part epilog
;
@@ -373,13 +392,15 @@ define amdgpu_ps float @mad_i32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
;
; GFX10-LABEL: mad_i32_ssv:
; GFX10: ; %bb.0:
+; GFX10-NEXT: ; implicit-def: $vgpr1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, s1, v[0:1]
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: mad_i32_ssv:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, s0, s1, v[0:1]
-; GFX11-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-NEXT: ; implicit-def: $vgpr1
+; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, s0, s1, v[0:1]
+; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: mad_i32_ssv:
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
index 9a9e66f10a62d..700a272bf0bac 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
@@ -1273,6 +1273,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
@@ -1404,6 +1405,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
@@ -1703,6 +1705,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v6
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v8
@@ -1785,6 +1788,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v6
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v8
@@ -13623,6 +13627,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
@@ -13754,6 +13759,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index 6ebb6aaa4520f..51a4aa1844db0 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -3237,6 +3237,8 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_lt_u32_e32 vcc_lo, v4, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
index 84f5eca2ceed0..8a995eb734a69 100644
--- a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
@@ -99,16 +99,22 @@ define amdgpu_ps float @test_maxmin_commuted_f32(float %a, float %b, float %c) {
}
define amdgpu_ps half @test_minmax_f16(half %a, half %b, half %c) {
-; TRUE16-LABEL: test_minmax_f16:
-; TRUE16: ; %bb.0:
-; TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
-; TRUE16-NEXT: ; return to shader part epilog
+; GFX1170-SDAG-TRUE16-LABEL: test_minmax_f16:
+; GFX1170-SDAG-TRUE16: ; %bb.0:
+; GFX1170-SDAG-TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX1170-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; FAKE16-LABEL: test_minmax_f16:
; FAKE16: ; %bb.0:
; FAKE16-NEXT: v_maximumminimum_f16 v0, v0, v1, v2
; FAKE16-NEXT: ; return to shader part epilog
;
+; GFX1170-GISEL-TRUE16-LABEL: test_minmax_f16:
+; GFX1170-GISEL-TRUE16: ; %bb.0:
+; GFX1170-GISEL-TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
+;
; GFX12-SDAG-TRUE16-LABEL: test_minmax_f16:
; GFX12-SDAG-TRUE16: ; %bb.0:
; GFX12-SDAG-TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
@@ -122,6 +128,7 @@ define amdgpu_ps half @test_minmax_f16(half %a, half %b, half %c) {
; GFX12-GISEL-TRUE16-LABEL: test_minmax_f16:
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-FAKE16-LABEL: test_minmax_f16:
@@ -134,16 +141,22 @@ define amdgpu_ps half @test_minmax_f16(half %a, half %b, half %c) {
}
define amdgpu_ps half @test_minmax_commuted_f16(half %a, half %b, half %c) {
-; TRUE16-LABEL: test_minmax_commuted_f16:
-; TRUE16: ; %bb.0:
-; TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
-; TRUE16-NEXT: ; return to shader part epilog
+; GFX1170-SDAG-TRUE16-LABEL: test_minmax_commuted_f16:
+; GFX1170-SDAG-TRUE16: ; %bb.0:
+; GFX1170-SDAG-TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX1170-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; FAKE16-LABEL: test_minmax_commuted_f16:
; FAKE16: ; %bb.0:
; FAKE16-NEXT: v_maximumminimum_f16 v0, v0, v1, v2
; FAKE16-NEXT: ; return to shader part epilog
;
+; GFX1170-GISEL-TRUE16-LABEL: test_minmax_commuted_f16:
+; GFX1170-GISEL-TRUE16: ; %bb.0:
+; GFX1170-GISEL-TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
+;
; GFX12-SDAG-TRUE16-LABEL: test_minmax_commuted_f16:
; GFX12-SDAG-TRUE16: ; %bb.0:
; GFX12-SDAG-TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
@@ -157,6 +170,7 @@ define amdgpu_ps half @test_minmax_commuted_f16(half %a, half %b, half %c) {
; GFX12-GISEL-TRUE16-LABEL: test_minmax_commuted_f16:
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: v_maximumminimum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-FAKE16-LABEL: test_minmax_commuted_f16:
@@ -169,16 +183,22 @@ define amdgpu_ps half @test_minmax_commuted_f16(half %a, half %b, half %c) {
}
define amdgpu_ps half @test_maxmin_commuted_f16(half %a, half %b, half %c) {
-; TRUE16-LABEL: test_maxmin_commuted_f16:
-; TRUE16: ; %bb.0:
-; TRUE16-NEXT: v_minimummaximum_f16 v0.l, v0.l, v1.l, v2.l
-; TRUE16-NEXT: ; return to shader part epilog
+; GFX1170-SDAG-TRUE16-LABEL: test_maxmin_commuted_f16:
+; GFX1170-SDAG-TRUE16: ; %bb.0:
+; GFX1170-SDAG-TRUE16-NEXT: v_minimummaximum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX1170-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; FAKE16-LABEL: test_maxmin_commuted_f16:
; FAKE16: ; %bb.0:
; FAKE16-NEXT: v_minimummaximum_f16 v0, v0, v1, v2
; FAKE16-NEXT: ; return to shader part epilog
;
+; GFX1170-GISEL-TRUE16-LABEL: test_maxmin_commuted_f16:
+; GFX1170-GISEL-TRUE16: ; %bb.0:
+; GFX1170-GISEL-TRUE16-NEXT: v_minimummaximum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
+;
; GFX12-SDAG-TRUE16-LABEL: test_maxmin_commuted_f16:
; GFX12-SDAG-TRUE16: ; %bb.0:
; GFX12-SDAG-TRUE16-NEXT: v_minimummaximum_f16 v0.l, v0.l, v1.l, v2.l
@@ -192,6 +212,7 @@ define amdgpu_ps half @test_maxmin_commuted_f16(half %a, half %b, half %c) {
; GFX12-GISEL-TRUE16-LABEL: test_maxmin_commuted_f16:
; GFX12-GISEL-TRUE16: ; %bb.0:
; GFX12-GISEL-TRUE16-NEXT: v_minimummaximum_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-GISEL-FAKE16-LABEL: test_maxmin_commuted_f16:
@@ -303,3 +324,5 @@ declare half @llvm.minimum.f16(half, half)
declare half @llvm.maximum.f16(half, half)
declare float @llvm.minimum.f32(float, float)
declare float @llvm.maximum.f32(float, float)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
index 8fe4249ce1d64..a84a952f46392 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
@@ -1288,6 +1288,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
@@ -1419,6 +1420,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
@@ -1720,6 +1722,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v6
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v8
@@ -1802,6 +1805,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v6
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v8
@@ -13664,6 +13668,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
@@ -13795,6 +13800,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index baaaf657478c3..6e325842d7d93 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -938,6 +938,7 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
; GISEL-GFX11-TRUE16-LABEL: test_minmax_f16_ieee_false:
; GISEL-GFX11-TRUE16: ; %bb.0:
; GISEL-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, v0.l, v1.l, v2.l
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX11-FAKE16-LABEL: test_minmax_f16_ieee_false:
@@ -958,6 +959,7 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
; GISEL-GFX1170-TRUE16-LABEL: test_minmax_f16_ieee_false:
; GISEL-GFX1170-TRUE16: ; %bb.0:
; GISEL-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
+; GISEL-GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX1170-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1170-FAKE16-LABEL: test_minmax_f16_ieee_false:
@@ -978,6 +980,7 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
; GISEL-GFX12-TRUE16-LABEL: test_minmax_f16_ieee_false:
; GISEL-GFX12-TRUE16: ; %bb.0:
; GISEL-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX12-FAKE16-LABEL: test_minmax_f16_ieee_false:
@@ -1001,6 +1004,7 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
; GISEL-GFX1250-TRUE16: ; %bb.0:
; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
+; GISEL-GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-FAKE16-LABEL: test_minmax_f16_ieee_false:
@@ -1210,6 +1214,7 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.l
; GISEL-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
@@ -1246,6 +1251,7 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
; GISEL-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1170-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
@@ -1294,6 +1300,7 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
; GISEL-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
@@ -1337,6 +1344,7 @@ define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
; GISEL-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GISEL-GFX1250-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
@@ -1367,6 +1375,7 @@ define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) {
; GISEL-GFX11-TRUE16-LABEL: test_maxmin_f16_ieee_false:
; GISEL-GFX11-TRUE16: ; %bb.0:
; GISEL-GFX11-TRUE16-NEXT: v_minmax_f16 v0.l, v0.l, v1.l, v2.l
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX11-FAKE16-LABEL: test_maxmin_f16_ieee_false:
@@ -1387,6 +1396,7 @@ define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) {
; GISEL-GFX1170-TRUE16-LABEL: test_maxmin_f16_ieee_false:
; GISEL-GFX1170-TRUE16: ; %bb.0:
; GISEL-GFX1170-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
+; GISEL-GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX1170-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1170-FAKE16-LABEL: test_maxmin_f16_ieee_false:
@@ -1407,6 +1417,7 @@ define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) {
; GISEL-GFX12-TRUE16-LABEL: test_maxmin_f16_ieee_false:
; GISEL-GFX12-TRUE16: ; %bb.0:
; GISEL-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX12-FAKE16-LABEL: test_maxmin_f16_ieee_false:
@@ -1430,6 +1441,7 @@ define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) {
; GISEL-GFX1250-TRUE16: ; %bb.0:
; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
+; GISEL-GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-FAKE16-LABEL: test_maxmin_f16_ieee_false:
@@ -1468,6 +1480,7 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.l
; GISEL-GFX11-TRUE16-NEXT: v_minmax_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
@@ -1504,6 +1517,7 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
; GISEL-GFX1170-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
; GISEL-GFX1170-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1170-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
@@ -1552,6 +1566,7 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
; GISEL-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
@@ -1595,6 +1610,7 @@ define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
; GISEL-GFX1250-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
; GISEL-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
+; GISEL-GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GISEL-GFX1250-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
diff --git a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
index 57981d1763959..b287662bdf648 100644
--- a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
@@ -74,21 +74,22 @@ define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, ptr addrspace(3)
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v0
; GFX9-NEXT: v_add_u32_e32 v12, v17, v0
+; GFX9-NEXT: v_add_u32_e32 v19, v9, v0
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_madak_f32 v3, v3, v7, 0x3727c5ac
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_mul_u32_u24_e32 v18, v3, v5
-; GFX9-NEXT: v_add_u32_e32 v19, v3, v16
-; GFX9-NEXT: v_add_u32_e32 v3, v9, v0
-; GFX9-NEXT: v_sub_u32_e32 v3, v3, v18
; GFX9-NEXT: v_sub_u32_e32 v12, v12, v18
-; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v19, v13
-; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v19, v15, v[3:4]
+; GFX9-NEXT: v_sub_u32_e32 v18, v19, v18
+; GFX9-NEXT: ; implicit-def: $vgpr19
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v16
+; GFX9-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v3, v15, v[18:19]
+; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v3, v13
; GFX9-NEXT: v_cmp_lt_u32_e64 s[6:7], v12, v14
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, v18, s[4:5]
; GFX9-NEXT: v_lshlrev_b64 v[18:19], 2, v[3:4]
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: v_add_co_u32_e64 v18, s[6:7], v10, v18
; GFX9-NEXT: v_addc_co_u32_e64 v19, s[6:7], v11, v19, s[6:7]
; GFX9-NEXT: global_load_dword v3, v[18:19], off
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
index dca6ad5efa859..394007a24f136 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
@@ -510,6 +510,7 @@ define amdgpu_kernel void @fadd_v2_v_imm(ptr addrspace(1) %a) {
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; PACKED-SDAG-NEXT: s_mov_b32 s2, 0x42c80000
+; PACKED-SDAG-NEXT: ; implicit-def: $sgpr3
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -537,6 +538,7 @@ define amdgpu_kernel void @fadd_v2_v_imm(ptr addrspace(1) %a) {
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-SDAG-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1250-SDAG-NEXT: s_mov_b32 s2, 0x42c80000
+; GFX1250-SDAG-NEXT: ; implicit-def: $sgpr3
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT: global_load_b64 v[0:1], v2, s[0:1] scale_offset
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
@@ -585,6 +587,7 @@ define amdgpu_kernel void @fadd_v2_v_v_splat(ptr addrspace(1) %a) {
; PACKED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v4, 3, v0
+; PACKED-SDAG-NEXT: ; implicit-def: $vgpr1
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[2:3], v4, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -921,6 +924,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg(ptr addrspace(1) %a, float %x) {
; PACKED-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; PACKED-SDAG-NEXT: ; implicit-def: $sgpr3
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -1000,6 +1004,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, float %x) {
; PACKED-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; PACKED-SDAG-NEXT: ; implicit-def: $sgpr3
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -1099,6 +1104,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi(ptr addrspace(1) %a, float %x) {
; PACKED-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; PACKED-SDAG-NEXT: ; implicit-def: $sgpr3
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -1873,6 +1879,7 @@ define amdgpu_kernel void @fmul_v2_v_imm(ptr addrspace(1) %a) {
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; PACKED-SDAG-NEXT: s_mov_b32 s2, 0x42c80000
+; PACKED-SDAG-NEXT: ; implicit-def: $sgpr3
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -1900,6 +1907,7 @@ define amdgpu_kernel void @fmul_v2_v_imm(ptr addrspace(1) %a) {
; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-SDAG-NEXT: v_and_b32_e32 v2, 0x3ff, v0
; GFX1250-SDAG-NEXT: s_mov_b32 s2, 0x42c80000
+; GFX1250-SDAG-NEXT: ; implicit-def: $sgpr3
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT: global_load_b64 v[0:1], v2, s[0:1] scale_offset
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
@@ -1948,6 +1956,7 @@ define amdgpu_kernel void @fmul_v2_v_v_splat(ptr addrspace(1) %a) {
; PACKED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v4, 3, v0
+; PACKED-SDAG-NEXT: ; implicit-def: $vgpr1
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[2:3], v4, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -2160,6 +2169,7 @@ define amdgpu_kernel void @fmul_v2_v_fneg(ptr addrspace(1) %a, float %x) {
; PACKED-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; PACKED-SDAG-NEXT: ; implicit-def: $sgpr3
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -2721,14 +2731,16 @@ define amdgpu_kernel void @fma_v2_v_imm(ptr addrspace(1) %a) {
; PACKED-SDAG: ; %bb.0:
; PACKED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v3, 3, v0
+; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; PACKED-SDAG-NEXT: v_mov_b32_e32 v2, 0x43480000
; PACKED-SDAG-NEXT: s_mov_b32 s2, 0x42c80000
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v3, s[0:1]
+; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
+; PACKED-SDAG-NEXT: ; implicit-def: $vgpr3
+; PACKED-SDAG-NEXT: ; implicit-def: $sgpr3
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
; PACKED-SDAG-NEXT: v_pk_fma_f32 v[0:1], v[0:1], s[2:3], v[2:3] op_sel_hi:[1,0,0]
-; PACKED-SDAG-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
+; PACKED-SDAG-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; PACKED-SDAG-NEXT: s_endpgm
;
; GFX90A-GISEL-LABEL: fma_v2_v_imm:
@@ -2773,6 +2785,8 @@ define amdgpu_kernel void @fma_v2_v_imm(ptr addrspace(1) %a) {
; GFX1250-SDAG-NEXT: s_mov_b32 s2, 0x43480000
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_mov_b32 s4, 0x42c80000
+; GFX1250-SDAG-NEXT: ; implicit-def: $sgpr3
+; GFX1250-SDAG-NEXT: ; implicit-def: $sgpr5
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT: global_load_b64 v[0:1], v2, s[0:1] scale_offset
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
@@ -2824,6 +2838,7 @@ define amdgpu_kernel void @fma_v2_v_v_splat(ptr addrspace(1) %a) {
; PACKED-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v4, 3, v0
+; PACKED-SDAG-NEXT: ; implicit-def: $vgpr1
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[2:3], v4, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -3099,6 +3114,7 @@ define amdgpu_kernel void @fma_v2_v_fneg(ptr addrspace(1) %a, float %x) {
; PACKED-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; PACKED-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; PACKED-SDAG-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; PACKED-SDAG-NEXT: ; implicit-def: $sgpr3
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; PACKED-SDAG-NEXT: s_waitcnt vmcnt(0)
@@ -3177,7 +3193,8 @@ define amdgpu_kernel void @add_vector_neg_bitcast_scalar_lo(ptr addrspace(1) %ou
; PACKED-SDAG-LABEL: add_vector_neg_bitcast_scalar_lo:
; PACKED-SDAG: ; %bb.0: ; %bb
; PACKED-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; PACKED-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; PACKED-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; PACKED-SDAG-NEXT: ; implicit-def: $vgpr3
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: v_mov_b32_e32 v0, s2
; PACKED-SDAG-NEXT: v_mov_b32_e32 v2, s3
@@ -3185,7 +3202,7 @@ define amdgpu_kernel void @add_vector_neg_bitcast_scalar_lo(ptr addrspace(1) %ou
; PACKED-SDAG-NEXT: ds_read_b32 v2, v2
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]
-; PACKED-SDAG-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
+; PACKED-SDAG-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; PACKED-SDAG-NEXT: s_endpgm
;
; PACKED-GISEL-LABEL: add_vector_neg_bitcast_scalar_lo:
@@ -3208,14 +3225,15 @@ define amdgpu_kernel void @add_vector_neg_bitcast_scalar_lo(ptr addrspace(1) %ou
; GFX1250-SDAG: ; %bb.0: ; %bb
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX1250-SDAG-NEXT: ; implicit-def: $vgpr3
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s2
-; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
; GFX1250-SDAG-NEXT: ds_load_2addr_b32 v[0:1], v0 offset1:1
; GFX1250-SDAG-NEXT: ds_load_b32 v2, v2
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
; GFX1250-SDAG-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]
-; GFX1250-SDAG-NEXT: global_store_b64 v3, v[0:1], s[0:1]
+; GFX1250-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: add_vector_neg_bitcast_scalar_lo:
@@ -3608,6 +3626,7 @@ define amdgpu_kernel void @fadd_fadd_fsub_0(<2 x float> %arg) {
; GFX90A-GISEL-LABEL: fadd_fadd_fsub_0:
; GFX90A-GISEL: ; %bb.0: ; %bb
; GFX90A-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: ; implicit-def: $sgpr3
; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], s[0:1], 0
; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s2, v1
@@ -3620,6 +3639,7 @@ define amdgpu_kernel void @fadd_fadd_fsub_0(<2 x float> %arg) {
; GFX942-GISEL-LABEL: fadd_fadd_fsub_0:
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX942-GISEL-NEXT: ; implicit-def: $sgpr3
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], s[0:1], 0
; GFX942-GISEL-NEXT: s_nop 0
@@ -3649,6 +3669,7 @@ define amdgpu_kernel void @fadd_fadd_fsub_0(<2 x float> %arg) {
; GFX1250-GISEL: ; %bb.0: ; %bb
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1250-GISEL-NEXT: ; implicit-def: $sgpr3
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3692,6 +3713,7 @@ define amdgpu_kernel void @fadd_fadd_fsub(<2 x float> %arg, <2 x float> %arg1, p
; PACKED-SDAG: ; %bb.0: ; %bb
; PACKED-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; PACKED-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; PACKED-SDAG-NEXT: ; implicit-def: $vgpr1
; PACKED-SDAG-NEXT: v_mov_b32_e32 v4, 0
; PACKED-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; PACKED-SDAG-NEXT: v_mov_b32_e32 v0, s3
@@ -3706,39 +3728,41 @@ define amdgpu_kernel void @fadd_fadd_fsub(<2 x float> %arg, <2 x float> %arg1, p
; GFX90A-GISEL-LABEL: fadd_fadd_fsub:
; GFX90A-GISEL: ; %bb.0: ; %bb
; GFX90A-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX90A-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX90A-GISEL-NEXT: ; implicit-def: $sgpr7
+; GFX90A-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34
; GFX90A-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], s[0:1], v[0:1]
-; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s4, v1
-; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[4:5], s[4:5] op_sel:[0,1]
+; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[6:7], s[6:7] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], s[2:3], v[0:1]
; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s1, v0
; GFX90A-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3] neg_lo:[0,1] neg_hi:[0,1]
-; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
+; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX90A-GISEL-NEXT: s_endpgm
;
; GFX942-GISEL-LABEL: fadd_fadd_fsub:
; GFX942-GISEL: ; %bb.0: ; %bb
; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX942-GISEL-NEXT: ; implicit-def: $sgpr7
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34
; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], s[0:1], v[0:1]
; GFX942-GISEL-NEXT: s_nop 0
-; GFX942-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX942-GISEL-NEXT: v_readfirstlane_b32 s6, v1
; GFX942-GISEL-NEXT: s_nop 1
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], s[2:3], v[0:1]
; GFX942-GISEL-NEXT: s_nop 0
; GFX942-GISEL-NEXT: v_readfirstlane_b32 s1, v0
; GFX942-GISEL-NEXT: s_nop 1
; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3] neg_lo:[0,1] neg_hi:[0,1]
-; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX942-GISEL-NEXT: s_endpgm
;
; GFX1250-SDAG-LABEL: fadd_fadd_fsub:
@@ -3750,6 +3774,7 @@ define amdgpu_kernel void @fadd_fadd_fsub(<2 x float> %arg, <2 x float> %arg1, p
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
; GFX1250-SDAG-NEXT: s_add_f32 s2, s1, s3
+; GFX1250-SDAG-NEXT: ; implicit-def: $sgpr3
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_3)
; GFX1250-SDAG-NEXT: v_pk_add_f32 v[2:3], v[0:1], s[2:3] op_sel_hi:[1,0]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -3768,6 +3793,7 @@ define amdgpu_kernel void @fadd_fadd_fsub(<2 x float> %arg, <2 x float> %arg1, p
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
+; GFX1250-GISEL-NEXT: ; implicit-def: $sgpr3
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v1
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
index 4612401e8b82a..7cf43eb26383a 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
@@ -60,6 +60,7 @@ define amdgpu_cs half @v_s_exp_f16(half inreg %src) {
; GFX12-GISEL-LABEL: v_s_exp_f16:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_exp_f16_e32 v0.l, s0
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: v_s_exp_f16:
@@ -170,6 +171,7 @@ define amdgpu_cs half @v_s_log_f16(half inreg %src) {
; GFX12-GISEL-LABEL: v_s_log_f16:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_log_f16_e32 v0.l, s0
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: v_s_log_f16:
@@ -728,6 +730,7 @@ define amdgpu_cs half @srcmods_abs_f16(half inreg %src) {
; GFX12-GISEL-LABEL: srcmods_abs_f16:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_log_f16_e64 v0.l, |s0|
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: srcmods_abs_f16:
@@ -751,6 +754,7 @@ define amdgpu_cs half @srcmods_neg_f16(half inreg %src) {
; GFX12-GISEL-LABEL: srcmods_neg_f16:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_log_f16_e64 v0.l, -s0
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: srcmods_neg_f16:
@@ -797,6 +801,7 @@ define amdgpu_cs half @fdiv_f16_i16(half inreg %a, i16 inreg %b) {
; GFX12-GISEL-LABEL: fdiv_f16_i16:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_cvt_f16_u16_e32 v0.l, s1
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v0
; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll b/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll
index 4740a21ed1313..bc53a888f3eb3 100644
--- a/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll
+++ b/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll
@@ -6,42 +6,42 @@ define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
; CHECK: ; %bb.0: ; %main_body
; CHECK-NEXT: CALL_FS
; CHECK-NEXT: ALU 24, @12, KC0[CB0:0-32], KC1[]
-; CHECK-NEXT: EXPORT T0.XYZW
+; CHECK-NEXT: EXPORT T2.XYZW
; CHECK-NEXT: EXPORT T0.0000
; CHECK-NEXT: EXPORT T0.0000
-; CHECK-NEXT: EXPORT T4.0YZW
-; CHECK-NEXT: EXPORT T3.XYZW
-; CHECK-NEXT: EXPORT T2.XY00
+; CHECK-NEXT: EXPORT T3.0YZW
+; CHECK-NEXT: EXPORT T0.XYZW
+; CHECK-NEXT: EXPORT T1.XY00
; CHECK-NEXT: EXPORT T0.0000
; CHECK-NEXT: EXPORT T0.0000
; CHECK-NEXT: CF_END
; CHECK-NEXT: PAD
; CHECK-NEXT: ALU clause starting at 12:
-; CHECK-NEXT: MUL_IEEE * T0.W, KC0[4].X, T1.X,
-; CHECK-NEXT: MULADD_IEEE T0.W, KC0[5].X, T1.Y, PV.W,
-; CHECK-NEXT: MUL_IEEE * T2.W, KC0[4].Y, T1.X,
-; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[6].X, T1.Z, PV.W,
-; CHECK-NEXT: MULADD_IEEE T0.X, KC0[7].X, T1.W, PV.W,
-; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[5].Y, T1.Y, T2.W,
-; CHECK-NEXT: MUL_IEEE * T2.W, KC0[4].Z, T1.X,
-; CHECK-NEXT: MOV T2.Y, KC0[2].Z,
-; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[5].Z, T1.Y, PV.W,
-; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[6].Y, T1.Z, T0.W,
-; CHECK-NEXT: MOV T2.X, KC0[2].Y,
-; CHECK-NEXT: MULADD_IEEE * T0.Y, KC0[7].Y, T1.W, PV.W,
-; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[6].Z, T1.Z, T2.W,
-; CHECK-NEXT: MULADD_IEEE T0.Z, KC0[7].Z, T1.W, PV.W,
-; CHECK-NEXT: MUL_IEEE * T0.W, KC0[4].W, T1.X,
-; CHECK-NEXT: MOV * T3.W, KC0[2].X,
-; CHECK-NEXT: MOV T3.Z, KC0[3].Z,
-; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[5].W, T1.Y, T0.W,
-; CHECK-NEXT: MOV * T4.W, KC0[0].Z,
-; CHECK-NEXT: MOV T3.Y, KC0[3].Y,
-; CHECK-NEXT: MOV * T4.Z, KC0[0].Y,
-; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[6].W, T1.Z, T0.W,
-; CHECK-NEXT: MOV T3.X, KC0[3].X,
-; CHECK-NEXT: MOV * T4.Y, KC0[0].X,
-; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[7].W, T1.W, T0.W,
+; CHECK-NEXT: MOV * T0.W, KC0[2].X,
+; CHECK-NEXT: MOV * T0.Z, KC0[3].Z,
+; CHECK-NEXT: MOV T0.Y, KC0[3].Y,
+; CHECK-NEXT: MUL_IEEE * T2.W, KC0[4].X, T1.X,
+; CHECK-NEXT: MOV T0.X, KC0[3].X,
+; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[5].X, T1.Y, PV.W,
+; CHECK-NEXT: MUL_IEEE * T3.W, KC0[4].Y, T1.X,
+; CHECK-NEXT: MULADD_IEEE T2.Z, KC0[5].Y, T1.Y, PV.W,
+; CHECK-NEXT: MUL_IEEE * T3.W, KC0[4].Z, T1.X,
+; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[6].X, T1.Z, T2.W,
+; CHECK-NEXT: MULADD_IEEE T2.X, KC0[7].X, T1.W, PV.W,
+; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[5].Z, T1.Y, T3.W,
+; CHECK-NEXT: MULADD_IEEE * T3.W, KC0[6].Y, T1.Z, T2.Z,
+; CHECK-NEXT: MULADD_IEEE T2.Y, KC0[7].Y, T1.W, PV.W,
+; CHECK-NEXT: MUL_IEEE * T3.W, KC0[4].W, T1.X,
+; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[6].Z, T1.Z, T2.W,
+; CHECK-NEXT: MULADD_IEEE T2.Z, KC0[7].Z, T1.W, PV.W,
+; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[5].W, T1.Y, T3.W,
+; CHECK-NEXT: MOV * T3.W, KC0[0].Z,
+; CHECK-NEXT: MOV T1.Y, KC0[2].Z,
+; CHECK-NEXT: MOV * T3.Z, KC0[0].Y,
+; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[6].W, T1.Z, T2.W,
+; CHECK-NEXT: MOV T1.X, KC0[2].Y,
+; CHECK-NEXT: MOV * T3.Y, KC0[0].X,
+; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[7].W, T1.W, T2.W,
main_body:
%0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll b/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
index 74bd338c7c022..ad3e1c64a3eb1 100644
--- a/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
+++ b/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
@@ -4412,6 +4412,7 @@ define i64 @v_mul_9_add_52_i64(i64 %arg) {
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 9, 52
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 9, v[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4866,6 +4867,7 @@ define i64 @v_mul_5_add_1_i64(i64 %arg) {
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 5, 1
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 5, v[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4960,6 +4962,7 @@ define i64 @v_mul_284_add_82_i64(i64 %arg) {
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, s6, v[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -5057,6 +5060,7 @@ define i64 @v_mul_934584645_add_8234599_i64(i64 %arg) {
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, s6, v[4:5]
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -5273,6 +5277,7 @@ define amdgpu_kernel void @compute_mad(ptr addrspace(4) %i18, ptr addrspace(4) %
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s2, s2, 0xffff
; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v1
+; GFX10-NEXT: ; implicit-def: $vgpr1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s8, s2, v[0:1]
; GFX10-NEXT: v_mul_lo_u32 v1, v3, v2
; GFX10-NEXT: v_add_co_u32 v2, s0, s0, v0
@@ -5366,6 +5371,7 @@ define amdgpu_kernel void @compute_mad(ptr addrspace(4) %i18, ptr addrspace(4) %
; GFX13-NEXT: v_mul_lo_u32 v4, v2, v1
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX13-NEXT: v_add_nc_u32_e32 v3, v4, v1
+; GFX13-NEXT: ; implicit-def: $vgpr1
; GFX13-NEXT: v_mad_co_u64_u32 v[0:1], null, s5, s4, v[0:1]
; GFX13-NEXT: v_mul_lo_u32 v1, v3, v2
; GFX13-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
index 1f9c493d050e7..f02823f2a87d6 100644
--- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
+++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-unused-lanes.ll
@@ -9,53 +9,53 @@ define <7 x i32> @multiple_predecessor_unused_lanes(<7 x i32> %ha, i32 %h.sel) {
; CHECK-LABEL: multiple_predecessor_unused_lanes:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v16, v6
-; CHECK-NEXT: v_and_b32_e32 v6, 3, v7
+; CHECK-NEXT: v_and_b32_e32 v7, 3, v7
; CHECK-NEXT: s_mov_b32 s0, exec_lo
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; CHECK-NEXT: v_cmpx_lt_i32_e32 0, v6
+; CHECK-NEXT: v_cmpx_lt_i32_e32 0, v7
; CHECK-NEXT: s_xor_b32 s0, exec_lo, s0
; CHECK-NEXT: s_cbranch_execz .LBB0_6
; CHECK-NEXT: ; %bb.1: ; %LeafBlock
; CHECK-NEXT: s_mov_b32 s1, exec_lo
-; CHECK-NEXT: v_cmpx_ne_u32_e32 1, v6
+; CHECK-NEXT: v_cmpx_ne_u32_e32 1, v7
; CHECK-NEXT: s_xor_b32 s1, exec_lo, s1
; CHECK-NEXT: ; %bb.2: ; %h.default
; CHECK-NEXT: v_xor_b32_e32 v5, 1, v5
-; CHECK-NEXT: v_mov_b32_e32 v22, v6
-; CHECK-NEXT: v_dual_mov_b32 v20, v4 :: v_dual_mov_b32 v19, v3
-; CHECK-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v1
-; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; CHECK-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v16, v0
-; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; CHECK-NEXT: ; implicit-def: $vgpr6
+; CHECK-NEXT: v_mov_b32_e32 v12, v6
+; CHECK-NEXT: v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; CHECK-NEXT: v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
+; CHECK-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
; CHECK-NEXT: ; %bb.3: ; %Flow
; CHECK-NEXT: s_and_not1_saveexec_b32 s1, s1
; CHECK-NEXT: ; %bb.4: ; %h.shuffle
-; CHECK-NEXT: v_mov_b32_e32 v17, v0
-; CHECK-NEXT: v_mov_b32_e32 v18, v0
-; CHECK-NEXT: v_mov_b32_e32 v20, v0
+; CHECK-NEXT: v_mov_b32_e32 v7, v0
+; CHECK-NEXT: v_mov_b32_e32 v8, v0
+; CHECK-NEXT: v_mov_b32_e32 v10, v0
+; CHECK-NEXT: ; implicit-def: $vgpr11
+; CHECK-NEXT: ; implicit-def: $vgpr12
; CHECK-NEXT: ; %bb.5: ; %Flow1
; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; CHECK-NEXT: ; implicit-def: $vgpr1
; CHECK-NEXT: .LBB0_6: ; %Flow2
; CHECK-NEXT: s_and_not1_saveexec_b32 s0, s0
; CHECK-NEXT: s_cbranch_execz .LBB0_8
; CHECK-NEXT: ; %bb.7: ; %h.add
-; CHECK-NEXT: v_or_b32_e32 v22, 1, v16
-; CHECK-NEXT: v_or_b32_e32 v21, 1, v5
-; CHECK-NEXT: v_or_b32_e32 v20, 1, v4
-; CHECK-NEXT: v_or_b32_e32 v19, 1, v3
-; CHECK-NEXT: v_or_b32_e32 v18, 1, v2
-; CHECK-NEXT: v_or_b32_e32 v17, 1, v1
-; CHECK-NEXT: v_or_b32_e32 v16, 1, v0
+; CHECK-NEXT: v_or_b32_e32 v12, 1, v6
+; CHECK-NEXT: v_or_b32_e32 v11, 1, v5
+; CHECK-NEXT: v_or_b32_e32 v10, 1, v4
+; CHECK-NEXT: v_or_b32_e32 v9, 1, v3
+; CHECK-NEXT: v_or_b32_e32 v8, 1, v2
+; CHECK-NEXT: v_or_b32_e32 v7, 1, v1
+; CHECK-NEXT: v_or_b32_e32 v6, 1, v0
; CHECK-NEXT: .LBB0_8: ; %UnifiedReturnBlock
; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s0
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; CHECK-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
-; CHECK-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
-; CHECK-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
-; CHECK-NEXT: v_mov_b32_e32 v6, v22
+; CHECK-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; CHECK-NEXT: v_dual_mov_b32 v2, v8 :: v_dual_mov_b32 v3, v9
+; CHECK-NEXT: v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
+; CHECK-NEXT: v_mov_b32_e32 v6, v12
; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
%h.case = and i32 %h.sel, 3
diff --git a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
index 767c258e2ecbd..1ec852be09853 100644
--- a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
+++ b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
@@ -570,6 +570,7 @@ define <3 x half> @v_repeat_divisor_f16_x3_arcp(half %x, half %y, half %z, half
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v3.l, v3.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.l
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.h, v1.l, v3.l
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
index 5aa2cc713a4ec..dbc48294b6c2e 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
@@ -494,6 +494,10 @@ define void @test_rewrite_mfma_subreg_insert0(float %arg0, float %arg1, ptr addr
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: global_load_dwordx4 a[0:3], v[2:3], off
+; CHECK-NEXT: ; implicit-def: $agpr4
+; CHECK-NEXT: ; implicit-def: $agpr5
+; CHECK-NEXT: ; implicit-def: $agpr6
+; CHECK-NEXT: ; implicit-def: $agpr7
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v1, a[0:3]
; CHECK-NEXT: ;;#ASMSTART
@@ -513,6 +517,11 @@ define void @test_rewrite_mfma_subreg_insert1(float %arg0, float %arg1, ptr addr
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: global_load_dwordx4 v[2:5], v[2:3], off
+; CHECK-NEXT: ; implicit-def: $agpr3
+; CHECK-NEXT: ; implicit-def: $agpr4
+; CHECK-NEXT: ; implicit-def: $agpr5
+; CHECK-NEXT: ; implicit-def: $agpr6
+; CHECK-NEXT: ; implicit-def: $agpr7
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v0, v1, v[2:5]
; CHECK-NEXT: s_nop 3
@@ -536,6 +545,8 @@ define void @test_rewrite_mfma_subreg_insert2(double %arg0, double %arg1, ptr ad
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: global_load_dwordx2 a[0:1], v[4:5], off
+; CHECK-NEXT: ; implicit-def: $agpr2
+; CHECK-NEXT: ; implicit-def: $agpr3
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mfma_f64_4x4x4_4b_f64 a[0:1], v[0:1], v[2:3], a[0:1]
; CHECK-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/roundeven.ll b/llvm/test/CodeGen/AMDGPU/roundeven.ll
index 44c860bd64033..2df66c4a57dfc 100644
--- a/llvm/test/CodeGen/AMDGPU/roundeven.ll
+++ b/llvm/test/CodeGen/AMDGPU/roundeven.ll
@@ -369,6 +369,7 @@ define half @v_roundeven_f16(half %x) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rndne_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_roundeven_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
index 71d76034778b7..612fbdef88c56 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
@@ -194,11 +194,13 @@ define amdgpu_vs half @frint_f16(half inreg %val) {
; GISEL-GFX11-LABEL: frint_f16:
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: v_rndne_f16_e32 v0.l, s0
+; GISEL-GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-NEXT: ; return to shader part epilog
;
; GISEL-GFX12-LABEL: frint_f16:
; GISEL-GFX12: ; %bb.0:
; GISEL-GFX12-NEXT: v_rndne_f16_e32 v0.l, s0
+; GISEL-GFX12-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-NEXT: ; return to shader part epilog
%res = call half @llvm.rint.f16(half %val)
ret half %res
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
index 40634bb5ad2e9..2363f0a67c96e 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
@@ -236,6 +236,7 @@ define amdgpu_kernel void @scalar_to_vector_v4i16() {
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: buffer_load_d16_u8 v0, off, s[0:3], 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
@@ -322,24 +323,23 @@ define amdgpu_kernel void @scalar_to_vector_v4f16() {
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-NEXT: buffer_load_d16_u8 v0, off, s[0:3], 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: ; kill: def $vgpr1_hi16 killed $sgpr0 killed $exec
-; GFX11-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: s_and_b32 s1, s0, 0xff00
; GFX11-NEXT: s_bfe_u32 s4, s0, 0x80008
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
; GFX11-NEXT: s_or_b32 s1, s4, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshl_b32 s4, s1, 16
; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
; GFX11-NEXT: s_or_b32 s0, s0, s4
; GFX11-NEXT: s_or_b32 s1, s1, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
index c253f42e0d3c8..66939a765a121 100644
--- a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
+++ b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
@@ -607,6 +607,10 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -622,30 +626,29 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -718,6 +721,7 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
@@ -726,14 +730,17 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
@@ -756,11 +763,9 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-NEXT: ; return to shader part epilog
;
; GFX9-FLATSCR-PAL-LABEL: ps_main:
@@ -784,6 +789,10 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -799,30 +808,29 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -900,6 +908,7 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
@@ -908,14 +917,17 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, v12
@@ -938,11 +950,9 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-PAL-NEXT: ; return to shader part epilog
;
; GFX11-FLATSCR-LABEL: ps_main:
@@ -957,16 +967,15 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:320
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v26, 0x3f5f2ee2
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v19, 0xbefcd89f :: v_dual_mov_b32 v30, v27
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v19, 0xbefcd89f
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
-; GFX11-FLATSCR-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, 0x3f638e37 :: v_dual_mov_b32 v4, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, 0x3f638e37
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, 0xbf523be3
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v17, 0xbeae29dc
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v4, v26 :: v_dual_mov_b32 v17, 0xbeae29dc
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[25:28], off offset:304
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:288
@@ -976,37 +985,42 @@ define amdgpu_ps float @ps_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3efcd89c
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v18, v17 :: v_dual_and_b32 v33, 0x1fc, v0
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, 0xbefcd8a3 :: v_dual_mov_b32 v15, v11
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, 0xbe31934f :: v_dual_mov_b32 v31, v11
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xb702e758
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[6:9], off offset:240
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[11:14], off offset:224
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v14, 0x3f20e7f5 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v0, 0xb702e758 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0x3f20e7f4
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr30
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX11-FLATSCR-NEXT: s_clause 0x3
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[17:20], off offset:272
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[0:3], off offset:256
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[21:24], off offset:208
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:192
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, 0x3f20e7f4
; GFX11-FLATSCR-NEXT: scratch_load_b32 v0, v33, off
+; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:832
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0xbf523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v32, 0x3f3d349c
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, v21
-; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[4:7], off offset:832
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v7, 0x3703c499 :: v_dual_mov_b32 v16, v28
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v16, v28 :: v_dual_mov_b32 v31, v11
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, v21 :: v_dual_mov_b32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v14, v17
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v13, v19
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v14, v17
; GFX11-FLATSCR-NEXT: s_clause 0x4
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[7:10], off offset:816
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[18:21], off offset:800
@@ -1611,6 +1625,10 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -1626,30 +1644,29 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -1722,6 +1739,7 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
@@ -1730,14 +1748,17 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
@@ -1760,11 +1781,9 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-NEXT: ; return to shader part epilog
;
; GFX9-FLATSCR-PAL-LABEL: vs_main:
@@ -1788,6 +1807,10 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -1803,30 +1826,29 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -1904,6 +1926,7 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
@@ -1912,14 +1935,17 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, v12
@@ -1942,11 +1968,9 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-PAL-NEXT: ; return to shader part epilog
;
; GFX11-FLATSCR-LABEL: vs_main:
@@ -1961,16 +1985,15 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:320
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v26, 0x3f5f2ee2
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v19, 0xbefcd89f :: v_dual_mov_b32 v30, v27
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v19, 0xbefcd89f
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
-; GFX11-FLATSCR-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, 0x3f638e37 :: v_dual_mov_b32 v4, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, 0x3f638e37
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, 0xbf523be3
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v17, 0xbeae29dc
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v4, v26 :: v_dual_mov_b32 v17, 0xbeae29dc
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[25:28], off offset:304
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:288
@@ -1980,37 +2003,42 @@ define amdgpu_vs float @vs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3efcd89c
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v18, v17 :: v_dual_and_b32 v33, 0x1fc, v0
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, 0xbefcd8a3 :: v_dual_mov_b32 v15, v11
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, 0xbe31934f :: v_dual_mov_b32 v31, v11
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xb702e758
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[6:9], off offset:240
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[11:14], off offset:224
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v14, 0x3f20e7f5 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v0, 0xb702e758 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0x3f20e7f4
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr30
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX11-FLATSCR-NEXT: s_clause 0x3
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[17:20], off offset:272
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[0:3], off offset:256
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[21:24], off offset:208
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:192
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, 0x3f20e7f4
; GFX11-FLATSCR-NEXT: scratch_load_b32 v0, v33, off
+; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:832
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0xbf523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v32, 0x3f3d349c
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, v21
-; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[4:7], off offset:832
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v7, 0x3703c499 :: v_dual_mov_b32 v16, v28
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v16, v28 :: v_dual_mov_b32 v31, v11
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, v21 :: v_dual_mov_b32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v14, v17
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v13, v19
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v14, v17
; GFX11-FLATSCR-NEXT: s_clause 0x4
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[7:10], off offset:816
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[18:21], off offset:800
@@ -2602,84 +2630,87 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX9-FLATSCR-LABEL: cs_main:
; GFX9-FLATSCR: ; %bb.0:
; GFX9-FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s0, s2
+; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, 0xbf20e7f4
+; GFX9-FLATSCR-NEXT: v_and_b32_e32 v9, 0x1fc, v0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xbf20e7f4
; GFX9-FLATSCR-NEXT: s_mov_b32 s0, 0
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x3f5f2ee2
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0x3f523be1
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
-; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:320
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v21, 0xbeae29dc
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, v3
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, v2
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, v1
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0x3eae29d8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0x3e319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0x3e31934f
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, 0xbf3d349e
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, 0xbf20e7f5
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v17, 0x3efcd89f
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v18, 0x3efcd89c
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v26, 0xbf5f2ee3
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v29, 0xbf523be3
-; GFX9-FLATSCR-NEXT: v_and_b32_e32 v31, 0x1fc, v0
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f638e37
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:288
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbefcd89f
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, 0xbefcd8a3
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v22, v21
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, 0xb702e758
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, 0xb7043519
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0xbe31934f
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0xbe319356
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:240
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[15:18], s0 offset:224
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v27, 0xbf638e39
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v28, v26
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v18, 0x3f20e7f5
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v19, v15
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v20, v29
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0x3703c499
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:304
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[21:24], s0 offset:272
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:256
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:208
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:192
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v31
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, v11
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, v12
-; GFX9-FLATSCR-NEXT: scratch_load_dword v32, v4, off
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v25, v7
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[7:10], s0 offset:720
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, 0xbf523be1
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3f3d349c
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, v2
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, v15
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v20, v3
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, v10
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3f5f2ee2
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3f523be1
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3f3d349e
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:320
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, 0x3eae29dc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v7
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v6
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:288
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v17, 0x3eae29d8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xbeae29dc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v18, 0x3e319356
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v19, 0x3e31934f
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v21, 0xbf3d349e
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf20e7f5
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, 0x3efcd89f
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, 0x3efcd89c
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v27, 0xbf5f2ee3
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v30, 0xbf523be3
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, 0x3f638e37
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 0xbefcd8a3
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v10, 0xb702e758
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xb7043519
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0xbe31934f
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0xbe319356
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[16:19], s0 offset:240
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[21:24], s0 offset:224
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v28, 0xbf638e39
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v29, v27
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, 0x3f20e7f5
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v25, v21
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v26, v30
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v17, 0x3703c499
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[5:8], s0 offset:304
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:272
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:256
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[27:30], s0 offset:208
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[23:26], s0 offset:192
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v9
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v14, v17
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v28, v0
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v29, v26
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v30, v1
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:784
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v22, v16
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0xbf5f2ee2
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, v1
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, v21
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:736
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:816
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v17, v23
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v18, v21
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[27:30], s0 offset:768
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:752
-; GFX9-FLATSCR-NEXT: v_add_u32_e32 v0, 0x200, v31
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:800
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[15:18], s0 offset:704
-; GFX9-FLATSCR-NEXT: scratch_load_dword v0, v0, off
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, v18
+; GFX9-FLATSCR-NEXT: scratch_load_dword v32, v1, off
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v13
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:720
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v10, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr11
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr12
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr13
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:832
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v26, v8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v10, 0xbf523be1
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0x3f3d349c
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, v7
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, v21
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v19, v16
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v20, v23
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v29, v5
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v31, v6
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:784
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v22
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0xbf5f2ee2
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, v6
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[23:26], s0 offset:736
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:816
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, v2
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, v0
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[28:31], s0 offset:768
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:752
+; GFX9-FLATSCR-NEXT: v_add_u32_e32 v5, 0x200, v9
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[1:4], s0 offset:800
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[21:24], s0 offset:704
+; GFX9-FLATSCR-NEXT: scratch_load_dword v0, v5, off
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: v_add_f32_e32 v0, v32, v0
; GFX9-FLATSCR-NEXT: ; return to shader part epilog
@@ -2726,6 +2757,7 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
@@ -2734,14 +2766,17 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
@@ -2764,11 +2799,9 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-NEXT: ; return to shader part epilog
;
; GFX9-FLATSCR-PAL-LABEL: cs_main:
@@ -2776,87 +2809,90 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-FLATSCR-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-FLATSCR-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x10
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, 0xbf20e7f4
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, 0x3f5f2ee2
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, 0x3f523be1
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
+; GFX9-FLATSCR-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-FLATSCR-PAL-NEXT: v_and_b32_e32 v9, 0x1fc, v0
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0xbf20e7f4
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3f5f2ee2
; GFX9-FLATSCR-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-FLATSCR-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-FLATSCR-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s0
; GFX9-FLATSCR-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-FLATSCR-PAL-NEXT: s_mov_b32 s0, 0
-; GFX9-FLATSCR-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:320
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v21, 0xbeae29dc
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, v3
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, v2
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, v1
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0x3eae29d8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0x3e319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0x3e31934f
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, 0xbf3d349e
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, 0xbf20e7f5
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v17, 0x3efcd89f
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, 0x3efcd89c
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v26, 0xbf5f2ee3
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v29, 0xbf523be3
-; GFX9-FLATSCR-PAL-NEXT: v_and_b32_e32 v31, 0x1fc, v0
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f638e37
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:288
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbefcd89f
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, 0xbefcd8a3
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v22, v21
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, 0xb702e758
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, 0xb7043519
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0xbe31934f
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0xbe319356
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:240
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[15:18], s0 offset:224
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v27, 0xbf638e39
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v28, v26
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, 0x3f20e7f5
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v19, v15
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v20, v29
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0x3703c499
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:304
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[21:24], s0 offset:272
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:256
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:208
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:192
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, v31
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, v11
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, v12
-; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v32, v4, off
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v25, v7
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[7:10], s0 offset:720
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, 0xbf523be1
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3f3d349c
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, v2
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, v15
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v20, v3
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, v10
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3f523be1
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3f3d349e
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:320
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, 0x3eae29dc
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, v7
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, v6
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:288
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v17, 0x3eae29d8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0xbeae29dc
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, 0x3e319356
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v19, 0x3e31934f
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v21, 0xbf3d349e
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v22, 0xbf20e7f5
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0x3efcd89f
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, 0x3efcd89c
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v27, 0xbf5f2ee3
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0xbf523be3
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, 0x3f638e37
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, 0xbefcd8a3
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v0
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, 0xb702e758
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0xb7043519
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0xbe31934f
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0xbe319356
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[16:19], s0 offset:240
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[21:24], s0 offset:224
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v28, 0xbf638e39
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v29, v27
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, 0x3f20e7f5
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v25, v21
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v26, v30
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v17, 0x3703c499
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[5:8], s0 offset:304
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:272
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:256
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[27:30], s0 offset:208
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[23:26], s0 offset:192
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v9
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, v17
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v28, v0
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v29, v26
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, v1
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:784
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v22, v16
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0xbf5f2ee2
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, v1
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v21
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:736
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:816
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v17, v23
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, v21
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[27:30], s0 offset:768
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[4:7], s0 offset:752
-; GFX9-FLATSCR-PAL-NEXT: v_add_u32_e32 v0, 0x200, v31
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:800
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[15:18], s0 offset:704
-; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v0, v0, off
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v18
+; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v32, v1, off
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, v13
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:720
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr11
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr12
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr13
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:832
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v26, v8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, 0xbf523be1
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0x3f3d349c
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, v7
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, v21
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v19, v16
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v20, v23
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v29, v5
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, v27
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v31, v6
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:784
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v22
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0xbf5f2ee2
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, v6
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, v0
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[23:26], s0 offset:736
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:816
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, v2
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v0
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[28:31], s0 offset:768
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[10:13], s0 offset:752
+; GFX9-FLATSCR-PAL-NEXT: v_add_u32_e32 v5, 0x200, v9
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[1:4], s0 offset:800
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[21:24], s0 offset:704
+; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v0, v5, off
; GFX9-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v32, v0
; GFX9-FLATSCR-PAL-NEXT: ; return to shader part epilog
@@ -2908,6 +2944,7 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
@@ -2916,14 +2953,17 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, v12
@@ -2946,11 +2986,9 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-PAL-NEXT: ; return to shader part epilog
;
; GFX11-FLATSCR-LABEL: cs_main:
@@ -2965,16 +3003,15 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:320
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v26, 0x3f5f2ee2
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v19, 0xbefcd89f :: v_dual_mov_b32 v30, v27
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v19, 0xbefcd89f
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
-; GFX11-FLATSCR-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, 0x3f638e37 :: v_dual_mov_b32 v4, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, 0x3f638e37
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, 0xbf523be3
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v17, 0xbeae29dc
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v4, v26 :: v_dual_mov_b32 v17, 0xbeae29dc
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[25:28], off offset:304
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:288
@@ -2984,37 +3021,42 @@ define amdgpu_cs float @cs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3efcd89c
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v18, v17 :: v_dual_and_b32 v33, 0x1fc, v0
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, 0xbefcd8a3 :: v_dual_mov_b32 v15, v11
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, 0xbe31934f :: v_dual_mov_b32 v31, v11
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xb702e758
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[6:9], off offset:240
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[11:14], off offset:224
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v14, 0x3f20e7f5 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v0, 0xb702e758 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0x3f20e7f4
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr30
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX11-FLATSCR-NEXT: s_clause 0x3
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[17:20], off offset:272
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[0:3], off offset:256
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[21:24], off offset:208
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:192
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, 0x3f20e7f4
; GFX11-FLATSCR-NEXT: scratch_load_b32 v0, v33, off
+; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:832
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0xbf523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v32, 0x3f3d349c
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, v21
-; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[4:7], off offset:832
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v7, 0x3703c499 :: v_dual_mov_b32 v16, v28
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v16, v28 :: v_dual_mov_b32 v31, v11
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, v21 :: v_dual_mov_b32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v14, v17
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v13, v19
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v14, v17
; GFX11-FLATSCR-NEXT: s_clause 0x4
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[7:10], off offset:816
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[18:21], off offset:800
@@ -3616,6 +3658,10 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -3631,30 +3677,29 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -3727,6 +3772,7 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
@@ -3735,14 +3781,17 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
@@ -3765,11 +3814,9 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-NEXT: ; return to shader part epilog
;
; GFX9-FLATSCR-PAL-LABEL: hs_main:
@@ -3793,6 +3840,10 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -3808,30 +3859,29 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -3909,6 +3959,7 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
@@ -3917,14 +3968,17 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, v12
@@ -3947,11 +4001,9 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-PAL-NEXT: ; return to shader part epilog
;
; GFX11-FLATSCR-LABEL: hs_main:
@@ -3966,16 +4018,15 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:320
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v26, 0x3f5f2ee2
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v19, 0xbefcd89f :: v_dual_mov_b32 v30, v27
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v19, 0xbefcd89f
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
-; GFX11-FLATSCR-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, 0x3f638e37 :: v_dual_mov_b32 v4, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, 0x3f638e37
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, 0xbf523be3
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v17, 0xbeae29dc
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v4, v26 :: v_dual_mov_b32 v17, 0xbeae29dc
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[25:28], off offset:304
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:288
@@ -3985,37 +4036,42 @@ define amdgpu_hs float @hs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3efcd89c
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v18, v17 :: v_dual_and_b32 v33, 0x1fc, v0
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, 0xbefcd8a3 :: v_dual_mov_b32 v15, v11
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, 0xbe31934f :: v_dual_mov_b32 v31, v11
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xb702e758
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[6:9], off offset:240
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[11:14], off offset:224
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v14, 0x3f20e7f5 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v0, 0xb702e758 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0x3f20e7f4
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr30
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX11-FLATSCR-NEXT: s_clause 0x3
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[17:20], off offset:272
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[0:3], off offset:256
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[21:24], off offset:208
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:192
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, 0x3f20e7f4
; GFX11-FLATSCR-NEXT: scratch_load_b32 v0, v33, off
+; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:832
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0xbf523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v32, 0x3f3d349c
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, v21
-; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[4:7], off offset:832
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v7, 0x3703c499 :: v_dual_mov_b32 v16, v28
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v16, v28 :: v_dual_mov_b32 v31, v11
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, v21 :: v_dual_mov_b32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v14, v17
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v13, v19
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v14, v17
; GFX11-FLATSCR-NEXT: s_clause 0x4
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[7:10], off offset:816
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[18:21], off offset:800
@@ -4617,6 +4673,10 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -4632,30 +4692,29 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -4728,6 +4787,7 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
@@ -4736,14 +4796,17 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
@@ -4766,11 +4829,9 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-NEXT: ; return to shader part epilog
;
; GFX9-FLATSCR-PAL-LABEL: gs_main:
@@ -4794,6 +4855,10 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -4809,30 +4874,29 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -4910,6 +4974,7 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
@@ -4918,14 +4983,17 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, v12
@@ -4948,11 +5016,9 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-PAL-NEXT: ; return to shader part epilog
;
; GFX11-FLATSCR-LABEL: gs_main:
@@ -4967,16 +5033,15 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:320
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v26, 0x3f5f2ee2
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v19, 0xbefcd89f :: v_dual_mov_b32 v30, v27
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v19, 0xbefcd89f
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
-; GFX11-FLATSCR-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, 0x3f638e37 :: v_dual_mov_b32 v4, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v25, 0x3f638e37
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, 0xbf523be3
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v17, 0xbeae29dc
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v4, v26 :: v_dual_mov_b32 v17, 0xbeae29dc
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[25:28], off offset:304
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:288
@@ -4986,37 +5051,42 @@ define amdgpu_gs float @gs_main(i32 %idx) {
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3efcd89c
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v18, v17 :: v_dual_and_b32 v33, 0x1fc, v0
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, 0xbefcd8a3 :: v_dual_mov_b32 v15, v11
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, 0xbe31934f :: v_dual_mov_b32 v31, v11
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xb702e758
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[6:9], off offset:240
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[11:14], off offset:224
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v14, 0x3f20e7f5 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v0, 0xb702e758 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0x3f20e7f4
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr30
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX11-FLATSCR-NEXT: s_clause 0x3
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[17:20], off offset:272
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[0:3], off offset:256
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[21:24], off offset:208
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:192
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, 0x3f20e7f4
; GFX11-FLATSCR-NEXT: scratch_load_b32 v0, v33, off
+; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:832
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0xbf523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v32, 0x3f3d349c
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, v21
-; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[4:7], off offset:832
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v7, 0x3703c499 :: v_dual_mov_b32 v16, v28
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v16, v28 :: v_dual_mov_b32 v31, v11
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, v21 :: v_dual_mov_b32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v14, v17
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v13, v19
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v14, v17
; GFX11-FLATSCR-NEXT: s_clause 0x4
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[7:10], off offset:816
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[18:21], off offset:800
@@ -5627,6 +5697,10 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -5642,30 +5716,29 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -5739,6 +5812,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
@@ -5747,14 +5821,17 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
@@ -5777,12 +5854,10 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-NEXT: s_mov_b32 s2, s7
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-NEXT: ; return to shader part epilog
;
; GFX9-FLATSCR-PAL-LABEL: hs_ir_uses_scratch_offset:
@@ -5806,6 +5881,10 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -5821,30 +5900,29 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -5923,6 +6001,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
@@ -5931,14 +6010,17 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, v12
@@ -5961,34 +6043,31 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-PAL-NEXT: s_mov_b32 s2, s5
; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-PAL-NEXT: ; return to shader part epilog
;
; GFX11-FLATSCR-LABEL: hs_ir_uses_scratch_offset:
; GFX11-FLATSCR: ; %bb.0:
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xbf20e7f4 :: v_dual_lshlrev_b32 v0, 2, v0
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v28, 0x3f3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v27, 0x3f523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, 0xbf5f2ee3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v27, 0x3f523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v26, 0x3f5f2ee2
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:320
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, v28 :: v_dual_mov_b32 v19, 0xbefcd89f
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, 0xbf523be3 :: v_dual_mov_b32 v23, v21
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, 0x3f638e37 :: v_dual_mov_b32 v4, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
; GFX11-FLATSCR-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v17, 0xbeae29dc :: v_dual_mov_b32 v16, v24
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[25:28], off offset:304
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:288
@@ -5998,37 +6077,42 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3efcd89c
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v18, v17 :: v_dual_and_b32 v33, 0x1fc, v0
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, 0xbefcd8a3 :: v_dual_mov_b32 v15, v11
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, 0xbe31934f :: v_dual_mov_b32 v31, v11
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xb702e758
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[6:9], off offset:240
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[11:14], off offset:224
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v14, 0x3f20e7f5 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v0, 0xb702e758 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0x3f20e7f4
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr30
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX11-FLATSCR-NEXT: s_clause 0x3
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[17:20], off offset:272
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[0:3], off offset:256
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[21:24], off offset:208
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:192
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, 0x3f20e7f4
; GFX11-FLATSCR-NEXT: scratch_load_b32 v0, v33, off
+; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:832
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0xbf523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v32, 0x3f3d349c
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, v21
-; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[4:7], off offset:832
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v7, 0x3703c499 :: v_dual_mov_b32 v16, v28
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v16, v28 :: v_dual_mov_b32 v31, v11
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, v21 :: v_dual_mov_b32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v14, v17
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v13, v19
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v14, v17
; GFX11-FLATSCR-NEXT: s_clause 0x4
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[7:10], off offset:816
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[18:21], off offset:800
@@ -6638,6 +6722,10 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -6653,30 +6741,29 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -6750,6 +6837,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v15, v11
@@ -6758,14 +6846,17 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
@@ -6788,12 +6879,10 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-NEXT: s_mov_b32 s2, s7
; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-NEXT: ; return to shader part epilog
;
; GFX9-FLATSCR-PAL-LABEL: gs_ir_uses_scratch_offset:
@@ -6817,6 +6906,10 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, v28
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, v27
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v13, 0x3efcd89f
@@ -6832,30 +6925,29 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v1, 0xb7043519
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v2, 0xbe31934f
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v3, 0xbe319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v8, 0x3e319356
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], s0 offset:224
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v25
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[26:29], s0 offset:304
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[17:20], s0 offset:272
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:256
-; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], s0 offset:240
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], s0 offset:208
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], s0 offset:192
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, v30
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
-; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v4, v7
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: scratch_load_dword v31, v0, off
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v21, v3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], s0 offset:720
+; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr1
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr2
+; GFX9-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr3
; GFX9-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:832
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
; GFX9-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0xbf523be1
@@ -6934,6 +7026,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v23, 0xbf638e39
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v24, v22
+; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:224
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v15, v11
@@ -6942,14 +7035,17 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[6:9], off offset:240
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[22:25], off offset:208
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[13:16], off offset:192
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v5, off
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr31
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr32
+; GFX10-FLATSCR-PAL-NEXT: ; implicit-def: $vgpr33
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v5, off
+; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:832
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v30, 0xbf523be1
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v33, 0x3f3d349c
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v31, v28
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v32, v11
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v7, 0x3703c499
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v16, v29
-; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v0, 0x3f20e7f4
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v9, v6
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v10, v13
; GFX10-FLATSCR-PAL-NEXT: v_mov_b32_e32 v18, v12
@@ -6972,34 +7068,31 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[30:33], off offset:752
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[3:6], off offset:720
; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[11:14], off offset:704
+; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v1, v34, off
; GFX10-FLATSCR-PAL-NEXT: s_mov_b32 s2, s5
; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:832
-; GFX10-FLATSCR-PAL-NEXT: scratch_load_dword v0, v34, off
-; GFX10-FLATSCR-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-FLATSCR-PAL-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-FLATSCR-PAL-NEXT: ; return to shader part epilog
;
; GFX11-FLATSCR-LABEL: gs_ir_uses_scratch_offset:
; GFX11-FLATSCR: ; %bb.0:
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xbf20e7f4 :: v_dual_lshlrev_b32 v0, 2, v0
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v28, 0x3f3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v27, 0x3f523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v21, 0xbf5f2ee3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v27, 0x3f523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v26, 0x3f5f2ee2
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:320
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, v28 :: v_dual_mov_b32 v19, 0xbefcd89f
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, 0xbf523be3 :: v_dual_mov_b32 v23, v21
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, 0x3f638e37 :: v_dual_mov_b32 v4, v26
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v3, v27
; GFX11-FLATSCR-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v17, 0xbeae29dc :: v_dual_mov_b32 v16, v24
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3eae29d8
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v8, 0x3e319356
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v9, 0x3e31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v11, 0xbf3d349e
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v6, 0x3eae29dc
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[25:28], off offset:304
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[1:4], off offset:288
@@ -7009,37 +7102,42 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3efcd89c
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v18, v17 :: v_dual_and_b32 v33, 0x1fc, v0
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, 0xbefcd8a3 :: v_dual_mov_b32 v15, v11
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v2, 0xbe31934f :: v_dual_mov_b32 v31, v11
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v0, 0xb702e758
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[6:9], off offset:240
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[11:14], off offset:224
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v14, 0x3f20e7f5 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x3703c499
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v0, 0xb702e758 :: v_dual_mov_b32 v9, v6
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v1, 0xb7043519 :: v_dual_mov_b32 v10, v13
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v2, 0xbe31934f
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0x3f20e7f4
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v22, 0xbf638e39
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr30
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr31
+; GFX11-FLATSCR-NEXT: ; implicit-def: $vgpr32
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
; GFX11-FLATSCR-NEXT: s_clause 0x3
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[17:20], off offset:272
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[0:3], off offset:256
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[21:24], off offset:208
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:192
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, 0x3f20e7f4
; GFX11-FLATSCR-NEXT: scratch_load_b32 v0, v33, off
+; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:832
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v29, 0xbf523be1
; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v32, 0x3f3d349c
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v24, v21
-; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[4:7], off offset:832
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v7, 0x3703c499 :: v_dual_mov_b32 v16, v28
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v30, v27
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v16, v28 :: v_dual_mov_b32 v31, v11
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v24, v21 :: v_dual_mov_b32 v25, v26
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v18, v12
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:784
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v31, 0xbf5f2ee2 :: v_dual_mov_b32 v32, v26
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v23, v25
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v18, v12
; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v20, v17 :: v_dual_mov_b32 v21, v3
+; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v5, v8
; GFX11-FLATSCR-NEXT: s_clause 0x1
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[29:32], off offset:752
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[13:16], off offset:736
-; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v5, v8 :: v_dual_mov_b32 v14, v17
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FLATSCR-NEXT: v_mov_b32_e32 v13, v19
+; GFX11-FLATSCR-NEXT: v_dual_mov_b32 v13, v19 :: v_dual_mov_b32 v14, v17
; GFX11-FLATSCR-NEXT: s_clause 0x4
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[7:10], off offset:816
; GFX11-FLATSCR-NEXT: scratch_store_b128 off, v[18:21], off offset:800
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
index fa705fb455ba8..4055efcef3367 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
@@ -2014,6 +2014,7 @@ define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 {
; NOSDWA: ; %bb.0: ; %bb
; NOSDWA-NEXT: s_mov_b32 s0, 0xffff
; NOSDWA-NEXT: s_and_b64 vcc, exec, -1
+; NOSDWA-NEXT: ; implicit-def: $vgpr1
; NOSDWA-NEXT: .LBB21_1: ; %bb1
; NOSDWA-NEXT: ; =>This Inner Loop Header: Depth=1
; NOSDWA-NEXT: ;;#ASMSTART
@@ -2031,6 +2032,7 @@ define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 {
; GFX89: ; %bb.0: ; %bb
; GFX89-NEXT: s_mov_b32 s0, 0xffff
; GFX89-NEXT: s_and_b64 vcc, exec, -1
+; GFX89-NEXT: ; implicit-def: $vgpr1
; GFX89-NEXT: .LBB21_1: ; %bb1
; GFX89-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX89-NEXT: ;;#ASMSTART
@@ -2048,6 +2050,7 @@ define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 {
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b64 vcc, exec, -1
+; GFX9-NEXT: ; implicit-def: $vgpr1
; GFX9-NEXT: .LBB21_1: ; %bb1
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: ;;#ASMSTART
@@ -2065,6 +2068,7 @@ define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 {
; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_mov_b32 s0, 0xffff
; GFX10-NEXT: s_mov_b32 vcc_lo, exec_lo
+; GFX10-NEXT: ; implicit-def: $vgpr1
; GFX10-NEXT: .LBB21_1: ; %bb1
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll b/llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
index e589a6341ea0e..702c3007b9c64 100644
--- a/llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
+++ b/llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
@@ -27,6 +27,7 @@ define amdgpu_kernel void @sext_i16_to_i64_uniform(ptr addrspace(1) %out, i16 %a
; GCN-NEXT: s_load_dword s6, s[4:5], 0xb
; GCN-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GCN-NEXT: ; implicit-def: $sgpr7
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll b/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
index 6f48e4d6e2dd2..1c7af65d36004 100644
--- a/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
@@ -8,6 +8,8 @@ define amdgpu_kernel void @v_sext_in_reg_i8_i16_shuffle_vector(ptr addrspace(1)
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v0, s[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
index 287d1dde21403..7160e8eb1c5af 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v2f32.ll
@@ -58,11 +58,12 @@ define void @v_shuffle_v2f32_v2f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v2f32__1_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +75,7 @@ define void @v_shuffle_v2f32_v2f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2f32_v2f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -110,11 +113,12 @@ define void @v_shuffle_v2f32_v2f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v2f32__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -126,6 +130,7 @@ define void @v_shuffle_v2f32_v2f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -138,6 +143,7 @@ define void @v_shuffle_v2f32_v2f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -353,24 +359,27 @@ define void @v_shuffle_v2f32_v2f32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2f32_v2f32__u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2f32_v2f32__u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -478,24 +487,27 @@ define void @v_shuffle_v2f32_v2f32__2_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2f32_v2f32__2_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2f32_v2f32__2_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -717,11 +729,12 @@ define void @v_shuffle_v2f32_v2f32__1_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v2f32__1_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -733,6 +746,7 @@ define void @v_shuffle_v2f32_v2f32__1_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -745,6 +759,7 @@ define void @v_shuffle_v2f32_v2f32__1_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1012,6 +1027,7 @@ define void @s_shuffle_v2f32_v2f32__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1024,6 +1040,7 @@ define void @s_shuffle_v2f32_v2f32__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1036,6 +1053,7 @@ define void @s_shuffle_v2f32_v2f32__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1068,6 +1086,7 @@ define void @s_shuffle_v2f32_v2f32__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1080,6 +1099,7 @@ define void @s_shuffle_v2f32_v2f32__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1092,6 +1112,7 @@ define void @s_shuffle_v2f32_v2f32__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1283,6 +1304,7 @@ define void @s_shuffle_v2f32_v2f32__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1295,6 +1317,7 @@ define void @s_shuffle_v2f32_v2f32__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1307,6 +1330,7 @@ define void @s_shuffle_v2f32_v2f32__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1388,6 +1412,7 @@ define void @s_shuffle_v2f32_v2f32__2_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1400,6 +1425,7 @@ define void @s_shuffle_v2f32_v2f32__2_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1412,6 +1438,7 @@ define void @s_shuffle_v2f32_v2f32__2_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1622,6 +1649,7 @@ define void @s_shuffle_v2f32_v2f32__1_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1634,6 +1662,7 @@ define void @s_shuffle_v2f32_v2f32__1_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1646,6 +1675,7 @@ define void @s_shuffle_v2f32_v2f32__1_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
index d5998e289c09d..f1940bfaf32ef 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v3f32.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2f32_v3f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2f32_v3f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2f32_v3f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +102,36 @@ define void @v_shuffle_v2f32_v3f32__2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v3f32__2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2f32_v3f32__2_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2f32_v3f32__2_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -153,6 +159,7 @@ define void @v_shuffle_v2f32_v3f32__4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -165,6 +172,7 @@ define void @v_shuffle_v2f32_v3f32__4_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -177,6 +185,7 @@ define void @v_shuffle_v2f32_v3f32__4_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -191,33 +200,36 @@ define void @v_shuffle_v2f32_v3f32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v3f32__5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2f32_v3f32__5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2f32_v3f32__5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -527,24 +539,27 @@ define void @v_shuffle_v2f32_v3f32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2f32_v3f32__u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx2 v3, v[4:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2f32_v3f32__u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v5, v0
+; GFX942-NEXT: global_store_dwordx2 v3, v[4:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -695,24 +710,27 @@ define void @v_shuffle_v2f32_v3f32__3_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2f32_v3f32__3_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx2 v3, v[4:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2f32_v3f32__3_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v5, v0
+; GFX942-NEXT: global_store_dwordx2 v3, v[4:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -743,6 +761,7 @@ define void @v_shuffle_v2f32_v3f32__4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
@@ -758,6 +777,7 @@ define void @v_shuffle_v2f32_v3f32__4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
@@ -1049,6 +1069,7 @@ define void @v_shuffle_v2f32_v3f32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1061,6 +1082,7 @@ define void @v_shuffle_v2f32_v3f32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1218,6 +1240,7 @@ define void @v_shuffle_v2f32_v3f32__3_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1230,6 +1253,7 @@ define void @v_shuffle_v2f32_v3f32__3_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1351,6 +1375,7 @@ define void @v_shuffle_v2f32_v3f32__1_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1363,6 +1388,7 @@ define void @v_shuffle_v2f32_v3f32__1_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1375,6 +1401,7 @@ define void @v_shuffle_v2f32_v3f32__1_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1388,33 +1415,36 @@ define void @v_shuffle_v2f32_v3f32__2_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v3f32__2_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2f32_v3f32__2_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2f32_v3f32__2_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -1779,6 +1809,7 @@ define void @v_shuffle_v2f32_v3f32__u_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1791,6 +1822,7 @@ define void @v_shuffle_v2f32_v3f32__u_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2109,6 +2141,7 @@ define void @s_shuffle_v2f32_v3f32__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2121,6 +2154,7 @@ define void @s_shuffle_v2f32_v3f32__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2133,6 +2167,7 @@ define void @s_shuffle_v2f32_v3f32__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2151,6 +2186,7 @@ define void @s_shuffle_v2f32_v3f32__2_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2163,6 +2199,7 @@ define void @s_shuffle_v2f32_v3f32__2_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2175,6 +2212,7 @@ define void @s_shuffle_v2f32_v3f32__2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2207,6 +2245,7 @@ define void @s_shuffle_v2f32_v3f32__4_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2219,6 +2258,7 @@ define void @s_shuffle_v2f32_v3f32__4_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2231,6 +2271,7 @@ define void @s_shuffle_v2f32_v3f32__4_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2250,6 +2291,7 @@ define void @s_shuffle_v2f32_v3f32__5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2262,6 +2304,7 @@ define void @s_shuffle_v2f32_v3f32__5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2274,6 +2317,7 @@ define void @s_shuffle_v2f32_v3f32__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2596,6 +2640,7 @@ define void @s_shuffle_v2f32_v3f32__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2608,6 +2653,7 @@ define void @s_shuffle_v2f32_v3f32__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2620,6 +2666,7 @@ define void @s_shuffle_v2f32_v3f32__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2746,6 +2793,7 @@ define void @s_shuffle_v2f32_v3f32__3_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2758,6 +2806,7 @@ define void @s_shuffle_v2f32_v3f32__3_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2770,6 +2819,7 @@ define void @s_shuffle_v2f32_v3f32__3_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3078,6 +3128,7 @@ define void @s_shuffle_v2f32_v3f32__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3090,6 +3141,7 @@ define void @s_shuffle_v2f32_v3f32__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3102,6 +3154,7 @@ define void @s_shuffle_v2f32_v3f32__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3228,6 +3281,7 @@ define void @s_shuffle_v2f32_v3f32__3_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3240,6 +3294,7 @@ define void @s_shuffle_v2f32_v3f32__3_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3252,6 +3307,7 @@ define void @s_shuffle_v2f32_v3f32__3_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3379,6 +3435,7 @@ define void @s_shuffle_v2f32_v3f32__1_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3391,6 +3448,7 @@ define void @s_shuffle_v2f32_v3f32__1_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3403,6 +3461,7 @@ define void @s_shuffle_v2f32_v3f32__1_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3421,6 +3480,7 @@ define void @s_shuffle_v2f32_v3f32__2_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3433,6 +3493,7 @@ define void @s_shuffle_v2f32_v3f32__2_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3445,6 +3506,7 @@ define void @s_shuffle_v2f32_v3f32__2_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3783,6 +3845,7 @@ define void @s_shuffle_v2f32_v3f32__u_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3795,6 +3858,7 @@ define void @s_shuffle_v2f32_v3f32__u_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3807,6 +3871,7 @@ define void @s_shuffle_v2f32_v3f32__u_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
index f1d147947ccdf..59dc9bb02f9c5 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v4f32.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2f32_v4f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2f32_v4f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2f32_v4f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -138,11 +141,12 @@ define void @v_shuffle_v2f32_v4f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v4f32__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +158,7 @@ define void @v_shuffle_v2f32_v4f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +171,7 @@ define void @v_shuffle_v2f32_v4f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -194,6 +200,7 @@ define void @v_shuffle_v2f32_v4f32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -206,6 +213,7 @@ define void @v_shuffle_v2f32_v4f32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +226,7 @@ define void @v_shuffle_v2f32_v4f32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -272,11 +281,12 @@ define void @v_shuffle_v2f32_v4f32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v4f32__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +298,7 @@ define void @v_shuffle_v2f32_v4f32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +311,7 @@ define void @v_shuffle_v2f32_v4f32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -331,6 +343,7 @@ define void @v_shuffle_v2f32_v4f32__7_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
@@ -346,6 +359,7 @@ define void @v_shuffle_v2f32_v4f32__7_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -439,6 +453,7 @@ define void @v_shuffle_v2f32_v4f32__7_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -454,6 +469,7 @@ define void @v_shuffle_v2f32_v4f32__7_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
@@ -711,8 +727,9 @@ define void @v_shuffle_v2f32_v4f32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -723,8 +740,9 @@ define void @v_shuffle_v2f32_v4f32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -922,8 +940,9 @@ define void @v_shuffle_v2f32_v4f32__4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -934,8 +953,9 @@ define void @v_shuffle_v2f32_v4f32__4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -966,6 +986,7 @@ define void @v_shuffle_v2f32_v4f32__5_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
@@ -981,6 +1002,7 @@ define void @v_shuffle_v2f32_v4f32__5_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -1419,6 +1441,7 @@ define void @v_shuffle_v2f32_v4f32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1431,6 +1454,7 @@ define void @v_shuffle_v2f32_v4f32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1629,6 +1653,7 @@ define void @v_shuffle_v2f32_v4f32__4_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1641,6 +1666,7 @@ define void @v_shuffle_v2f32_v4f32__4_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1676,6 +1702,7 @@ define void @v_shuffle_v2f32_v4f32__5_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -1691,6 +1718,7 @@ define void @v_shuffle_v2f32_v4f32__5_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
@@ -2163,6 +2191,7 @@ define void @v_shuffle_v2f32_v4f32__1_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2175,6 +2204,7 @@ define void @v_shuffle_v2f32_v4f32__1_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2187,6 +2217,7 @@ define void @v_shuffle_v2f32_v4f32__1_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2239,11 +2270,12 @@ define void @v_shuffle_v2f32_v4f32__3_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v4f32__3_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2255,6 +2287,7 @@ define void @v_shuffle_v2f32_v4f32__3_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2267,6 +2300,7 @@ define void @v_shuffle_v2f32_v4f32__3_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2771,6 +2805,7 @@ define void @v_shuffle_v2f32_v4f32__u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2783,6 +2818,7 @@ define void @v_shuffle_v2f32_v4f32__u_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2868,10 +2904,11 @@ define void @v_shuffle_v2f32_v4f32__1_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -2887,6 +2924,7 @@ define void @v_shuffle_v2f32_v4f32__1_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]
@@ -2974,10 +3012,11 @@ define void @v_shuffle_v2f32_v4f32__3_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -2989,11 +3028,11 @@ define void @v_shuffle_v2f32_v4f32__3_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -3574,6 +3613,7 @@ define void @s_shuffle_v2f32_v4f32__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3586,6 +3626,7 @@ define void @s_shuffle_v2f32_v4f32__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3598,6 +3639,7 @@ define void @s_shuffle_v2f32_v4f32__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3658,6 +3700,7 @@ define void @s_shuffle_v2f32_v4f32__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3670,6 +3713,7 @@ define void @s_shuffle_v2f32_v4f32__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3682,6 +3726,7 @@ define void @s_shuffle_v2f32_v4f32__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3714,6 +3759,7 @@ define void @s_shuffle_v2f32_v4f32__5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3726,6 +3772,7 @@ define void @s_shuffle_v2f32_v4f32__5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3738,6 +3785,7 @@ define void @s_shuffle_v2f32_v4f32__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3800,6 +3848,7 @@ define void @s_shuffle_v2f32_v4f32__7_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3812,6 +3861,7 @@ define void @s_shuffle_v2f32_v4f32__7_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3824,6 +3874,7 @@ define void @s_shuffle_v2f32_v4f32__7_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4217,6 +4268,7 @@ define void @s_shuffle_v2f32_v4f32__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4229,6 +4281,7 @@ define void @s_shuffle_v2f32_v4f32__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4241,6 +4294,7 @@ define void @s_shuffle_v2f32_v4f32__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4412,6 +4466,7 @@ define void @s_shuffle_v2f32_v4f32__4_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4424,6 +4479,7 @@ define void @s_shuffle_v2f32_v4f32__4_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4436,6 +4492,7 @@ define void @s_shuffle_v2f32_v4f32__4_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4872,6 +4929,7 @@ define void @s_shuffle_v2f32_v4f32__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4884,6 +4942,7 @@ define void @s_shuffle_v2f32_v4f32__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4896,6 +4955,7 @@ define void @s_shuffle_v2f32_v4f32__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5067,6 +5127,7 @@ define void @s_shuffle_v2f32_v4f32__4_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5079,6 +5140,7 @@ define void @s_shuffle_v2f32_v4f32__4_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5091,6 +5153,7 @@ define void @s_shuffle_v2f32_v4f32__4_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5617,6 +5680,7 @@ define void @s_shuffle_v2f32_v4f32__1_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5629,6 +5693,7 @@ define void @s_shuffle_v2f32_v4f32__1_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5641,6 +5706,7 @@ define void @s_shuffle_v2f32_v4f32__1_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5701,6 +5767,7 @@ define void @s_shuffle_v2f32_v4f32__3_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5713,6 +5780,7 @@ define void @s_shuffle_v2f32_v4f32__3_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5725,6 +5793,7 @@ define void @s_shuffle_v2f32_v4f32__3_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -6207,6 +6276,7 @@ define void @s_shuffle_v2f32_v4f32__u_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -6219,6 +6289,7 @@ define void @s_shuffle_v2f32_v4f32__u_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -6231,6 +6302,7 @@ define void @s_shuffle_v2f32_v4f32__u_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
index c17adef30c77a..0a2a7b61c7322 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2f32.v8f32.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2f32_v8f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2f32_v8f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2f32_v8f32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -142,6 +145,7 @@ define void @v_shuffle_v2f32_v8f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -154,6 +158,7 @@ define void @v_shuffle_v2f32_v8f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +171,7 @@ define void @v_shuffle_v2f32_v8f32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -222,6 +228,7 @@ define void @v_shuffle_v2f32_v8f32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -234,6 +241,7 @@ define void @v_shuffle_v2f32_v8f32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -246,6 +254,7 @@ define void @v_shuffle_v2f32_v8f32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -298,11 +307,12 @@ define void @v_shuffle_v2f32_v8f32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v8f32__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -314,6 +324,7 @@ define void @v_shuffle_v2f32_v8f32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -326,6 +337,7 @@ define void @v_shuffle_v2f32_v8f32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -354,6 +366,7 @@ define void @v_shuffle_v2f32_v8f32__9_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -366,6 +379,7 @@ define void @v_shuffle_v2f32_v8f32__9_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -378,6 +392,7 @@ define void @v_shuffle_v2f32_v8f32__9_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -436,6 +451,7 @@ define void @v_shuffle_v2f32_v8f32__11_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -448,6 +464,7 @@ define void @v_shuffle_v2f32_v8f32__11_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -460,6 +477,7 @@ define void @v_shuffle_v2f32_v8f32__11_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -518,6 +536,7 @@ define void @v_shuffle_v2f32_v8f32__13_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -530,6 +549,7 @@ define void @v_shuffle_v2f32_v8f32__13_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -542,6 +562,7 @@ define void @v_shuffle_v2f32_v8f32__13_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -596,11 +617,12 @@ define void @v_shuffle_v2f32_v8f32__15_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v8f32__15_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -612,6 +634,7 @@ define void @v_shuffle_v2f32_v8f32__15_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -624,6 +647,7 @@ define void @v_shuffle_v2f32_v8f32__15_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -655,6 +679,7 @@ define void @v_shuffle_v2f32_v8f32__15_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -670,6 +695,7 @@ define void @v_shuffle_v2f32_v8f32__15_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -763,6 +789,7 @@ define void @v_shuffle_v2f32_v8f32__15_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -778,6 +805,7 @@ define void @v_shuffle_v2f32_v8f32__15_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -867,6 +895,7 @@ define void @v_shuffle_v2f32_v8f32__15_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -882,6 +911,7 @@ define void @v_shuffle_v2f32_v8f32__15_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -971,6 +1001,7 @@ define void @v_shuffle_v2f32_v8f32__15_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[14:15], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -986,6 +1017,7 @@ define void @v_shuffle_v2f32_v8f32__15_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[14:15], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -1419,8 +1451,9 @@ define void @v_shuffle_v2f32_v8f32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1431,8 +1464,9 @@ define void @v_shuffle_v2f32_v8f32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x float> asm "; def $0", "=v"()
@@ -1802,8 +1836,9 @@ define void @v_shuffle_v2f32_v8f32__8_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1814,8 +1849,9 @@ define void @v_shuffle_v2f32_v8f32__8_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x float> asm "; def $0", "=v"()
@@ -1846,6 +1882,7 @@ define void @v_shuffle_v2f32_v8f32__9_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -1861,6 +1898,7 @@ define void @v_shuffle_v2f32_v8f32__9_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -1952,6 +1990,7 @@ define void @v_shuffle_v2f32_v8f32__11_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -1967,6 +2006,7 @@ define void @v_shuffle_v2f32_v8f32__11_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -2058,6 +2098,7 @@ define void @v_shuffle_v2f32_v8f32__13_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -2073,6 +2114,7 @@ define void @v_shuffle_v2f32_v8f32__13_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -2891,6 +2933,7 @@ define void @v_shuffle_v2f32_v8f32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2903,6 +2946,7 @@ define void @v_shuffle_v2f32_v8f32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3273,6 +3317,7 @@ define void @v_shuffle_v2f32_v8f32__8_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3285,6 +3330,7 @@ define void @v_shuffle_v2f32_v8f32__8_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3320,6 +3366,7 @@ define void @v_shuffle_v2f32_v8f32__9_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3335,6 +3382,7 @@ define void @v_shuffle_v2f32_v8f32__9_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -3426,6 +3474,7 @@ define void @v_shuffle_v2f32_v8f32__11_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3441,6 +3490,7 @@ define void @v_shuffle_v2f32_v8f32__11_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -3532,6 +3582,7 @@ define void @v_shuffle_v2f32_v8f32__13_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3547,6 +3598,7 @@ define void @v_shuffle_v2f32_v8f32__13_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -4361,6 +4413,7 @@ define void @v_shuffle_v2f32_v8f32__u_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4373,6 +4426,7 @@ define void @v_shuffle_v2f32_v8f32__u_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4743,6 +4797,7 @@ define void @v_shuffle_v2f32_v8f32__8_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4755,6 +4810,7 @@ define void @v_shuffle_v2f32_v8f32__8_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4790,6 +4846,7 @@ define void @v_shuffle_v2f32_v8f32__9_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -4805,6 +4862,7 @@ define void @v_shuffle_v2f32_v8f32__9_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -4896,6 +4954,7 @@ define void @v_shuffle_v2f32_v8f32__11_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -4911,6 +4970,7 @@ define void @v_shuffle_v2f32_v8f32__11_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -5002,6 +5062,7 @@ define void @v_shuffle_v2f32_v8f32__13_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -5017,6 +5078,7 @@ define void @v_shuffle_v2f32_v8f32__13_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -5831,6 +5893,7 @@ define void @v_shuffle_v2f32_v8f32__u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -5843,6 +5906,7 @@ define void @v_shuffle_v2f32_v8f32__u_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6213,6 +6277,7 @@ define void @v_shuffle_v2f32_v8f32__8_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6225,6 +6290,7 @@ define void @v_shuffle_v2f32_v8f32__8_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6260,6 +6326,7 @@ define void @v_shuffle_v2f32_v8f32__9_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6275,6 +6342,7 @@ define void @v_shuffle_v2f32_v8f32__9_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -6366,6 +6434,7 @@ define void @v_shuffle_v2f32_v8f32__11_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6381,6 +6450,7 @@ define void @v_shuffle_v2f32_v8f32__11_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -6472,6 +6542,7 @@ define void @v_shuffle_v2f32_v8f32__13_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6487,6 +6558,7 @@ define void @v_shuffle_v2f32_v8f32__13_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -7339,6 +7411,7 @@ define void @v_shuffle_v2f32_v8f32__1_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7351,6 +7424,7 @@ define void @v_shuffle_v2f32_v8f32__1_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7363,6 +7437,7 @@ define void @v_shuffle_v2f32_v8f32__1_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7419,6 +7494,7 @@ define void @v_shuffle_v2f32_v8f32__3_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7431,6 +7507,7 @@ define void @v_shuffle_v2f32_v8f32__3_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7443,6 +7520,7 @@ define void @v_shuffle_v2f32_v8f32__3_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7499,6 +7577,7 @@ define void @v_shuffle_v2f32_v8f32__5_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7511,6 +7590,7 @@ define void @v_shuffle_v2f32_v8f32__5_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7523,6 +7603,7 @@ define void @v_shuffle_v2f32_v8f32__5_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7575,11 +7656,12 @@ define void @v_shuffle_v2f32_v8f32__7_8(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2f32_v8f32__7_8:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -7591,6 +7673,7 @@ define void @v_shuffle_v2f32_v8f32__7_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7603,6 +7686,7 @@ define void @v_shuffle_v2f32_v8f32__7_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -8667,6 +8751,7 @@ define void @v_shuffle_v2f32_v8f32__u_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -8679,6 +8764,7 @@ define void @v_shuffle_v2f32_v8f32__u_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -8764,10 +8850,11 @@ define void @v_shuffle_v2f32_v8f32__1_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8783,6 +8870,7 @@ define void @v_shuffle_v2f32_v8f32__1_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -8870,10 +8958,11 @@ define void @v_shuffle_v2f32_v8f32__3_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8889,6 +8978,7 @@ define void @v_shuffle_v2f32_v8f32__3_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -8976,10 +9066,11 @@ define void @v_shuffle_v2f32_v8f32__5_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8995,6 +9086,7 @@ define void @v_shuffle_v2f32_v8f32__5_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -9082,10 +9174,11 @@ define void @v_shuffle_v2f32_v8f32__7_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -9097,11 +9190,11 @@ define void @v_shuffle_v2f32_v8f32__7_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -10199,6 +10292,7 @@ define void @v_shuffle_v2f32_v8f32__u_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -10211,6 +10305,7 @@ define void @v_shuffle_v2f32_v8f32__u_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -10296,10 +10391,11 @@ define void @v_shuffle_v2f32_v8f32__1_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10315,6 +10411,7 @@ define void @v_shuffle_v2f32_v8f32__1_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -10402,10 +10499,11 @@ define void @v_shuffle_v2f32_v8f32__3_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10421,6 +10519,7 @@ define void @v_shuffle_v2f32_v8f32__3_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -10508,10 +10607,11 @@ define void @v_shuffle_v2f32_v8f32__5_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10527,6 +10627,7 @@ define void @v_shuffle_v2f32_v8f32__5_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -10614,10 +10715,11 @@ define void @v_shuffle_v2f32_v8f32__7_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[12:13] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10629,11 +10731,11 @@ define void @v_shuffle_v2f32_v8f32__7_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[12:13] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -11731,6 +11833,7 @@ define void @v_shuffle_v2f32_v8f32__u_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -11743,6 +11846,7 @@ define void @v_shuffle_v2f32_v8f32__u_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -11828,10 +11932,11 @@ define void @v_shuffle_v2f32_v8f32__1_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11847,6 +11952,7 @@ define void @v_shuffle_v2f32_v8f32__1_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -11934,10 +12040,11 @@ define void @v_shuffle_v2f32_v8f32__3_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11953,6 +12060,7 @@ define void @v_shuffle_v2f32_v8f32__3_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -12040,10 +12148,11 @@ define void @v_shuffle_v2f32_v8f32__5_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[12:13] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12059,6 +12168,7 @@ define void @v_shuffle_v2f32_v8f32__5_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[12:13] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -12146,10 +12256,11 @@ define void @v_shuffle_v2f32_v8f32__7_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr15
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[14:15] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12161,11 +12272,11 @@ define void @v_shuffle_v2f32_v8f32__7_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr15
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[14:15] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -13306,6 +13417,7 @@ define void @s_shuffle_v2f32_v8f32__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13318,6 +13430,7 @@ define void @s_shuffle_v2f32_v8f32__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13330,6 +13443,7 @@ define void @s_shuffle_v2f32_v8f32__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13390,6 +13504,7 @@ define void @s_shuffle_v2f32_v8f32__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13402,6 +13517,7 @@ define void @s_shuffle_v2f32_v8f32__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13414,6 +13530,7 @@ define void @s_shuffle_v2f32_v8f32__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13470,9 +13587,10 @@ define void @s_shuffle_v2f32_v8f32__5_u() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -13482,9 +13600,10 @@ define void @s_shuffle_v2f32_v8f32__5_u() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -13496,6 +13615,7 @@ define void @s_shuffle_v2f32_v8f32__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13556,6 +13676,7 @@ define void @s_shuffle_v2f32_v8f32__7_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13568,6 +13689,7 @@ define void @s_shuffle_v2f32_v8f32__7_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13580,6 +13702,7 @@ define void @s_shuffle_v2f32_v8f32__7_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13612,6 +13735,7 @@ define void @s_shuffle_v2f32_v8f32__9_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13624,6 +13748,7 @@ define void @s_shuffle_v2f32_v8f32__9_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13636,6 +13761,7 @@ define void @s_shuffle_v2f32_v8f32__9_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13698,6 +13824,7 @@ define void @s_shuffle_v2f32_v8f32__11_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13710,6 +13837,7 @@ define void @s_shuffle_v2f32_v8f32__11_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13722,6 +13850,7 @@ define void @s_shuffle_v2f32_v8f32__11_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13780,9 +13909,10 @@ define void @s_shuffle_v2f32_v8f32__13_u() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -13792,9 +13922,10 @@ define void @s_shuffle_v2f32_v8f32__13_u() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -13806,6 +13937,7 @@ define void @s_shuffle_v2f32_v8f32__13_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13868,6 +14000,7 @@ define void @s_shuffle_v2f32_v8f32__15_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13880,6 +14013,7 @@ define void @s_shuffle_v2f32_v8f32__15_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13892,6 +14026,7 @@ define void @s_shuffle_v2f32_v8f32__15_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -14663,6 +14798,7 @@ define void @s_shuffle_v2f32_v8f32__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -14675,6 +14811,7 @@ define void @s_shuffle_v2f32_v8f32__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -14687,6 +14824,7 @@ define void @s_shuffle_v2f32_v8f32__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -15011,6 +15149,7 @@ define void @s_shuffle_v2f32_v8f32__8_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -15023,6 +15162,7 @@ define void @s_shuffle_v2f32_v8f32__8_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -15035,6 +15175,7 @@ define void @s_shuffle_v2f32_v8f32__8_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -16007,6 +16148,7 @@ define void @s_shuffle_v2f32_v8f32__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -16019,6 +16161,7 @@ define void @s_shuffle_v2f32_v8f32__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -16031,6 +16174,7 @@ define void @s_shuffle_v2f32_v8f32__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -16355,6 +16499,7 @@ define void @s_shuffle_v2f32_v8f32__8_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -16367,6 +16512,7 @@ define void @s_shuffle_v2f32_v8f32__8_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -16379,6 +16525,7 @@ define void @s_shuffle_v2f32_v8f32__8_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -17448,9 +17595,10 @@ define void @s_shuffle_v2f32_v8f32__u_4() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -17460,9 +17608,10 @@ define void @s_shuffle_v2f32_v8f32__u_4() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -17474,6 +17623,7 @@ define void @s_shuffle_v2f32_v8f32__u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -17796,9 +17946,10 @@ define void @s_shuffle_v2f32_v8f32__8_4() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -17808,9 +17959,10 @@ define void @s_shuffle_v2f32_v8f32__8_4() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -17822,6 +17974,7 @@ define void @s_shuffle_v2f32_v8f32__8_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -18790,6 +18943,7 @@ define void @s_shuffle_v2f32_v8f32__u_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -18802,6 +18956,7 @@ define void @s_shuffle_v2f32_v8f32__u_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -18814,6 +18969,7 @@ define void @s_shuffle_v2f32_v8f32__u_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19138,6 +19294,7 @@ define void @s_shuffle_v2f32_v8f32__8_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19150,6 +19307,7 @@ define void @s_shuffle_v2f32_v8f32__8_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19162,6 +19320,7 @@ define void @s_shuffle_v2f32_v8f32__8_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20277,6 +20436,7 @@ define void @s_shuffle_v2f32_v8f32__1_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20289,6 +20449,7 @@ define void @s_shuffle_v2f32_v8f32__1_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20301,6 +20462,7 @@ define void @s_shuffle_v2f32_v8f32__1_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20361,6 +20523,7 @@ define void @s_shuffle_v2f32_v8f32__3_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20373,6 +20536,7 @@ define void @s_shuffle_v2f32_v8f32__3_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20385,6 +20549,7 @@ define void @s_shuffle_v2f32_v8f32__3_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20441,9 +20606,10 @@ define void @s_shuffle_v2f32_v8f32__5_8() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -20453,9 +20619,10 @@ define void @s_shuffle_v2f32_v8f32__5_8() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -20467,6 +20634,7 @@ define void @s_shuffle_v2f32_v8f32__5_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20527,6 +20695,7 @@ define void @s_shuffle_v2f32_v8f32__7_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20539,6 +20708,7 @@ define void @s_shuffle_v2f32_v8f32__7_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20551,6 +20721,7 @@ define void @s_shuffle_v2f32_v8f32__7_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -21506,6 +21677,7 @@ define void @s_shuffle_v2f32_v8f32__u_10() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -21518,6 +21690,7 @@ define void @s_shuffle_v2f32_v8f32__u_10() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -21530,6 +21703,7 @@ define void @s_shuffle_v2f32_v8f32__u_10() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -22999,9 +23173,10 @@ define void @s_shuffle_v2f32_v8f32__u_12() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -23011,9 +23186,10 @@ define void @s_shuffle_v2f32_v8f32__u_12() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -23025,6 +23201,7 @@ define void @s_shuffle_v2f32_v8f32__u_12() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -24426,6 +24603,7 @@ define void @s_shuffle_v2f32_v8f32__u_14() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -24438,6 +24616,7 @@ define void @s_shuffle_v2f32_v8f32__u_14() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -24450,6 +24629,7 @@ define void @s_shuffle_v2f32_v8f32__u_14() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
index a86ca0a4a23c6..c3613de4adb37 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v2i32.ll
@@ -58,11 +58,12 @@ define void @v_shuffle_v2i32_v2i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v2i32__1_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +75,7 @@ define void @v_shuffle_v2i32_v2i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2i32_v2i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -110,11 +113,12 @@ define void @v_shuffle_v2i32_v2i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v2i32__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -126,6 +130,7 @@ define void @v_shuffle_v2i32_v2i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -138,6 +143,7 @@ define void @v_shuffle_v2i32_v2i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -353,24 +359,27 @@ define void @v_shuffle_v2i32_v2i32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2i32_v2i32__u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i32_v2i32__u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -478,24 +487,27 @@ define void @v_shuffle_v2i32_v2i32__2_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2i32_v2i32__2_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i32_v2i32__2_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -717,11 +729,12 @@ define void @v_shuffle_v2i32_v2i32__1_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v2i32__1_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -733,6 +746,7 @@ define void @v_shuffle_v2i32_v2i32__1_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -745,6 +759,7 @@ define void @v_shuffle_v2i32_v2i32__1_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1012,6 +1027,7 @@ define void @s_shuffle_v2i32_v2i32__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1024,6 +1040,7 @@ define void @s_shuffle_v2i32_v2i32__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1036,6 +1053,7 @@ define void @s_shuffle_v2i32_v2i32__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1068,6 +1086,7 @@ define void @s_shuffle_v2i32_v2i32__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1080,6 +1099,7 @@ define void @s_shuffle_v2i32_v2i32__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1092,6 +1112,7 @@ define void @s_shuffle_v2i32_v2i32__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1283,6 +1304,7 @@ define void @s_shuffle_v2i32_v2i32__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1295,6 +1317,7 @@ define void @s_shuffle_v2i32_v2i32__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1307,6 +1330,7 @@ define void @s_shuffle_v2i32_v2i32__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1388,6 +1412,7 @@ define void @s_shuffle_v2i32_v2i32__2_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1400,6 +1425,7 @@ define void @s_shuffle_v2i32_v2i32__2_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1412,6 +1438,7 @@ define void @s_shuffle_v2i32_v2i32__2_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1622,6 +1649,7 @@ define void @s_shuffle_v2i32_v2i32__1_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1634,6 +1662,7 @@ define void @s_shuffle_v2i32_v2i32__1_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1646,6 +1675,7 @@ define void @s_shuffle_v2i32_v2i32__1_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
index d46ca61cff64d..832ed701479a1 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v3i32.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2i32_v3i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2i32_v3i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2i32_v3i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +102,36 @@ define void @v_shuffle_v2i32_v3i32__2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v3i32__2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i32_v3i32__2_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i32_v3i32__2_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -153,6 +159,7 @@ define void @v_shuffle_v2i32_v3i32__4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -165,6 +172,7 @@ define void @v_shuffle_v2i32_v3i32__4_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -177,6 +185,7 @@ define void @v_shuffle_v2i32_v3i32__4_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -191,33 +200,36 @@ define void @v_shuffle_v2i32_v3i32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v3i32__5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i32_v3i32__5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i32_v3i32__5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -527,24 +539,27 @@ define void @v_shuffle_v2i32_v3i32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2i32_v3i32__u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx2 v3, v[4:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i32_v3i32__u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v5, v0
+; GFX942-NEXT: global_store_dwordx2 v3, v[4:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -695,24 +710,27 @@ define void @v_shuffle_v2i32_v3i32__3_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2i32_v3i32__3_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx2 v3, v[4:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i32_v3i32__3_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v5, v0
+; GFX942-NEXT: global_store_dwordx2 v3, v[4:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -743,6 +761,7 @@ define void @v_shuffle_v2i32_v3i32__4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
@@ -758,6 +777,7 @@ define void @v_shuffle_v2i32_v3i32__4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
@@ -1049,6 +1069,7 @@ define void @v_shuffle_v2i32_v3i32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1061,6 +1082,7 @@ define void @v_shuffle_v2i32_v3i32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1218,6 +1240,7 @@ define void @v_shuffle_v2i32_v3i32__3_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1230,6 +1253,7 @@ define void @v_shuffle_v2i32_v3i32__3_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1351,6 +1375,7 @@ define void @v_shuffle_v2i32_v3i32__1_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1363,6 +1388,7 @@ define void @v_shuffle_v2i32_v3i32__1_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1375,6 +1401,7 @@ define void @v_shuffle_v2i32_v3i32__1_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1388,33 +1415,36 @@ define void @v_shuffle_v2i32_v3i32__2_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v3i32__2_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i32_v3i32__2_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i32_v3i32__2_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -1779,6 +1809,7 @@ define void @v_shuffle_v2i32_v3i32__u_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1791,6 +1822,7 @@ define void @v_shuffle_v2i32_v3i32__u_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2109,6 +2141,7 @@ define void @s_shuffle_v2i32_v3i32__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2121,6 +2154,7 @@ define void @s_shuffle_v2i32_v3i32__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2133,6 +2167,7 @@ define void @s_shuffle_v2i32_v3i32__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2151,6 +2186,7 @@ define void @s_shuffle_v2i32_v3i32__2_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2163,6 +2199,7 @@ define void @s_shuffle_v2i32_v3i32__2_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2175,6 +2212,7 @@ define void @s_shuffle_v2i32_v3i32__2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2207,6 +2245,7 @@ define void @s_shuffle_v2i32_v3i32__4_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2219,6 +2258,7 @@ define void @s_shuffle_v2i32_v3i32__4_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2231,6 +2271,7 @@ define void @s_shuffle_v2i32_v3i32__4_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2250,6 +2291,7 @@ define void @s_shuffle_v2i32_v3i32__5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2262,6 +2304,7 @@ define void @s_shuffle_v2i32_v3i32__5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2274,6 +2317,7 @@ define void @s_shuffle_v2i32_v3i32__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2596,6 +2640,7 @@ define void @s_shuffle_v2i32_v3i32__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2608,6 +2653,7 @@ define void @s_shuffle_v2i32_v3i32__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2620,6 +2666,7 @@ define void @s_shuffle_v2i32_v3i32__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2746,6 +2793,7 @@ define void @s_shuffle_v2i32_v3i32__3_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2758,6 +2806,7 @@ define void @s_shuffle_v2i32_v3i32__3_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2770,6 +2819,7 @@ define void @s_shuffle_v2i32_v3i32__3_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3078,6 +3128,7 @@ define void @s_shuffle_v2i32_v3i32__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3090,6 +3141,7 @@ define void @s_shuffle_v2i32_v3i32__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3102,6 +3154,7 @@ define void @s_shuffle_v2i32_v3i32__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3228,6 +3281,7 @@ define void @s_shuffle_v2i32_v3i32__3_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3240,6 +3294,7 @@ define void @s_shuffle_v2i32_v3i32__3_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3252,6 +3307,7 @@ define void @s_shuffle_v2i32_v3i32__3_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3379,6 +3435,7 @@ define void @s_shuffle_v2i32_v3i32__1_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3391,6 +3448,7 @@ define void @s_shuffle_v2i32_v3i32__1_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3403,6 +3461,7 @@ define void @s_shuffle_v2i32_v3i32__1_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3421,6 +3480,7 @@ define void @s_shuffle_v2i32_v3i32__2_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3433,6 +3493,7 @@ define void @s_shuffle_v2i32_v3i32__2_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3445,6 +3506,7 @@ define void @s_shuffle_v2i32_v3i32__2_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3783,6 +3845,7 @@ define void @s_shuffle_v2i32_v3i32__u_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3795,6 +3858,7 @@ define void @s_shuffle_v2i32_v3i32__u_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3807,6 +3871,7 @@ define void @s_shuffle_v2i32_v3i32__u_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
index 39c6a447788e4..95010532a682f 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v4i32.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2i32_v4i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2i32_v4i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2i32_v4i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -138,11 +141,12 @@ define void @v_shuffle_v2i32_v4i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v4i32__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +158,7 @@ define void @v_shuffle_v2i32_v4i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +171,7 @@ define void @v_shuffle_v2i32_v4i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -194,6 +200,7 @@ define void @v_shuffle_v2i32_v4i32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -206,6 +213,7 @@ define void @v_shuffle_v2i32_v4i32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +226,7 @@ define void @v_shuffle_v2i32_v4i32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -272,11 +281,12 @@ define void @v_shuffle_v2i32_v4i32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v4i32__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +298,7 @@ define void @v_shuffle_v2i32_v4i32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +311,7 @@ define void @v_shuffle_v2i32_v4i32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -331,6 +343,7 @@ define void @v_shuffle_v2i32_v4i32__7_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
@@ -346,6 +359,7 @@ define void @v_shuffle_v2i32_v4i32__7_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -439,6 +453,7 @@ define void @v_shuffle_v2i32_v4i32__7_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -454,6 +469,7 @@ define void @v_shuffle_v2i32_v4i32__7_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
@@ -711,8 +727,9 @@ define void @v_shuffle_v2i32_v4i32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -723,8 +740,9 @@ define void @v_shuffle_v2i32_v4i32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -922,8 +940,9 @@ define void @v_shuffle_v2i32_v4i32__4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -934,8 +953,9 @@ define void @v_shuffle_v2i32_v4i32__4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -966,6 +986,7 @@ define void @v_shuffle_v2i32_v4i32__5_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
@@ -981,6 +1002,7 @@ define void @v_shuffle_v2i32_v4i32__5_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -1419,6 +1441,7 @@ define void @v_shuffle_v2i32_v4i32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1431,6 +1454,7 @@ define void @v_shuffle_v2i32_v4i32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1629,6 +1653,7 @@ define void @v_shuffle_v2i32_v4i32__4_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1641,6 +1666,7 @@ define void @v_shuffle_v2i32_v4i32__4_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1676,6 +1702,7 @@ define void @v_shuffle_v2i32_v4i32__5_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -1691,6 +1718,7 @@ define void @v_shuffle_v2i32_v4i32__5_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
@@ -2163,6 +2191,7 @@ define void @v_shuffle_v2i32_v4i32__1_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2175,6 +2204,7 @@ define void @v_shuffle_v2i32_v4i32__1_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2187,6 +2217,7 @@ define void @v_shuffle_v2i32_v4i32__1_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2239,11 +2270,12 @@ define void @v_shuffle_v2i32_v4i32__3_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v4i32__3_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2255,6 +2287,7 @@ define void @v_shuffle_v2i32_v4i32__3_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2267,6 +2300,7 @@ define void @v_shuffle_v2i32_v4i32__3_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2771,6 +2805,7 @@ define void @v_shuffle_v2i32_v4i32__u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2783,6 +2818,7 @@ define void @v_shuffle_v2i32_v4i32__u_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2868,10 +2904,11 @@ define void @v_shuffle_v2i32_v4i32__1_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -2887,6 +2924,7 @@ define void @v_shuffle_v2i32_v4i32__1_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]
@@ -2974,10 +3012,11 @@ define void @v_shuffle_v2i32_v4i32__3_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -2989,11 +3028,11 @@ define void @v_shuffle_v2i32_v4i32__3_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -3574,6 +3613,7 @@ define void @s_shuffle_v2i32_v4i32__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3586,6 +3626,7 @@ define void @s_shuffle_v2i32_v4i32__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3598,6 +3639,7 @@ define void @s_shuffle_v2i32_v4i32__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3658,6 +3700,7 @@ define void @s_shuffle_v2i32_v4i32__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3670,6 +3713,7 @@ define void @s_shuffle_v2i32_v4i32__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3682,6 +3726,7 @@ define void @s_shuffle_v2i32_v4i32__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3714,6 +3759,7 @@ define void @s_shuffle_v2i32_v4i32__5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3726,6 +3772,7 @@ define void @s_shuffle_v2i32_v4i32__5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3738,6 +3785,7 @@ define void @s_shuffle_v2i32_v4i32__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3800,6 +3848,7 @@ define void @s_shuffle_v2i32_v4i32__7_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3812,6 +3861,7 @@ define void @s_shuffle_v2i32_v4i32__7_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3824,6 +3874,7 @@ define void @s_shuffle_v2i32_v4i32__7_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4217,6 +4268,7 @@ define void @s_shuffle_v2i32_v4i32__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4229,6 +4281,7 @@ define void @s_shuffle_v2i32_v4i32__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4241,6 +4294,7 @@ define void @s_shuffle_v2i32_v4i32__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4412,6 +4466,7 @@ define void @s_shuffle_v2i32_v4i32__4_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4424,6 +4479,7 @@ define void @s_shuffle_v2i32_v4i32__4_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4436,6 +4492,7 @@ define void @s_shuffle_v2i32_v4i32__4_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4872,6 +4929,7 @@ define void @s_shuffle_v2i32_v4i32__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4884,6 +4942,7 @@ define void @s_shuffle_v2i32_v4i32__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4896,6 +4955,7 @@ define void @s_shuffle_v2i32_v4i32__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5067,6 +5127,7 @@ define void @s_shuffle_v2i32_v4i32__4_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5079,6 +5140,7 @@ define void @s_shuffle_v2i32_v4i32__4_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5091,6 +5153,7 @@ define void @s_shuffle_v2i32_v4i32__4_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5617,6 +5680,7 @@ define void @s_shuffle_v2i32_v4i32__1_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5629,6 +5693,7 @@ define void @s_shuffle_v2i32_v4i32__1_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5641,6 +5706,7 @@ define void @s_shuffle_v2i32_v4i32__1_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5701,6 +5767,7 @@ define void @s_shuffle_v2i32_v4i32__3_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5713,6 +5780,7 @@ define void @s_shuffle_v2i32_v4i32__3_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5725,6 +5793,7 @@ define void @s_shuffle_v2i32_v4i32__3_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -6207,6 +6276,7 @@ define void @s_shuffle_v2i32_v4i32__u_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -6219,6 +6289,7 @@ define void @s_shuffle_v2i32_v4i32__u_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -6231,6 +6302,7 @@ define void @s_shuffle_v2i32_v4i32__u_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
index 0917a6ecaa5c4..973e5564f65ea 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i32.v8i32.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2i32_v8i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2i32_v8i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2i32_v8i32__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -142,6 +145,7 @@ define void @v_shuffle_v2i32_v8i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -154,6 +158,7 @@ define void @v_shuffle_v2i32_v8i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +171,7 @@ define void @v_shuffle_v2i32_v8i32__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -222,6 +228,7 @@ define void @v_shuffle_v2i32_v8i32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -234,6 +241,7 @@ define void @v_shuffle_v2i32_v8i32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -246,6 +254,7 @@ define void @v_shuffle_v2i32_v8i32__5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -298,11 +307,12 @@ define void @v_shuffle_v2i32_v8i32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v8i32__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -314,6 +324,7 @@ define void @v_shuffle_v2i32_v8i32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -326,6 +337,7 @@ define void @v_shuffle_v2i32_v8i32__7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -354,6 +366,7 @@ define void @v_shuffle_v2i32_v8i32__9_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -366,6 +379,7 @@ define void @v_shuffle_v2i32_v8i32__9_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -378,6 +392,7 @@ define void @v_shuffle_v2i32_v8i32__9_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -436,6 +451,7 @@ define void @v_shuffle_v2i32_v8i32__11_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -448,6 +464,7 @@ define void @v_shuffle_v2i32_v8i32__11_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -460,6 +477,7 @@ define void @v_shuffle_v2i32_v8i32__11_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -518,6 +536,7 @@ define void @v_shuffle_v2i32_v8i32__13_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -530,6 +549,7 @@ define void @v_shuffle_v2i32_v8i32__13_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -542,6 +562,7 @@ define void @v_shuffle_v2i32_v8i32__13_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -596,11 +617,12 @@ define void @v_shuffle_v2i32_v8i32__15_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v8i32__15_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -612,6 +634,7 @@ define void @v_shuffle_v2i32_v8i32__15_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -624,6 +647,7 @@ define void @v_shuffle_v2i32_v8i32__15_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -655,6 +679,7 @@ define void @v_shuffle_v2i32_v8i32__15_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -670,6 +695,7 @@ define void @v_shuffle_v2i32_v8i32__15_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -763,6 +789,7 @@ define void @v_shuffle_v2i32_v8i32__15_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -778,6 +805,7 @@ define void @v_shuffle_v2i32_v8i32__15_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -867,6 +895,7 @@ define void @v_shuffle_v2i32_v8i32__15_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -882,6 +911,7 @@ define void @v_shuffle_v2i32_v8i32__15_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -971,6 +1001,7 @@ define void @v_shuffle_v2i32_v8i32__15_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[14:15], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -986,6 +1017,7 @@ define void @v_shuffle_v2i32_v8i32__15_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[14:15], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -1419,8 +1451,9 @@ define void @v_shuffle_v2i32_v8i32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1431,8 +1464,9 @@ define void @v_shuffle_v2i32_v8i32__u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x i32> asm "; def $0", "=v"()
@@ -1802,8 +1836,9 @@ define void @v_shuffle_v2i32_v8i32__8_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1814,8 +1849,9 @@ define void @v_shuffle_v2i32_v8i32__8_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x i32> asm "; def $0", "=v"()
@@ -1846,6 +1882,7 @@ define void @v_shuffle_v2i32_v8i32__9_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -1861,6 +1898,7 @@ define void @v_shuffle_v2i32_v8i32__9_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -1952,6 +1990,7 @@ define void @v_shuffle_v2i32_v8i32__11_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -1967,6 +2006,7 @@ define void @v_shuffle_v2i32_v8i32__11_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -2058,6 +2098,7 @@ define void @v_shuffle_v2i32_v8i32__13_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -2073,6 +2114,7 @@ define void @v_shuffle_v2i32_v8i32__13_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -2891,6 +2933,7 @@ define void @v_shuffle_v2i32_v8i32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2903,6 +2946,7 @@ define void @v_shuffle_v2i32_v8i32__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3273,6 +3317,7 @@ define void @v_shuffle_v2i32_v8i32__8_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3285,6 +3330,7 @@ define void @v_shuffle_v2i32_v8i32__8_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3320,6 +3366,7 @@ define void @v_shuffle_v2i32_v8i32__9_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3335,6 +3382,7 @@ define void @v_shuffle_v2i32_v8i32__9_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -3426,6 +3474,7 @@ define void @v_shuffle_v2i32_v8i32__11_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3441,6 +3490,7 @@ define void @v_shuffle_v2i32_v8i32__11_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -3532,6 +3582,7 @@ define void @v_shuffle_v2i32_v8i32__13_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3547,6 +3598,7 @@ define void @v_shuffle_v2i32_v8i32__13_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -4361,6 +4413,7 @@ define void @v_shuffle_v2i32_v8i32__u_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4373,6 +4426,7 @@ define void @v_shuffle_v2i32_v8i32__u_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4743,6 +4797,7 @@ define void @v_shuffle_v2i32_v8i32__8_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4755,6 +4810,7 @@ define void @v_shuffle_v2i32_v8i32__8_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4790,6 +4846,7 @@ define void @v_shuffle_v2i32_v8i32__9_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -4805,6 +4862,7 @@ define void @v_shuffle_v2i32_v8i32__9_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -4896,6 +4954,7 @@ define void @v_shuffle_v2i32_v8i32__11_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -4911,6 +4970,7 @@ define void @v_shuffle_v2i32_v8i32__11_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -5002,6 +5062,7 @@ define void @v_shuffle_v2i32_v8i32__13_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -5017,6 +5078,7 @@ define void @v_shuffle_v2i32_v8i32__13_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -5831,6 +5893,7 @@ define void @v_shuffle_v2i32_v8i32__u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -5843,6 +5906,7 @@ define void @v_shuffle_v2i32_v8i32__u_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6213,6 +6277,7 @@ define void @v_shuffle_v2i32_v8i32__8_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6225,6 +6290,7 @@ define void @v_shuffle_v2i32_v8i32__8_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6260,6 +6326,7 @@ define void @v_shuffle_v2i32_v8i32__9_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6275,6 +6342,7 @@ define void @v_shuffle_v2i32_v8i32__9_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -6366,6 +6434,7 @@ define void @v_shuffle_v2i32_v8i32__11_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6381,6 +6450,7 @@ define void @v_shuffle_v2i32_v8i32__11_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -6472,6 +6542,7 @@ define void @v_shuffle_v2i32_v8i32__13_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6487,6 +6558,7 @@ define void @v_shuffle_v2i32_v8i32__13_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -7339,6 +7411,7 @@ define void @v_shuffle_v2i32_v8i32__1_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7351,6 +7424,7 @@ define void @v_shuffle_v2i32_v8i32__1_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7363,6 +7437,7 @@ define void @v_shuffle_v2i32_v8i32__1_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7419,6 +7494,7 @@ define void @v_shuffle_v2i32_v8i32__3_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7431,6 +7507,7 @@ define void @v_shuffle_v2i32_v8i32__3_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7443,6 +7520,7 @@ define void @v_shuffle_v2i32_v8i32__3_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7499,6 +7577,7 @@ define void @v_shuffle_v2i32_v8i32__5_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7511,6 +7590,7 @@ define void @v_shuffle_v2i32_v8i32__5_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7523,6 +7603,7 @@ define void @v_shuffle_v2i32_v8i32__5_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7575,11 +7656,12 @@ define void @v_shuffle_v2i32_v8i32__7_8(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i32_v8i32__7_8:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -7591,6 +7673,7 @@ define void @v_shuffle_v2i32_v8i32__7_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7603,6 +7686,7 @@ define void @v_shuffle_v2i32_v8i32__7_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -8667,6 +8751,7 @@ define void @v_shuffle_v2i32_v8i32__u_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -8679,6 +8764,7 @@ define void @v_shuffle_v2i32_v8i32__u_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -8764,10 +8850,11 @@ define void @v_shuffle_v2i32_v8i32__1_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8783,6 +8870,7 @@ define void @v_shuffle_v2i32_v8i32__1_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -8870,10 +8958,11 @@ define void @v_shuffle_v2i32_v8i32__3_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8889,6 +8978,7 @@ define void @v_shuffle_v2i32_v8i32__3_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -8976,10 +9066,11 @@ define void @v_shuffle_v2i32_v8i32__5_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8995,6 +9086,7 @@ define void @v_shuffle_v2i32_v8i32__5_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -9082,10 +9174,11 @@ define void @v_shuffle_v2i32_v8i32__7_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -9097,11 +9190,11 @@ define void @v_shuffle_v2i32_v8i32__7_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -10199,6 +10292,7 @@ define void @v_shuffle_v2i32_v8i32__u_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -10211,6 +10305,7 @@ define void @v_shuffle_v2i32_v8i32__u_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -10296,10 +10391,11 @@ define void @v_shuffle_v2i32_v8i32__1_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10315,6 +10411,7 @@ define void @v_shuffle_v2i32_v8i32__1_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -10402,10 +10499,11 @@ define void @v_shuffle_v2i32_v8i32__3_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10421,6 +10519,7 @@ define void @v_shuffle_v2i32_v8i32__3_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -10508,10 +10607,11 @@ define void @v_shuffle_v2i32_v8i32__5_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10527,6 +10627,7 @@ define void @v_shuffle_v2i32_v8i32__5_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -10614,10 +10715,11 @@ define void @v_shuffle_v2i32_v8i32__7_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[12:13] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10629,11 +10731,11 @@ define void @v_shuffle_v2i32_v8i32__7_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[12:13] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -11731,6 +11833,7 @@ define void @v_shuffle_v2i32_v8i32__u_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -11743,6 +11846,7 @@ define void @v_shuffle_v2i32_v8i32__u_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -11828,10 +11932,11 @@ define void @v_shuffle_v2i32_v8i32__1_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11847,6 +11952,7 @@ define void @v_shuffle_v2i32_v8i32__1_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -11934,10 +12040,11 @@ define void @v_shuffle_v2i32_v8i32__3_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11953,6 +12060,7 @@ define void @v_shuffle_v2i32_v8i32__3_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -12040,10 +12148,11 @@ define void @v_shuffle_v2i32_v8i32__5_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[12:13] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12059,6 +12168,7 @@ define void @v_shuffle_v2i32_v8i32__5_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[12:13] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -12146,10 +12256,11 @@ define void @v_shuffle_v2i32_v8i32__7_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr15
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[14:15] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12161,11 +12272,11 @@ define void @v_shuffle_v2i32_v8i32__7_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr15
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[14:15] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -13306,6 +13417,7 @@ define void @s_shuffle_v2i32_v8i32__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13318,6 +13430,7 @@ define void @s_shuffle_v2i32_v8i32__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13330,6 +13443,7 @@ define void @s_shuffle_v2i32_v8i32__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13390,6 +13504,7 @@ define void @s_shuffle_v2i32_v8i32__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13402,6 +13517,7 @@ define void @s_shuffle_v2i32_v8i32__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13414,6 +13530,7 @@ define void @s_shuffle_v2i32_v8i32__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13470,9 +13587,10 @@ define void @s_shuffle_v2i32_v8i32__5_u() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -13482,9 +13600,10 @@ define void @s_shuffle_v2i32_v8i32__5_u() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -13496,6 +13615,7 @@ define void @s_shuffle_v2i32_v8i32__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13556,6 +13676,7 @@ define void @s_shuffle_v2i32_v8i32__7_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13568,6 +13689,7 @@ define void @s_shuffle_v2i32_v8i32__7_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13580,6 +13702,7 @@ define void @s_shuffle_v2i32_v8i32__7_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13612,6 +13735,7 @@ define void @s_shuffle_v2i32_v8i32__9_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13624,6 +13748,7 @@ define void @s_shuffle_v2i32_v8i32__9_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13636,6 +13761,7 @@ define void @s_shuffle_v2i32_v8i32__9_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13698,6 +13824,7 @@ define void @s_shuffle_v2i32_v8i32__11_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13710,6 +13837,7 @@ define void @s_shuffle_v2i32_v8i32__11_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13722,6 +13850,7 @@ define void @s_shuffle_v2i32_v8i32__11_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13780,9 +13909,10 @@ define void @s_shuffle_v2i32_v8i32__13_u() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -13792,9 +13922,10 @@ define void @s_shuffle_v2i32_v8i32__13_u() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -13806,6 +13937,7 @@ define void @s_shuffle_v2i32_v8i32__13_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13868,6 +14000,7 @@ define void @s_shuffle_v2i32_v8i32__15_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13880,6 +14013,7 @@ define void @s_shuffle_v2i32_v8i32__15_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13892,6 +14026,7 @@ define void @s_shuffle_v2i32_v8i32__15_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -14663,6 +14798,7 @@ define void @s_shuffle_v2i32_v8i32__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -14675,6 +14811,7 @@ define void @s_shuffle_v2i32_v8i32__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -14687,6 +14824,7 @@ define void @s_shuffle_v2i32_v8i32__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -15011,6 +15149,7 @@ define void @s_shuffle_v2i32_v8i32__8_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -15023,6 +15162,7 @@ define void @s_shuffle_v2i32_v8i32__8_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -15035,6 +15175,7 @@ define void @s_shuffle_v2i32_v8i32__8_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -16007,6 +16148,7 @@ define void @s_shuffle_v2i32_v8i32__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -16019,6 +16161,7 @@ define void @s_shuffle_v2i32_v8i32__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -16031,6 +16174,7 @@ define void @s_shuffle_v2i32_v8i32__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -16355,6 +16499,7 @@ define void @s_shuffle_v2i32_v8i32__8_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -16367,6 +16512,7 @@ define void @s_shuffle_v2i32_v8i32__8_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -16379,6 +16525,7 @@ define void @s_shuffle_v2i32_v8i32__8_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -17448,9 +17595,10 @@ define void @s_shuffle_v2i32_v8i32__u_4() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -17460,9 +17608,10 @@ define void @s_shuffle_v2i32_v8i32__u_4() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -17474,6 +17623,7 @@ define void @s_shuffle_v2i32_v8i32__u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -17796,9 +17946,10 @@ define void @s_shuffle_v2i32_v8i32__8_4() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -17808,9 +17959,10 @@ define void @s_shuffle_v2i32_v8i32__8_4() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -17822,6 +17974,7 @@ define void @s_shuffle_v2i32_v8i32__8_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -18790,6 +18943,7 @@ define void @s_shuffle_v2i32_v8i32__u_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -18802,6 +18956,7 @@ define void @s_shuffle_v2i32_v8i32__u_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -18814,6 +18969,7 @@ define void @s_shuffle_v2i32_v8i32__u_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19138,6 +19294,7 @@ define void @s_shuffle_v2i32_v8i32__8_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19150,6 +19307,7 @@ define void @s_shuffle_v2i32_v8i32__8_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19162,6 +19320,7 @@ define void @s_shuffle_v2i32_v8i32__8_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20277,6 +20436,7 @@ define void @s_shuffle_v2i32_v8i32__1_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20289,6 +20449,7 @@ define void @s_shuffle_v2i32_v8i32__1_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20301,6 +20462,7 @@ define void @s_shuffle_v2i32_v8i32__1_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20361,6 +20523,7 @@ define void @s_shuffle_v2i32_v8i32__3_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20373,6 +20536,7 @@ define void @s_shuffle_v2i32_v8i32__3_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20385,6 +20549,7 @@ define void @s_shuffle_v2i32_v8i32__3_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20441,9 +20606,10 @@ define void @s_shuffle_v2i32_v8i32__5_8() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -20453,9 +20619,10 @@ define void @s_shuffle_v2i32_v8i32__5_8() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -20467,6 +20634,7 @@ define void @s_shuffle_v2i32_v8i32__5_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20527,6 +20695,7 @@ define void @s_shuffle_v2i32_v8i32__7_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20539,6 +20708,7 @@ define void @s_shuffle_v2i32_v8i32__7_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20551,6 +20721,7 @@ define void @s_shuffle_v2i32_v8i32__7_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -21506,6 +21677,7 @@ define void @s_shuffle_v2i32_v8i32__u_10() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -21518,6 +21690,7 @@ define void @s_shuffle_v2i32_v8i32__u_10() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -21530,6 +21703,7 @@ define void @s_shuffle_v2i32_v8i32__u_10() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -22999,9 +23173,10 @@ define void @s_shuffle_v2i32_v8i32__u_12() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -23011,9 +23186,10 @@ define void @s_shuffle_v2i32_v8i32__u_12() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -23025,6 +23201,7 @@ define void @s_shuffle_v2i32_v8i32__u_12() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -24426,6 +24603,7 @@ define void @s_shuffle_v2i32_v8i32__u_14() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -24438,6 +24616,7 @@ define void @s_shuffle_v2i32_v8i32__u_14() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -24450,6 +24629,7 @@ define void @s_shuffle_v2i32_v8i32__u_14() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
index 1df6f21f15594..fac8ad12b2f8b 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v2i64.ll
@@ -58,33 +58,39 @@ define void @v_shuffle_v2i64_v2i64__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v2i64__1_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v2i64__1_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v2i64__1_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -108,33 +114,39 @@ define void @v_shuffle_v2i64_v2i64__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v2i64__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v2i64__3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v2i64__3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -723,33 +735,39 @@ define void @v_shuffle_v2i64_v2i64__1_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v2i64__1_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v2i64__1_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v2i64__1_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -1023,6 +1041,8 @@ define void @s_shuffle_v2i64_v2i64__1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -1036,6 +1056,8 @@ define void @s_shuffle_v2i64_v2i64__1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -1049,6 +1071,8 @@ define void @s_shuffle_v2i64_v2i64__1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -1082,6 +1106,8 @@ define void @s_shuffle_v2i64_v2i64__3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -1095,6 +1121,8 @@ define void @s_shuffle_v2i64_v2i64__3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -1108,6 +1136,8 @@ define void @s_shuffle_v2i64_v2i64__3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -1314,6 +1344,8 @@ define void @s_shuffle_v2i64_v2i64__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -1327,6 +1359,8 @@ define void @s_shuffle_v2i64_v2i64__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -1340,6 +1374,8 @@ define void @s_shuffle_v2i64_v2i64__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -1429,6 +1465,8 @@ define void @s_shuffle_v2i64_v2i64__2_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -1442,6 +1480,8 @@ define void @s_shuffle_v2i64_v2i64__2_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -1455,6 +1495,8 @@ define void @s_shuffle_v2i64_v2i64__2_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -1669,6 +1711,8 @@ define void @s_shuffle_v2i64_v2i64__1_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -1682,6 +1726,8 @@ define void @s_shuffle_v2i64_v2i64__1_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -1695,6 +1741,8 @@ define void @s_shuffle_v2i64_v2i64__1_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
index 13b16f778aa97..6f55892bbdae6 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v3i64.ll
@@ -62,6 +62,8 @@ define void @v_shuffle_v2i64_v3i64__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -73,6 +75,8 @@ define void @v_shuffle_v2i64_v3i64__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -84,6 +88,8 @@ define void @v_shuffle_v2i64_v3i64__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -97,33 +103,39 @@ define void @v_shuffle_v2i64_v3i64__2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v3i64__2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v3i64__2_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v3i64__2_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -151,6 +163,8 @@ define void @v_shuffle_v2i64_v3i64__4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -162,6 +176,8 @@ define void @v_shuffle_v2i64_v3i64__4_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -173,6 +189,8 @@ define void @v_shuffle_v2i64_v3i64__4_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -187,33 +205,39 @@ define void @v_shuffle_v2i64_v3i64__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v3i64__5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v3i64__5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v3i64__5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -1369,6 +1393,8 @@ define void @v_shuffle_v2i64_v3i64__1_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1380,6 +1406,8 @@ define void @v_shuffle_v2i64_v3i64__1_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1391,6 +1419,8 @@ define void @v_shuffle_v2i64_v3i64__1_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1404,33 +1434,39 @@ define void @v_shuffle_v2i64_v3i64__2_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v3i64__2_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v3i64__2_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v3i64__2_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -2145,6 +2181,8 @@ define void @s_shuffle_v2i64_v3i64__1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -2158,6 +2196,8 @@ define void @s_shuffle_v2i64_v3i64__1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -2171,6 +2211,8 @@ define void @s_shuffle_v2i64_v3i64__1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -2188,6 +2230,8 @@ define void @s_shuffle_v2i64_v3i64__2_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -2199,6 +2243,8 @@ define void @s_shuffle_v2i64_v3i64__2_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -2210,6 +2256,8 @@ define void @s_shuffle_v2i64_v3i64__2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -2244,6 +2292,8 @@ define void @s_shuffle_v2i64_v3i64__4_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -2257,6 +2307,8 @@ define void @s_shuffle_v2i64_v3i64__4_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -2270,6 +2322,8 @@ define void @s_shuffle_v2i64_v3i64__4_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -2288,6 +2342,8 @@ define void @s_shuffle_v2i64_v3i64__5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -2299,6 +2355,8 @@ define void @s_shuffle_v2i64_v3i64__5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -2310,6 +2368,8 @@ define void @s_shuffle_v2i64_v3i64__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -2550,6 +2610,8 @@ define void @s_shuffle_v2i64_v3i64__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -2563,6 +2625,8 @@ define void @s_shuffle_v2i64_v3i64__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -2576,6 +2640,8 @@ define void @s_shuffle_v2i64_v3i64__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -2684,6 +2750,8 @@ define void @s_shuffle_v2i64_v3i64__3_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -2697,6 +2765,8 @@ define void @s_shuffle_v2i64_v3i64__3_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -2710,6 +2780,8 @@ define void @s_shuffle_v2i64_v3i64__3_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -3001,10 +3073,12 @@ define void @s_shuffle_v2i64_v3i64__u_2() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:9]
+; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3014,10 +3088,12 @@ define void @s_shuffle_v2i64_v3i64__u_2() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:9]
+; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3029,6 +3105,8 @@ define void @s_shuffle_v2i64_v3i64__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -3135,10 +3213,12 @@ define void @s_shuffle_v2i64_v3i64__3_2() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:9]
+; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3148,10 +3228,12 @@ define void @s_shuffle_v2i64_v3i64__3_2() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:9]
+; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3163,6 +3245,8 @@ define void @s_shuffle_v2i64_v3i64__3_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -3299,6 +3383,8 @@ define void @s_shuffle_v2i64_v3i64__1_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3312,6 +3398,8 @@ define void @s_shuffle_v2i64_v3i64__1_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3325,6 +3413,8 @@ define void @s_shuffle_v2i64_v3i64__1_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3342,6 +3432,8 @@ define void @s_shuffle_v2i64_v3i64__2_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3353,6 +3445,8 @@ define void @s_shuffle_v2i64_v3i64__2_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3364,6 +3458,8 @@ define void @s_shuffle_v2i64_v3i64__2_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3714,10 +3810,12 @@ define void @s_shuffle_v2i64_v3i64__u_5() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:9]
+; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3727,10 +3825,12 @@ define void @s_shuffle_v2i64_v3i64__u_5() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:9]
+; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3742,6 +3842,8 @@ define void @s_shuffle_v2i64_v3i64__u_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
index e756a7ae1682d..bebdff06a3446 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v4i64.ll
@@ -62,6 +62,8 @@ define void @v_shuffle_v2i64_v4i64__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -73,6 +75,8 @@ define void @v_shuffle_v2i64_v4i64__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -84,6 +88,8 @@ define void @v_shuffle_v2i64_v4i64__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -136,33 +142,39 @@ define void @v_shuffle_v2i64_v4i64__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v4i64__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v4i64__3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v4i64__3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -190,6 +202,8 @@ define void @v_shuffle_v2i64_v4i64__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -201,6 +215,8 @@ define void @v_shuffle_v2i64_v4i64__5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -212,6 +228,8 @@ define void @v_shuffle_v2i64_v4i64__5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -266,33 +284,39 @@ define void @v_shuffle_v2i64_v4i64__7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v4i64__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v4i64__7_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v4i64__7_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -2213,6 +2237,8 @@ define void @v_shuffle_v2i64_v4i64__1_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2224,6 +2250,8 @@ define void @v_shuffle_v2i64_v4i64__1_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2235,6 +2263,8 @@ define void @v_shuffle_v2i64_v4i64__1_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2287,33 +2317,39 @@ define void @v_shuffle_v2i64_v4i64__3_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2i64_v4i64__3_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v4i64__3_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v4i64__3_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -3673,6 +3709,8 @@ define void @s_shuffle_v2i64_v4i64__1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3686,6 +3724,8 @@ define void @s_shuffle_v2i64_v4i64__1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3699,6 +3739,8 @@ define void @s_shuffle_v2i64_v4i64__1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3758,6 +3800,8 @@ define void @s_shuffle_v2i64_v4i64__3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3771,6 +3815,8 @@ define void @s_shuffle_v2i64_v4i64__3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3784,6 +3830,8 @@ define void @s_shuffle_v2i64_v4i64__3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3817,6 +3865,8 @@ define void @s_shuffle_v2i64_v4i64__5_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3830,6 +3880,8 @@ define void @s_shuffle_v2i64_v4i64__5_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3843,6 +3895,8 @@ define void @s_shuffle_v2i64_v4i64__5_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3904,6 +3958,8 @@ define void @s_shuffle_v2i64_v4i64__7_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3917,6 +3973,8 @@ define void @s_shuffle_v2i64_v4i64__7_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3930,6 +3988,8 @@ define void @s_shuffle_v2i64_v4i64__7_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -4326,6 +4386,8 @@ define void @s_shuffle_v2i64_v4i64__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -4339,6 +4401,8 @@ define void @s_shuffle_v2i64_v4i64__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -4352,6 +4416,8 @@ define void @s_shuffle_v2i64_v4i64__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -4511,6 +4577,8 @@ define void @s_shuffle_v2i64_v4i64__4_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -4524,6 +4592,8 @@ define void @s_shuffle_v2i64_v4i64__4_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -4537,6 +4607,8 @@ define void @s_shuffle_v2i64_v4i64__4_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -4960,10 +5032,12 @@ define void @s_shuffle_v2i64_v4i64__u_2() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -4973,10 +5047,12 @@ define void @s_shuffle_v2i64_v4i64__u_2() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -4988,6 +5064,8 @@ define void @s_shuffle_v2i64_v4i64__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -5145,10 +5223,12 @@ define void @s_shuffle_v2i64_v4i64__4_2() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -5158,10 +5238,12 @@ define void @s_shuffle_v2i64_v4i64__4_2() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -5173,6 +5255,8 @@ define void @s_shuffle_v2i64_v4i64__4_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -5654,6 +5738,8 @@ define void @s_shuffle_v2i64_v4i64__1_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -5667,6 +5753,8 @@ define void @s_shuffle_v2i64_v4i64__1_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -5680,6 +5768,8 @@ define void @s_shuffle_v2i64_v4i64__1_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -5739,6 +5829,8 @@ define void @s_shuffle_v2i64_v4i64__3_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -5752,6 +5844,8 @@ define void @s_shuffle_v2i64_v4i64__3_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -5765,6 +5859,8 @@ define void @s_shuffle_v2i64_v4i64__3_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -6209,10 +6305,12 @@ define void @s_shuffle_v2i64_v4i64__u_6() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6222,10 +6320,12 @@ define void @s_shuffle_v2i64_v4i64__u_6() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -6237,6 +6337,8 @@ define void @s_shuffle_v2i64_v4i64__u_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
index a747af428c1b5..9af3d6584a78b 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
@@ -62,6 +62,8 @@ define void @v_shuffle_v2i64_v8i64__1_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v16, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -73,6 +75,8 @@ define void @v_shuffle_v2i64_v8i64__1_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v16, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -84,6 +88,8 @@ define void @v_shuffle_v2i64_v8i64__1_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v16, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -140,6 +146,8 @@ define void @v_shuffle_v2i64_v8i64__3_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -151,6 +159,8 @@ define void @v_shuffle_v2i64_v8i64__3_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -162,6 +172,8 @@ define void @v_shuffle_v2i64_v8i64__3_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +230,8 @@ define void @v_shuffle_v2i64_v8i64__5_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr12
+; GFX900-NEXT: ; implicit-def: $vgpr13
; GFX900-NEXT: global_store_dwordx4 v16, v[10:13], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -229,6 +243,8 @@ define void @v_shuffle_v2i64_v8i64__5_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr12
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: global_store_dwordx4 v16, v[10:13], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -240,6 +256,8 @@ define void @v_shuffle_v2i64_v8i64__5_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr12
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: global_store_dwordx4 v16, v[10:13], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -292,33 +310,39 @@ define void @v_shuffle_v2i64_v8i64__7_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-LABEL: v_shuffle_v2i64_v8i64__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v16, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v16, v[14:17], s[16:17]
+; GFX900-NEXT: v_mov_b32_e32 v0, 0
+; GFX900-NEXT: ; implicit-def: $vgpr16
+; GFX900-NEXT: ; implicit-def: $vgpr17
+; GFX900-NEXT: global_store_dwordx4 v0, v[14:17], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v8i64__7_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: v_mov_b32_e32 v18, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v16, v[14:17], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr16
+; GFX90A-NEXT: ; implicit-def: $vgpr17
+; GFX90A-NEXT: global_store_dwordx4 v18, v[14:17], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v8i64__7_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: v_mov_b32_e32 v18, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v16, v[14:17], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr16
+; GFX942-NEXT: ; implicit-def: $vgpr17
+; GFX942-NEXT: global_store_dwordx4 v18, v[14:17], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x i64> asm "; def $0", "=v"()
@@ -346,6 +370,8 @@ define void @v_shuffle_v2i64_v8i64__9_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v16, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -357,6 +383,8 @@ define void @v_shuffle_v2i64_v8i64__9_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v16, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -368,6 +396,8 @@ define void @v_shuffle_v2i64_v8i64__9_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v16, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -426,6 +456,8 @@ define void @v_shuffle_v2i64_v8i64__11_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -437,6 +469,8 @@ define void @v_shuffle_v2i64_v8i64__11_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -448,6 +482,8 @@ define void @v_shuffle_v2i64_v8i64__11_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -506,6 +542,8 @@ define void @v_shuffle_v2i64_v8i64__13_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr12
+; GFX900-NEXT: ; implicit-def: $vgpr13
; GFX900-NEXT: global_store_dwordx4 v16, v[10:13], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -517,6 +555,8 @@ define void @v_shuffle_v2i64_v8i64__13_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr12
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: global_store_dwordx4 v16, v[10:13], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -528,6 +568,8 @@ define void @v_shuffle_v2i64_v8i64__13_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr12
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: global_store_dwordx4 v16, v[10:13], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -582,33 +624,39 @@ define void @v_shuffle_v2i64_v8i64__15_u(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-LABEL: v_shuffle_v2i64_v8i64__15_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v16, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v16, v[14:17], s[16:17]
+; GFX900-NEXT: v_mov_b32_e32 v0, 0
+; GFX900-NEXT: ; implicit-def: $vgpr16
+; GFX900-NEXT: ; implicit-def: $vgpr17
+; GFX900-NEXT: global_store_dwordx4 v0, v[14:17], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v8i64__15_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: v_mov_b32_e32 v18, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v16, v[14:17], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr16
+; GFX90A-NEXT: ; implicit-def: $vgpr17
+; GFX90A-NEXT: global_store_dwordx4 v18, v[14:17], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v8i64__15_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: v_mov_b32_e32 v18, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v16, v[14:17], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr16
+; GFX942-NEXT: ; implicit-def: $vgpr17
+; GFX942-NEXT: global_store_dwordx4 v18, v[14:17], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x i64> asm "; def $0", "=v"()
@@ -7609,6 +7657,8 @@ define void @v_shuffle_v2i64_v8i64__1_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v16, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7620,6 +7670,8 @@ define void @v_shuffle_v2i64_v8i64__1_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v16, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7631,6 +7683,8 @@ define void @v_shuffle_v2i64_v8i64__1_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v16, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7687,6 +7741,8 @@ define void @v_shuffle_v2i64_v8i64__3_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7698,6 +7754,8 @@ define void @v_shuffle_v2i64_v8i64__3_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7709,6 +7767,8 @@ define void @v_shuffle_v2i64_v8i64__3_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7765,6 +7825,8 @@ define void @v_shuffle_v2i64_v8i64__5_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr12
+; GFX900-NEXT: ; implicit-def: $vgpr13
; GFX900-NEXT: global_store_dwordx4 v16, v[10:13], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7776,6 +7838,8 @@ define void @v_shuffle_v2i64_v8i64__5_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr12
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: global_store_dwordx4 v16, v[10:13], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7787,6 +7851,8 @@ define void @v_shuffle_v2i64_v8i64__5_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr12
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: global_store_dwordx4 v16, v[10:13], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7839,33 +7905,39 @@ define void @v_shuffle_v2i64_v8i64__7_8(ptr addrspace(1) inreg %ptr) #0 {
; GFX900-LABEL: v_shuffle_v2i64_v8i64__7_8:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v16, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v16, v[14:17], s[16:17]
+; GFX900-NEXT: v_mov_b32_e32 v0, 0
+; GFX900-NEXT: ; implicit-def: $vgpr16
+; GFX900-NEXT: ; implicit-def: $vgpr17
+; GFX900-NEXT: global_store_dwordx4 v0, v[14:17], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2i64_v8i64__7_8:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: v_mov_b32_e32 v18, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v16, v[14:17], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr16
+; GFX90A-NEXT: ; implicit-def: $vgpr17
+; GFX90A-NEXT: global_store_dwordx4 v18, v[14:17], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2i64_v8i64__7_8:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: v_mov_b32_e32 v18, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v16, v[14:17], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr16
+; GFX942-NEXT: ; implicit-def: $vgpr17
+; GFX942-NEXT: global_store_dwordx4 v18, v[14:17], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x i64> asm "; def $0", "=v"()
@@ -13845,6 +13917,8 @@ define void @s_shuffle_v2i64_v8i64__1_u() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -13858,6 +13932,8 @@ define void @s_shuffle_v2i64_v8i64__1_u() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -13871,6 +13947,8 @@ define void @s_shuffle_v2i64_v8i64__1_u() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -13930,6 +14008,8 @@ define void @s_shuffle_v2i64_v8i64__3_u() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -13943,6 +14023,8 @@ define void @s_shuffle_v2i64_v8i64__3_u() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -13956,6 +14038,8 @@ define void @s_shuffle_v2i64_v8i64__3_u() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -14019,6 +14103,8 @@ define void @s_shuffle_v2i64_v8i64__5_u() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s14
; GFX900-NEXT: s_mov_b32 s9, s15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -14032,6 +14118,8 @@ define void @s_shuffle_v2i64_v8i64__5_u() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s14
; GFX90A-NEXT: s_mov_b32 s9, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -14045,6 +14133,8 @@ define void @s_shuffle_v2i64_v8i64__5_u() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -14109,6 +14199,8 @@ define void @s_shuffle_v2i64_v8i64__7_u() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -14122,6 +14214,8 @@ define void @s_shuffle_v2i64_v8i64__7_u() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -14135,6 +14229,8 @@ define void @s_shuffle_v2i64_v8i64__7_u() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s14
; GFX942-NEXT: s_mov_b32 s9, s15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -14168,6 +14264,8 @@ define void @s_shuffle_v2i64_v8i64__9_u() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -14181,6 +14279,8 @@ define void @s_shuffle_v2i64_v8i64__9_u() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -14194,6 +14294,8 @@ define void @s_shuffle_v2i64_v8i64__9_u() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -14255,6 +14357,8 @@ define void @s_shuffle_v2i64_v8i64__11_u() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -14268,6 +14372,8 @@ define void @s_shuffle_v2i64_v8i64__11_u() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -14281,6 +14387,8 @@ define void @s_shuffle_v2i64_v8i64__11_u() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -14346,6 +14454,8 @@ define void @s_shuffle_v2i64_v8i64__13_u() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s14
; GFX900-NEXT: s_mov_b32 s9, s15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -14359,6 +14469,8 @@ define void @s_shuffle_v2i64_v8i64__13_u() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s14
; GFX90A-NEXT: s_mov_b32 s9, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -14372,6 +14484,8 @@ define void @s_shuffle_v2i64_v8i64__13_u() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -14438,6 +14552,8 @@ define void @s_shuffle_v2i64_v8i64__15_u() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -14451,6 +14567,8 @@ define void @s_shuffle_v2i64_v8i64__15_u() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -14464,6 +14582,8 @@ define void @s_shuffle_v2i64_v8i64__15_u() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s14
; GFX942-NEXT: s_mov_b32 s9, s15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -15475,6 +15595,8 @@ define void @s_shuffle_v2i64_v8i64__u_0() #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -15488,6 +15610,8 @@ define void @s_shuffle_v2i64_v8i64__u_0() #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -15501,6 +15625,8 @@ define void @s_shuffle_v2i64_v8i64__u_0() #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -15862,6 +15988,8 @@ define void @s_shuffle_v2i64_v8i64__8_0() #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -15875,6 +16003,8 @@ define void @s_shuffle_v2i64_v8i64__8_0() #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -15888,6 +16018,8 @@ define void @s_shuffle_v2i64_v8i64__8_0() #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -17044,10 +17176,12 @@ define void @s_shuffle_v2i64_v8i64__u_2() #0 {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
+; GFX900-NEXT: ; def s[8:23]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -17057,10 +17191,12 @@ define void @s_shuffle_v2i64_v8i64__u_2() #0 {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
+; GFX90A-NEXT: ; def s[8:23]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -17072,6 +17208,8 @@ define void @s_shuffle_v2i64_v8i64__u_2() #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -17431,10 +17569,12 @@ define void @s_shuffle_v2i64_v8i64__8_2() #0 {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
+; GFX900-NEXT: ; def s[8:23]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -17444,10 +17584,12 @@ define void @s_shuffle_v2i64_v8i64__8_2() #0 {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
+; GFX90A-NEXT: ; def s[8:23]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -17459,6 +17601,8 @@ define void @s_shuffle_v2i64_v8i64__8_2() #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -18631,44 +18775,20 @@ define void @s_shuffle_v2i64_v8i64__14_3() #0 {
}
define void @s_shuffle_v2i64_v8i64__u_4() #0 {
-; GFX900-LABEL: s_shuffle_v2i64_v8i64__u_4:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s12
-; GFX900-NEXT: s_mov_b32 s11, s13
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use s[8:11]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX90A-LABEL: s_shuffle_v2i64_v8i64__u_4:
-; GFX90A: ; %bb.0:
-; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s12
-; GFX90A-NEXT: s_mov_b32 s11, s13
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; use s[8:11]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX942-LABEL: s_shuffle_v2i64_v8i64__u_4:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s8
-; GFX942-NEXT: s_mov_b32 s11, s9
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; use s[8:11]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: s_shuffle_v2i64_v8i64__u_4:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[4:19]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr8
+; GFX9-NEXT: ; implicit-def: $sgpr9
+; GFX9-NEXT: s_mov_b32 s10, s12
+; GFX9-NEXT: s_mov_b32 s11, s13
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use s[8:11]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x i64> asm "; def $0", "=s"()
%shuf = shufflevector <8 x i64> %vec0, <8 x i64> poison, <2 x i32> <i32 poison, i32 4>
call void asm sideeffect "; use $0", "{s[8:11]}"(<2 x i64> %shuf)
@@ -18898,44 +19018,20 @@ define void @s_shuffle_v2i64_v8i64__7_4() #0 {
}
define void @s_shuffle_v2i64_v8i64__8_4() #0 {
-; GFX900-LABEL: s_shuffle_v2i64_v8i64__8_4:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s12
-; GFX900-NEXT: s_mov_b32 s11, s13
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use s[8:11]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX90A-LABEL: s_shuffle_v2i64_v8i64__8_4:
-; GFX90A: ; %bb.0:
-; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s12
-; GFX90A-NEXT: s_mov_b32 s11, s13
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; use s[8:11]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX942-LABEL: s_shuffle_v2i64_v8i64__8_4:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s8
-; GFX942-NEXT: s_mov_b32 s11, s9
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; use s[8:11]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: s_shuffle_v2i64_v8i64__8_4:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[4:19]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr8
+; GFX9-NEXT: ; implicit-def: $sgpr9
+; GFX9-NEXT: s_mov_b32 s10, s12
+; GFX9-NEXT: s_mov_b32 s11, s13
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use s[8:11]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x i64> asm "; def $0", "=s"()
%shuf = shufflevector <8 x i64> %vec0, <8 x i64> poison, <2 x i32> <i32 8, i32 4>
call void asm sideeffect "; use $0", "{s[8:11]}"(<2 x i64> %shuf)
@@ -20341,6 +20437,8 @@ define void @s_shuffle_v2i64_v8i64__u_6() #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s16
; GFX900-NEXT: s_mov_b32 s11, s17
; GFX900-NEXT: ;;#ASMSTART
@@ -20354,6 +20452,8 @@ define void @s_shuffle_v2i64_v8i64__u_6() #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s16
; GFX90A-NEXT: s_mov_b32 s11, s17
; GFX90A-NEXT: ;;#ASMSTART
@@ -20367,6 +20467,8 @@ define void @s_shuffle_v2i64_v8i64__u_6() #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s12
; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
@@ -20728,6 +20830,8 @@ define void @s_shuffle_v2i64_v8i64__8_6() #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s16
; GFX900-NEXT: s_mov_b32 s11, s17
; GFX900-NEXT: ;;#ASMSTART
@@ -20741,6 +20845,8 @@ define void @s_shuffle_v2i64_v8i64__8_6() #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s16
; GFX90A-NEXT: s_mov_b32 s11, s17
; GFX90A-NEXT: ;;#ASMSTART
@@ -20754,6 +20860,8 @@ define void @s_shuffle_v2i64_v8i64__8_6() #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s12
; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
@@ -22531,6 +22639,8 @@ define void @s_shuffle_v2i64_v8i64__1_8() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -22544,6 +22654,8 @@ define void @s_shuffle_v2i64_v8i64__1_8() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -22557,6 +22669,8 @@ define void @s_shuffle_v2i64_v8i64__1_8() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -22616,6 +22730,8 @@ define void @s_shuffle_v2i64_v8i64__3_8() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -22629,6 +22745,8 @@ define void @s_shuffle_v2i64_v8i64__3_8() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -22642,6 +22760,8 @@ define void @s_shuffle_v2i64_v8i64__3_8() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -22705,6 +22825,8 @@ define void @s_shuffle_v2i64_v8i64__5_8() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s14
; GFX900-NEXT: s_mov_b32 s9, s15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -22718,6 +22840,8 @@ define void @s_shuffle_v2i64_v8i64__5_8() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s14
; GFX90A-NEXT: s_mov_b32 s9, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -22731,6 +22855,8 @@ define void @s_shuffle_v2i64_v8i64__5_8() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -22795,6 +22921,8 @@ define void @s_shuffle_v2i64_v8i64__7_8() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -22808,6 +22936,8 @@ define void @s_shuffle_v2i64_v8i64__7_8() #0 {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -22821,6 +22951,8 @@ define void @s_shuffle_v2i64_v8i64__7_8() #0 {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s14
; GFX942-NEXT: s_mov_b32 s9, s15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -24009,10 +24141,12 @@ define void @s_shuffle_v2i64_v8i64__u_10() #0 {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
+; GFX900-NEXT: ; def s[8:23]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -24022,10 +24156,12 @@ define void @s_shuffle_v2i64_v8i64__u_10() #0 {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
+; GFX90A-NEXT: ; def s[8:23]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -24037,6 +24173,8 @@ define void @s_shuffle_v2i64_v8i64__u_10() #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -25869,44 +26007,20 @@ define void @s_shuffle_v2i64_v8i64__14_11() #0 {
}
define void @s_shuffle_v2i64_v8i64__u_12() #0 {
-; GFX900-LABEL: s_shuffle_v2i64_v8i64__u_12:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:19]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s12
-; GFX900-NEXT: s_mov_b32 s11, s13
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use s[8:11]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX90A-LABEL: s_shuffle_v2i64_v8i64__u_12:
-; GFX90A: ; %bb.0:
-; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:19]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s12
-; GFX90A-NEXT: s_mov_b32 s11, s13
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; use s[8:11]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX942-LABEL: s_shuffle_v2i64_v8i64__u_12:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s8
-; GFX942-NEXT: s_mov_b32 s11, s9
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; use s[8:11]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: s_shuffle_v2i64_v8i64__u_12:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[4:19]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr8
+; GFX9-NEXT: ; implicit-def: $sgpr9
+; GFX9-NEXT: s_mov_b32 s10, s12
+; GFX9-NEXT: s_mov_b32 s11, s13
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use s[8:11]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x i64> asm "; def $0", "=s"()
%vec1 = call <8 x i64> asm "; def $0", "=s"()
%shuf = shufflevector <8 x i64> %vec0, <8 x i64> %vec1, <2 x i32> <i32 poison, i32 12>
@@ -27732,6 +27846,8 @@ define void @s_shuffle_v2i64_v8i64__u_14() #0 {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s16
; GFX900-NEXT: s_mov_b32 s11, s17
; GFX900-NEXT: ;;#ASMSTART
@@ -27745,6 +27861,8 @@ define void @s_shuffle_v2i64_v8i64__u_14() #0 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s16
; GFX90A-NEXT: s_mov_b32 s11, s17
; GFX90A-NEXT: ;;#ASMSTART
@@ -27758,6 +27876,8 @@ define void @s_shuffle_v2i64_v8i64__u_14() #0 {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s12
; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
index 411d8b735b9b6..bae94ff4267a8 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v2p0.ll
@@ -58,33 +58,39 @@ define void @v_shuffle_v2p0_v2p0__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v2p0__1_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v2p0__1_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v2p0__1_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -108,33 +114,39 @@ define void @v_shuffle_v2p0_v2p0__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v2p0__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v2p0__3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v2p0__3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -723,33 +735,39 @@ define void @v_shuffle_v2p0_v2p0__1_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v2p0__1_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v2p0__1_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v2p0__1_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -1023,6 +1041,8 @@ define void @s_shuffle_v2p0_v2p0__1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -1036,6 +1056,8 @@ define void @s_shuffle_v2p0_v2p0__1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -1049,6 +1071,8 @@ define void @s_shuffle_v2p0_v2p0__1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -1082,6 +1106,8 @@ define void @s_shuffle_v2p0_v2p0__3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -1095,6 +1121,8 @@ define void @s_shuffle_v2p0_v2p0__3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -1108,6 +1136,8 @@ define void @s_shuffle_v2p0_v2p0__3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -1314,6 +1344,8 @@ define void @s_shuffle_v2p0_v2p0__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -1327,6 +1359,8 @@ define void @s_shuffle_v2p0_v2p0__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -1340,6 +1374,8 @@ define void @s_shuffle_v2p0_v2p0__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -1429,6 +1465,8 @@ define void @s_shuffle_v2p0_v2p0__2_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -1442,6 +1480,8 @@ define void @s_shuffle_v2p0_v2p0__2_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -1455,6 +1495,8 @@ define void @s_shuffle_v2p0_v2p0__2_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -1669,6 +1711,8 @@ define void @s_shuffle_v2p0_v2p0__1_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -1682,6 +1726,8 @@ define void @s_shuffle_v2p0_v2p0__1_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -1695,6 +1741,8 @@ define void @s_shuffle_v2p0_v2p0__1_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
index 385dc73531d14..633b70a431873 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v3p0.ll
@@ -62,6 +62,8 @@ define void @v_shuffle_v2p0_v3p0__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -73,6 +75,8 @@ define void @v_shuffle_v2p0_v3p0__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -84,6 +88,8 @@ define void @v_shuffle_v2p0_v3p0__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -97,33 +103,39 @@ define void @v_shuffle_v2p0_v3p0__2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v3p0__2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v3p0__2_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v3p0__2_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -151,6 +163,8 @@ define void @v_shuffle_v2p0_v3p0__4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -162,6 +176,8 @@ define void @v_shuffle_v2p0_v3p0__4_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -173,6 +189,8 @@ define void @v_shuffle_v2p0_v3p0__4_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -187,33 +205,39 @@ define void @v_shuffle_v2p0_v3p0__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v3p0__5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v3p0__5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v3p0__5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -1369,6 +1393,8 @@ define void @v_shuffle_v2p0_v3p0__1_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1380,6 +1406,8 @@ define void @v_shuffle_v2p0_v3p0__1_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1391,6 +1419,8 @@ define void @v_shuffle_v2p0_v3p0__1_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1404,33 +1434,39 @@ define void @v_shuffle_v2p0_v3p0__2_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v3p0__2_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v3p0__2_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v3p0__2_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -2145,6 +2181,8 @@ define void @s_shuffle_v2p0_v3p0__1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -2158,6 +2196,8 @@ define void @s_shuffle_v2p0_v3p0__1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -2171,6 +2211,8 @@ define void @s_shuffle_v2p0_v3p0__1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -2188,6 +2230,8 @@ define void @s_shuffle_v2p0_v3p0__2_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -2199,6 +2243,8 @@ define void @s_shuffle_v2p0_v3p0__2_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -2210,6 +2256,8 @@ define void @s_shuffle_v2p0_v3p0__2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -2244,6 +2292,8 @@ define void @s_shuffle_v2p0_v3p0__4_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -2257,6 +2307,8 @@ define void @s_shuffle_v2p0_v3p0__4_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -2270,6 +2322,8 @@ define void @s_shuffle_v2p0_v3p0__4_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -2288,6 +2342,8 @@ define void @s_shuffle_v2p0_v3p0__5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -2299,6 +2355,8 @@ define void @s_shuffle_v2p0_v3p0__5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -2310,6 +2368,8 @@ define void @s_shuffle_v2p0_v3p0__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -2550,6 +2610,8 @@ define void @s_shuffle_v2p0_v3p0__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -2563,6 +2625,8 @@ define void @s_shuffle_v2p0_v3p0__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -2576,6 +2640,8 @@ define void @s_shuffle_v2p0_v3p0__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -2684,6 +2750,8 @@ define void @s_shuffle_v2p0_v3p0__3_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -2697,6 +2765,8 @@ define void @s_shuffle_v2p0_v3p0__3_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -2710,6 +2780,8 @@ define void @s_shuffle_v2p0_v3p0__3_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -3001,10 +3073,12 @@ define void @s_shuffle_v2p0_v3p0__u_2() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:9]
+; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3014,10 +3088,12 @@ define void @s_shuffle_v2p0_v3p0__u_2() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:9]
+; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3029,6 +3105,8 @@ define void @s_shuffle_v2p0_v3p0__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -3135,10 +3213,12 @@ define void @s_shuffle_v2p0_v3p0__3_2() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:9]
+; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3148,10 +3228,12 @@ define void @s_shuffle_v2p0_v3p0__3_2() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:9]
+; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3163,6 +3245,8 @@ define void @s_shuffle_v2p0_v3p0__3_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -3299,6 +3383,8 @@ define void @s_shuffle_v2p0_v3p0__1_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3312,6 +3398,8 @@ define void @s_shuffle_v2p0_v3p0__1_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3325,6 +3413,8 @@ define void @s_shuffle_v2p0_v3p0__1_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3342,6 +3432,8 @@ define void @s_shuffle_v2p0_v3p0__2_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3353,6 +3445,8 @@ define void @s_shuffle_v2p0_v3p0__2_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3364,6 +3458,8 @@ define void @s_shuffle_v2p0_v3p0__2_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3714,10 +3810,12 @@ define void @s_shuffle_v2p0_v3p0__u_5() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:9]
+; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3727,10 +3825,12 @@ define void @s_shuffle_v2p0_v3p0__u_5() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:9]
+; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3742,6 +3842,8 @@ define void @s_shuffle_v2p0_v3p0__u_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
index 70d72571b9897..71cc1b45654f9 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p0.v4p0.ll
@@ -62,6 +62,8 @@ define void @v_shuffle_v2p0_v4p0__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -73,6 +75,8 @@ define void @v_shuffle_v2p0_v4p0__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -84,6 +88,8 @@ define void @v_shuffle_v2p0_v4p0__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -136,33 +142,39 @@ define void @v_shuffle_v2p0_v4p0__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v4p0__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v4p0__3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v4p0__3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -190,6 +202,8 @@ define void @v_shuffle_v2p0_v4p0__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -201,6 +215,8 @@ define void @v_shuffle_v2p0_v4p0__5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -212,6 +228,8 @@ define void @v_shuffle_v2p0_v4p0__5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -266,33 +284,39 @@ define void @v_shuffle_v2p0_v4p0__7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v4p0__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v4p0__7_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v4p0__7_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -2213,6 +2237,8 @@ define void @v_shuffle_v2p0_v4p0__1_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2224,6 +2250,8 @@ define void @v_shuffle_v2p0_v4p0__1_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2235,6 +2263,8 @@ define void @v_shuffle_v2p0_v4p0__1_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2287,33 +2317,39 @@ define void @v_shuffle_v2p0_v4p0__3_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p0_v4p0__3_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p0_v4p0__3_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p0_v4p0__3_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -3673,6 +3709,8 @@ define void @s_shuffle_v2p0_v4p0__1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3686,6 +3724,8 @@ define void @s_shuffle_v2p0_v4p0__1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3699,6 +3739,8 @@ define void @s_shuffle_v2p0_v4p0__1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3758,6 +3800,8 @@ define void @s_shuffle_v2p0_v4p0__3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3771,6 +3815,8 @@ define void @s_shuffle_v2p0_v4p0__3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3784,6 +3830,8 @@ define void @s_shuffle_v2p0_v4p0__3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3817,6 +3865,8 @@ define void @s_shuffle_v2p0_v4p0__5_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3830,6 +3880,8 @@ define void @s_shuffle_v2p0_v4p0__5_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3843,6 +3895,8 @@ define void @s_shuffle_v2p0_v4p0__5_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3904,6 +3958,8 @@ define void @s_shuffle_v2p0_v4p0__7_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3917,6 +3973,8 @@ define void @s_shuffle_v2p0_v4p0__7_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3930,6 +3988,8 @@ define void @s_shuffle_v2p0_v4p0__7_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -4326,6 +4386,8 @@ define void @s_shuffle_v2p0_v4p0__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -4339,6 +4401,8 @@ define void @s_shuffle_v2p0_v4p0__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -4352,6 +4416,8 @@ define void @s_shuffle_v2p0_v4p0__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -4511,6 +4577,8 @@ define void @s_shuffle_v2p0_v4p0__4_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -4524,6 +4592,8 @@ define void @s_shuffle_v2p0_v4p0__4_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -4537,6 +4607,8 @@ define void @s_shuffle_v2p0_v4p0__4_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -4960,10 +5032,12 @@ define void @s_shuffle_v2p0_v4p0__u_2() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -4973,10 +5047,12 @@ define void @s_shuffle_v2p0_v4p0__u_2() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -4988,6 +5064,8 @@ define void @s_shuffle_v2p0_v4p0__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -5145,10 +5223,12 @@ define void @s_shuffle_v2p0_v4p0__4_2() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -5158,10 +5238,12 @@ define void @s_shuffle_v2p0_v4p0__4_2() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -5173,6 +5255,8 @@ define void @s_shuffle_v2p0_v4p0__4_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
@@ -5654,6 +5738,8 @@ define void @s_shuffle_v2p0_v4p0__1_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -5667,6 +5753,8 @@ define void @s_shuffle_v2p0_v4p0__1_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -5680,6 +5768,8 @@ define void @s_shuffle_v2p0_v4p0__1_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -5739,6 +5829,8 @@ define void @s_shuffle_v2p0_v4p0__3_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -5752,6 +5844,8 @@ define void @s_shuffle_v2p0_v4p0__3_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -5765,6 +5859,8 @@ define void @s_shuffle_v2p0_v4p0__3_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -6209,10 +6305,12 @@ define void @s_shuffle_v2p0_v4p0__u_6() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s10, s12
+; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6222,10 +6320,12 @@ define void @s_shuffle_v2p0_v4p0__u_6() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s10, s12
+; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -6237,6 +6337,8 @@ define void @s_shuffle_v2p0_v4p0__u_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
index 02fb06ef54d42..5da7b4e5880dd 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v2p3.ll
@@ -58,11 +58,12 @@ define void @v_shuffle_v2p3_v2p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v2p3__1_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +75,7 @@ define void @v_shuffle_v2p3_v2p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2p3_v2p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -110,11 +113,12 @@ define void @v_shuffle_v2p3_v2p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v2p3__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -126,6 +130,7 @@ define void @v_shuffle_v2p3_v2p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -138,6 +143,7 @@ define void @v_shuffle_v2p3_v2p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -353,24 +359,27 @@ define void @v_shuffle_v2p3_v2p3__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2p3_v2p3__u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p3_v2p3__u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -478,24 +487,27 @@ define void @v_shuffle_v2p3_v2p3__2_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2p3_v2p3__2_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p3_v2p3__2_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -717,11 +729,12 @@ define void @v_shuffle_v2p3_v2p3__1_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v2p3__1_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -733,6 +746,7 @@ define void @v_shuffle_v2p3_v2p3__1_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -745,6 +759,7 @@ define void @v_shuffle_v2p3_v2p3__1_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1012,6 +1027,7 @@ define void @s_shuffle_v2p3_v2p3__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1024,6 +1040,7 @@ define void @s_shuffle_v2p3_v2p3__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1036,6 +1053,7 @@ define void @s_shuffle_v2p3_v2p3__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1068,6 +1086,7 @@ define void @s_shuffle_v2p3_v2p3__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1080,6 +1099,7 @@ define void @s_shuffle_v2p3_v2p3__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1092,6 +1112,7 @@ define void @s_shuffle_v2p3_v2p3__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1283,6 +1304,7 @@ define void @s_shuffle_v2p3_v2p3__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1295,6 +1317,7 @@ define void @s_shuffle_v2p3_v2p3__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1307,6 +1330,7 @@ define void @s_shuffle_v2p3_v2p3__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1388,6 +1412,7 @@ define void @s_shuffle_v2p3_v2p3__2_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1400,6 +1425,7 @@ define void @s_shuffle_v2p3_v2p3__2_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1412,6 +1438,7 @@ define void @s_shuffle_v2p3_v2p3__2_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -1622,6 +1649,7 @@ define void @s_shuffle_v2p3_v2p3__1_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -1634,6 +1662,7 @@ define void @s_shuffle_v2p3_v2p3__1_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -1646,6 +1675,7 @@ define void @s_shuffle_v2p3_v2p3__1_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
index d0f00f8363aed..2bf5594dc76ce 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v3p3.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2p3_v3p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2p3_v3p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2p3_v3p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +102,36 @@ define void @v_shuffle_v2p3_v3p3__2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v3p3__2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p3_v3p3__2_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p3_v3p3__2_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -153,6 +159,7 @@ define void @v_shuffle_v2p3_v3p3__4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -165,6 +172,7 @@ define void @v_shuffle_v2p3_v3p3__4_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -177,6 +185,7 @@ define void @v_shuffle_v2p3_v3p3__4_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -191,33 +200,36 @@ define void @v_shuffle_v2p3_v3p3__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v3p3__5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p3_v3p3__5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p3_v3p3__5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -527,24 +539,27 @@ define void @v_shuffle_v2p3_v3p3__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2p3_v3p3__u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx2 v3, v[4:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p3_v3p3__u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v5, v0
+; GFX942-NEXT: global_store_dwordx2 v3, v[4:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -695,24 +710,27 @@ define void @v_shuffle_v2p3_v3p3__3_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v2p3_v3p3__3_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx2 v3, v[4:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p3_v3p3__3_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v5, v0
+; GFX942-NEXT: global_store_dwordx2 v3, v[4:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -743,6 +761,7 @@ define void @v_shuffle_v2p3_v3p3__4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
@@ -758,6 +777,7 @@ define void @v_shuffle_v2p3_v3p3__4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
@@ -1049,6 +1069,7 @@ define void @v_shuffle_v2p3_v3p3__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1061,6 +1082,7 @@ define void @v_shuffle_v2p3_v3p3__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1218,6 +1240,7 @@ define void @v_shuffle_v2p3_v3p3__3_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1230,6 +1253,7 @@ define void @v_shuffle_v2p3_v3p3__3_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1351,6 +1375,7 @@ define void @v_shuffle_v2p3_v3p3__1_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1363,6 +1388,7 @@ define void @v_shuffle_v2p3_v3p3__1_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1375,6 +1401,7 @@ define void @v_shuffle_v2p3_v3p3__1_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1388,33 +1415,36 @@ define void @v_shuffle_v2p3_v3p3__2_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v3p3__2_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v2p3_v3p3__2_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v3, v[2:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v2p3_v3p3__2_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v3, v[2:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1779,6 +1809,7 @@ define void @v_shuffle_v2p3_v3p3__u_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1791,6 +1822,7 @@ define void @v_shuffle_v2p3_v3p3__u_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2109,6 +2141,7 @@ define void @s_shuffle_v2p3_v3p3__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2121,6 +2154,7 @@ define void @s_shuffle_v2p3_v3p3__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2133,6 +2167,7 @@ define void @s_shuffle_v2p3_v3p3__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2151,6 +2186,7 @@ define void @s_shuffle_v2p3_v3p3__2_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2163,6 +2199,7 @@ define void @s_shuffle_v2p3_v3p3__2_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2175,6 +2212,7 @@ define void @s_shuffle_v2p3_v3p3__2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2207,6 +2245,7 @@ define void @s_shuffle_v2p3_v3p3__4_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2219,6 +2258,7 @@ define void @s_shuffle_v2p3_v3p3__4_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2231,6 +2271,7 @@ define void @s_shuffle_v2p3_v3p3__4_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2250,6 +2291,7 @@ define void @s_shuffle_v2p3_v3p3__5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2262,6 +2304,7 @@ define void @s_shuffle_v2p3_v3p3__5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2274,6 +2317,7 @@ define void @s_shuffle_v2p3_v3p3__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2596,6 +2640,7 @@ define void @s_shuffle_v2p3_v3p3__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2608,6 +2653,7 @@ define void @s_shuffle_v2p3_v3p3__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2620,6 +2666,7 @@ define void @s_shuffle_v2p3_v3p3__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2746,6 +2793,7 @@ define void @s_shuffle_v2p3_v3p3__3_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2758,6 +2806,7 @@ define void @s_shuffle_v2p3_v3p3__3_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2770,6 +2819,7 @@ define void @s_shuffle_v2p3_v3p3__3_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3078,6 +3128,7 @@ define void @s_shuffle_v2p3_v3p3__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3090,6 +3141,7 @@ define void @s_shuffle_v2p3_v3p3__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3102,6 +3154,7 @@ define void @s_shuffle_v2p3_v3p3__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3228,6 +3281,7 @@ define void @s_shuffle_v2p3_v3p3__3_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3240,6 +3294,7 @@ define void @s_shuffle_v2p3_v3p3__3_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3252,6 +3307,7 @@ define void @s_shuffle_v2p3_v3p3__3_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3379,6 +3435,7 @@ define void @s_shuffle_v2p3_v3p3__1_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3391,6 +3448,7 @@ define void @s_shuffle_v2p3_v3p3__1_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3403,6 +3461,7 @@ define void @s_shuffle_v2p3_v3p3__1_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3421,6 +3480,7 @@ define void @s_shuffle_v2p3_v3p3__2_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr7
; GFX900-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3433,6 +3493,7 @@ define void @s_shuffle_v2p3_v3p3__2_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr7
; GFX90A-NEXT: s_mov_b64 s[8:9], s[6:7]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3445,6 +3506,7 @@ define void @s_shuffle_v2p3_v3p3__2_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr3
; GFX942-NEXT: s_mov_b64 s[8:9], s[2:3]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3783,6 +3845,7 @@ define void @s_shuffle_v2p3_v3p3__u_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3795,6 +3858,7 @@ define void @s_shuffle_v2p3_v3p3__u_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3807,6 +3871,7 @@ define void @s_shuffle_v2p3_v3p3__u_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
index c35361721e9b0..65c5da4ec3d5a 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v4p3.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2p3_v4p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2p3_v4p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2p3_v4p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -138,11 +141,12 @@ define void @v_shuffle_v2p3_v4p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v4p3__3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +158,7 @@ define void @v_shuffle_v2p3_v4p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +171,7 @@ define void @v_shuffle_v2p3_v4p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -194,6 +200,7 @@ define void @v_shuffle_v2p3_v4p3__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -206,6 +213,7 @@ define void @v_shuffle_v2p3_v4p3__5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +226,7 @@ define void @v_shuffle_v2p3_v4p3__5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -272,11 +281,12 @@ define void @v_shuffle_v2p3_v4p3__7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v4p3__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +298,7 @@ define void @v_shuffle_v2p3_v4p3__7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +311,7 @@ define void @v_shuffle_v2p3_v4p3__7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -331,6 +343,7 @@ define void @v_shuffle_v2p3_v4p3__7_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
@@ -346,6 +359,7 @@ define void @v_shuffle_v2p3_v4p3__7_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -439,6 +453,7 @@ define void @v_shuffle_v2p3_v4p3__7_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -454,6 +469,7 @@ define void @v_shuffle_v2p3_v4p3__7_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
@@ -711,8 +727,9 @@ define void @v_shuffle_v2p3_v4p3__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -723,8 +740,9 @@ define void @v_shuffle_v2p3_v4p3__u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -922,8 +940,9 @@ define void @v_shuffle_v2p3_v4p3__4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -934,8 +953,9 @@ define void @v_shuffle_v2p3_v4p3__4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -966,6 +986,7 @@ define void @v_shuffle_v2p3_v4p3__5_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
@@ -981,6 +1002,7 @@ define void @v_shuffle_v2p3_v4p3__5_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -1419,6 +1441,7 @@ define void @v_shuffle_v2p3_v4p3__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1431,6 +1454,7 @@ define void @v_shuffle_v2p3_v4p3__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1629,6 +1653,7 @@ define void @v_shuffle_v2p3_v4p3__4_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1641,6 +1666,7 @@ define void @v_shuffle_v2p3_v4p3__4_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1676,6 +1702,7 @@ define void @v_shuffle_v2p3_v4p3__5_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -1691,6 +1718,7 @@ define void @v_shuffle_v2p3_v4p3__5_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
@@ -2163,6 +2191,7 @@ define void @v_shuffle_v2p3_v4p3__1_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v4, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2175,6 +2204,7 @@ define void @v_shuffle_v2p3_v4p3__1_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2187,6 +2217,7 @@ define void @v_shuffle_v2p3_v4p3__1_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2239,11 +2270,12 @@ define void @v_shuffle_v2p3_v4p3__3_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v4p3__3_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[3:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx2 v5, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2255,6 +2287,7 @@ define void @v_shuffle_v2p3_v4p3__3_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2267,6 +2300,7 @@ define void @v_shuffle_v2p3_v4p3__3_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2771,6 +2805,7 @@ define void @v_shuffle_v2p3_v4p3__u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2783,6 +2818,7 @@ define void @v_shuffle_v2p3_v4p3__u_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2868,10 +2904,11 @@ define void @v_shuffle_v2p3_v4p3__1_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -2887,6 +2924,7 @@ define void @v_shuffle_v2p3_v4p3__1_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]
@@ -2974,10 +3012,11 @@ define void @v_shuffle_v2p3_v4p3__3_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -2989,11 +3028,11 @@ define void @v_shuffle_v2p3_v4p3__3_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -3574,6 +3613,7 @@ define void @s_shuffle_v2p3_v4p3__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3586,6 +3626,7 @@ define void @s_shuffle_v2p3_v4p3__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3598,6 +3639,7 @@ define void @s_shuffle_v2p3_v4p3__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3658,6 +3700,7 @@ define void @s_shuffle_v2p3_v4p3__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3670,6 +3713,7 @@ define void @s_shuffle_v2p3_v4p3__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3682,6 +3726,7 @@ define void @s_shuffle_v2p3_v4p3__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3714,6 +3759,7 @@ define void @s_shuffle_v2p3_v4p3__5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3726,6 +3772,7 @@ define void @s_shuffle_v2p3_v4p3__5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3738,6 +3785,7 @@ define void @s_shuffle_v2p3_v4p3__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3800,6 +3848,7 @@ define void @s_shuffle_v2p3_v4p3__7_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3812,6 +3861,7 @@ define void @s_shuffle_v2p3_v4p3__7_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3824,6 +3874,7 @@ define void @s_shuffle_v2p3_v4p3__7_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4217,6 +4268,7 @@ define void @s_shuffle_v2p3_v4p3__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4229,6 +4281,7 @@ define void @s_shuffle_v2p3_v4p3__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4241,6 +4294,7 @@ define void @s_shuffle_v2p3_v4p3__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4412,6 +4466,7 @@ define void @s_shuffle_v2p3_v4p3__4_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4424,6 +4479,7 @@ define void @s_shuffle_v2p3_v4p3__4_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4436,6 +4492,7 @@ define void @s_shuffle_v2p3_v4p3__4_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4872,6 +4929,7 @@ define void @s_shuffle_v2p3_v4p3__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4884,6 +4942,7 @@ define void @s_shuffle_v2p3_v4p3__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4896,6 +4955,7 @@ define void @s_shuffle_v2p3_v4p3__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5067,6 +5127,7 @@ define void @s_shuffle_v2p3_v4p3__4_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5079,6 +5140,7 @@ define void @s_shuffle_v2p3_v4p3__4_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5091,6 +5153,7 @@ define void @s_shuffle_v2p3_v4p3__4_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5617,6 +5680,7 @@ define void @s_shuffle_v2p3_v4p3__1_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5629,6 +5693,7 @@ define void @s_shuffle_v2p3_v4p3__1_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5641,6 +5706,7 @@ define void @s_shuffle_v2p3_v4p3__1_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5701,6 +5767,7 @@ define void @s_shuffle_v2p3_v4p3__3_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5713,6 +5780,7 @@ define void @s_shuffle_v2p3_v4p3__3_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5725,6 +5793,7 @@ define void @s_shuffle_v2p3_v4p3__3_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -6207,6 +6276,7 @@ define void @s_shuffle_v2p3_v4p3__u_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -6219,6 +6289,7 @@ define void @s_shuffle_v2p3_v4p3__u_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -6231,6 +6302,7 @@ define void @s_shuffle_v2p3_v4p3__u_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
index 86ec2bc9816bc..99af1f22b69f2 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2p3.v8p3.ll
@@ -62,6 +62,7 @@ define void @v_shuffle_v2p3_v8p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +75,7 @@ define void @v_shuffle_v2p3_v8p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +88,7 @@ define void @v_shuffle_v2p3_v8p3__1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -142,6 +145,7 @@ define void @v_shuffle_v2p3_v8p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -154,6 +158,7 @@ define void @v_shuffle_v2p3_v8p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +171,7 @@ define void @v_shuffle_v2p3_v8p3__3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -222,6 +228,7 @@ define void @v_shuffle_v2p3_v8p3__5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -234,6 +241,7 @@ define void @v_shuffle_v2p3_v8p3__5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -246,6 +254,7 @@ define void @v_shuffle_v2p3_v8p3__5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -298,11 +307,12 @@ define void @v_shuffle_v2p3_v8p3__7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v8p3__7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -314,6 +324,7 @@ define void @v_shuffle_v2p3_v8p3__7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -326,6 +337,7 @@ define void @v_shuffle_v2p3_v8p3__7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -354,6 +366,7 @@ define void @v_shuffle_v2p3_v8p3__9_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -366,6 +379,7 @@ define void @v_shuffle_v2p3_v8p3__9_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -378,6 +392,7 @@ define void @v_shuffle_v2p3_v8p3__9_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -436,6 +451,7 @@ define void @v_shuffle_v2p3_v8p3__11_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -448,6 +464,7 @@ define void @v_shuffle_v2p3_v8p3__11_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -460,6 +477,7 @@ define void @v_shuffle_v2p3_v8p3__11_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -518,6 +536,7 @@ define void @v_shuffle_v2p3_v8p3__13_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -530,6 +549,7 @@ define void @v_shuffle_v2p3_v8p3__13_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -542,6 +562,7 @@ define void @v_shuffle_v2p3_v8p3__13_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -596,11 +617,12 @@ define void @v_shuffle_v2p3_v8p3__15_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v8p3__15_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -612,6 +634,7 @@ define void @v_shuffle_v2p3_v8p3__15_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -624,6 +647,7 @@ define void @v_shuffle_v2p3_v8p3__15_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -655,6 +679,7 @@ define void @v_shuffle_v2p3_v8p3__15_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -670,6 +695,7 @@ define void @v_shuffle_v2p3_v8p3__15_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -763,6 +789,7 @@ define void @v_shuffle_v2p3_v8p3__15_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -778,6 +805,7 @@ define void @v_shuffle_v2p3_v8p3__15_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -867,6 +895,7 @@ define void @v_shuffle_v2p3_v8p3__15_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -882,6 +911,7 @@ define void @v_shuffle_v2p3_v8p3__15_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -971,6 +1001,7 @@ define void @v_shuffle_v2p3_v8p3__15_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[14:15], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -986,6 +1017,7 @@ define void @v_shuffle_v2p3_v8p3__15_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[14:15], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -1419,8 +1451,9 @@ define void @v_shuffle_v2p3_v8p3__u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1431,8 +1464,9 @@ define void @v_shuffle_v2p3_v8p3__u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1802,8 +1836,9 @@ define void @v_shuffle_v2p3_v8p3__8_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v1, v0
-; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1814,8 +1849,9 @@ define void @v_shuffle_v2p3_v8p3__8_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, v0
-; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v0
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <8 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1846,6 +1882,7 @@ define void @v_shuffle_v2p3_v8p3__9_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -1861,6 +1898,7 @@ define void @v_shuffle_v2p3_v8p3__9_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -1952,6 +1990,7 @@ define void @v_shuffle_v2p3_v8p3__11_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -1967,6 +2006,7 @@ define void @v_shuffle_v2p3_v8p3__11_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -2058,6 +2098,7 @@ define void @v_shuffle_v2p3_v8p3__13_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
@@ -2073,6 +2114,7 @@ define void @v_shuffle_v2p3_v8p3__13_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
@@ -2891,6 +2933,7 @@ define void @v_shuffle_v2p3_v8p3__u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2903,6 +2946,7 @@ define void @v_shuffle_v2p3_v8p3__u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3273,6 +3317,7 @@ define void @v_shuffle_v2p3_v8p3__8_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3285,6 +3330,7 @@ define void @v_shuffle_v2p3_v8p3__8_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3320,6 +3366,7 @@ define void @v_shuffle_v2p3_v8p3__9_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3335,6 +3382,7 @@ define void @v_shuffle_v2p3_v8p3__9_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -3426,6 +3474,7 @@ define void @v_shuffle_v2p3_v8p3__11_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3441,6 +3490,7 @@ define void @v_shuffle_v2p3_v8p3__11_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -3532,6 +3582,7 @@ define void @v_shuffle_v2p3_v8p3__13_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -3547,6 +3598,7 @@ define void @v_shuffle_v2p3_v8p3__13_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[2:3] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -4361,6 +4413,7 @@ define void @v_shuffle_v2p3_v8p3__u_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4373,6 +4426,7 @@ define void @v_shuffle_v2p3_v8p3__u_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4743,6 +4797,7 @@ define void @v_shuffle_v2p3_v8p3__8_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4755,6 +4810,7 @@ define void @v_shuffle_v2p3_v8p3__8_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4790,6 +4846,7 @@ define void @v_shuffle_v2p3_v8p3__9_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -4805,6 +4862,7 @@ define void @v_shuffle_v2p3_v8p3__9_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -4896,6 +4954,7 @@ define void @v_shuffle_v2p3_v8p3__11_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -4911,6 +4970,7 @@ define void @v_shuffle_v2p3_v8p3__11_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -5002,6 +5062,7 @@ define void @v_shuffle_v2p3_v8p3__13_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -5017,6 +5078,7 @@ define void @v_shuffle_v2p3_v8p3__13_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -5831,6 +5893,7 @@ define void @v_shuffle_v2p3_v8p3__u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -5843,6 +5906,7 @@ define void @v_shuffle_v2p3_v8p3__u_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6213,6 +6277,7 @@ define void @v_shuffle_v2p3_v8p3__8_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6225,6 +6290,7 @@ define void @v_shuffle_v2p3_v8p3__8_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6260,6 +6326,7 @@ define void @v_shuffle_v2p3_v8p3__9_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6275,6 +6342,7 @@ define void @v_shuffle_v2p3_v8p3__9_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[8:9], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -6366,6 +6434,7 @@ define void @v_shuffle_v2p3_v8p3__11_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6381,6 +6450,7 @@ define void @v_shuffle_v2p3_v8p3__11_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[10:11], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -6472,6 +6542,7 @@ define void @v_shuffle_v2p3_v8p3__13_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -6487,6 +6558,7 @@ define void @v_shuffle_v2p3_v8p3__13_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[12:13], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
@@ -7339,6 +7411,7 @@ define void @v_shuffle_v2p3_v8p3__1_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
; GFX900-NEXT: global_store_dwordx2 v8, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7351,6 +7424,7 @@ define void @v_shuffle_v2p3_v8p3__1_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7363,6 +7437,7 @@ define void @v_shuffle_v2p3_v8p3__1_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7419,6 +7494,7 @@ define void @v_shuffle_v2p3_v8p3__3_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx2 v8, v[3:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7431,6 +7507,7 @@ define void @v_shuffle_v2p3_v8p3__3_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7443,6 +7520,7 @@ define void @v_shuffle_v2p3_v8p3__3_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7499,6 +7577,7 @@ define void @v_shuffle_v2p3_v8p3__5_8(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx2 v8, v[5:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7511,6 +7590,7 @@ define void @v_shuffle_v2p3_v8p3__5_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7523,6 +7603,7 @@ define void @v_shuffle_v2p3_v8p3__5_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7575,11 +7656,12 @@ define void @v_shuffle_v2p3_v8p3__7_8(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v2p3_v8p3__7_8:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[7:8], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: global_store_dwordx2 v9, v[7:8], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -7591,6 +7673,7 @@ define void @v_shuffle_v2p3_v8p3__7_8(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7603,6 +7686,7 @@ define void @v_shuffle_v2p3_v8p3__7_8(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -8667,6 +8751,7 @@ define void @v_shuffle_v2p3_v8p3__u_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -8679,6 +8764,7 @@ define void @v_shuffle_v2p3_v8p3__u_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -8764,10 +8850,11 @@ define void @v_shuffle_v2p3_v8p3__1_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8783,6 +8870,7 @@ define void @v_shuffle_v2p3_v8p3__1_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -8870,10 +8958,11 @@ define void @v_shuffle_v2p3_v8p3__3_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8889,6 +8978,7 @@ define void @v_shuffle_v2p3_v8p3__3_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -8976,10 +9066,11 @@ define void @v_shuffle_v2p3_v8p3__5_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -8995,6 +9086,7 @@ define void @v_shuffle_v2p3_v8p3__5_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -9082,10 +9174,11 @@ define void @v_shuffle_v2p3_v8p3__7_10(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -9097,11 +9190,11 @@ define void @v_shuffle_v2p3_v8p3__7_10(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -10199,6 +10292,7 @@ define void @v_shuffle_v2p3_v8p3__u_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -10211,6 +10305,7 @@ define void @v_shuffle_v2p3_v8p3__u_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v4
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -10296,10 +10391,11 @@ define void @v_shuffle_v2p3_v8p3__1_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10315,6 +10411,7 @@ define void @v_shuffle_v2p3_v8p3__1_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[6:7] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -10402,10 +10499,11 @@ define void @v_shuffle_v2p3_v8p3__3_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10421,6 +10519,7 @@ define void @v_shuffle_v2p3_v8p3__3_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -10508,10 +10607,11 @@ define void @v_shuffle_v2p3_v8p3__5_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10527,6 +10627,7 @@ define void @v_shuffle_v2p3_v8p3__5_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -10614,10 +10715,11 @@ define void @v_shuffle_v2p3_v8p3__7_12(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[12:13] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -10629,11 +10731,11 @@ define void @v_shuffle_v2p3_v8p3__7_12(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[12:13] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -11731,6 +11833,7 @@ define void @v_shuffle_v2p3_v8p3__u_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr0
; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -11743,6 +11846,7 @@ define void @v_shuffle_v2p3_v8p3__u_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v1, v6
+; GFX942-NEXT: ; implicit-def: $vgpr0
; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -11828,10 +11932,11 @@ define void @v_shuffle_v2p3_v8p3__1_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[8:9] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11847,6 +11952,7 @@ define void @v_shuffle_v2p3_v8p3__1_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[8:9] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -11934,10 +12040,11 @@ define void @v_shuffle_v2p3_v8p3__3_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[10:11] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v12, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -11953,6 +12060,7 @@ define void @v_shuffle_v2p3_v8p3__3_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[10:11] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v12, v[0:1], s[0:1]
@@ -12040,10 +12148,11 @@ define void @v_shuffle_v2p3_v8p3__5_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr13
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[12:13] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v14, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12059,6 +12168,7 @@ define void @v_shuffle_v2p3_v8p3__5_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[12:13] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v14, v[0:1], s[0:1]
@@ -12146,10 +12256,11 @@ define void @v_shuffle_v2p3_v8p3__7_14(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr15
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[14:15] op_sel:[1,0]
; GFX90A-NEXT: global_store_dwordx2 v16, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -12161,11 +12272,11 @@ define void @v_shuffle_v2p3_v8p3__7_14(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: ; implicit-def: $vgpr15
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[14:15] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx2 v16, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
@@ -13306,6 +13417,7 @@ define void @s_shuffle_v2p3_v8p3__1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13318,6 +13430,7 @@ define void @s_shuffle_v2p3_v8p3__1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13330,6 +13443,7 @@ define void @s_shuffle_v2p3_v8p3__1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13390,6 +13504,7 @@ define void @s_shuffle_v2p3_v8p3__3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13402,6 +13517,7 @@ define void @s_shuffle_v2p3_v8p3__3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13414,6 +13530,7 @@ define void @s_shuffle_v2p3_v8p3__3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13470,9 +13587,10 @@ define void @s_shuffle_v2p3_v8p3__5_u() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -13482,9 +13600,10 @@ define void @s_shuffle_v2p3_v8p3__5_u() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -13496,6 +13615,7 @@ define void @s_shuffle_v2p3_v8p3__5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13556,6 +13676,7 @@ define void @s_shuffle_v2p3_v8p3__7_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13568,6 +13689,7 @@ define void @s_shuffle_v2p3_v8p3__7_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13580,6 +13702,7 @@ define void @s_shuffle_v2p3_v8p3__7_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13612,6 +13735,7 @@ define void @s_shuffle_v2p3_v8p3__9_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13624,6 +13748,7 @@ define void @s_shuffle_v2p3_v8p3__9_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13636,6 +13761,7 @@ define void @s_shuffle_v2p3_v8p3__9_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13698,6 +13824,7 @@ define void @s_shuffle_v2p3_v8p3__11_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13710,6 +13837,7 @@ define void @s_shuffle_v2p3_v8p3__11_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13722,6 +13850,7 @@ define void @s_shuffle_v2p3_v8p3__11_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13780,9 +13909,10 @@ define void @s_shuffle_v2p3_v8p3__13_u() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -13792,9 +13922,10 @@ define void @s_shuffle_v2p3_v8p3__13_u() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -13806,6 +13937,7 @@ define void @s_shuffle_v2p3_v8p3__13_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -13868,6 +14000,7 @@ define void @s_shuffle_v2p3_v8p3__15_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -13880,6 +14013,7 @@ define void @s_shuffle_v2p3_v8p3__15_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -13892,6 +14026,7 @@ define void @s_shuffle_v2p3_v8p3__15_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -14663,6 +14798,7 @@ define void @s_shuffle_v2p3_v8p3__u_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -14675,6 +14811,7 @@ define void @s_shuffle_v2p3_v8p3__u_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -14687,6 +14824,7 @@ define void @s_shuffle_v2p3_v8p3__u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -15011,6 +15149,7 @@ define void @s_shuffle_v2p3_v8p3__8_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -15023,6 +15162,7 @@ define void @s_shuffle_v2p3_v8p3__8_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -15035,6 +15175,7 @@ define void @s_shuffle_v2p3_v8p3__8_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -16007,6 +16148,7 @@ define void @s_shuffle_v2p3_v8p3__u_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -16019,6 +16161,7 @@ define void @s_shuffle_v2p3_v8p3__u_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -16031,6 +16174,7 @@ define void @s_shuffle_v2p3_v8p3__u_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -16355,6 +16499,7 @@ define void @s_shuffle_v2p3_v8p3__8_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -16367,6 +16512,7 @@ define void @s_shuffle_v2p3_v8p3__8_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -16379,6 +16525,7 @@ define void @s_shuffle_v2p3_v8p3__8_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -17448,9 +17595,10 @@ define void @s_shuffle_v2p3_v8p3__u_4() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -17460,9 +17608,10 @@ define void @s_shuffle_v2p3_v8p3__u_4() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -17474,6 +17623,7 @@ define void @s_shuffle_v2p3_v8p3__u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -17796,9 +17946,10 @@ define void @s_shuffle_v2p3_v8p3__8_4() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -17808,9 +17959,10 @@ define void @s_shuffle_v2p3_v8p3__8_4() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -17822,6 +17974,7 @@ define void @s_shuffle_v2p3_v8p3__8_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -18790,6 +18943,7 @@ define void @s_shuffle_v2p3_v8p3__u_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -18802,6 +18956,7 @@ define void @s_shuffle_v2p3_v8p3__u_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -18814,6 +18969,7 @@ define void @s_shuffle_v2p3_v8p3__u_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19138,6 +19294,7 @@ define void @s_shuffle_v2p3_v8p3__8_6() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19150,6 +19307,7 @@ define void @s_shuffle_v2p3_v8p3__8_6() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19162,6 +19320,7 @@ define void @s_shuffle_v2p3_v8p3__8_6() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20277,6 +20436,7 @@ define void @s_shuffle_v2p3_v8p3__1_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20289,6 +20449,7 @@ define void @s_shuffle_v2p3_v8p3__1_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20301,6 +20462,7 @@ define void @s_shuffle_v2p3_v8p3__1_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20361,6 +20523,7 @@ define void @s_shuffle_v2p3_v8p3__3_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20373,6 +20536,7 @@ define void @s_shuffle_v2p3_v8p3__3_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20385,6 +20549,7 @@ define void @s_shuffle_v2p3_v8p3__3_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20441,9 +20606,10 @@ define void @s_shuffle_v2p3_v8p3__5_8() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: s_mov_b32 s8, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -20453,9 +20619,10 @@ define void @s_shuffle_v2p3_v8p3__5_8() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: s_mov_b32 s8, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -20467,6 +20634,7 @@ define void @s_shuffle_v2p3_v8p3__5_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -20527,6 +20695,7 @@ define void @s_shuffle_v2p3_v8p3__7_8() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -20539,6 +20708,7 @@ define void @s_shuffle_v2p3_v8p3__7_8() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -20551,6 +20721,7 @@ define void @s_shuffle_v2p3_v8p3__7_8() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -21506,6 +21677,7 @@ define void @s_shuffle_v2p3_v8p3__u_10() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -21518,6 +21690,7 @@ define void @s_shuffle_v2p3_v8p3__u_10() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -21530,6 +21703,7 @@ define void @s_shuffle_v2p3_v8p3__u_10() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -22999,9 +23173,10 @@ define void @s_shuffle_v2p3_v8p3__u_12() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s9, s8
+; GFX900-NEXT: ; implicit-def: $sgpr8
+; GFX900-NEXT: s_mov_b32 s9, s12
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -23011,9 +23186,10 @@ define void @s_shuffle_v2p3_v8p3__u_12() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s9, s8
+; GFX90A-NEXT: ; implicit-def: $sgpr8
+; GFX90A-NEXT: s_mov_b32 s9, s12
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -23025,6 +23201,7 @@ define void @s_shuffle_v2p3_v8p3__u_12() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -24426,6 +24603,7 @@ define void @s_shuffle_v2p3_v8p3__u_14() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -24438,6 +24616,7 @@ define void @s_shuffle_v2p3_v8p3__u_14() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -24450,6 +24629,7 @@ define void @s_shuffle_v2p3_v8p3__u_14() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
index 5914253b5f58e..9a22abf85e53a 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
@@ -2160,6 +2160,7 @@ define void @s_shuffle_v3bf16_v2bf16__0_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2171,6 +2172,7 @@ define void @s_shuffle_v3bf16_v2bf16__0_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2182,6 +2184,7 @@ define void @s_shuffle_v3bf16_v2bf16__0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2201,6 +2204,7 @@ define void @s_shuffle_v3bf16_v2bf16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2213,6 +2217,7 @@ define void @s_shuffle_v3bf16_v2bf16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2225,6 +2230,7 @@ define void @s_shuffle_v3bf16_v2bf16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2259,6 +2265,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2271,6 +2278,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2283,6 +2291,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2308,6 +2317,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_0_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2324,6 +2334,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_0_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2340,6 +2351,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_0_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -2365,6 +2377,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_1_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2382,6 +2395,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_1_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2399,6 +2413,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_1_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -2419,6 +2434,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_2_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2432,6 +2448,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_2_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2445,6 +2462,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_2_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2466,6 +2484,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_3_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2479,6 +2498,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_3_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2492,6 +2512,7 @@ define void @s_shuffle_v3bf16_v2bf16__3_3_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3399,6 +3420,7 @@ define void @s_shuffle_v3bf16_v2bf16__0_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3410,6 +3432,7 @@ define void @s_shuffle_v3bf16_v2bf16__0_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3421,6 +3444,7 @@ define void @s_shuffle_v3bf16_v2bf16__0_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3440,6 +3464,7 @@ define void @s_shuffle_v3bf16_v2bf16__1_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3452,6 +3477,7 @@ define void @s_shuffle_v3bf16_v2bf16__1_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3464,6 +3490,7 @@ define void @s_shuffle_v3bf16_v2bf16__1_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
index cd4dbe93e8a11..d7219a296bf90 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
@@ -4817,6 +4817,7 @@ define void @s_shuffle_v3bf16_v3bf16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4829,6 +4830,7 @@ define void @s_shuffle_v3bf16_v3bf16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4841,6 +4843,7 @@ define void @s_shuffle_v3bf16_v3bf16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4861,6 +4864,7 @@ define void @s_shuffle_v3bf16_v3bf16__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4873,6 +4877,7 @@ define void @s_shuffle_v3bf16_v3bf16__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4885,6 +4890,7 @@ define void @s_shuffle_v3bf16_v3bf16__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4921,6 +4927,7 @@ define void @s_shuffle_v3bf16_v3bf16__4_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4933,6 +4940,7 @@ define void @s_shuffle_v3bf16_v3bf16__4_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4945,6 +4953,7 @@ define void @s_shuffle_v3bf16_v3bf16__4_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4967,6 +4976,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4979,6 +4989,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4991,6 +5002,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5017,6 +5029,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_0_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5032,6 +5045,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_0_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5047,6 +5061,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_0_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5073,6 +5088,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_1_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5089,6 +5105,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_1_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5105,6 +5122,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_1_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5130,6 +5148,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_2_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5145,6 +5164,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_2_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5160,6 +5180,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_2_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5181,6 +5202,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5193,6 +5215,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5205,6 +5228,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5228,6 +5252,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_4_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5241,6 +5266,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_4_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5254,6 +5280,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_4_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5276,6 +5303,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5288,6 +5316,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5300,6 +5329,7 @@ define void @s_shuffle_v3bf16_v3bf16__5_5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7411,6 +7441,7 @@ define void @s_shuffle_v3bf16_v3bf16__1_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7423,6 +7454,7 @@ define void @s_shuffle_v3bf16_v3bf16__1_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7435,6 +7467,7 @@ define void @s_shuffle_v3bf16_v3bf16__1_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7455,6 +7488,7 @@ define void @s_shuffle_v3bf16_v3bf16__2_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7467,6 +7501,7 @@ define void @s_shuffle_v3bf16_v3bf16__2_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7479,6 +7514,7 @@ define void @s_shuffle_v3bf16_v3bf16__2_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
index 311ca98227da3..cb2805f1d77cd 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
@@ -7960,6 +7960,7 @@ define void @s_shuffle_v3bf16_v4bf16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7972,6 +7973,7 @@ define void @s_shuffle_v3bf16_v4bf16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7984,6 +7986,7 @@ define void @s_shuffle_v3bf16_v4bf16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8003,6 +8006,7 @@ define void @s_shuffle_v3bf16_v4bf16__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8015,6 +8019,7 @@ define void @s_shuffle_v3bf16_v4bf16__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8027,6 +8032,7 @@ define void @s_shuffle_v3bf16_v4bf16__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8046,6 +8052,7 @@ define void @s_shuffle_v3bf16_v4bf16__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8058,6 +8065,7 @@ define void @s_shuffle_v3bf16_v4bf16__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8070,6 +8078,7 @@ define void @s_shuffle_v3bf16_v4bf16__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8104,6 +8113,7 @@ define void @s_shuffle_v3bf16_v4bf16__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8116,6 +8126,7 @@ define void @s_shuffle_v3bf16_v4bf16__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8128,6 +8139,7 @@ define void @s_shuffle_v3bf16_v4bf16__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8148,6 +8160,7 @@ define void @s_shuffle_v3bf16_v4bf16__6_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8160,6 +8173,7 @@ define void @s_shuffle_v3bf16_v4bf16__6_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8172,6 +8186,7 @@ define void @s_shuffle_v3bf16_v4bf16__6_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8192,6 +8207,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8204,6 +8220,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8216,6 +8233,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8241,6 +8259,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8257,6 +8276,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8273,6 +8293,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8298,6 +8319,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_1_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8315,6 +8337,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_1_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8332,6 +8355,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_1_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8356,6 +8380,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8372,6 +8397,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8388,6 +8414,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8413,6 +8440,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_3_u() {
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8430,6 +8458,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_3_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8447,6 +8476,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_3_u() {
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8467,6 +8497,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_4_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8480,6 +8511,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_4_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8493,6 +8525,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_4_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8516,6 +8549,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_5_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8530,6 +8564,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_5_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8544,6 +8579,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_5_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8564,6 +8600,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_6_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8577,6 +8614,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_6_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8590,6 +8628,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_6_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8611,6 +8650,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_7_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8624,6 +8664,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_7_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8637,6 +8678,7 @@ define void @s_shuffle_v3bf16_v4bf16__7_7_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12403,6 +12445,7 @@ define void @s_shuffle_v3bf16_v4bf16__1_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12415,6 +12458,7 @@ define void @s_shuffle_v3bf16_v4bf16__1_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12427,6 +12471,7 @@ define void @s_shuffle_v3bf16_v4bf16__1_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12446,6 +12491,7 @@ define void @s_shuffle_v3bf16_v4bf16__2_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12458,6 +12504,7 @@ define void @s_shuffle_v3bf16_v4bf16__2_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12470,6 +12517,7 @@ define void @s_shuffle_v3bf16_v4bf16__2_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12489,6 +12537,7 @@ define void @s_shuffle_v3bf16_v4bf16__3_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12501,6 +12550,7 @@ define void @s_shuffle_v3bf16_v4bf16__3_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12513,6 +12563,7 @@ define void @s_shuffle_v3bf16_v4bf16__3_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
index 99cb8a38f57c3..ce10db665bbd2 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
@@ -2160,6 +2160,7 @@ define void @s_shuffle_v3f16_v2f16__0_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2171,6 +2172,7 @@ define void @s_shuffle_v3f16_v2f16__0_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2182,6 +2184,7 @@ define void @s_shuffle_v3f16_v2f16__0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2201,6 +2204,7 @@ define void @s_shuffle_v3f16_v2f16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2213,6 +2217,7 @@ define void @s_shuffle_v3f16_v2f16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2225,6 +2230,7 @@ define void @s_shuffle_v3f16_v2f16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2259,6 +2265,7 @@ define void @s_shuffle_v3f16_v2f16__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2271,6 +2278,7 @@ define void @s_shuffle_v3f16_v2f16__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2283,6 +2291,7 @@ define void @s_shuffle_v3f16_v2f16__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2308,6 +2317,7 @@ define void @s_shuffle_v3f16_v2f16__3_0_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2324,6 +2334,7 @@ define void @s_shuffle_v3f16_v2f16__3_0_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2340,6 +2351,7 @@ define void @s_shuffle_v3f16_v2f16__3_0_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -2365,6 +2377,7 @@ define void @s_shuffle_v3f16_v2f16__3_1_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2382,6 +2395,7 @@ define void @s_shuffle_v3f16_v2f16__3_1_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2399,6 +2413,7 @@ define void @s_shuffle_v3f16_v2f16__3_1_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -2419,6 +2434,7 @@ define void @s_shuffle_v3f16_v2f16__3_2_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2432,6 +2448,7 @@ define void @s_shuffle_v3f16_v2f16__3_2_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2445,6 +2462,7 @@ define void @s_shuffle_v3f16_v2f16__3_2_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2466,6 +2484,7 @@ define void @s_shuffle_v3f16_v2f16__3_3_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2479,6 +2498,7 @@ define void @s_shuffle_v3f16_v2f16__3_3_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2492,6 +2512,7 @@ define void @s_shuffle_v3f16_v2f16__3_3_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3399,6 +3420,7 @@ define void @s_shuffle_v3f16_v2f16__0_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3410,6 +3432,7 @@ define void @s_shuffle_v3f16_v2f16__0_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3421,6 +3444,7 @@ define void @s_shuffle_v3f16_v2f16__0_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3440,6 +3464,7 @@ define void @s_shuffle_v3f16_v2f16__1_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3452,6 +3477,7 @@ define void @s_shuffle_v3f16_v2f16__1_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3464,6 +3490,7 @@ define void @s_shuffle_v3f16_v2f16__1_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
index 0854ff2ebfc5d..e75af5c94d4ba 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
@@ -4817,6 +4817,7 @@ define void @s_shuffle_v3f16_v3f16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4829,6 +4830,7 @@ define void @s_shuffle_v3f16_v3f16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4841,6 +4843,7 @@ define void @s_shuffle_v3f16_v3f16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4861,6 +4864,7 @@ define void @s_shuffle_v3f16_v3f16__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4873,6 +4877,7 @@ define void @s_shuffle_v3f16_v3f16__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4885,6 +4890,7 @@ define void @s_shuffle_v3f16_v3f16__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4921,6 +4927,7 @@ define void @s_shuffle_v3f16_v3f16__4_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4933,6 +4940,7 @@ define void @s_shuffle_v3f16_v3f16__4_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4945,6 +4953,7 @@ define void @s_shuffle_v3f16_v3f16__4_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4967,6 +4976,7 @@ define void @s_shuffle_v3f16_v3f16__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4979,6 +4989,7 @@ define void @s_shuffle_v3f16_v3f16__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4991,6 +5002,7 @@ define void @s_shuffle_v3f16_v3f16__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5017,6 +5029,7 @@ define void @s_shuffle_v3f16_v3f16__5_0_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5032,6 +5045,7 @@ define void @s_shuffle_v3f16_v3f16__5_0_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5047,6 +5061,7 @@ define void @s_shuffle_v3f16_v3f16__5_0_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5073,6 +5088,7 @@ define void @s_shuffle_v3f16_v3f16__5_1_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5089,6 +5105,7 @@ define void @s_shuffle_v3f16_v3f16__5_1_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5105,6 +5122,7 @@ define void @s_shuffle_v3f16_v3f16__5_1_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5130,6 +5148,7 @@ define void @s_shuffle_v3f16_v3f16__5_2_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5145,6 +5164,7 @@ define void @s_shuffle_v3f16_v3f16__5_2_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5160,6 +5180,7 @@ define void @s_shuffle_v3f16_v3f16__5_2_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5181,6 +5202,7 @@ define void @s_shuffle_v3f16_v3f16__5_3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5193,6 +5215,7 @@ define void @s_shuffle_v3f16_v3f16__5_3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5205,6 +5228,7 @@ define void @s_shuffle_v3f16_v3f16__5_3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5228,6 +5252,7 @@ define void @s_shuffle_v3f16_v3f16__5_4_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5241,6 +5266,7 @@ define void @s_shuffle_v3f16_v3f16__5_4_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5254,6 +5280,7 @@ define void @s_shuffle_v3f16_v3f16__5_4_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5276,6 +5303,7 @@ define void @s_shuffle_v3f16_v3f16__5_5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5288,6 +5316,7 @@ define void @s_shuffle_v3f16_v3f16__5_5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5300,6 +5329,7 @@ define void @s_shuffle_v3f16_v3f16__5_5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7411,6 +7441,7 @@ define void @s_shuffle_v3f16_v3f16__1_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7423,6 +7454,7 @@ define void @s_shuffle_v3f16_v3f16__1_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7435,6 +7467,7 @@ define void @s_shuffle_v3f16_v3f16__1_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7455,6 +7488,7 @@ define void @s_shuffle_v3f16_v3f16__2_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7467,6 +7501,7 @@ define void @s_shuffle_v3f16_v3f16__2_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7479,6 +7514,7 @@ define void @s_shuffle_v3f16_v3f16__2_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
index ecc7ff618932b..0d3bd7ad0f816 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
@@ -7960,6 +7960,7 @@ define void @s_shuffle_v3f16_v4f16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7972,6 +7973,7 @@ define void @s_shuffle_v3f16_v4f16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7984,6 +7986,7 @@ define void @s_shuffle_v3f16_v4f16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8003,6 +8006,7 @@ define void @s_shuffle_v3f16_v4f16__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8015,6 +8019,7 @@ define void @s_shuffle_v3f16_v4f16__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8027,6 +8032,7 @@ define void @s_shuffle_v3f16_v4f16__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8046,6 +8052,7 @@ define void @s_shuffle_v3f16_v4f16__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8058,6 +8065,7 @@ define void @s_shuffle_v3f16_v4f16__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8070,6 +8078,7 @@ define void @s_shuffle_v3f16_v4f16__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8104,6 +8113,7 @@ define void @s_shuffle_v3f16_v4f16__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8116,6 +8126,7 @@ define void @s_shuffle_v3f16_v4f16__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8128,6 +8139,7 @@ define void @s_shuffle_v3f16_v4f16__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8148,6 +8160,7 @@ define void @s_shuffle_v3f16_v4f16__6_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8160,6 +8173,7 @@ define void @s_shuffle_v3f16_v4f16__6_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8172,6 +8186,7 @@ define void @s_shuffle_v3f16_v4f16__6_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8192,6 +8207,7 @@ define void @s_shuffle_v3f16_v4f16__7_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8204,6 +8220,7 @@ define void @s_shuffle_v3f16_v4f16__7_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8216,6 +8233,7 @@ define void @s_shuffle_v3f16_v4f16__7_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8241,6 +8259,7 @@ define void @s_shuffle_v3f16_v4f16__7_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8257,6 +8276,7 @@ define void @s_shuffle_v3f16_v4f16__7_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8273,6 +8293,7 @@ define void @s_shuffle_v3f16_v4f16__7_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8298,6 +8319,7 @@ define void @s_shuffle_v3f16_v4f16__7_1_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8315,6 +8337,7 @@ define void @s_shuffle_v3f16_v4f16__7_1_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8332,6 +8355,7 @@ define void @s_shuffle_v3f16_v4f16__7_1_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8356,6 +8380,7 @@ define void @s_shuffle_v3f16_v4f16__7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8372,6 +8397,7 @@ define void @s_shuffle_v3f16_v4f16__7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8388,6 +8414,7 @@ define void @s_shuffle_v3f16_v4f16__7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8413,6 +8440,7 @@ define void @s_shuffle_v3f16_v4f16__7_3_u() {
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8430,6 +8458,7 @@ define void @s_shuffle_v3f16_v4f16__7_3_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8447,6 +8476,7 @@ define void @s_shuffle_v3f16_v4f16__7_3_u() {
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8467,6 +8497,7 @@ define void @s_shuffle_v3f16_v4f16__7_4_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8480,6 +8511,7 @@ define void @s_shuffle_v3f16_v4f16__7_4_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8493,6 +8525,7 @@ define void @s_shuffle_v3f16_v4f16__7_4_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8516,6 +8549,7 @@ define void @s_shuffle_v3f16_v4f16__7_5_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8530,6 +8564,7 @@ define void @s_shuffle_v3f16_v4f16__7_5_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8544,6 +8579,7 @@ define void @s_shuffle_v3f16_v4f16__7_5_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8564,6 +8600,7 @@ define void @s_shuffle_v3f16_v4f16__7_6_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8577,6 +8614,7 @@ define void @s_shuffle_v3f16_v4f16__7_6_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8590,6 +8628,7 @@ define void @s_shuffle_v3f16_v4f16__7_6_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8611,6 +8650,7 @@ define void @s_shuffle_v3f16_v4f16__7_7_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8624,6 +8664,7 @@ define void @s_shuffle_v3f16_v4f16__7_7_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8637,6 +8678,7 @@ define void @s_shuffle_v3f16_v4f16__7_7_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12403,6 +12445,7 @@ define void @s_shuffle_v3f16_v4f16__1_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12415,6 +12458,7 @@ define void @s_shuffle_v3f16_v4f16__1_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12427,6 +12471,7 @@ define void @s_shuffle_v3f16_v4f16__1_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12446,6 +12491,7 @@ define void @s_shuffle_v3f16_v4f16__2_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12458,6 +12504,7 @@ define void @s_shuffle_v3f16_v4f16__2_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12470,6 +12517,7 @@ define void @s_shuffle_v3f16_v4f16__2_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12489,6 +12537,7 @@ define void @s_shuffle_v3f16_v4f16__3_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12501,6 +12550,7 @@ define void @s_shuffle_v3f16_v4f16__3_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12513,6 +12563,7 @@ define void @s_shuffle_v3f16_v4f16__3_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
index d38b17c04947b..b3ff7e7389cc2 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v2f32.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v3f32_v2f32__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v2f32__0_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v2f32__0_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v2f32__0_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -58,35 +61,42 @@ define void @v_shuffle_v3f32_v2f32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v2f32__1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v2f32__1_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v2f32__1_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -110,35 +120,42 @@ define void @v_shuffle_v3f32_v2f32__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v2f32__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v2f32__3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v2f32__3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -159,6 +176,7 @@ define void @v_shuffle_v3f32_v2f32__3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -166,32 +184,35 @@ define void @v_shuffle_v3f32_v2f32__3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3f32_v2f32__3_0_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
-; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ;;#ASMSTART
+; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v2f32__3_0_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:3]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def v[2:3]
+; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v0
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -205,14 +226,15 @@ define void @v_shuffle_v3f32_v2f32__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v2f32__3_1_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -227,6 +249,7 @@ define void @v_shuffle_v3f32_v2f32__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -241,6 +264,7 @@ define void @v_shuffle_v3f32_v2f32__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
@@ -257,12 +281,13 @@ define void @v_shuffle_v3f32_v2f32__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v2f32__3_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v0
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -275,6 +300,7 @@ define void @v_shuffle_v3f32_v2f32__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -286,6 +312,7 @@ define void @v_shuffle_v3f32_v2f32__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v0
@@ -303,12 +330,13 @@ define void @v_shuffle_v3f32_v2f32__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v2f32__3_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -318,9 +346,10 @@ define void @v_shuffle_v3f32_v2f32__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -330,9 +359,10 @@ define void @v_shuffle_v3f32_v2f32__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -1178,32 +1208,35 @@ define void @v_shuffle_v3f32_v2f32__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3f32_v2f32__3_u_1:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v8, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v2f32__3_u_1:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v8, v1
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -1341,33 +1374,36 @@ define void @v_shuffle_v3f32_v2f32__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v2f32__0_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v2f32__0_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v2f32__0_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -1380,35 +1416,42 @@ define void @v_shuffle_v3f32_v2f32__1_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v2f32__1_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v2f32__1_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v2f32__1_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -1845,6 +1888,7 @@ define void @v_shuffle_v3f32_v2f32__3_u_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v6, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1856,6 +1900,7 @@ define void @v_shuffle_v3f32_v2f32__3_u_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v6, v1
@@ -2050,6 +2095,7 @@ define void @s_shuffle_v3f32_v2f32__0_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2061,6 +2107,7 @@ define void @s_shuffle_v3f32_v2f32__0_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2072,6 +2119,7 @@ define void @s_shuffle_v3f32_v2f32__0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2090,6 +2138,8 @@ define void @s_shuffle_v3f32_v2f32__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2102,6 +2152,8 @@ define void @s_shuffle_v3f32_v2f32__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2114,6 +2166,8 @@ define void @s_shuffle_v3f32_v2f32__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2146,6 +2200,8 @@ define void @s_shuffle_v3f32_v2f32__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2158,6 +2214,8 @@ define void @s_shuffle_v3f32_v2f32__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2170,6 +2228,8 @@ define void @s_shuffle_v3f32_v2f32__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2194,6 +2254,7 @@ define void @s_shuffle_v3f32_v2f32__3_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2210,6 +2271,7 @@ define void @s_shuffle_v3f32_v2f32__3_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2226,6 +2288,7 @@ define void @s_shuffle_v3f32_v2f32__3_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2248,6 +2311,7 @@ define void @s_shuffle_v3f32_v2f32__3_1_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2263,6 +2327,7 @@ define void @s_shuffle_v3f32_v2f32__3_1_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2278,6 +2343,7 @@ define void @s_shuffle_v3f32_v2f32__3_1_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2298,6 +2364,7 @@ define void @s_shuffle_v3f32_v2f32__3_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2311,6 +2378,7 @@ define void @s_shuffle_v3f32_v2f32__3_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2324,6 +2392,7 @@ define void @s_shuffle_v3f32_v2f32__3_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2342,6 +2411,7 @@ define void @s_shuffle_v3f32_v2f32__3_3_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
@@ -2901,6 +2971,7 @@ define void @s_shuffle_v3f32_v2f32__3_u_1() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2917,6 +2988,7 @@ define void @s_shuffle_v3f32_v2f32__3_u_1() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2933,6 +3005,7 @@ define void @s_shuffle_v3f32_v2f32__3_u_1() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3082,6 +3155,7 @@ define void @s_shuffle_v3f32_v2f32__0_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -3093,6 +3167,7 @@ define void @s_shuffle_v3f32_v2f32__0_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -3104,6 +3179,7 @@ define void @s_shuffle_v3f32_v2f32__0_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3122,6 +3198,8 @@ define void @s_shuffle_v3f32_v2f32__1_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -3134,6 +3212,8 @@ define void @s_shuffle_v3f32_v2f32__1_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -3146,6 +3226,8 @@ define void @s_shuffle_v3f32_v2f32__1_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3442,6 +3524,7 @@ define void @s_shuffle_v3f32_v2f32__3_u_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -3455,6 +3538,7 @@ define void @s_shuffle_v3f32_v2f32__3_u_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -3468,6 +3552,7 @@ define void @s_shuffle_v3f32_v2f32__3_u_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
index 4032d31cbb041..64495b0269bcb 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v3f32.ll
@@ -58,11 +58,13 @@ define void @v_shuffle_v3f32_v3f32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +76,8 @@ define void @v_shuffle_v3f32_v3f32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +90,8 @@ define void @v_shuffle_v3f32_v3f32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +105,39 @@ define void @v_shuffle_v3f32_v3f32__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v3f32__2_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v3f32__2_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -149,11 +161,13 @@ define void @v_shuffle_v3f32_v3f32__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -165,6 +179,8 @@ define void @v_shuffle_v3f32_v3f32__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -177,6 +193,8 @@ define void @v_shuffle_v3f32_v3f32__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -191,33 +209,39 @@ define void @v_shuffle_v3f32_v3f32__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v3f32__5_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v3f32__5_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -238,6 +262,7 @@ define void @v_shuffle_v3f32_v3f32__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -253,6 +278,7 @@ define void @v_shuffle_v3f32_v3f32__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v7, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -269,6 +295,7 @@ define void @v_shuffle_v3f32_v3f32__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx3 v7, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -290,6 +317,7 @@ define void @v_shuffle_v3f32_v3f32__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -304,6 +332,7 @@ define void @v_shuffle_v3f32_v3f32__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -315,6 +344,7 @@ define void @v_shuffle_v3f32_v3f32__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -333,14 +363,15 @@ define void @v_shuffle_v3f32_v3f32__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__5_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -355,6 +386,7 @@ define void @v_shuffle_v3f32_v3f32__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -370,6 +402,7 @@ define void @v_shuffle_v3f32_v3f32__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -384,37 +417,40 @@ define void @v_shuffle_v3f32_v3f32__5_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__5_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v3f32__5_3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v3f32__5_3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -428,37 +464,40 @@ define void @v_shuffle_v3f32_v3f32__5_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__5_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v3f32__5_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v3f32__5_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -472,37 +511,40 @@ define void @v_shuffle_v3f32_v3f32__5_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__5_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v3f32__5_5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v3f32__5_5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -1747,14 +1789,15 @@ define void @v_shuffle_v3f32_v3f32__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:4]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
-; GFX90A-NEXT: v_mov_b32_e32 v4, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, v5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx3 v7, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1762,14 +1805,15 @@ define void @v_shuffle_v3f32_v3f32__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:4]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
-; GFX942-NEXT: v_mov_b32_e32 v4, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx3 v7, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -2630,11 +2674,13 @@ define void @v_shuffle_v3f32_v3f32__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__1_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2646,6 +2692,8 @@ define void @v_shuffle_v3f32_v3f32__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2658,6 +2706,8 @@ define void @v_shuffle_v3f32_v3f32__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2671,33 +2721,39 @@ define void @v_shuffle_v3f32_v3f32__2_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v3f32__2_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v3f32__2_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v3f32__2_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -4316,6 +4372,8 @@ define void @s_shuffle_v3f32_v3f32__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4328,6 +4386,8 @@ define void @s_shuffle_v3f32_v3f32__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4340,6 +4400,8 @@ define void @s_shuffle_v3f32_v3f32__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4358,6 +4420,8 @@ define void @s_shuffle_v3f32_v3f32__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4370,6 +4434,8 @@ define void @s_shuffle_v3f32_v3f32__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4382,6 +4448,8 @@ define void @s_shuffle_v3f32_v3f32__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4414,6 +4482,8 @@ define void @s_shuffle_v3f32_v3f32__4_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4426,6 +4496,8 @@ define void @s_shuffle_v3f32_v3f32__4_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4438,6 +4510,8 @@ define void @s_shuffle_v3f32_v3f32__4_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4457,6 +4531,8 @@ define void @s_shuffle_v3f32_v3f32__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4469,6 +4545,8 @@ define void @s_shuffle_v3f32_v3f32__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4481,6 +4559,8 @@ define void @s_shuffle_v3f32_v3f32__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4505,6 +4585,7 @@ define void @s_shuffle_v3f32_v3f32__5_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4521,6 +4602,7 @@ define void @s_shuffle_v3f32_v3f32__5_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4537,6 +4619,7 @@ define void @s_shuffle_v3f32_v3f32__5_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4559,6 +4642,7 @@ define void @s_shuffle_v3f32_v3f32__5_1_u() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4574,6 +4658,7 @@ define void @s_shuffle_v3f32_v3f32__5_1_u() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4589,6 +4674,7 @@ define void @s_shuffle_v3f32_v3f32__5_1_u() {
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4612,6 +4698,7 @@ define void @s_shuffle_v3f32_v3f32__5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4628,6 +4715,7 @@ define void @s_shuffle_v3f32_v3f32__5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4644,6 +4732,7 @@ define void @s_shuffle_v3f32_v3f32__5_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4664,6 +4753,7 @@ define void @s_shuffle_v3f32_v3f32__5_3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4677,6 +4767,7 @@ define void @s_shuffle_v3f32_v3f32__5_3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4690,6 +4781,7 @@ define void @s_shuffle_v3f32_v3f32__5_3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4709,6 +4801,7 @@ define void @s_shuffle_v3f32_v3f32__5_4_u() {
; GFX9-NEXT: ; def s[8:10]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
; GFX9-NEXT: ;;#ASMEND
@@ -4729,6 +4822,7 @@ define void @s_shuffle_v3f32_v3f32__5_5_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4742,6 +4836,7 @@ define void @s_shuffle_v3f32_v3f32__5_5_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4755,6 +4850,7 @@ define void @s_shuffle_v3f32_v3f32__5_5_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -5062,6 +5158,7 @@ define void @s_shuffle_v3f32_v3f32__u_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -5075,6 +5172,7 @@ define void @s_shuffle_v3f32_v3f32__u_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -5088,6 +5186,7 @@ define void @s_shuffle_v3f32_v3f32__u_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -5222,6 +5321,7 @@ define void @s_shuffle_v3f32_v3f32__3_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -5235,6 +5335,7 @@ define void @s_shuffle_v3f32_v3f32__3_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -5248,6 +5349,7 @@ define void @s_shuffle_v3f32_v3f32__3_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -5387,6 +5489,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_0() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -5403,6 +5506,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_0() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -5419,6 +5523,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_0() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -5873,6 +5978,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_1() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -5889,6 +5995,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_1() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -5905,6 +6012,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_1() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6681,6 +6789,8 @@ define void @s_shuffle_v3f32_v3f32__1_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -6693,6 +6803,8 @@ define void @s_shuffle_v3f32_v3f32__1_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -6705,6 +6817,8 @@ define void @s_shuffle_v3f32_v3f32__1_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6723,6 +6837,8 @@ define void @s_shuffle_v3f32_v3f32__2_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -6735,6 +6851,8 @@ define void @s_shuffle_v3f32_v3f32__2_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -6747,6 +6865,8 @@ define void @s_shuffle_v3f32_v3f32__2_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6877,6 +6997,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -6890,6 +7011,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -6903,6 +7025,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -7386,6 +7509,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -7399,6 +7523,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -7412,6 +7537,7 @@ define void @s_shuffle_v3f32_v3f32__5_u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
index 2e4131d378906..2540ca3d66b8f 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f32.v4f32.ll
@@ -62,6 +62,8 @@ define void @v_shuffle_v3f32_v4f32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +76,8 @@ define void @v_shuffle_v3f32_v4f32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +90,8 @@ define void @v_shuffle_v3f32_v4f32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +105,39 @@ define void @v_shuffle_v3f32_v4f32__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v4f32__2_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v4f32__2_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -138,11 +150,13 @@ define void @v_shuffle_v3f32_v4f32__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +168,8 @@ define void @v_shuffle_v3f32_v4f32__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +182,8 @@ define void @v_shuffle_v3f32_v4f32__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -194,6 +212,8 @@ define void @v_shuffle_v3f32_v4f32__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -206,6 +226,8 @@ define void @v_shuffle_v3f32_v4f32__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +240,8 @@ define void @v_shuffle_v3f32_v4f32__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -232,33 +256,39 @@ define void @v_shuffle_v3f32_v4f32__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__6_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v4f32__6_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v4f32__6_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -272,11 +302,13 @@ define void @v_shuffle_v3f32_v4f32__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__7_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +320,8 @@ define void @v_shuffle_v3f32_v4f32__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +334,8 @@ define void @v_shuffle_v3f32_v4f32__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -321,6 +357,7 @@ define void @v_shuffle_v3f32_v4f32__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v8, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -337,6 +374,7 @@ define void @v_shuffle_v3f32_v4f32__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v5
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -351,6 +389,7 @@ define void @v_shuffle_v3f32_v4f32__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v5
; GFX942-NEXT: v_mov_b32_e32 v3, v0
@@ -375,6 +414,7 @@ define void @v_shuffle_v3f32_v4f32__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v7, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -390,6 +430,7 @@ define void @v_shuffle_v3f32_v4f32__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v6, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -404,6 +445,7 @@ define void @v_shuffle_v3f32_v4f32__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
; GFX942-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1]
@@ -427,6 +469,7 @@ define void @v_shuffle_v3f32_v4f32__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -443,6 +486,7 @@ define void @v_shuffle_v3f32_v4f32__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v8, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -459,6 +503,7 @@ define void @v_shuffle_v3f32_v4f32__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v1, v2
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v8, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -473,14 +518,15 @@ define void @v_shuffle_v3f32_v4f32__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__7_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -495,6 +541,7 @@ define void @v_shuffle_v3f32_v4f32__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v8, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -509,6 +556,7 @@ define void @v_shuffle_v3f32_v4f32__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v7
; GFX942-NEXT: global_store_dwordx3 v8, v[2:4], s[0:1]
@@ -525,38 +573,42 @@ define void @v_shuffle_v3f32_v4f32__7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__7_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v4f32__7_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v4f32__7_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v0
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -570,12 +622,13 @@ define void @v_shuffle_v3f32_v4f32__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__7_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -587,6 +640,7 @@ define void @v_shuffle_v3f32_v4f32__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -599,6 +653,7 @@ define void @v_shuffle_v3f32_v4f32__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -613,12 +668,13 @@ define void @v_shuffle_v3f32_v4f32__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__7_6_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -631,6 +687,7 @@ define void @v_shuffle_v3f32_v4f32__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -644,6 +701,7 @@ define void @v_shuffle_v3f32_v4f32__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -658,12 +716,13 @@ define void @v_shuffle_v3f32_v4f32__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__7_7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -673,9 +732,10 @@ define void @v_shuffle_v3f32_v4f32__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -685,9 +745,10 @@ define void @v_shuffle_v3f32_v4f32__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -2355,9 +2416,10 @@ define void @v_shuffle_v3f32_v4f32__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v5
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v6, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v2, v5
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2371,10 +2433,11 @@ define void @v_shuffle_v3f32_v4f32__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v5
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v2, v5
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v6, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -3971,6 +4034,7 @@ define void @v_shuffle_v3f32_v4f32__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx3 v8, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3987,6 +4051,7 @@ define void @v_shuffle_v3f32_v4f32__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx3 v8, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4386,6 +4451,8 @@ define void @v_shuffle_v3f32_v4f32__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4398,6 +4465,8 @@ define void @v_shuffle_v3f32_v4f32__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4410,6 +4479,8 @@ define void @v_shuffle_v3f32_v4f32__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4423,33 +4494,39 @@ define void @v_shuffle_v3f32_v4f32__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__2_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3f32_v4f32__2_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v4f32__2_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -4462,11 +4539,13 @@ define void @v_shuffle_v3f32_v4f32__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3f32_v4f32__3_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -4478,6 +4557,8 @@ define void @v_shuffle_v3f32_v4f32__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4490,6 +4571,8 @@ define void @v_shuffle_v3f32_v4f32__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -5461,26 +5544,29 @@ define void @v_shuffle_v3f32_v4f32__7_u_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3f32_v4f32__7_u_5:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v8, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3f32_v4f32__7_u_5:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v8, v1
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -7031,6 +7117,7 @@ define void @v_shuffle_v3f32_v4f32__7_u_7(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7044,6 +7131,7 @@ define void @v_shuffle_v3f32_v4f32__7_u_7(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7480,6 +7568,8 @@ define void @s_shuffle_v3f32_v4f32__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7492,6 +7582,8 @@ define void @s_shuffle_v3f32_v4f32__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7504,6 +7596,8 @@ define void @s_shuffle_v3f32_v4f32__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7522,6 +7616,8 @@ define void @s_shuffle_v3f32_v4f32__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7534,6 +7630,8 @@ define void @s_shuffle_v3f32_v4f32__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7546,6 +7644,8 @@ define void @s_shuffle_v3f32_v4f32__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7564,6 +7664,8 @@ define void @s_shuffle_v3f32_v4f32__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7576,6 +7678,8 @@ define void @s_shuffle_v3f32_v4f32__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7588,6 +7692,8 @@ define void @s_shuffle_v3f32_v4f32__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7620,6 +7726,8 @@ define void @s_shuffle_v3f32_v4f32__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7632,6 +7740,8 @@ define void @s_shuffle_v3f32_v4f32__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7644,6 +7754,8 @@ define void @s_shuffle_v3f32_v4f32__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7663,6 +7775,8 @@ define void @s_shuffle_v3f32_v4f32__6_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7675,6 +7789,8 @@ define void @s_shuffle_v3f32_v4f32__6_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7687,6 +7803,8 @@ define void @s_shuffle_v3f32_v4f32__6_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7706,6 +7824,8 @@ define void @s_shuffle_v3f32_v4f32__7_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7718,6 +7838,8 @@ define void @s_shuffle_v3f32_v4f32__7_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7730,6 +7852,8 @@ define void @s_shuffle_v3f32_v4f32__7_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7754,6 +7878,7 @@ define void @s_shuffle_v3f32_v4f32__7_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7770,6 +7895,7 @@ define void @s_shuffle_v3f32_v4f32__7_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7786,6 +7912,7 @@ define void @s_shuffle_v3f32_v4f32__7_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7808,6 +7935,7 @@ define void @s_shuffle_v3f32_v4f32__7_1_u() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7823,6 +7951,7 @@ define void @s_shuffle_v3f32_v4f32__7_1_u() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7838,6 +7967,7 @@ define void @s_shuffle_v3f32_v4f32__7_1_u() {
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7861,6 +7991,7 @@ define void @s_shuffle_v3f32_v4f32__7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7877,6 +8008,7 @@ define void @s_shuffle_v3f32_v4f32__7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7893,6 +8025,7 @@ define void @s_shuffle_v3f32_v4f32__7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7916,6 +8049,7 @@ define void @s_shuffle_v3f32_v4f32__7_3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7932,6 +8066,7 @@ define void @s_shuffle_v3f32_v4f32__7_3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7948,6 +8083,7 @@ define void @s_shuffle_v3f32_v4f32__7_3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7968,6 +8104,7 @@ define void @s_shuffle_v3f32_v4f32__7_4_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7981,6 +8118,7 @@ define void @s_shuffle_v3f32_v4f32__7_4_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7994,6 +8132,7 @@ define void @s_shuffle_v3f32_v4f32__7_4_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8013,6 +8152,7 @@ define void @s_shuffle_v3f32_v4f32__7_5_u() {
; GFX9-NEXT: ; def s[8:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
; GFX9-NEXT: ;;#ASMEND
@@ -8033,6 +8173,7 @@ define void @s_shuffle_v3f32_v4f32__7_6_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -8046,6 +8187,7 @@ define void @s_shuffle_v3f32_v4f32__7_6_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -8059,6 +8201,7 @@ define void @s_shuffle_v3f32_v4f32__7_6_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8079,6 +8222,7 @@ define void @s_shuffle_v3f32_v4f32__7_7_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -8092,6 +8236,7 @@ define void @s_shuffle_v3f32_v4f32__7_7_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -8105,6 +8250,7 @@ define void @s_shuffle_v3f32_v4f32__7_7_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8519,6 +8665,7 @@ define void @s_shuffle_v3f32_v4f32__u_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8532,6 +8679,7 @@ define void @s_shuffle_v3f32_v4f32__u_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8545,6 +8693,7 @@ define void @s_shuffle_v3f32_v4f32__u_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8727,6 +8876,7 @@ define void @s_shuffle_v3f32_v4f32__4_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8740,6 +8890,7 @@ define void @s_shuffle_v3f32_v4f32__4_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8753,6 +8904,7 @@ define void @s_shuffle_v3f32_v4f32__4_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8950,6 +9102,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_0() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -8966,6 +9119,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_0() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -8982,6 +9136,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_0() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -9626,6 +9781,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_1() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -9642,6 +9798,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_1() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -9658,6 +9815,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_1() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -10680,6 +10838,7 @@ define void @s_shuffle_v3f32_v4f32__u_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -10693,6 +10852,7 @@ define void @s_shuffle_v3f32_v4f32__u_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -10706,6 +10866,7 @@ define void @s_shuffle_v3f32_v4f32__u_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -10888,6 +11049,7 @@ define void @s_shuffle_v3f32_v4f32__4_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -10901,6 +11063,7 @@ define void @s_shuffle_v3f32_v4f32__4_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -10914,6 +11077,7 @@ define void @s_shuffle_v3f32_v4f32__4_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -11111,6 +11275,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_3() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11127,6 +11292,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_3() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11143,6 +11309,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_3() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11558,6 +11725,8 @@ define void @s_shuffle_v3f32_v4f32__1_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11570,6 +11739,8 @@ define void @s_shuffle_v3f32_v4f32__1_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11582,6 +11753,8 @@ define void @s_shuffle_v3f32_v4f32__1_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11600,6 +11773,8 @@ define void @s_shuffle_v3f32_v4f32__2_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11612,6 +11787,8 @@ define void @s_shuffle_v3f32_v4f32__2_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11624,6 +11801,8 @@ define void @s_shuffle_v3f32_v4f32__2_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11642,6 +11821,8 @@ define void @s_shuffle_v3f32_v4f32__3_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11654,6 +11835,8 @@ define void @s_shuffle_v3f32_v4f32__3_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11666,6 +11849,8 @@ define void @s_shuffle_v3f32_v4f32__3_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11845,6 +12030,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -11858,6 +12044,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -11871,6 +12058,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -12536,6 +12724,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -12549,6 +12738,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -12562,6 +12752,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -13534,6 +13725,7 @@ define void @s_shuffle_v3f32_v4f32__u_7_7() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -13547,6 +13739,7 @@ define void @s_shuffle_v3f32_v4f32__u_7_7() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -13560,6 +13753,7 @@ define void @s_shuffle_v3f32_v4f32__u_7_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -13927,6 +14121,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_7() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -13940,6 +14135,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_7() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -13953,6 +14149,7 @@ define void @s_shuffle_v3f32_v4f32__7_u_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
index 7d5ba7c5f9d89..b1ac4ca8d5070 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
@@ -2147,6 +2147,7 @@ define void @s_shuffle_v3i16_v2i16__0_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2158,6 +2159,7 @@ define void @s_shuffle_v3i16_v2i16__0_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2169,6 +2171,7 @@ define void @s_shuffle_v3i16_v2i16__0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2188,6 +2191,7 @@ define void @s_shuffle_v3i16_v2i16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2200,6 +2204,7 @@ define void @s_shuffle_v3i16_v2i16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2212,6 +2217,7 @@ define void @s_shuffle_v3i16_v2i16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2246,6 +2252,7 @@ define void @s_shuffle_v3i16_v2i16__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2258,6 +2265,7 @@ define void @s_shuffle_v3i16_v2i16__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2270,6 +2278,7 @@ define void @s_shuffle_v3i16_v2i16__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2295,6 +2304,7 @@ define void @s_shuffle_v3i16_v2i16__3_0_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2311,6 +2321,7 @@ define void @s_shuffle_v3i16_v2i16__3_0_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2327,6 +2338,7 @@ define void @s_shuffle_v3i16_v2i16__3_0_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -2350,6 +2362,7 @@ define void @s_shuffle_v3i16_v2i16__3_1_u() {
; GFX900-NEXT: ; def s5
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -2365,6 +2378,7 @@ define void @s_shuffle_v3i16_v2i16__3_1_u() {
; GFX90A-NEXT: ; def s5
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -2380,6 +2394,7 @@ define void @s_shuffle_v3i16_v2i16__3_1_u() {
; GFX942-NEXT: ; def s1
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -2400,6 +2415,7 @@ define void @s_shuffle_v3i16_v2i16__3_2_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2413,6 +2429,7 @@ define void @s_shuffle_v3i16_v2i16__3_2_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2426,6 +2443,7 @@ define void @s_shuffle_v3i16_v2i16__3_2_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -2446,6 +2464,7 @@ define void @s_shuffle_v3i16_v2i16__3_3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -2458,6 +2477,7 @@ define void @s_shuffle_v3i16_v2i16__3_3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -2470,6 +2490,7 @@ define void @s_shuffle_v3i16_v2i16__3_3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3335,6 +3356,7 @@ define void @s_shuffle_v3i16_v2i16__0_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3346,6 +3368,7 @@ define void @s_shuffle_v3i16_v2i16__0_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3357,6 +3380,7 @@ define void @s_shuffle_v3i16_v2i16__0_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3376,6 +3400,7 @@ define void @s_shuffle_v3i16_v2i16__1_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3388,6 +3413,7 @@ define void @s_shuffle_v3i16_v2i16__1_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3400,6 +3426,7 @@ define void @s_shuffle_v3i16_v2i16__1_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
index 0cf6da3659dde..4d352ad8a425f 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v3i16.ll
@@ -4777,6 +4777,7 @@ define void @s_shuffle_v3i16_v3i16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4789,6 +4790,7 @@ define void @s_shuffle_v3i16_v3i16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4801,6 +4803,7 @@ define void @s_shuffle_v3i16_v3i16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4821,6 +4824,7 @@ define void @s_shuffle_v3i16_v3i16__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4833,6 +4837,7 @@ define void @s_shuffle_v3i16_v3i16__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4845,6 +4850,7 @@ define void @s_shuffle_v3i16_v3i16__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4881,6 +4887,7 @@ define void @s_shuffle_v3i16_v3i16__4_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4893,6 +4900,7 @@ define void @s_shuffle_v3i16_v3i16__4_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4905,6 +4913,7 @@ define void @s_shuffle_v3i16_v3i16__4_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4927,6 +4936,7 @@ define void @s_shuffle_v3i16_v3i16__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -4939,6 +4949,7 @@ define void @s_shuffle_v3i16_v3i16__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -4951,6 +4962,7 @@ define void @s_shuffle_v3i16_v3i16__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -4977,6 +4989,7 @@ define void @s_shuffle_v3i16_v3i16__5_0_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -4992,6 +5005,7 @@ define void @s_shuffle_v3i16_v3i16__5_0_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5007,6 +5021,7 @@ define void @s_shuffle_v3i16_v3i16__5_0_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5032,6 +5047,7 @@ define void @s_shuffle_v3i16_v3i16__5_1_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_lh_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5047,6 +5063,7 @@ define void @s_shuffle_v3i16_v3i16__5_1_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_lh_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5062,6 +5079,7 @@ define void @s_shuffle_v3i16_v3i16__5_1_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_lh_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5087,6 +5105,7 @@ define void @s_shuffle_v3i16_v3i16__5_2_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5102,6 +5121,7 @@ define void @s_shuffle_v3i16_v3i16__5_2_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5117,6 +5137,7 @@ define void @s_shuffle_v3i16_v3i16__5_2_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -5138,6 +5159,7 @@ define void @s_shuffle_v3i16_v3i16__5_3_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5150,6 +5172,7 @@ define void @s_shuffle_v3i16_v3i16__5_3_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5162,6 +5185,7 @@ define void @s_shuffle_v3i16_v3i16__5_3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5184,6 +5208,7 @@ define void @s_shuffle_v3i16_v3i16__5_4_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_lh_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5196,6 +5221,7 @@ define void @s_shuffle_v3i16_v3i16__5_4_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_lh_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5208,6 +5234,7 @@ define void @s_shuffle_v3i16_v3i16__5_4_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_lh_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5230,6 +5257,7 @@ define void @s_shuffle_v3i16_v3i16__5_5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5242,6 +5270,7 @@ define void @s_shuffle_v3i16_v3i16__5_5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5254,6 +5283,7 @@ define void @s_shuffle_v3i16_v3i16__5_5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7347,6 +7377,7 @@ define void @s_shuffle_v3i16_v3i16__1_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7359,6 +7390,7 @@ define void @s_shuffle_v3i16_v3i16__1_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7371,6 +7403,7 @@ define void @s_shuffle_v3i16_v3i16__1_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7391,6 +7424,7 @@ define void @s_shuffle_v3i16_v3i16__2_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7403,6 +7437,7 @@ define void @s_shuffle_v3i16_v3i16__2_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7415,6 +7450,7 @@ define void @s_shuffle_v3i16_v3i16__2_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
index 977055e546bba..a3e1b8164f737 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v4i16.ll
@@ -7918,6 +7918,7 @@ define void @s_shuffle_v3i16_v4i16__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7930,6 +7931,7 @@ define void @s_shuffle_v3i16_v4i16__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7942,6 +7944,7 @@ define void @s_shuffle_v3i16_v4i16__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7961,6 +7964,7 @@ define void @s_shuffle_v3i16_v4i16__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7973,6 +7977,7 @@ define void @s_shuffle_v3i16_v4i16__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7985,6 +7990,7 @@ define void @s_shuffle_v3i16_v4i16__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8004,6 +8010,7 @@ define void @s_shuffle_v3i16_v4i16__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8016,6 +8023,7 @@ define void @s_shuffle_v3i16_v4i16__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8028,6 +8036,7 @@ define void @s_shuffle_v3i16_v4i16__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8062,6 +8071,7 @@ define void @s_shuffle_v3i16_v4i16__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8074,6 +8084,7 @@ define void @s_shuffle_v3i16_v4i16__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8086,6 +8097,7 @@ define void @s_shuffle_v3i16_v4i16__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8106,6 +8118,7 @@ define void @s_shuffle_v3i16_v4i16__6_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8118,6 +8131,7 @@ define void @s_shuffle_v3i16_v4i16__6_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8130,6 +8144,7 @@ define void @s_shuffle_v3i16_v4i16__6_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8150,6 +8165,7 @@ define void @s_shuffle_v3i16_v4i16__7_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8162,6 +8178,7 @@ define void @s_shuffle_v3i16_v4i16__7_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8174,6 +8191,7 @@ define void @s_shuffle_v3i16_v4i16__7_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8199,6 +8217,7 @@ define void @s_shuffle_v3i16_v4i16__7_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8215,6 +8234,7 @@ define void @s_shuffle_v3i16_v4i16__7_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8231,6 +8251,7 @@ define void @s_shuffle_v3i16_v4i16__7_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8254,6 +8275,7 @@ define void @s_shuffle_v3i16_v4i16__7_1_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8269,6 +8291,7 @@ define void @s_shuffle_v3i16_v4i16__7_1_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8284,6 +8307,7 @@ define void @s_shuffle_v3i16_v4i16__7_1_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8308,6 +8332,7 @@ define void @s_shuffle_v3i16_v4i16__7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8324,6 +8349,7 @@ define void @s_shuffle_v3i16_v4i16__7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8340,6 +8366,7 @@ define void @s_shuffle_v3i16_v4i16__7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8363,6 +8390,7 @@ define void @s_shuffle_v3i16_v4i16__7_3_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s7, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -8378,6 +8406,7 @@ define void @s_shuffle_v3i16_v4i16__7_3_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s7, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -8393,6 +8422,7 @@ define void @s_shuffle_v3i16_v4i16__7_3_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s3, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -8413,6 +8443,7 @@ define void @s_shuffle_v3i16_v4i16__7_4_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8426,6 +8457,7 @@ define void @s_shuffle_v3i16_v4i16__7_4_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8439,6 +8471,7 @@ define void @s_shuffle_v3i16_v4i16__7_4_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8459,6 +8492,7 @@ define void @s_shuffle_v3i16_v4i16__7_5_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8471,6 +8505,7 @@ define void @s_shuffle_v3i16_v4i16__7_5_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8483,6 +8518,7 @@ define void @s_shuffle_v3i16_v4i16__7_5_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8504,6 +8540,7 @@ define void @s_shuffle_v3i16_v4i16__7_6_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8517,6 +8554,7 @@ define void @s_shuffle_v3i16_v4i16__7_6_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8530,6 +8568,7 @@ define void @s_shuffle_v3i16_v4i16__7_6_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -8550,6 +8589,7 @@ define void @s_shuffle_v3i16_v4i16__7_7_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s5, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -8562,6 +8602,7 @@ define void @s_shuffle_v3i16_v4i16__7_7_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s5, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -8574,6 +8615,7 @@ define void @s_shuffle_v3i16_v4i16__7_7_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s1, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12217,6 +12259,7 @@ define void @s_shuffle_v3i16_v4i16__1_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12229,6 +12272,7 @@ define void @s_shuffle_v3i16_v4i16__1_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12241,6 +12285,7 @@ define void @s_shuffle_v3i16_v4i16__1_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12260,6 +12305,7 @@ define void @s_shuffle_v3i16_v4i16__2_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12272,6 +12318,7 @@ define void @s_shuffle_v3i16_v4i16__2_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12284,6 +12331,7 @@ define void @s_shuffle_v3i16_v4i16__2_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12303,6 +12351,7 @@ define void @s_shuffle_v3i16_v4i16__3_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12315,6 +12364,7 @@ define void @s_shuffle_v3i16_v4i16__3_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12327,6 +12377,7 @@ define void @s_shuffle_v3i16_v4i16__3_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
index 6a0527f7cca24..371e900dbd450 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v2i32.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v3i32_v2i32__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v2i32__0_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v2i32__0_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v2i32__0_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -58,35 +61,42 @@ define void @v_shuffle_v3i32_v2i32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v2i32__1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v2i32__1_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v2i32__1_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -110,35 +120,42 @@ define void @v_shuffle_v3i32_v2i32__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v2i32__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v2i32__3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v2i32__3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -159,6 +176,7 @@ define void @v_shuffle_v3i32_v2i32__3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -166,32 +184,35 @@ define void @v_shuffle_v3i32_v2i32__3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3i32_v2i32__3_0_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
-; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ;;#ASMSTART
+; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v2i32__3_0_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:3]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def v[2:3]
+; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v0
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -205,14 +226,15 @@ define void @v_shuffle_v3i32_v2i32__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v2i32__3_1_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -227,6 +249,7 @@ define void @v_shuffle_v3i32_v2i32__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -241,6 +264,7 @@ define void @v_shuffle_v3i32_v2i32__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
@@ -257,12 +281,13 @@ define void @v_shuffle_v3i32_v2i32__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v2i32__3_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v0
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -275,6 +300,7 @@ define void @v_shuffle_v3i32_v2i32__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -286,6 +312,7 @@ define void @v_shuffle_v3i32_v2i32__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v0
@@ -303,12 +330,13 @@ define void @v_shuffle_v3i32_v2i32__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v2i32__3_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -318,9 +346,10 @@ define void @v_shuffle_v3i32_v2i32__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -330,9 +359,10 @@ define void @v_shuffle_v3i32_v2i32__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -1178,32 +1208,35 @@ define void @v_shuffle_v3i32_v2i32__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3i32_v2i32__3_u_1:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v8, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v2i32__3_u_1:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v8, v1
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -1341,33 +1374,36 @@ define void @v_shuffle_v3i32_v2i32__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v2i32__0_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v2i32__0_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v2i32__0_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -1380,35 +1416,42 @@ define void @v_shuffle_v3i32_v2i32__1_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v2i32__1_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v2i32__1_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v2i32__1_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -1845,6 +1888,7 @@ define void @v_shuffle_v3i32_v2i32__3_u_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v6, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1856,6 +1900,7 @@ define void @v_shuffle_v3i32_v2i32__3_u_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v6, v1
@@ -2050,6 +2095,7 @@ define void @s_shuffle_v3i32_v2i32__0_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2061,6 +2107,7 @@ define void @s_shuffle_v3i32_v2i32__0_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2072,6 +2119,7 @@ define void @s_shuffle_v3i32_v2i32__0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2090,6 +2138,8 @@ define void @s_shuffle_v3i32_v2i32__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2102,6 +2152,8 @@ define void @s_shuffle_v3i32_v2i32__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2114,6 +2166,8 @@ define void @s_shuffle_v3i32_v2i32__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2146,6 +2200,8 @@ define void @s_shuffle_v3i32_v2i32__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2158,6 +2214,8 @@ define void @s_shuffle_v3i32_v2i32__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2170,6 +2228,8 @@ define void @s_shuffle_v3i32_v2i32__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2194,6 +2254,7 @@ define void @s_shuffle_v3i32_v2i32__3_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2210,6 +2271,7 @@ define void @s_shuffle_v3i32_v2i32__3_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2226,6 +2288,7 @@ define void @s_shuffle_v3i32_v2i32__3_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2248,6 +2311,7 @@ define void @s_shuffle_v3i32_v2i32__3_1_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2263,6 +2327,7 @@ define void @s_shuffle_v3i32_v2i32__3_1_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2278,6 +2343,7 @@ define void @s_shuffle_v3i32_v2i32__3_1_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2298,6 +2364,7 @@ define void @s_shuffle_v3i32_v2i32__3_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2311,6 +2378,7 @@ define void @s_shuffle_v3i32_v2i32__3_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2324,6 +2392,7 @@ define void @s_shuffle_v3i32_v2i32__3_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2342,6 +2411,7 @@ define void @s_shuffle_v3i32_v2i32__3_3_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
@@ -2901,6 +2971,7 @@ define void @s_shuffle_v3i32_v2i32__3_u_1() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2917,6 +2988,7 @@ define void @s_shuffle_v3i32_v2i32__3_u_1() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2933,6 +3005,7 @@ define void @s_shuffle_v3i32_v2i32__3_u_1() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3082,6 +3155,7 @@ define void @s_shuffle_v3i32_v2i32__0_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -3093,6 +3167,7 @@ define void @s_shuffle_v3i32_v2i32__0_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -3104,6 +3179,7 @@ define void @s_shuffle_v3i32_v2i32__0_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3122,6 +3198,8 @@ define void @s_shuffle_v3i32_v2i32__1_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -3134,6 +3212,8 @@ define void @s_shuffle_v3i32_v2i32__1_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -3146,6 +3226,8 @@ define void @s_shuffle_v3i32_v2i32__1_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3442,6 +3524,7 @@ define void @s_shuffle_v3i32_v2i32__3_u_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -3455,6 +3538,7 @@ define void @s_shuffle_v3i32_v2i32__3_u_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -3468,6 +3552,7 @@ define void @s_shuffle_v3i32_v2i32__3_u_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
index 65ceea2299e10..36c199391b581 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v3i32.ll
@@ -58,11 +58,13 @@ define void @v_shuffle_v3i32_v3i32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +76,8 @@ define void @v_shuffle_v3i32_v3i32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +90,8 @@ define void @v_shuffle_v3i32_v3i32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +105,39 @@ define void @v_shuffle_v3i32_v3i32__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v3i32__2_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v3i32__2_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -149,11 +161,13 @@ define void @v_shuffle_v3i32_v3i32__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -165,6 +179,8 @@ define void @v_shuffle_v3i32_v3i32__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -177,6 +193,8 @@ define void @v_shuffle_v3i32_v3i32__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -191,33 +209,39 @@ define void @v_shuffle_v3i32_v3i32__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v3i32__5_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v3i32__5_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -238,6 +262,7 @@ define void @v_shuffle_v3i32_v3i32__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -253,6 +278,7 @@ define void @v_shuffle_v3i32_v3i32__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v7, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -269,6 +295,7 @@ define void @v_shuffle_v3i32_v3i32__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx3 v7, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -290,6 +317,7 @@ define void @v_shuffle_v3i32_v3i32__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -304,6 +332,7 @@ define void @v_shuffle_v3i32_v3i32__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -315,6 +344,7 @@ define void @v_shuffle_v3i32_v3i32__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -333,14 +363,15 @@ define void @v_shuffle_v3i32_v3i32__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__5_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -355,6 +386,7 @@ define void @v_shuffle_v3i32_v3i32__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -370,6 +402,7 @@ define void @v_shuffle_v3i32_v3i32__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -384,37 +417,40 @@ define void @v_shuffle_v3i32_v3i32__5_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__5_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v3i32__5_3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v3i32__5_3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -428,37 +464,40 @@ define void @v_shuffle_v3i32_v3i32__5_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__5_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v3i32__5_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v3i32__5_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -472,37 +511,40 @@ define void @v_shuffle_v3i32_v3i32__5_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__5_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v3i32__5_5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v3i32__5_5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -1747,14 +1789,15 @@ define void @v_shuffle_v3i32_v3i32__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:4]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
-; GFX90A-NEXT: v_mov_b32_e32 v4, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, v5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx3 v7, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1762,14 +1805,15 @@ define void @v_shuffle_v3i32_v3i32__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:4]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
-; GFX942-NEXT: v_mov_b32_e32 v4, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx3 v7, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -2630,11 +2674,13 @@ define void @v_shuffle_v3i32_v3i32__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__1_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2646,6 +2692,8 @@ define void @v_shuffle_v3i32_v3i32__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2658,6 +2706,8 @@ define void @v_shuffle_v3i32_v3i32__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2671,33 +2721,39 @@ define void @v_shuffle_v3i32_v3i32__2_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v3i32__2_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v3i32__2_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v3i32__2_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -4316,6 +4372,8 @@ define void @s_shuffle_v3i32_v3i32__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4328,6 +4386,8 @@ define void @s_shuffle_v3i32_v3i32__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4340,6 +4400,8 @@ define void @s_shuffle_v3i32_v3i32__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4358,6 +4420,8 @@ define void @s_shuffle_v3i32_v3i32__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4370,6 +4434,8 @@ define void @s_shuffle_v3i32_v3i32__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4382,6 +4448,8 @@ define void @s_shuffle_v3i32_v3i32__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4414,6 +4482,8 @@ define void @s_shuffle_v3i32_v3i32__4_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4426,6 +4496,8 @@ define void @s_shuffle_v3i32_v3i32__4_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4438,6 +4510,8 @@ define void @s_shuffle_v3i32_v3i32__4_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4457,6 +4531,8 @@ define void @s_shuffle_v3i32_v3i32__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4469,6 +4545,8 @@ define void @s_shuffle_v3i32_v3i32__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4481,6 +4559,8 @@ define void @s_shuffle_v3i32_v3i32__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4505,6 +4585,7 @@ define void @s_shuffle_v3i32_v3i32__5_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4521,6 +4602,7 @@ define void @s_shuffle_v3i32_v3i32__5_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4537,6 +4619,7 @@ define void @s_shuffle_v3i32_v3i32__5_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4559,6 +4642,7 @@ define void @s_shuffle_v3i32_v3i32__5_1_u() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4574,6 +4658,7 @@ define void @s_shuffle_v3i32_v3i32__5_1_u() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4589,6 +4674,7 @@ define void @s_shuffle_v3i32_v3i32__5_1_u() {
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4612,6 +4698,7 @@ define void @s_shuffle_v3i32_v3i32__5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4628,6 +4715,7 @@ define void @s_shuffle_v3i32_v3i32__5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4644,6 +4732,7 @@ define void @s_shuffle_v3i32_v3i32__5_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4664,6 +4753,7 @@ define void @s_shuffle_v3i32_v3i32__5_3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4677,6 +4767,7 @@ define void @s_shuffle_v3i32_v3i32__5_3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4690,6 +4781,7 @@ define void @s_shuffle_v3i32_v3i32__5_3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4709,6 +4801,7 @@ define void @s_shuffle_v3i32_v3i32__5_4_u() {
; GFX9-NEXT: ; def s[8:10]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
; GFX9-NEXT: ;;#ASMEND
@@ -4729,6 +4822,7 @@ define void @s_shuffle_v3i32_v3i32__5_5_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4742,6 +4836,7 @@ define void @s_shuffle_v3i32_v3i32__5_5_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4755,6 +4850,7 @@ define void @s_shuffle_v3i32_v3i32__5_5_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -5062,6 +5158,7 @@ define void @s_shuffle_v3i32_v3i32__u_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -5075,6 +5172,7 @@ define void @s_shuffle_v3i32_v3i32__u_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -5088,6 +5186,7 @@ define void @s_shuffle_v3i32_v3i32__u_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -5222,6 +5321,7 @@ define void @s_shuffle_v3i32_v3i32__3_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -5235,6 +5335,7 @@ define void @s_shuffle_v3i32_v3i32__3_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -5248,6 +5349,7 @@ define void @s_shuffle_v3i32_v3i32__3_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -5387,6 +5489,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_0() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -5403,6 +5506,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_0() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -5419,6 +5523,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_0() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -5873,6 +5978,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_1() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -5889,6 +5995,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_1() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -5905,6 +6012,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_1() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6681,6 +6789,8 @@ define void @s_shuffle_v3i32_v3i32__1_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -6693,6 +6803,8 @@ define void @s_shuffle_v3i32_v3i32__1_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -6705,6 +6817,8 @@ define void @s_shuffle_v3i32_v3i32__1_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6723,6 +6837,8 @@ define void @s_shuffle_v3i32_v3i32__2_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -6735,6 +6851,8 @@ define void @s_shuffle_v3i32_v3i32__2_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -6747,6 +6865,8 @@ define void @s_shuffle_v3i32_v3i32__2_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6877,6 +6997,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -6890,6 +7011,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -6903,6 +7025,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -7386,6 +7509,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -7399,6 +7523,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -7412,6 +7537,7 @@ define void @s_shuffle_v3i32_v3i32__5_u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
index 3d838b9952147..4466fe8e7a522 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i32.v4i32.ll
@@ -62,6 +62,8 @@ define void @v_shuffle_v3i32_v4i32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +76,8 @@ define void @v_shuffle_v3i32_v4i32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +90,8 @@ define void @v_shuffle_v3i32_v4i32__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +105,39 @@ define void @v_shuffle_v3i32_v4i32__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v4i32__2_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v4i32__2_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -138,11 +150,13 @@ define void @v_shuffle_v3i32_v4i32__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +168,8 @@ define void @v_shuffle_v3i32_v4i32__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +182,8 @@ define void @v_shuffle_v3i32_v4i32__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -194,6 +212,8 @@ define void @v_shuffle_v3i32_v4i32__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -206,6 +226,8 @@ define void @v_shuffle_v3i32_v4i32__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +240,8 @@ define void @v_shuffle_v3i32_v4i32__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -232,33 +256,39 @@ define void @v_shuffle_v3i32_v4i32__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__6_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v4i32__6_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v4i32__6_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -272,11 +302,13 @@ define void @v_shuffle_v3i32_v4i32__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__7_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +320,8 @@ define void @v_shuffle_v3i32_v4i32__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +334,8 @@ define void @v_shuffle_v3i32_v4i32__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -321,6 +357,7 @@ define void @v_shuffle_v3i32_v4i32__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v8, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -337,6 +374,7 @@ define void @v_shuffle_v3i32_v4i32__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v5
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -351,6 +389,7 @@ define void @v_shuffle_v3i32_v4i32__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v5
; GFX942-NEXT: v_mov_b32_e32 v3, v0
@@ -375,6 +414,7 @@ define void @v_shuffle_v3i32_v4i32__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v7, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -390,6 +430,7 @@ define void @v_shuffle_v3i32_v4i32__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v6, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -404,6 +445,7 @@ define void @v_shuffle_v3i32_v4i32__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
; GFX942-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1]
@@ -427,6 +469,7 @@ define void @v_shuffle_v3i32_v4i32__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -443,6 +486,7 @@ define void @v_shuffle_v3i32_v4i32__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v8, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -459,6 +503,7 @@ define void @v_shuffle_v3i32_v4i32__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v1, v2
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v8, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -473,14 +518,15 @@ define void @v_shuffle_v3i32_v4i32__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__7_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -495,6 +541,7 @@ define void @v_shuffle_v3i32_v4i32__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v8, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -509,6 +556,7 @@ define void @v_shuffle_v3i32_v4i32__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v7
; GFX942-NEXT: global_store_dwordx3 v8, v[2:4], s[0:1]
@@ -525,38 +573,42 @@ define void @v_shuffle_v3i32_v4i32__7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__7_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v4i32__7_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v4i32__7_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v0
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -570,12 +622,13 @@ define void @v_shuffle_v3i32_v4i32__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__7_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -587,6 +640,7 @@ define void @v_shuffle_v3i32_v4i32__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -599,6 +653,7 @@ define void @v_shuffle_v3i32_v4i32__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -613,12 +668,13 @@ define void @v_shuffle_v3i32_v4i32__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__7_6_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -631,6 +687,7 @@ define void @v_shuffle_v3i32_v4i32__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -644,6 +701,7 @@ define void @v_shuffle_v3i32_v4i32__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -658,12 +716,13 @@ define void @v_shuffle_v3i32_v4i32__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__7_7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -673,9 +732,10 @@ define void @v_shuffle_v3i32_v4i32__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -685,9 +745,10 @@ define void @v_shuffle_v3i32_v4i32__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -2355,9 +2416,10 @@ define void @v_shuffle_v3i32_v4i32__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v5
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v6, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v2, v5
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2371,10 +2433,11 @@ define void @v_shuffle_v3i32_v4i32__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v5
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v2, v5
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v6, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -3971,6 +4034,7 @@ define void @v_shuffle_v3i32_v4i32__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx3 v8, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3987,6 +4051,7 @@ define void @v_shuffle_v3i32_v4i32__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx3 v8, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4386,6 +4451,8 @@ define void @v_shuffle_v3i32_v4i32__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4398,6 +4465,8 @@ define void @v_shuffle_v3i32_v4i32__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4410,6 +4479,8 @@ define void @v_shuffle_v3i32_v4i32__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4423,33 +4494,39 @@ define void @v_shuffle_v3i32_v4i32__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__2_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i32_v4i32__2_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v4i32__2_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -4462,11 +4539,13 @@ define void @v_shuffle_v3i32_v4i32__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i32_v4i32__3_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -4478,6 +4557,8 @@ define void @v_shuffle_v3i32_v4i32__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4490,6 +4571,8 @@ define void @v_shuffle_v3i32_v4i32__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -5461,26 +5544,29 @@ define void @v_shuffle_v3i32_v4i32__7_u_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3i32_v4i32__7_u_5:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v8, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i32_v4i32__7_u_5:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v8, v1
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -7031,6 +7117,7 @@ define void @v_shuffle_v3i32_v4i32__7_u_7(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7044,6 +7131,7 @@ define void @v_shuffle_v3i32_v4i32__7_u_7(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7480,6 +7568,8 @@ define void @s_shuffle_v3i32_v4i32__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7492,6 +7582,8 @@ define void @s_shuffle_v3i32_v4i32__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7504,6 +7596,8 @@ define void @s_shuffle_v3i32_v4i32__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7522,6 +7616,8 @@ define void @s_shuffle_v3i32_v4i32__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7534,6 +7630,8 @@ define void @s_shuffle_v3i32_v4i32__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7546,6 +7644,8 @@ define void @s_shuffle_v3i32_v4i32__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7564,6 +7664,8 @@ define void @s_shuffle_v3i32_v4i32__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7576,6 +7678,8 @@ define void @s_shuffle_v3i32_v4i32__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7588,6 +7692,8 @@ define void @s_shuffle_v3i32_v4i32__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7620,6 +7726,8 @@ define void @s_shuffle_v3i32_v4i32__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7632,6 +7740,8 @@ define void @s_shuffle_v3i32_v4i32__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7644,6 +7754,8 @@ define void @s_shuffle_v3i32_v4i32__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7663,6 +7775,8 @@ define void @s_shuffle_v3i32_v4i32__6_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7675,6 +7789,8 @@ define void @s_shuffle_v3i32_v4i32__6_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7687,6 +7803,8 @@ define void @s_shuffle_v3i32_v4i32__6_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7706,6 +7824,8 @@ define void @s_shuffle_v3i32_v4i32__7_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7718,6 +7838,8 @@ define void @s_shuffle_v3i32_v4i32__7_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7730,6 +7852,8 @@ define void @s_shuffle_v3i32_v4i32__7_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7754,6 +7878,7 @@ define void @s_shuffle_v3i32_v4i32__7_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7770,6 +7895,7 @@ define void @s_shuffle_v3i32_v4i32__7_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7786,6 +7912,7 @@ define void @s_shuffle_v3i32_v4i32__7_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7808,6 +7935,7 @@ define void @s_shuffle_v3i32_v4i32__7_1_u() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7823,6 +7951,7 @@ define void @s_shuffle_v3i32_v4i32__7_1_u() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7838,6 +7967,7 @@ define void @s_shuffle_v3i32_v4i32__7_1_u() {
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7861,6 +7991,7 @@ define void @s_shuffle_v3i32_v4i32__7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7877,6 +8008,7 @@ define void @s_shuffle_v3i32_v4i32__7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7893,6 +8025,7 @@ define void @s_shuffle_v3i32_v4i32__7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7916,6 +8049,7 @@ define void @s_shuffle_v3i32_v4i32__7_3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7932,6 +8066,7 @@ define void @s_shuffle_v3i32_v4i32__7_3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7948,6 +8083,7 @@ define void @s_shuffle_v3i32_v4i32__7_3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7968,6 +8104,7 @@ define void @s_shuffle_v3i32_v4i32__7_4_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7981,6 +8118,7 @@ define void @s_shuffle_v3i32_v4i32__7_4_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7994,6 +8132,7 @@ define void @s_shuffle_v3i32_v4i32__7_4_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8013,6 +8152,7 @@ define void @s_shuffle_v3i32_v4i32__7_5_u() {
; GFX9-NEXT: ; def s[8:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
; GFX9-NEXT: ;;#ASMEND
@@ -8033,6 +8173,7 @@ define void @s_shuffle_v3i32_v4i32__7_6_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -8046,6 +8187,7 @@ define void @s_shuffle_v3i32_v4i32__7_6_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -8059,6 +8201,7 @@ define void @s_shuffle_v3i32_v4i32__7_6_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8079,6 +8222,7 @@ define void @s_shuffle_v3i32_v4i32__7_7_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -8092,6 +8236,7 @@ define void @s_shuffle_v3i32_v4i32__7_7_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -8105,6 +8250,7 @@ define void @s_shuffle_v3i32_v4i32__7_7_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8519,6 +8665,7 @@ define void @s_shuffle_v3i32_v4i32__u_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8532,6 +8679,7 @@ define void @s_shuffle_v3i32_v4i32__u_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8545,6 +8693,7 @@ define void @s_shuffle_v3i32_v4i32__u_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8727,6 +8876,7 @@ define void @s_shuffle_v3i32_v4i32__4_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8740,6 +8890,7 @@ define void @s_shuffle_v3i32_v4i32__4_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8753,6 +8904,7 @@ define void @s_shuffle_v3i32_v4i32__4_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8950,6 +9102,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_0() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -8966,6 +9119,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_0() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -8982,6 +9136,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_0() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -9626,6 +9781,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_1() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -9642,6 +9798,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_1() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -9658,6 +9815,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_1() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -10680,6 +10838,7 @@ define void @s_shuffle_v3i32_v4i32__u_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -10693,6 +10852,7 @@ define void @s_shuffle_v3i32_v4i32__u_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -10706,6 +10866,7 @@ define void @s_shuffle_v3i32_v4i32__u_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -10888,6 +11049,7 @@ define void @s_shuffle_v3i32_v4i32__4_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -10901,6 +11063,7 @@ define void @s_shuffle_v3i32_v4i32__4_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -10914,6 +11077,7 @@ define void @s_shuffle_v3i32_v4i32__4_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -11111,6 +11275,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_3() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11127,6 +11292,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_3() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11143,6 +11309,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_3() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11558,6 +11725,8 @@ define void @s_shuffle_v3i32_v4i32__1_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11570,6 +11739,8 @@ define void @s_shuffle_v3i32_v4i32__1_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11582,6 +11753,8 @@ define void @s_shuffle_v3i32_v4i32__1_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11600,6 +11773,8 @@ define void @s_shuffle_v3i32_v4i32__2_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11612,6 +11787,8 @@ define void @s_shuffle_v3i32_v4i32__2_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11624,6 +11801,8 @@ define void @s_shuffle_v3i32_v4i32__2_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11642,6 +11821,8 @@ define void @s_shuffle_v3i32_v4i32__3_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11654,6 +11835,8 @@ define void @s_shuffle_v3i32_v4i32__3_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11666,6 +11849,8 @@ define void @s_shuffle_v3i32_v4i32__3_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11845,6 +12030,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -11858,6 +12044,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -11871,6 +12058,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -12536,6 +12724,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -12549,6 +12738,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -12562,6 +12752,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -13534,6 +13725,7 @@ define void @s_shuffle_v3i32_v4i32__u_7_7() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -13547,6 +13739,7 @@ define void @s_shuffle_v3i32_v4i32__u_7_7() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -13560,6 +13753,7 @@ define void @s_shuffle_v3i32_v4i32__u_7_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -13927,6 +14121,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_7() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -13940,6 +14135,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_7() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -13953,6 +14149,7 @@ define void @s_shuffle_v3i32_v4i32__7_u_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
index a6ac456246f8e..54c0f2a524754 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v2i64.ll
@@ -58,33 +58,39 @@ define void @v_shuffle_v3i64_v2i64__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v2i64__1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v2i64__1_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v2i64__1_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -108,33 +114,39 @@ define void @v_shuffle_v3i64_v2i64__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v2i64__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v2i64__3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v2i64__3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -796,6 +808,8 @@ define void @v_shuffle_v3i64_v2i64__3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -811,6 +825,8 @@ define void @v_shuffle_v3i64_v2i64__3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -826,6 +842,8 @@ define void @v_shuffle_v3i64_v2i64__3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v8, v[4:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1191,6 +1209,8 @@ define void @v_shuffle_v3i64_v2i64__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v6, v[4:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1206,6 +1226,8 @@ define void @v_shuffle_v3i64_v2i64__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v6, v[4:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1222,6 +1244,8 @@ define void @v_shuffle_v3i64_v2i64__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v6, v[4:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1397,33 +1421,39 @@ define void @v_shuffle_v3i64_v2i64__1_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v2i64__1_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v2i64__1_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v2i64__1_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -1496,36 +1526,42 @@ define void @v_shuffle_v3i64_v2i64__3_u_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v2i64__3_u_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v2i64__3_u_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v2i64__3_u_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -1845,36 +1881,42 @@ define void @v_shuffle_v3i64_v2i64__3_u_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v2i64__3_u_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v6, v[2:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v2i64__3_u_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v6, v[2:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v2i64__3_u_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v6, v[2:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -2058,6 +2100,8 @@ define void @s_shuffle_v3i64_v2i64__0_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2069,6 +2113,8 @@ define void @s_shuffle_v3i64_v2i64__0_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2080,6 +2126,8 @@ define void @s_shuffle_v3i64_v2i64__0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -2100,6 +2148,10 @@ define void @s_shuffle_v3i64_v2i64__1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2113,6 +2165,10 @@ define void @s_shuffle_v3i64_v2i64__1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2126,6 +2182,10 @@ define void @s_shuffle_v3i64_v2i64__1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2159,6 +2219,10 @@ define void @s_shuffle_v3i64_v2i64__3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2172,6 +2236,10 @@ define void @s_shuffle_v3i64_v2i64__3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2185,6 +2253,10 @@ define void @s_shuffle_v3i64_v2i64__3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2210,6 +2282,8 @@ define void @s_shuffle_v3i64_v2i64__3_0_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2228,6 +2302,8 @@ define void @s_shuffle_v3i64_v2i64__3_0_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2246,6 +2322,8 @@ define void @s_shuffle_v3i64_v2i64__3_0_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2269,6 +2347,8 @@ define void @s_shuffle_v3i64_v2i64__3_1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2285,6 +2365,8 @@ define void @s_shuffle_v3i64_v2i64__3_1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2301,6 +2383,8 @@ define void @s_shuffle_v3i64_v2i64__3_1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2323,6 +2407,8 @@ define void @s_shuffle_v3i64_v2i64__3_2_u() {
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2338,6 +2424,8 @@ define void @s_shuffle_v3i64_v2i64__3_2_u() {
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2353,6 +2441,8 @@ define void @s_shuffle_v3i64_v2i64__3_2_u() {
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2373,6 +2463,8 @@ define void @s_shuffle_v3i64_v2i64__3_3_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -2981,6 +3073,8 @@ define void @s_shuffle_v3i64_v2i64__3_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -2999,6 +3093,8 @@ define void @s_shuffle_v3i64_v2i64__3_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -3017,6 +3113,8 @@ define void @s_shuffle_v3i64_v2i64__3_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: s_mov_b32 s13, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -3185,6 +3283,8 @@ define void @s_shuffle_v3i64_v2i64__0_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -3196,6 +3296,8 @@ define void @s_shuffle_v3i64_v2i64__0_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -3207,6 +3309,8 @@ define void @s_shuffle_v3i64_v2i64__0_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -3227,6 +3331,10 @@ define void @s_shuffle_v3i64_v2i64__1_2_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -3240,6 +3348,10 @@ define void @s_shuffle_v3i64_v2i64__1_2_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -3253,6 +3365,10 @@ define void @s_shuffle_v3i64_v2i64__1_2_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -3574,6 +3690,8 @@ define void @s_shuffle_v3i64_v2i64__3_u_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -3589,6 +3707,8 @@ define void @s_shuffle_v3i64_v2i64__3_u_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -3604,6 +3724,8 @@ define void @s_shuffle_v3i64_v2i64__3_u_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: s_mov_b32 s13, s3
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
index 805ca205d89d5..44611c8b0c306 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v3i64.ll
@@ -65,6 +65,8 @@ define void @v_shuffle_v3i64_v3i64__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -76,6 +78,8 @@ define void @v_shuffle_v3i64_v3i64__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +91,8 @@ define void @v_shuffle_v3i64_v3i64__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -100,33 +106,39 @@ define void @v_shuffle_v3i64_v3i64__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v3i64__2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v3i64__2_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v3i64__2_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -154,6 +166,8 @@ define void @v_shuffle_v3i64_v3i64__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -165,6 +179,8 @@ define void @v_shuffle_v3i64_v3i64__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -176,6 +192,8 @@ define void @v_shuffle_v3i64_v3i64__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -190,33 +208,39 @@ define void @v_shuffle_v3i64_v3i64__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v3i64__5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v3i64__5_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v3i64__5_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -1189,6 +1213,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v12, v[6:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1204,6 +1230,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v12, v[6:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1219,6 +1247,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v12, v[6:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v12, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1806,6 +1836,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v10, v[6:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v10, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1821,6 +1853,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v10, v[6:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v10, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1837,6 +1871,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v10, v[6:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v10, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2420,6 +2456,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v8, v[6:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2435,6 +2473,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v8, v[6:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2451,6 +2491,8 @@ define void @v_shuffle_v3i64_v3i64__5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v8, v[6:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2745,6 +2787,8 @@ define void @v_shuffle_v3i64_v3i64__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2756,6 +2800,8 @@ define void @v_shuffle_v3i64_v3i64__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2767,6 +2813,8 @@ define void @v_shuffle_v3i64_v3i64__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2780,33 +2828,39 @@ define void @v_shuffle_v3i64_v3i64__2_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v3i64__2_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v3i64__2_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v3i64__2_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -2928,36 +2982,42 @@ define void @v_shuffle_v3i64_v3i64__5_u_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v3i64__5_u_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v3i64__5_u_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v3i64__5_u_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -3534,36 +3594,42 @@ define void @v_shuffle_v3i64_v3i64__5_u_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v3i64__5_u_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v6, v[2:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v3i64__5_u_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v6, v[2:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v3i64__5_u_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v6, v[2:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -4091,36 +4157,42 @@ define void @v_shuffle_v3i64_v3i64__5_u_5(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v3i64__5_u_5:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v6, v[4:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v3i64__5_u_5:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v6, v[4:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v3i64__5_u_5:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v6, v[4:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v8, v[4:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -4447,6 +4519,10 @@ define void @s_shuffle_v3i64_v3i64__1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4460,6 +4536,10 @@ define void @s_shuffle_v3i64_v3i64__1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4473,6 +4553,10 @@ define void @s_shuffle_v3i64_v3i64__1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -4490,6 +4574,10 @@ define void @s_shuffle_v3i64_v3i64__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4501,6 +4589,10 @@ define void @s_shuffle_v3i64_v3i64__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4512,6 +4604,10 @@ define void @s_shuffle_v3i64_v3i64__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -4546,6 +4642,10 @@ define void @s_shuffle_v3i64_v3i64__4_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4559,6 +4659,10 @@ define void @s_shuffle_v3i64_v3i64__4_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4572,6 +4676,10 @@ define void @s_shuffle_v3i64_v3i64__4_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -4590,6 +4698,10 @@ define void @s_shuffle_v3i64_v3i64__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4601,6 +4713,10 @@ define void @s_shuffle_v3i64_v3i64__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4612,6 +4728,10 @@ define void @s_shuffle_v3i64_v3i64__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -4636,6 +4756,8 @@ define void @s_shuffle_v3i64_v3i64__5_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4652,6 +4774,8 @@ define void @s_shuffle_v3i64_v3i64__5_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4668,6 +4792,8 @@ define void @s_shuffle_v3i64_v3i64__5_0_u() {
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -4689,6 +4815,8 @@ define void @s_shuffle_v3i64_v3i64__5_1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4703,6 +4831,8 @@ define void @s_shuffle_v3i64_v3i64__5_1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4714,6 +4844,8 @@ define void @s_shuffle_v3i64_v3i64__5_1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -4742,6 +4874,8 @@ define void @s_shuffle_v3i64_v3i64__5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4758,6 +4892,8 @@ define void @s_shuffle_v3i64_v3i64__5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4774,6 +4910,8 @@ define void @s_shuffle_v3i64_v3i64__5_2_u() {
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -4794,6 +4932,8 @@ define void @s_shuffle_v3i64_v3i64__5_3_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s4
; GFX9-NEXT: s_mov_b32 s11, s5
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -4814,6 +4954,8 @@ define void @s_shuffle_v3i64_v3i64__5_4_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s6
; GFX9-NEXT: s_mov_b32 s11, s7
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -4834,6 +4976,8 @@ define void @s_shuffle_v3i64_v3i64__5_5_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s8
; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -5598,13 +5742,15 @@ define void @s_shuffle_v3i64_v3i64__5_u_1() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[8:13]
+; GFX900-NEXT: ; def s[12:17]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s12, s10
-; GFX900-NEXT: s_mov_b32 s13, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: s_mov_b32 s12, s14
+; GFX900-NEXT: s_mov_b32 s13, s15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -5614,13 +5760,15 @@ define void @s_shuffle_v3i64_v3i64__5_u_1() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[8:13]
+; GFX90A-NEXT: ; def s[12:17]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s12, s10
-; GFX90A-NEXT: s_mov_b32 s13, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: s_mov_b32 s12, s14
+; GFX90A-NEXT: s_mov_b32 s13, s15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -5632,6 +5780,8 @@ define void @s_shuffle_v3i64_v3i64__5_u_1() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -6373,6 +6523,10 @@ define void @s_shuffle_v3i64_v3i64__1_3_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -6386,6 +6540,10 @@ define void @s_shuffle_v3i64_v3i64__1_3_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -6399,6 +6557,10 @@ define void @s_shuffle_v3i64_v3i64__1_3_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -6416,6 +6578,10 @@ define void @s_shuffle_v3i64_v3i64__2_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -6427,6 +6593,10 @@ define void @s_shuffle_v3i64_v3i64__2_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -6438,6 +6608,10 @@ define void @s_shuffle_v3i64_v3i64__2_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
index 7c38923e4836e..e1fb6b2a903bd 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i64.v4i64.ll
@@ -65,6 +65,8 @@ define void @v_shuffle_v3i64_v4i64__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -76,6 +78,8 @@ define void @v_shuffle_v3i64_v4i64__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +91,8 @@ define void @v_shuffle_v3i64_v4i64__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -104,6 +110,8 @@ define void @v_shuffle_v3i64_v4i64__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -115,6 +123,8 @@ define void @v_shuffle_v3i64_v4i64__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -126,6 +136,8 @@ define void @v_shuffle_v3i64_v4i64__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -139,33 +151,39 @@ define void @v_shuffle_v3i64_v4i64__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v4i64__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v4i64__3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v4i64__3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -193,6 +211,8 @@ define void @v_shuffle_v3i64_v4i64__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -204,6 +224,8 @@ define void @v_shuffle_v3i64_v4i64__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -215,6 +237,8 @@ define void @v_shuffle_v3i64_v4i64__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -233,6 +257,8 @@ define void @v_shuffle_v3i64_v4i64__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -244,6 +270,8 @@ define void @v_shuffle_v3i64_v4i64__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -255,6 +283,8 @@ define void @v_shuffle_v3i64_v4i64__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -269,33 +299,39 @@ define void @v_shuffle_v3i64_v4i64__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v4i64__7_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v4i64__7_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v4i64__7_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -1579,6 +1615,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v16, v[8:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1594,6 +1632,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v16, v[8:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1609,6 +1649,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v16, v[8:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2418,6 +2460,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v14, v[8:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v14, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2433,6 +2477,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v14, v[8:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v14, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2449,6 +2495,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v14, v[8:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v14, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3255,6 +3303,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v12, v[8:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -3270,6 +3320,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v12, v[8:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3286,6 +3338,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v12, v[8:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v12, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4087,6 +4141,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v10, v[8:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4102,6 +4158,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v10, v[8:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4118,6 +4176,8 @@ define void @v_shuffle_v3i64_v4i64__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v10, v[8:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4524,6 +4584,8 @@ define void @v_shuffle_v3i64_v4i64__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4535,6 +4597,8 @@ define void @v_shuffle_v3i64_v4i64__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4546,6 +4610,8 @@ define void @v_shuffle_v3i64_v4i64__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4563,6 +4629,8 @@ define void @v_shuffle_v3i64_v4i64__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4574,6 +4642,8 @@ define void @v_shuffle_v3i64_v4i64__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4585,6 +4655,8 @@ define void @v_shuffle_v3i64_v4i64__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4598,33 +4670,39 @@ define void @v_shuffle_v3i64_v4i64__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v4i64__3_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v4i64__3_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v4i64__3_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -4795,36 +4873,42 @@ define void @v_shuffle_v3i64_v4i64__7_u_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v4i64__7_u_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v4i64__7_u_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v4i64__7_u_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -5609,36 +5693,42 @@ define void @v_shuffle_v3i64_v4i64__7_u_5(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v4i64__7_u_5:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v10, v[2:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v4i64__7_u_5:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v10, v[2:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v4i64__7_u_5:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v10, v[2:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -6423,36 +6513,42 @@ define void @v_shuffle_v3i64_v4i64__7_u_6(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v4i64__7_u_6:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v10, v[4:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v4i64__7_u_6:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v10, v[4:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v4i64__7_u_6:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v8, v[4:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v10, v[4:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -7188,36 +7284,42 @@ define void @v_shuffle_v3i64_v4i64__7_u_7(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3i64_v4i64__7_u_7:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[6:7], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v10, v[6:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3i64_v4i64__7_u_7:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v8, v[6:7], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v10, v[6:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3i64_v4i64__7_u_7:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v8, v[6:7], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v10, v[6:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -7645,6 +7747,10 @@ define void @s_shuffle_v3i64_v4i64__1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7658,6 +7764,10 @@ define void @s_shuffle_v3i64_v4i64__1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7671,6 +7781,10 @@ define void @s_shuffle_v3i64_v4i64__1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -7688,6 +7802,10 @@ define void @s_shuffle_v3i64_v4i64__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7699,6 +7817,10 @@ define void @s_shuffle_v3i64_v4i64__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7710,6 +7832,10 @@ define void @s_shuffle_v3i64_v4i64__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -7730,6 +7856,10 @@ define void @s_shuffle_v3i64_v4i64__3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7743,6 +7873,10 @@ define void @s_shuffle_v3i64_v4i64__3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7756,6 +7890,10 @@ define void @s_shuffle_v3i64_v4i64__3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -7789,6 +7927,10 @@ define void @s_shuffle_v3i64_v4i64__5_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7802,6 +7944,10 @@ define void @s_shuffle_v3i64_v4i64__5_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7815,6 +7961,10 @@ define void @s_shuffle_v3i64_v4i64__5_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -7833,6 +7983,10 @@ define void @s_shuffle_v3i64_v4i64__6_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7844,6 +7998,10 @@ define void @s_shuffle_v3i64_v4i64__6_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7855,6 +8013,10 @@ define void @s_shuffle_v3i64_v4i64__6_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -7876,6 +8038,10 @@ define void @s_shuffle_v3i64_v4i64__7_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7889,6 +8055,10 @@ define void @s_shuffle_v3i64_v4i64__7_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7902,6 +8072,10 @@ define void @s_shuffle_v3i64_v4i64__7_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -7927,6 +8101,8 @@ define void @s_shuffle_v3i64_v4i64__7_0_u() {
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7945,6 +8121,8 @@ define void @s_shuffle_v3i64_v4i64__7_0_u() {
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7956,6 +8134,8 @@ define void @s_shuffle_v3i64_v4i64__7_0_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
@@ -7987,6 +8167,8 @@ define void @s_shuffle_v3i64_v4i64__7_1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8003,6 +8185,8 @@ define void @s_shuffle_v3i64_v4i64__7_1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8019,6 +8203,8 @@ define void @s_shuffle_v3i64_v4i64__7_1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -8044,6 +8230,8 @@ define void @s_shuffle_v3i64_v4i64__7_2_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8062,6 +8250,8 @@ define void @s_shuffle_v3i64_v4i64__7_2_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8080,6 +8270,8 @@ define void @s_shuffle_v3i64_v4i64__7_2_u() {
; GFX942-NEXT: s_mov_b32 s9, s15
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -8103,6 +8295,8 @@ define void @s_shuffle_v3i64_v4i64__7_3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8119,6 +8313,8 @@ define void @s_shuffle_v3i64_v4i64__7_3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8130,6 +8326,8 @@ define void @s_shuffle_v3i64_v4i64__7_3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
@@ -8158,6 +8356,8 @@ define void @s_shuffle_v3i64_v4i64__7_4_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8173,6 +8373,8 @@ define void @s_shuffle_v3i64_v4i64__7_4_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8188,6 +8390,8 @@ define void @s_shuffle_v3i64_v4i64__7_4_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -8208,6 +8412,8 @@ define void @s_shuffle_v3i64_v4i64__7_5_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s14
; GFX9-NEXT: s_mov_b32 s9, s15
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -8230,6 +8436,8 @@ define void @s_shuffle_v3i64_v4i64__7_6_u() {
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8245,6 +8453,8 @@ define void @s_shuffle_v3i64_v4i64__7_6_u() {
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8260,6 +8470,8 @@ define void @s_shuffle_v3i64_v4i64__7_6_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -8280,6 +8492,8 @@ define void @s_shuffle_v3i64_v4i64__7_7_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -9547,6 +9761,8 @@ define void @s_shuffle_v3i64_v4i64__7_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s14
; GFX900-NEXT: s_mov_b32 s9, s15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -9565,6 +9781,8 @@ define void @s_shuffle_v3i64_v4i64__7_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s14
; GFX90A-NEXT: s_mov_b32 s9, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -9584,6 +9802,8 @@ define void @s_shuffle_v3i64_v4i64__7_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s13, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -10977,15 +11197,17 @@ define void @s_shuffle_v3i64_v4i64__7_u_3() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[12:19]
+; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s18
-; GFX900-NEXT: s_mov_b32 s9, s19
-; GFX900-NEXT: s_mov_b32 s12, s10
-; GFX900-NEXT: s_mov_b32 s13, s11
+; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: s_mov_b32 s12, s14
+; GFX900-NEXT: s_mov_b32 s13, s15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -10995,15 +11217,17 @@ define void @s_shuffle_v3i64_v4i64__7_u_3() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[12:19]
+; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s18
-; GFX90A-NEXT: s_mov_b32 s9, s19
-; GFX90A-NEXT: s_mov_b32 s12, s10
-; GFX90A-NEXT: s_mov_b32 s13, s11
+; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: s_mov_b32 s12, s14
+; GFX90A-NEXT: s_mov_b32 s13, s15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -11020,6 +11244,8 @@ define void @s_shuffle_v3i64_v4i64__7_u_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s14
; GFX942-NEXT: s_mov_b32 s9, s15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s6
; GFX942-NEXT: s_mov_b32 s13, s7
; GFX942-NEXT: ;;#ASMSTART
@@ -11486,6 +11712,10 @@ define void @s_shuffle_v3i64_v4i64__1_4_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -11499,6 +11729,10 @@ define void @s_shuffle_v3i64_v4i64__1_4_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -11512,6 +11746,10 @@ define void @s_shuffle_v3i64_v4i64__1_4_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -11529,6 +11767,10 @@ define void @s_shuffle_v3i64_v4i64__2_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -11540,6 +11782,10 @@ define void @s_shuffle_v3i64_v4i64__2_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -11551,6 +11797,10 @@ define void @s_shuffle_v3i64_v4i64__2_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -11571,6 +11821,10 @@ define void @s_shuffle_v3i64_v4i64__3_4_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -11584,6 +11838,10 @@ define void @s_shuffle_v3i64_v4i64__3_4_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -11597,6 +11855,10 @@ define void @s_shuffle_v3i64_v4i64__3_4_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -12312,6 +12574,8 @@ define void @s_shuffle_v3i64_v4i64__7_u_5() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -12327,6 +12591,8 @@ define void @s_shuffle_v3i64_v4i64__7_u_5() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -12342,6 +12608,8 @@ define void @s_shuffle_v3i64_v4i64__7_u_5() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: s_mov_b32 s13, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -13759,12 +14027,14 @@ define void @s_shuffle_v3i64_v4i64__7_u_7() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s10
-; GFX900-NEXT: s_mov_b32 s9, s11
-; GFX900-NEXT: s_mov_b32 s12, s10
-; GFX900-NEXT: s_mov_b32 s13, s11
+; GFX900-NEXT: s_mov_b32 s8, s14
+; GFX900-NEXT: s_mov_b32 s9, s15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: s_mov_b32 s12, s14
+; GFX900-NEXT: s_mov_b32 s13, s15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -13774,12 +14044,14 @@ define void @s_shuffle_v3i64_v4i64__7_u_7() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s10
-; GFX90A-NEXT: s_mov_b32 s9, s11
-; GFX90A-NEXT: s_mov_b32 s12, s10
-; GFX90A-NEXT: s_mov_b32 s13, s11
+; GFX90A-NEXT: s_mov_b32 s8, s14
+; GFX90A-NEXT: s_mov_b32 s9, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: s_mov_b32 s12, s14
+; GFX90A-NEXT: s_mov_b32 s13, s15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -13793,6 +14065,8 @@ define void @s_shuffle_v3i64_v4i64__7_u_7() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s6
; GFX942-NEXT: s_mov_b32 s13, s7
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
index dfa64c4adfb9b..d0449c28cade6 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v2p0.ll
@@ -58,33 +58,39 @@ define void @v_shuffle_v3p0_v2p0__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v2p0__1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v2p0__1_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v2p0__1_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -108,33 +114,39 @@ define void @v_shuffle_v3p0_v2p0__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v2p0__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v2p0__3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v2p0__3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -796,6 +808,8 @@ define void @v_shuffle_v3p0_v2p0__3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -811,6 +825,8 @@ define void @v_shuffle_v3p0_v2p0__3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -826,6 +842,8 @@ define void @v_shuffle_v3p0_v2p0__3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v8, v[4:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1191,6 +1209,8 @@ define void @v_shuffle_v3p0_v2p0__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v6, v[4:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1206,6 +1226,8 @@ define void @v_shuffle_v3p0_v2p0__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v6, v[4:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1222,6 +1244,8 @@ define void @v_shuffle_v3p0_v2p0__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v6, v[4:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1397,33 +1421,39 @@ define void @v_shuffle_v3p0_v2p0__1_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v2p0__1_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v2p0__1_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v2p0__1_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -1496,36 +1526,42 @@ define void @v_shuffle_v3p0_v2p0__3_u_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v2p0__3_u_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v2p0__3_u_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v2p0__3_u_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -1845,36 +1881,42 @@ define void @v_shuffle_v3p0_v2p0__3_u_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v2p0__3_u_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v6, v[2:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v2p0__3_u_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v4, v[2:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v6, v[2:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v2p0__3_u_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v6, v[2:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -2058,6 +2100,8 @@ define void @s_shuffle_v3p0_v2p0__0_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2069,6 +2113,8 @@ define void @s_shuffle_v3p0_v2p0__0_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2080,6 +2126,8 @@ define void @s_shuffle_v3p0_v2p0__0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -2100,6 +2148,10 @@ define void @s_shuffle_v3p0_v2p0__1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2113,6 +2165,10 @@ define void @s_shuffle_v3p0_v2p0__1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2126,6 +2182,10 @@ define void @s_shuffle_v3p0_v2p0__1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2159,6 +2219,10 @@ define void @s_shuffle_v3p0_v2p0__3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2172,6 +2236,10 @@ define void @s_shuffle_v3p0_v2p0__3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2185,6 +2253,10 @@ define void @s_shuffle_v3p0_v2p0__3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2210,6 +2282,8 @@ define void @s_shuffle_v3p0_v2p0__3_0_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2228,6 +2302,8 @@ define void @s_shuffle_v3p0_v2p0__3_0_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2246,6 +2322,8 @@ define void @s_shuffle_v3p0_v2p0__3_0_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2269,6 +2347,8 @@ define void @s_shuffle_v3p0_v2p0__3_1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2285,6 +2365,8 @@ define void @s_shuffle_v3p0_v2p0__3_1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2301,6 +2383,8 @@ define void @s_shuffle_v3p0_v2p0__3_1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2323,6 +2407,8 @@ define void @s_shuffle_v3p0_v2p0__3_2_u() {
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -2338,6 +2424,8 @@ define void @s_shuffle_v3p0_v2p0__3_2_u() {
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -2353,6 +2441,8 @@ define void @s_shuffle_v3p0_v2p0__3_2_u() {
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -2373,6 +2463,8 @@ define void @s_shuffle_v3p0_v2p0__3_3_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -2981,6 +3073,8 @@ define void @s_shuffle_v3p0_v2p0__3_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -2999,6 +3093,8 @@ define void @s_shuffle_v3p0_v2p0__3_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -3017,6 +3113,8 @@ define void @s_shuffle_v3p0_v2p0__3_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: s_mov_b32 s13, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -3185,6 +3283,8 @@ define void @s_shuffle_v3p0_v2p0__0_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -3196,6 +3296,8 @@ define void @s_shuffle_v3p0_v2p0__0_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -3207,6 +3309,8 @@ define void @s_shuffle_v3p0_v2p0__0_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -3227,6 +3331,10 @@ define void @s_shuffle_v3p0_v2p0__1_2_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -3240,6 +3348,10 @@ define void @s_shuffle_v3p0_v2p0__1_2_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -3253,6 +3365,10 @@ define void @s_shuffle_v3p0_v2p0__1_2_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -3574,6 +3690,8 @@ define void @s_shuffle_v3p0_v2p0__3_u_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -3589,6 +3707,8 @@ define void @s_shuffle_v3p0_v2p0__3_u_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -3604,6 +3724,8 @@ define void @s_shuffle_v3p0_v2p0__3_u_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: s_mov_b32 s13, s3
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
index f67b580bccf33..92cd68b6e60fa 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v3p0.ll
@@ -65,6 +65,8 @@ define void @v_shuffle_v3p0_v3p0__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -76,6 +78,8 @@ define void @v_shuffle_v3p0_v3p0__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +91,8 @@ define void @v_shuffle_v3p0_v3p0__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -100,33 +106,39 @@ define void @v_shuffle_v3p0_v3p0__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v3p0__2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v3p0__2_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v3p0__2_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -154,6 +166,8 @@ define void @v_shuffle_v3p0_v3p0__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -165,6 +179,8 @@ define void @v_shuffle_v3p0_v3p0__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -176,6 +192,8 @@ define void @v_shuffle_v3p0_v3p0__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -190,33 +208,39 @@ define void @v_shuffle_v3p0_v3p0__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v3p0__5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v3p0__5_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v3p0__5_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -1189,6 +1213,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v12, v[6:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1204,6 +1230,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v12, v[6:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1219,6 +1247,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v12, v[6:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v12, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1806,6 +1836,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v10, v[6:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v10, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1821,6 +1853,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v10, v[6:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v10, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1837,6 +1871,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v10, v[6:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v10, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2420,6 +2456,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v8, v[6:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2435,6 +2473,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v8, v[6:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2451,6 +2491,8 @@ define void @v_shuffle_v3p0_v3p0__5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v8, v[6:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2745,6 +2787,8 @@ define void @v_shuffle_v3p0_v3p0__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2756,6 +2800,8 @@ define void @v_shuffle_v3p0_v3p0__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2767,6 +2813,8 @@ define void @v_shuffle_v3p0_v3p0__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2780,33 +2828,39 @@ define void @v_shuffle_v3p0_v3p0__2_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v3p0__2_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v3p0__2_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v3p0__2_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -2928,36 +2982,42 @@ define void @v_shuffle_v3p0_v3p0__5_u_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v3p0__5_u_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v3p0__5_u_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v6, v[0:1], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v3p0__5_u_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -3534,36 +3594,42 @@ define void @v_shuffle_v3p0_v3p0__5_u_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v3p0__5_u_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v6, v[2:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v3p0__5_u_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v6, v[2:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v3p0__5_u_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v6, v[2:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -4091,36 +4157,42 @@ define void @v_shuffle_v3p0_v3p0__5_u_5(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v3p0__5_u_5:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v6, v[4:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v3p0__5_u_5:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v6, v[4:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v3p0__5_u_5:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v6, v[4:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v8, v[4:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -4447,6 +4519,10 @@ define void @s_shuffle_v3p0_v3p0__1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4460,6 +4536,10 @@ define void @s_shuffle_v3p0_v3p0__1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4473,6 +4553,10 @@ define void @s_shuffle_v3p0_v3p0__1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -4490,6 +4574,10 @@ define void @s_shuffle_v3p0_v3p0__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4501,6 +4589,10 @@ define void @s_shuffle_v3p0_v3p0__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4512,6 +4604,10 @@ define void @s_shuffle_v3p0_v3p0__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -4546,6 +4642,10 @@ define void @s_shuffle_v3p0_v3p0__4_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4559,6 +4659,10 @@ define void @s_shuffle_v3p0_v3p0__4_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4572,6 +4676,10 @@ define void @s_shuffle_v3p0_v3p0__4_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -4590,6 +4698,10 @@ define void @s_shuffle_v3p0_v3p0__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4601,6 +4713,10 @@ define void @s_shuffle_v3p0_v3p0__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4612,6 +4728,10 @@ define void @s_shuffle_v3p0_v3p0__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -4636,6 +4756,8 @@ define void @s_shuffle_v3p0_v3p0__5_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4652,6 +4774,8 @@ define void @s_shuffle_v3p0_v3p0__5_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4668,6 +4792,8 @@ define void @s_shuffle_v3p0_v3p0__5_0_u() {
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -4689,6 +4815,8 @@ define void @s_shuffle_v3p0_v3p0__5_1_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4703,6 +4831,8 @@ define void @s_shuffle_v3p0_v3p0__5_1_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4714,6 +4844,8 @@ define void @s_shuffle_v3p0_v3p0__5_1_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -4742,6 +4874,8 @@ define void @s_shuffle_v3p0_v3p0__5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -4758,6 +4892,8 @@ define void @s_shuffle_v3p0_v3p0__5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -4774,6 +4910,8 @@ define void @s_shuffle_v3p0_v3p0__5_2_u() {
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -4794,6 +4932,8 @@ define void @s_shuffle_v3p0_v3p0__5_3_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s4
; GFX9-NEXT: s_mov_b32 s11, s5
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -4814,6 +4954,8 @@ define void @s_shuffle_v3p0_v3p0__5_4_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s6
; GFX9-NEXT: s_mov_b32 s11, s7
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -4834,6 +4976,8 @@ define void @s_shuffle_v3p0_v3p0__5_5_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s8
; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -5598,13 +5742,15 @@ define void @s_shuffle_v3p0_v3p0__5_u_1() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[8:13]
+; GFX900-NEXT: ; def s[12:17]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s12, s10
-; GFX900-NEXT: s_mov_b32 s13, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: s_mov_b32 s12, s14
+; GFX900-NEXT: s_mov_b32 s13, s15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -5614,13 +5760,15 @@ define void @s_shuffle_v3p0_v3p0__5_u_1() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[8:13]
+; GFX90A-NEXT: ; def s[12:17]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s12, s10
-; GFX90A-NEXT: s_mov_b32 s13, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: s_mov_b32 s12, s14
+; GFX90A-NEXT: s_mov_b32 s13, s15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -5632,6 +5780,8 @@ define void @s_shuffle_v3p0_v3p0__5_u_1() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -6373,6 +6523,10 @@ define void @s_shuffle_v3p0_v3p0__1_3_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -6386,6 +6540,10 @@ define void @s_shuffle_v3p0_v3p0__1_3_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -6399,6 +6557,10 @@ define void @s_shuffle_v3p0_v3p0__1_3_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -6416,6 +6578,10 @@ define void @s_shuffle_v3p0_v3p0__2_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -6427,6 +6593,10 @@ define void @s_shuffle_v3p0_v3p0__2_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -6438,6 +6608,10 @@ define void @s_shuffle_v3p0_v3p0__2_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
index b1708c4212e48..4763af6214027 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p0.v4p0.ll
@@ -65,6 +65,8 @@ define void @v_shuffle_v3p0_v4p0__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -76,6 +78,8 @@ define void @v_shuffle_v3p0_v4p0__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +91,8 @@ define void @v_shuffle_v3p0_v4p0__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -104,6 +110,8 @@ define void @v_shuffle_v3p0_v4p0__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -115,6 +123,8 @@ define void @v_shuffle_v3p0_v4p0__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -126,6 +136,8 @@ define void @v_shuffle_v3p0_v4p0__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -139,33 +151,39 @@ define void @v_shuffle_v3p0_v4p0__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v4p0__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v4p0__3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v4p0__3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -193,6 +211,8 @@ define void @v_shuffle_v3p0_v4p0__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -204,6 +224,8 @@ define void @v_shuffle_v3p0_v4p0__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -215,6 +237,8 @@ define void @v_shuffle_v3p0_v4p0__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -233,6 +257,8 @@ define void @v_shuffle_v3p0_v4p0__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -244,6 +270,8 @@ define void @v_shuffle_v3p0_v4p0__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -255,6 +283,8 @@ define void @v_shuffle_v3p0_v4p0__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -269,33 +299,39 @@ define void @v_shuffle_v3p0_v4p0__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v4p0__7_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v4p0__7_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v4p0__7_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -1579,6 +1615,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v16, v[8:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1594,6 +1632,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v16, v[8:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1609,6 +1649,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v16, v[8:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2418,6 +2460,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v14, v[8:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v14, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2433,6 +2477,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v14, v[8:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v14, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2449,6 +2495,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v14, v[8:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v14, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3255,6 +3303,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v12, v[8:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -3270,6 +3320,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v12, v[8:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3286,6 +3338,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v12, v[8:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v12, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4087,6 +4141,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx2 v10, v[8:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4102,6 +4158,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx2 v10, v[8:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4118,6 +4176,8 @@ define void @v_shuffle_v3p0_v4p0__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx2 v10, v[8:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4524,6 +4584,8 @@ define void @v_shuffle_v3p0_v4p0__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4535,6 +4597,8 @@ define void @v_shuffle_v3p0_v4p0__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4546,6 +4610,8 @@ define void @v_shuffle_v3p0_v4p0__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4563,6 +4629,8 @@ define void @v_shuffle_v3p0_v4p0__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4574,6 +4642,8 @@ define void @v_shuffle_v3p0_v4p0__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4585,6 +4655,8 @@ define void @v_shuffle_v3p0_v4p0__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4598,33 +4670,39 @@ define void @v_shuffle_v3p0_v4p0__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v4p0__3_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v4p0__3_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v4p0__3_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -4795,36 +4873,42 @@ define void @v_shuffle_v3p0_v4p0__7_u_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v4p0__7_u_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v4p0__7_u_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v10, v[0:1], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v4p0__7_u_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v8, v[0:1], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -5609,36 +5693,42 @@ define void @v_shuffle_v3p0_v4p0__7_u_5(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v4p0__7_u_5:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v10, v[2:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v4p0__7_u_5:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v8, v[2:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v10, v[2:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v4p0__7_u_5:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v8, v[2:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v10, v[2:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -6423,36 +6513,42 @@ define void @v_shuffle_v3p0_v4p0__7_u_6(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v4p0__7_u_6:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v10, v[4:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v4p0__7_u_6:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v8, v[4:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v10, v[4:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v4p0__7_u_6:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v8, v[4:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v10, v[4:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -7188,36 +7284,42 @@ define void @v_shuffle_v3p0_v4p0__7_u_7(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p0_v4p0__7_u_7:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v8, v[6:7], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx2 v10, v[6:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p0_v4p0__7_u_7:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v8, v[6:7], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx2 v10, v[6:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p0_v4p0__7_u_7:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v8, v[6:7], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx2 v10, v[6:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -7645,6 +7747,10 @@ define void @s_shuffle_v3p0_v4p0__1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7658,6 +7764,10 @@ define void @s_shuffle_v3p0_v4p0__1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7671,6 +7781,10 @@ define void @s_shuffle_v3p0_v4p0__1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -7688,6 +7802,10 @@ define void @s_shuffle_v3p0_v4p0__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7699,6 +7817,10 @@ define void @s_shuffle_v3p0_v4p0__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7710,6 +7832,10 @@ define void @s_shuffle_v3p0_v4p0__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -7730,6 +7856,10 @@ define void @s_shuffle_v3p0_v4p0__3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7743,6 +7873,10 @@ define void @s_shuffle_v3p0_v4p0__3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7756,6 +7890,10 @@ define void @s_shuffle_v3p0_v4p0__3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -7789,6 +7927,10 @@ define void @s_shuffle_v3p0_v4p0__5_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7802,6 +7944,10 @@ define void @s_shuffle_v3p0_v4p0__5_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7815,6 +7961,10 @@ define void @s_shuffle_v3p0_v4p0__5_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -7833,6 +7983,10 @@ define void @s_shuffle_v3p0_v4p0__6_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7844,6 +7998,10 @@ define void @s_shuffle_v3p0_v4p0__6_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7855,6 +8013,10 @@ define void @s_shuffle_v3p0_v4p0__6_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -7876,6 +8038,10 @@ define void @s_shuffle_v3p0_v4p0__7_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7889,6 +8055,10 @@ define void @s_shuffle_v3p0_v4p0__7_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7902,6 +8072,10 @@ define void @s_shuffle_v3p0_v4p0__7_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -7927,6 +8101,8 @@ define void @s_shuffle_v3p0_v4p0__7_0_u() {
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -7945,6 +8121,8 @@ define void @s_shuffle_v3p0_v4p0__7_0_u() {
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -7956,6 +8134,8 @@ define void @s_shuffle_v3p0_v4p0__7_0_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
@@ -7987,6 +8167,8 @@ define void @s_shuffle_v3p0_v4p0__7_1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8003,6 +8185,8 @@ define void @s_shuffle_v3p0_v4p0__7_1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8019,6 +8203,8 @@ define void @s_shuffle_v3p0_v4p0__7_1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -8044,6 +8230,8 @@ define void @s_shuffle_v3p0_v4p0__7_2_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8062,6 +8250,8 @@ define void @s_shuffle_v3p0_v4p0__7_2_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8080,6 +8270,8 @@ define void @s_shuffle_v3p0_v4p0__7_2_u() {
; GFX942-NEXT: s_mov_b32 s9, s15
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -8103,6 +8295,8 @@ define void @s_shuffle_v3p0_v4p0__7_3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8119,6 +8313,8 @@ define void @s_shuffle_v3p0_v4p0__7_3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8130,6 +8326,8 @@ define void @s_shuffle_v3p0_v4p0__7_3_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
@@ -8158,6 +8356,8 @@ define void @s_shuffle_v3p0_v4p0__7_4_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8173,6 +8373,8 @@ define void @s_shuffle_v3p0_v4p0__7_4_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8188,6 +8390,8 @@ define void @s_shuffle_v3p0_v4p0__7_4_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -8208,6 +8412,8 @@ define void @s_shuffle_v3p0_v4p0__7_5_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s14
; GFX9-NEXT: s_mov_b32 s9, s15
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -8230,6 +8436,8 @@ define void @s_shuffle_v3p0_v4p0__7_6_u() {
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -8245,6 +8453,8 @@ define void @s_shuffle_v3p0_v4p0__7_6_u() {
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -8260,6 +8470,8 @@ define void @s_shuffle_v3p0_v4p0__7_6_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -8280,6 +8492,8 @@ define void @s_shuffle_v3p0_v4p0__7_7_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:13]
; GFX9-NEXT: ;;#ASMEND
@@ -9547,6 +9761,8 @@ define void @s_shuffle_v3p0_v4p0__7_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s14
; GFX900-NEXT: s_mov_b32 s9, s15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -9565,6 +9781,8 @@ define void @s_shuffle_v3p0_v4p0__7_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s14
; GFX90A-NEXT: s_mov_b32 s9, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -9584,6 +9802,8 @@ define void @s_shuffle_v3p0_v4p0__7_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s13, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -10977,15 +11197,17 @@ define void @s_shuffle_v3p0_v4p0__7_u_3() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[12:19]
+; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s18
-; GFX900-NEXT: s_mov_b32 s9, s19
-; GFX900-NEXT: s_mov_b32 s12, s10
-; GFX900-NEXT: s_mov_b32 s13, s11
+; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: s_mov_b32 s12, s14
+; GFX900-NEXT: s_mov_b32 s13, s15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -10995,15 +11217,17 @@ define void @s_shuffle_v3p0_v4p0__7_u_3() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[12:19]
+; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s18
-; GFX90A-NEXT: s_mov_b32 s9, s19
-; GFX90A-NEXT: s_mov_b32 s12, s10
-; GFX90A-NEXT: s_mov_b32 s13, s11
+; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: s_mov_b32 s12, s14
+; GFX90A-NEXT: s_mov_b32 s13, s15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -11020,6 +11244,8 @@ define void @s_shuffle_v3p0_v4p0__7_u_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s14
; GFX942-NEXT: s_mov_b32 s9, s15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s6
; GFX942-NEXT: s_mov_b32 s13, s7
; GFX942-NEXT: ;;#ASMSTART
@@ -11486,6 +11712,10 @@ define void @s_shuffle_v3p0_v4p0__1_4_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -11499,6 +11729,10 @@ define void @s_shuffle_v3p0_v4p0__1_4_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -11512,6 +11746,10 @@ define void @s_shuffle_v3p0_v4p0__1_4_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -11529,6 +11767,10 @@ define void @s_shuffle_v3p0_v4p0__2_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -11540,6 +11782,10 @@ define void @s_shuffle_v3p0_v4p0__2_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -11551,6 +11797,10 @@ define void @s_shuffle_v3p0_v4p0__2_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
@@ -11571,6 +11821,10 @@ define void @s_shuffle_v3p0_v4p0__3_4_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -11584,6 +11838,10 @@ define void @s_shuffle_v3p0_v4p0__3_4_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -11597,6 +11855,10 @@ define void @s_shuffle_v3p0_v4p0__3_4_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:13]
; GFX942-NEXT: ;;#ASMEND
@@ -12312,6 +12574,8 @@ define void @s_shuffle_v3p0_v4p0__7_u_5() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -12327,6 +12591,8 @@ define void @s_shuffle_v3p0_v4p0__7_u_5() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -12342,6 +12608,8 @@ define void @s_shuffle_v3p0_v4p0__7_u_5() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: s_mov_b32 s13, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -13759,12 +14027,14 @@ define void @s_shuffle_v3p0_v4p0__7_u_7() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[8:15]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s10
-; GFX900-NEXT: s_mov_b32 s9, s11
-; GFX900-NEXT: s_mov_b32 s12, s10
-; GFX900-NEXT: s_mov_b32 s13, s11
+; GFX900-NEXT: s_mov_b32 s8, s14
+; GFX900-NEXT: s_mov_b32 s9, s15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: s_mov_b32 s12, s14
+; GFX900-NEXT: s_mov_b32 s13, s15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:13]
; GFX900-NEXT: ;;#ASMEND
@@ -13774,12 +14044,14 @@ define void @s_shuffle_v3p0_v4p0__7_u_7() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s10
-; GFX90A-NEXT: s_mov_b32 s9, s11
-; GFX90A-NEXT: s_mov_b32 s12, s10
-; GFX90A-NEXT: s_mov_b32 s13, s11
+; GFX90A-NEXT: s_mov_b32 s8, s14
+; GFX90A-NEXT: s_mov_b32 s9, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: s_mov_b32 s12, s14
+; GFX90A-NEXT: s_mov_b32 s13, s15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:13]
; GFX90A-NEXT: ;;#ASMEND
@@ -13793,6 +14065,8 @@ define void @s_shuffle_v3p0_v4p0__7_u_7() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s12, s6
; GFX942-NEXT: s_mov_b32 s13, s7
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
index db1cf9faff8ec..39d599b6903cb 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v2p3.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v3p3_v2p3__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v2p3__0_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v2p3__0_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v2p3__0_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -58,35 +61,42 @@ define void @v_shuffle_v3p3_v2p3__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v2p3__1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v2p3__1_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v2p3__1_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -110,35 +120,42 @@ define void @v_shuffle_v3p3_v2p3__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v2p3__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v2p3__3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v2p3__3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -159,6 +176,7 @@ define void @v_shuffle_v3p3_v2p3__3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -166,32 +184,35 @@ define void @v_shuffle_v3p3_v2p3__3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3p3_v2p3__3_0_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
-; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ;;#ASMSTART
+; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v2p3__3_0_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:3]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def v[2:3]
+; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v0
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -205,14 +226,15 @@ define void @v_shuffle_v3p3_v2p3__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v2p3__3_1_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -227,6 +249,7 @@ define void @v_shuffle_v3p3_v2p3__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -241,6 +264,7 @@ define void @v_shuffle_v3p3_v2p3__3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
@@ -257,12 +281,13 @@ define void @v_shuffle_v3p3_v2p3__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v2p3__3_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v0
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -275,6 +300,7 @@ define void @v_shuffle_v3p3_v2p3__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -286,6 +312,7 @@ define void @v_shuffle_v3p3_v2p3__3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v0
@@ -303,12 +330,13 @@ define void @v_shuffle_v3p3_v2p3__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v2p3__3_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -318,9 +346,10 @@ define void @v_shuffle_v3p3_v2p3__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -330,9 +359,10 @@ define void @v_shuffle_v3p3_v2p3__3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1178,32 +1208,35 @@ define void @v_shuffle_v3p3_v2p3__3_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3p3_v2p3__3_u_1:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v8, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v2p3__3_u_1:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v8, v1
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1341,33 +1374,36 @@ define void @v_shuffle_v3p3_v2p3__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v2p3__0_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v2p3__0_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v2p3__0_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1380,35 +1416,42 @@ define void @v_shuffle_v3p3_v2p3__1_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v2p3__1_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v2, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v2p3__1_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx3 v2, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v2p3__1_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx3 v2, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v2, v[4:6], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1845,6 +1888,7 @@ define void @v_shuffle_v3p3_v2p3__3_u_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v6, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx3 v2, v[4:6], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1856,6 +1900,7 @@ define void @v_shuffle_v3p3_v2p3__3_u_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v6, v1
@@ -2050,6 +2095,7 @@ define void @s_shuffle_v3p3_v2p3__0_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2061,6 +2107,7 @@ define void @s_shuffle_v3p3_v2p3__0_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2072,6 +2119,7 @@ define void @s_shuffle_v3p3_v2p3__0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2090,6 +2138,8 @@ define void @s_shuffle_v3p3_v2p3__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2102,6 +2152,8 @@ define void @s_shuffle_v3p3_v2p3__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2114,6 +2166,8 @@ define void @s_shuffle_v3p3_v2p3__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2146,6 +2200,8 @@ define void @s_shuffle_v3p3_v2p3__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2158,6 +2214,8 @@ define void @s_shuffle_v3p3_v2p3__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2170,6 +2228,8 @@ define void @s_shuffle_v3p3_v2p3__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -2194,6 +2254,7 @@ define void @s_shuffle_v3p3_v2p3__3_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2210,6 +2271,7 @@ define void @s_shuffle_v3p3_v2p3__3_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2226,6 +2288,7 @@ define void @s_shuffle_v3p3_v2p3__3_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2248,6 +2311,7 @@ define void @s_shuffle_v3p3_v2p3__3_1_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2263,6 +2327,7 @@ define void @s_shuffle_v3p3_v2p3__3_1_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2278,6 +2343,7 @@ define void @s_shuffle_v3p3_v2p3__3_1_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2298,6 +2364,7 @@ define void @s_shuffle_v3p3_v2p3__3_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -2311,6 +2378,7 @@ define void @s_shuffle_v3p3_v2p3__3_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -2324,6 +2392,7 @@ define void @s_shuffle_v3p3_v2p3__3_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -2342,6 +2411,7 @@ define void @s_shuffle_v3p3_v2p3__3_3_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
@@ -2901,6 +2971,7 @@ define void @s_shuffle_v3p3_v2p3__3_u_1() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -2917,6 +2988,7 @@ define void @s_shuffle_v3p3_v2p3__3_u_1() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -2933,6 +3005,7 @@ define void @s_shuffle_v3p3_v2p3__3_u_1() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3082,6 +3155,7 @@ define void @s_shuffle_v3p3_v2p3__0_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -3093,6 +3167,7 @@ define void @s_shuffle_v3p3_v2p3__0_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -3104,6 +3179,7 @@ define void @s_shuffle_v3p3_v2p3__0_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3122,6 +3198,8 @@ define void @s_shuffle_v3p3_v2p3__1_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -3134,6 +3212,8 @@ define void @s_shuffle_v3p3_v2p3__1_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -3146,6 +3226,8 @@ define void @s_shuffle_v3p3_v2p3__1_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -3442,6 +3524,7 @@ define void @s_shuffle_v3p3_v2p3__3_u_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -3455,6 +3538,7 @@ define void @s_shuffle_v3p3_v2p3__3_u_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -3468,6 +3552,7 @@ define void @s_shuffle_v3p3_v2p3__3_u_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
index cbcb0b64e2ef8..7bc6866aadfa7 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v3p3.ll
@@ -58,11 +58,13 @@ define void @v_shuffle_v3p3_v3p3__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +76,8 @@ define void @v_shuffle_v3p3_v3p3__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +90,8 @@ define void @v_shuffle_v3p3_v3p3__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +105,39 @@ define void @v_shuffle_v3p3_v3p3__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v3p3__2_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v3p3__2_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -149,11 +161,13 @@ define void @v_shuffle_v3p3_v3p3__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -165,6 +179,8 @@ define void @v_shuffle_v3p3_v3p3__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -177,6 +193,8 @@ define void @v_shuffle_v3p3_v3p3__4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -191,33 +209,39 @@ define void @v_shuffle_v3p3_v3p3__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v3p3__5_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v3p3__5_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -238,6 +262,7 @@ define void @v_shuffle_v3p3_v3p3__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -253,6 +278,7 @@ define void @v_shuffle_v3p3_v3p3__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v7, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -269,6 +295,7 @@ define void @v_shuffle_v3p3_v3p3__5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx3 v7, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -290,6 +317,7 @@ define void @v_shuffle_v3p3_v3p3__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -304,6 +332,7 @@ define void @v_shuffle_v3p3_v3p3__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -315,6 +344,7 @@ define void @v_shuffle_v3p3_v3p3__5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -333,14 +363,15 @@ define void @v_shuffle_v3p3_v3p3__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__5_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -355,6 +386,7 @@ define void @v_shuffle_v3p3_v3p3__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -370,6 +402,7 @@ define void @v_shuffle_v3p3_v3p3__5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -384,37 +417,40 @@ define void @v_shuffle_v3p3_v3p3__5_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__5_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v3p3__5_3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v3p3__5_3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -428,37 +464,40 @@ define void @v_shuffle_v3p3_v3p3__5_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__5_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v3p3__5_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v3p3__5_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -472,37 +511,40 @@ define void @v_shuffle_v3p3_v3p3__5_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__5_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v3p3__5_5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v3p3__5_5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1747,14 +1789,15 @@ define void @v_shuffle_v3p3_v3p3__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:4]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
-; GFX90A-NEXT: v_mov_b32_e32 v4, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, v5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx3 v7, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1762,14 +1805,15 @@ define void @v_shuffle_v3p3_v3p3__5_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:4]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
-; GFX942-NEXT: v_mov_b32_e32 v4, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx3 v7, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -2630,11 +2674,13 @@ define void @v_shuffle_v3p3_v3p3__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__1_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[1:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2646,6 +2692,8 @@ define void @v_shuffle_v3p3_v3p3__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2658,6 +2706,8 @@ define void @v_shuffle_v3p3_v3p3__1_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2671,33 +2721,39 @@ define void @v_shuffle_v3p3_v3p3__2_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v3p3__2_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v3p3__2_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v3, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v3p3__2_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v3, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -4316,6 +4372,8 @@ define void @s_shuffle_v3p3_v3p3__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4328,6 +4386,8 @@ define void @s_shuffle_v3p3_v3p3__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4340,6 +4400,8 @@ define void @s_shuffle_v3p3_v3p3__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4358,6 +4420,8 @@ define void @s_shuffle_v3p3_v3p3__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4370,6 +4434,8 @@ define void @s_shuffle_v3p3_v3p3__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4382,6 +4448,8 @@ define void @s_shuffle_v3p3_v3p3__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4414,6 +4482,8 @@ define void @s_shuffle_v3p3_v3p3__4_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4426,6 +4496,8 @@ define void @s_shuffle_v3p3_v3p3__4_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4438,6 +4510,8 @@ define void @s_shuffle_v3p3_v3p3__4_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4457,6 +4531,8 @@ define void @s_shuffle_v3p3_v3p3__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -4469,6 +4545,8 @@ define void @s_shuffle_v3p3_v3p3__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -4481,6 +4559,8 @@ define void @s_shuffle_v3p3_v3p3__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -4505,6 +4585,7 @@ define void @s_shuffle_v3p3_v3p3__5_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4521,6 +4602,7 @@ define void @s_shuffle_v3p3_v3p3__5_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4537,6 +4619,7 @@ define void @s_shuffle_v3p3_v3p3__5_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4559,6 +4642,7 @@ define void @s_shuffle_v3p3_v3p3__5_1_u() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4574,6 +4658,7 @@ define void @s_shuffle_v3p3_v3p3__5_1_u() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4589,6 +4674,7 @@ define void @s_shuffle_v3p3_v3p3__5_1_u() {
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4612,6 +4698,7 @@ define void @s_shuffle_v3p3_v3p3__5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4628,6 +4715,7 @@ define void @s_shuffle_v3p3_v3p3__5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4644,6 +4732,7 @@ define void @s_shuffle_v3p3_v3p3__5_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4664,6 +4753,7 @@ define void @s_shuffle_v3p3_v3p3__5_3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4677,6 +4767,7 @@ define void @s_shuffle_v3p3_v3p3__5_3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4690,6 +4781,7 @@ define void @s_shuffle_v3p3_v3p3__5_3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -4709,6 +4801,7 @@ define void @s_shuffle_v3p3_v3p3__5_4_u() {
; GFX9-NEXT: ; def s[8:10]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
; GFX9-NEXT: ;;#ASMEND
@@ -4729,6 +4822,7 @@ define void @s_shuffle_v3p3_v3p3__5_5_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -4742,6 +4836,7 @@ define void @s_shuffle_v3p3_v3p3__5_5_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -4755,6 +4850,7 @@ define void @s_shuffle_v3p3_v3p3__5_5_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -5062,6 +5158,7 @@ define void @s_shuffle_v3p3_v3p3__u_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -5075,6 +5172,7 @@ define void @s_shuffle_v3p3_v3p3__u_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -5088,6 +5186,7 @@ define void @s_shuffle_v3p3_v3p3__u_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -5222,6 +5321,7 @@ define void @s_shuffle_v3p3_v3p3__3_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -5235,6 +5335,7 @@ define void @s_shuffle_v3p3_v3p3__3_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -5248,6 +5349,7 @@ define void @s_shuffle_v3p3_v3p3__3_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -5387,6 +5489,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_0() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -5403,6 +5506,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_0() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -5419,6 +5523,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_0() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -5873,6 +5978,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_1() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -5889,6 +5995,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_1() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -5905,6 +6012,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_1() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6681,6 +6789,8 @@ define void @s_shuffle_v3p3_v3p3__1_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -6693,6 +6803,8 @@ define void @s_shuffle_v3p3_v3p3__1_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -6705,6 +6817,8 @@ define void @s_shuffle_v3p3_v3p3__1_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6723,6 +6837,8 @@ define void @s_shuffle_v3p3_v3p3__2_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -6735,6 +6851,8 @@ define void @s_shuffle_v3p3_v3p3__2_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -6747,6 +6865,8 @@ define void @s_shuffle_v3p3_v3p3__2_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -6877,6 +6997,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -6890,6 +7011,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -6903,6 +7025,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -7386,6 +7509,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -7399,6 +7523,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -7412,6 +7537,7 @@ define void @s_shuffle_v3p3_v3p3__5_u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
index 6127b40404f5e..7b7d98c3d0ca5 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3p3.v4p3.ll
@@ -62,6 +62,8 @@ define void @v_shuffle_v3p3_v4p3__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -74,6 +76,8 @@ define void @v_shuffle_v3p3_v4p3__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +90,8 @@ define void @v_shuffle_v3p3_v4p3__1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +105,39 @@ define void @v_shuffle_v3p3_v4p3__2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v4p3__2_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v4p3__2_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -138,11 +150,13 @@ define void @v_shuffle_v3p3_v4p3__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +168,8 @@ define void @v_shuffle_v3p3_v4p3__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +182,8 @@ define void @v_shuffle_v3p3_v4p3__3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -194,6 +212,8 @@ define void @v_shuffle_v3p3_v4p3__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -206,6 +226,8 @@ define void @v_shuffle_v3p3_v4p3__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +240,8 @@ define void @v_shuffle_v3p3_v4p3__5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -232,33 +256,39 @@ define void @v_shuffle_v3p3_v4p3__6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__6_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v4p3__6_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v4p3__6_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -272,11 +302,13 @@ define void @v_shuffle_v3p3_v4p3__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__7_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +320,8 @@ define void @v_shuffle_v3p3_v4p3__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +334,8 @@ define void @v_shuffle_v3p3_v4p3__7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -321,6 +357,7 @@ define void @v_shuffle_v3p3_v4p3__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v8, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -337,6 +374,7 @@ define void @v_shuffle_v3p3_v4p3__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v5
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -351,6 +389,7 @@ define void @v_shuffle_v3p3_v4p3__7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v5
; GFX942-NEXT: v_mov_b32_e32 v3, v0
@@ -375,6 +414,7 @@ define void @v_shuffle_v3p3_v4p3__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v7, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -390,6 +430,7 @@ define void @v_shuffle_v3p3_v4p3__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v6, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -404,6 +445,7 @@ define void @v_shuffle_v3p3_v4p3__7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
; GFX942-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1]
@@ -427,6 +469,7 @@ define void @v_shuffle_v3p3_v4p3__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -443,6 +486,7 @@ define void @v_shuffle_v3p3_v4p3__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v8, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -459,6 +503,7 @@ define void @v_shuffle_v3p3_v4p3__7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v1, v2
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v8, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -473,14 +518,15 @@ define void @v_shuffle_v3p3_v4p3__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__7_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -495,6 +541,7 @@ define void @v_shuffle_v3p3_v4p3__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr4
; GFX90A-NEXT: global_store_dwordx3 v8, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -509,6 +556,7 @@ define void @v_shuffle_v3p3_v4p3__7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v7
; GFX942-NEXT: global_store_dwordx3 v8, v[2:4], s[0:1]
@@ -525,38 +573,42 @@ define void @v_shuffle_v3p3_v4p3__7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__7_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v4p3__7_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v4p3__7_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v0
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -570,12 +622,13 @@ define void @v_shuffle_v3p3_v4p3__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__7_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -587,6 +640,7 @@ define void @v_shuffle_v3p3_v4p3__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -599,6 +653,7 @@ define void @v_shuffle_v3p3_v4p3__7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -613,12 +668,13 @@ define void @v_shuffle_v3p3_v4p3__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__7_6_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -631,6 +687,7 @@ define void @v_shuffle_v3p3_v4p3__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -644,6 +701,7 @@ define void @v_shuffle_v3p3_v4p3__7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v2
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -658,12 +716,13 @@ define void @v_shuffle_v3p3_v4p3__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__7_7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx3 v5, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -673,9 +732,10 @@ define void @v_shuffle_v3p3_v4p3__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -685,9 +745,10 @@ define void @v_shuffle_v3p3_v4p3__7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -2355,9 +2416,10 @@ define void @v_shuffle_v3p3_v4p3__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v5
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v6, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v2, v5
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx3 v6, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2371,10 +2433,11 @@ define void @v_shuffle_v3p3_v4p3__7_u_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v5
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v2, v5
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx3 v6, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -3971,6 +4034,7 @@ define void @v_shuffle_v3p3_v4p3__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v7
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx3 v8, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3987,6 +4051,7 @@ define void @v_shuffle_v3p3_v4p3__7_u_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v0, v7
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx3 v8, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4386,6 +4451,8 @@ define void @v_shuffle_v3p3_v4p3__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
; GFX900-NEXT: global_store_dwordx3 v4, v[1:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4398,6 +4465,8 @@ define void @v_shuffle_v3p3_v4p3__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4410,6 +4479,8 @@ define void @v_shuffle_v3p3_v4p3__1_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4423,33 +4494,39 @@ define void @v_shuffle_v3p3_v4p3__2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__2_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v3p3_v4p3__2_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v5, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx3 v4, v[2:4], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx3 v5, v[2:4], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v4p3__2_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v5, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx3 v4, v[2:4], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx3 v5, v[2:4], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -4462,11 +4539,13 @@ define void @v_shuffle_v3p3_v4p3__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v3p3_v4p3__3_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx3 v4, v[3:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx3 v6, v[3:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -4478,6 +4557,8 @@ define void @v_shuffle_v3p3_v4p3__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4490,6 +4571,8 @@ define void @v_shuffle_v3p3_v4p3__3_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -5461,26 +5544,29 @@ define void @v_shuffle_v3p3_v4p3__7_u_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v3p3_v4p3__7_u_5:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v8, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx3 v4, v[6:8], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v3p3_v4p3__7_u_5:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v8, v1
+; GFX942-NEXT: global_store_dwordx3 v4, v[6:8], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -7031,6 +7117,7 @@ define void @v_shuffle_v3p3_v4p3__7_u_7(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx3 v4, v[0:2], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7044,6 +7131,7 @@ define void @v_shuffle_v3p3_v4p3__7_u_7(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx3 v4, v[0:2], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7480,6 +7568,8 @@ define void @s_shuffle_v3p3_v4p3__1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7492,6 +7582,8 @@ define void @s_shuffle_v3p3_v4p3__1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7504,6 +7596,8 @@ define void @s_shuffle_v3p3_v4p3__1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7522,6 +7616,8 @@ define void @s_shuffle_v3p3_v4p3__2_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7534,6 +7630,8 @@ define void @s_shuffle_v3p3_v4p3__2_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7546,6 +7644,8 @@ define void @s_shuffle_v3p3_v4p3__2_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7564,6 +7664,8 @@ define void @s_shuffle_v3p3_v4p3__3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7576,6 +7678,8 @@ define void @s_shuffle_v3p3_v4p3__3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7588,6 +7692,8 @@ define void @s_shuffle_v3p3_v4p3__3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7620,6 +7726,8 @@ define void @s_shuffle_v3p3_v4p3__5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7632,6 +7740,8 @@ define void @s_shuffle_v3p3_v4p3__5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7644,6 +7754,8 @@ define void @s_shuffle_v3p3_v4p3__5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7663,6 +7775,8 @@ define void @s_shuffle_v3p3_v4p3__6_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7675,6 +7789,8 @@ define void @s_shuffle_v3p3_v4p3__6_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7687,6 +7803,8 @@ define void @s_shuffle_v3p3_v4p3__6_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7706,6 +7824,8 @@ define void @s_shuffle_v3p3_v4p3__7_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -7718,6 +7838,8 @@ define void @s_shuffle_v3p3_v4p3__7_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -7730,6 +7852,8 @@ define void @s_shuffle_v3p3_v4p3__7_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -7754,6 +7878,7 @@ define void @s_shuffle_v3p3_v4p3__7_0_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7770,6 +7895,7 @@ define void @s_shuffle_v3p3_v4p3__7_0_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7786,6 +7912,7 @@ define void @s_shuffle_v3p3_v4p3__7_0_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7808,6 +7935,7 @@ define void @s_shuffle_v3p3_v4p3__7_1_u() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7823,6 +7951,7 @@ define void @s_shuffle_v3p3_v4p3__7_1_u() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7838,6 +7967,7 @@ define void @s_shuffle_v3p3_v4p3__7_1_u() {
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7861,6 +7991,7 @@ define void @s_shuffle_v3p3_v4p3__7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7877,6 +8008,7 @@ define void @s_shuffle_v3p3_v4p3__7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7893,6 +8025,7 @@ define void @s_shuffle_v3p3_v4p3__7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7916,6 +8049,7 @@ define void @s_shuffle_v3p3_v4p3__7_3_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7932,6 +8066,7 @@ define void @s_shuffle_v3p3_v4p3__7_3_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7948,6 +8083,7 @@ define void @s_shuffle_v3p3_v4p3__7_3_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -7968,6 +8104,7 @@ define void @s_shuffle_v3p3_v4p3__7_4_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -7981,6 +8118,7 @@ define void @s_shuffle_v3p3_v4p3__7_4_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -7994,6 +8132,7 @@ define void @s_shuffle_v3p3_v4p3__7_4_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8013,6 +8152,7 @@ define void @s_shuffle_v3p3_v4p3__7_5_u() {
; GFX9-NEXT: ; def s[8:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:10]
; GFX9-NEXT: ;;#ASMEND
@@ -8033,6 +8173,7 @@ define void @s_shuffle_v3p3_v4p3__7_6_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -8046,6 +8187,7 @@ define void @s_shuffle_v3p3_v4p3__7_6_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -8059,6 +8201,7 @@ define void @s_shuffle_v3p3_v4p3__7_6_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8079,6 +8222,7 @@ define void @s_shuffle_v3p3_v4p3__7_7_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
; GFX900-NEXT: ;;#ASMEND
@@ -8092,6 +8236,7 @@ define void @s_shuffle_v3p3_v4p3__7_7_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
; GFX90A-NEXT: ;;#ASMEND
@@ -8105,6 +8250,7 @@ define void @s_shuffle_v3p3_v4p3__7_7_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
; GFX942-NEXT: ;;#ASMEND
@@ -8519,6 +8665,7 @@ define void @s_shuffle_v3p3_v4p3__u_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8532,6 +8679,7 @@ define void @s_shuffle_v3p3_v4p3__u_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8545,6 +8693,7 @@ define void @s_shuffle_v3p3_v4p3__u_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8727,6 +8876,7 @@ define void @s_shuffle_v3p3_v4p3__4_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8740,6 +8890,7 @@ define void @s_shuffle_v3p3_v4p3__4_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8753,6 +8904,7 @@ define void @s_shuffle_v3p3_v4p3__4_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8950,6 +9102,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_0() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -8966,6 +9119,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_0() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -8982,6 +9136,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_0() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -9626,6 +9781,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_1() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -9642,6 +9798,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_1() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -9658,6 +9815,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_1() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -10680,6 +10838,7 @@ define void @s_shuffle_v3p3_v4p3__u_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -10693,6 +10852,7 @@ define void @s_shuffle_v3p3_v4p3__u_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -10706,6 +10866,7 @@ define void @s_shuffle_v3p3_v4p3__u_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -10888,6 +11049,7 @@ define void @s_shuffle_v3p3_v4p3__4_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -10901,6 +11063,7 @@ define void @s_shuffle_v3p3_v4p3__4_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -10914,6 +11077,7 @@ define void @s_shuffle_v3p3_v4p3__4_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -11111,6 +11275,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_3() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11127,6 +11292,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_3() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11143,6 +11309,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_3() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11558,6 +11725,8 @@ define void @s_shuffle_v3p3_v4p3__1_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11570,6 +11739,8 @@ define void @s_shuffle_v3p3_v4p3__1_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11582,6 +11753,8 @@ define void @s_shuffle_v3p3_v4p3__1_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11600,6 +11773,8 @@ define void @s_shuffle_v3p3_v4p3__2_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11612,6 +11787,8 @@ define void @s_shuffle_v3p3_v4p3__2_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11624,6 +11801,8 @@ define void @s_shuffle_v3p3_v4p3__2_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11642,6 +11821,8 @@ define void @s_shuffle_v3p3_v4p3__3_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:10]
@@ -11654,6 +11835,8 @@ define void @s_shuffle_v3p3_v4p3__3_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:10]
@@ -11666,6 +11849,8 @@ define void @s_shuffle_v3p3_v4p3__3_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:10]
@@ -11845,6 +12030,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -11858,6 +12044,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -11871,6 +12058,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -12536,6 +12724,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -12549,6 +12738,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -12562,6 +12752,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -13534,6 +13725,7 @@ define void @s_shuffle_v3p3_v4p3__u_7_7() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -13547,6 +13739,7 @@ define void @s_shuffle_v3p3_v4p3__u_7_7() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -13560,6 +13753,7 @@ define void @s_shuffle_v3p3_v4p3__u_7_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
@@ -13927,6 +14121,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_7() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s7
; GFX900-NEXT: ;;#ASMSTART
@@ -13940,6 +14135,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_7() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
; GFX90A-NEXT: ;;#ASMSTART
@@ -13953,6 +14149,7 @@ define void @s_shuffle_v3p3_v4p3__7_u_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s3
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
index 670b220b219c7..9d804d5c05327 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v2bf16.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v4bf16_v2bf16__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4bf16_v2bf16__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4bf16_v2bf16__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4bf16_v2bf16__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -61,9 +64,10 @@ define void @v_shuffle_v4bf16_v2bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -73,9 +77,10 @@ define void @v_shuffle_v4bf16_v2bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -85,9 +90,10 @@ define void @v_shuffle_v4bf16_v2bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -114,9 +120,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -126,9 +133,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -138,9 +146,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -157,12 +166,13 @@ define void @v_shuffle_v4bf16_v2bf16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v2
+; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -172,12 +182,13 @@ define void @v_shuffle_v4bf16_v2bf16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v2
+; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -187,13 +198,14 @@ define void @v_shuffle_v4bf16_v2bf16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v2
+; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -211,12 +223,13 @@ define void @v_shuffle_v4bf16_v2bf16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v2
+; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -227,12 +240,13 @@ define void @v_shuffle_v4bf16_v2bf16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v2
+; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -243,13 +257,14 @@ define void @v_shuffle_v4bf16_v2bf16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v2
+; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_perm_b32 v0, v0, v2, s2
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -266,9 +281,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -278,9 +294,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -290,9 +307,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -310,9 +328,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v0, s4
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -323,9 +342,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v0, s4
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -336,9 +356,10 @@ define void @v_shuffle_v4bf16_v2bf16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v0, s2
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -2100,33 +2121,36 @@ define void @v_shuffle_v4bf16_v2bf16__0_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4bf16_v2bf16__0_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4bf16_v2bf16__0_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4bf16_v2bf16__0_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -2142,9 +2166,10 @@ define void @v_shuffle_v4bf16_v2bf16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2154,9 +2179,10 @@ define void @v_shuffle_v4bf16_v2bf16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2166,9 +2192,10 @@ define void @v_shuffle_v4bf16_v2bf16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x bfloat> asm "; def $0", "=v"()
@@ -3290,6 +3317,7 @@ define void @s_shuffle_v4bf16_v2bf16__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3301,6 +3329,7 @@ define void @s_shuffle_v4bf16_v2bf16__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3312,6 +3341,7 @@ define void @s_shuffle_v4bf16_v2bf16__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3330,6 +3360,7 @@ define void @s_shuffle_v4bf16_v2bf16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3342,6 +3373,7 @@ define void @s_shuffle_v4bf16_v2bf16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3354,6 +3386,7 @@ define void @s_shuffle_v4bf16_v2bf16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3386,6 +3419,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3398,6 +3432,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3410,6 +3445,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3434,6 +3470,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_0_u_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3450,6 +3487,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_0_u_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3466,6 +3504,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_0_u_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -3490,6 +3529,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_1_u_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3507,6 +3547,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_1_u_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3524,6 +3565,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_1_u_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -3543,6 +3585,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_2_u_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3556,6 +3599,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_2_u_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3569,6 +3613,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_2_u_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3589,6 +3634,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_3_u_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3602,6 +3648,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_3_u_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3615,6 +3662,7 @@ define void @s_shuffle_v4bf16_v2bf16__3_3_u_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5376,6 +5424,7 @@ define void @s_shuffle_v4bf16_v2bf16__0_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5387,6 +5436,7 @@ define void @s_shuffle_v4bf16_v2bf16__0_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5398,6 +5448,7 @@ define void @s_shuffle_v4bf16_v2bf16__0_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5416,6 +5467,7 @@ define void @s_shuffle_v4bf16_v2bf16__1_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5428,6 +5480,7 @@ define void @s_shuffle_v4bf16_v2bf16__1_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5440,6 +5493,7 @@ define void @s_shuffle_v4bf16_v2bf16__1_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
index 89ce868b03546..2162ea145f617 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v3bf16.ll
@@ -65,6 +65,7 @@ define void @v_shuffle_v4bf16_v3bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -77,6 +78,7 @@ define void @v_shuffle_v4bf16_v3bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -89,6 +91,7 @@ define void @v_shuffle_v4bf16_v3bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -103,11 +106,12 @@ define void @v_shuffle_v4bf16_v3bf16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4bf16_v3bf16__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -119,6 +123,7 @@ define void @v_shuffle_v4bf16_v3bf16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -131,6 +136,7 @@ define void @v_shuffle_v4bf16_v3bf16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -162,6 +168,7 @@ define void @v_shuffle_v4bf16_v3bf16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -174,6 +181,7 @@ define void @v_shuffle_v4bf16_v3bf16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -186,6 +194,7 @@ define void @v_shuffle_v4bf16_v3bf16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -202,11 +211,12 @@ define void @v_shuffle_v4bf16_v3bf16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4bf16_v3bf16__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -218,6 +228,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -230,6 +241,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -255,6 +267,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -271,6 +284,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -286,6 +300,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v0, v3, s2
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -313,6 +328,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -329,6 +345,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_bfi_b32 v0, s4, v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -344,6 +361,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_bfi_b32 v0, s2, v3, v0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -371,6 +389,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -387,6 +406,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -404,6 +424,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v1, v3, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -426,6 +447,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -439,6 +461,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x5040100
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -452,6 +475,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x5040100
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -474,6 +498,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0xffff
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -487,6 +512,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0xffff
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -500,6 +526,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0xffff
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_bfi_b32 v0, s2, v1, v0
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -522,6 +549,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -535,6 +563,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x5040100
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -548,6 +577,7 @@ define void @v_shuffle_v4bf16_v3bf16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x5040100
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v1, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4412,6 +4442,7 @@ define void @v_shuffle_v4bf16_v3bf16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4424,6 +4455,7 @@ define void @v_shuffle_v4bf16_v3bf16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4436,6 +4468,7 @@ define void @v_shuffle_v4bf16_v3bf16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4450,11 +4483,12 @@ define void @v_shuffle_v4bf16_v3bf16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4bf16_v3bf16__2_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -4466,6 +4500,7 @@ define void @v_shuffle_v4bf16_v3bf16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4478,6 +4513,7 @@ define void @v_shuffle_v4bf16_v3bf16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7339,6 +7375,7 @@ define void @s_shuffle_v4bf16_v3bf16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7351,6 +7388,7 @@ define void @s_shuffle_v4bf16_v3bf16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7363,6 +7401,7 @@ define void @s_shuffle_v4bf16_v3bf16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7382,6 +7421,7 @@ define void @s_shuffle_v4bf16_v3bf16__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7394,6 +7434,7 @@ define void @s_shuffle_v4bf16_v3bf16__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7406,6 +7447,7 @@ define void @s_shuffle_v4bf16_v3bf16__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7440,6 +7482,7 @@ define void @s_shuffle_v4bf16_v3bf16__4_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7452,6 +7495,7 @@ define void @s_shuffle_v4bf16_v3bf16__4_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7464,6 +7508,7 @@ define void @s_shuffle_v4bf16_v3bf16__4_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7485,6 +7530,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7497,6 +7543,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7509,6 +7556,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7534,6 +7582,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_0_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7549,6 +7598,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_0_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7564,6 +7614,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_0_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7589,6 +7640,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_1_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7605,6 +7657,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_1_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7621,6 +7674,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_1_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7645,6 +7699,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_2_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7660,6 +7715,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_2_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7675,6 +7731,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_2_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7695,6 +7752,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7707,6 +7765,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7719,6 +7778,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7741,6 +7801,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_4_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7754,6 +7815,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_4_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7767,6 +7829,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_4_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7788,6 +7851,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7800,6 +7864,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7812,6 +7877,7 @@ define void @s_shuffle_v4bf16_v3bf16__5_5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -11492,6 +11558,7 @@ define void @s_shuffle_v4bf16_v3bf16__1_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -11504,6 +11571,7 @@ define void @s_shuffle_v4bf16_v3bf16__1_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -11516,6 +11584,7 @@ define void @s_shuffle_v4bf16_v3bf16__1_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -11535,6 +11604,7 @@ define void @s_shuffle_v4bf16_v3bf16__2_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -11547,6 +11617,7 @@ define void @s_shuffle_v4bf16_v3bf16__2_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -11559,6 +11630,7 @@ define void @s_shuffle_v4bf16_v3bf16__2_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
index 8e24d6e02f3ff..e5195b4adab0a 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4bf16.v4bf16.ll
@@ -63,6 +63,7 @@ define void @v_shuffle_v4bf16_v4bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -75,6 +76,7 @@ define void @v_shuffle_v4bf16_v4bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +89,7 @@ define void @v_shuffle_v4bf16_v4bf16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -100,11 +103,12 @@ define void @v_shuffle_v4bf16_v4bf16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4bf16_v4bf16__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -116,6 +120,7 @@ define void @v_shuffle_v4bf16_v4bf16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -128,6 +133,7 @@ define void @v_shuffle_v4bf16_v4bf16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -146,6 +152,7 @@ define void @v_shuffle_v4bf16_v4bf16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -158,6 +165,7 @@ define void @v_shuffle_v4bf16_v4bf16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -170,6 +178,7 @@ define void @v_shuffle_v4bf16_v4bf16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -199,6 +208,7 @@ define void @v_shuffle_v4bf16_v4bf16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -211,6 +221,7 @@ define void @v_shuffle_v4bf16_v4bf16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -223,6 +234,7 @@ define void @v_shuffle_v4bf16_v4bf16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -237,11 +249,12 @@ define void @v_shuffle_v4bf16_v4bf16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4bf16_v4bf16__6_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -253,6 +266,7 @@ define void @v_shuffle_v4bf16_v4bf16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -265,6 +279,7 @@ define void @v_shuffle_v4bf16_v4bf16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -284,6 +299,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -296,6 +312,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -308,6 +325,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -330,6 +348,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -345,6 +364,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -359,6 +379,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -384,6 +405,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -400,6 +422,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -415,6 +438,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v0, v3, s2
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -439,6 +463,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -454,6 +479,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -470,6 +496,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -493,6 +520,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -509,6 +537,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -526,6 +555,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v1, v3, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -545,6 +575,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -557,6 +588,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -569,6 +601,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -589,6 +622,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -602,6 +636,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -615,6 +650,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -634,6 +670,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -646,6 +683,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -658,6 +696,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -678,6 +717,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -691,6 +731,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -704,6 +745,7 @@ define void @v_shuffle_v4bf16_v4bf16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v1, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7045,6 +7087,7 @@ define void @v_shuffle_v4bf16_v4bf16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7057,6 +7100,7 @@ define void @v_shuffle_v4bf16_v4bf16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7069,6 +7113,7 @@ define void @v_shuffle_v4bf16_v4bf16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7082,11 +7127,12 @@ define void @v_shuffle_v4bf16_v4bf16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4bf16_v4bf16__2_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -7098,6 +7144,7 @@ define void @v_shuffle_v4bf16_v4bf16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7110,6 +7157,7 @@ define void @v_shuffle_v4bf16_v4bf16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7128,6 +7176,7 @@ define void @v_shuffle_v4bf16_v4bf16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7140,6 +7189,7 @@ define void @v_shuffle_v4bf16_v4bf16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7152,6 +7202,7 @@ define void @v_shuffle_v4bf16_v4bf16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -12151,6 +12202,7 @@ define void @s_shuffle_v4bf16_v4bf16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12163,6 +12215,7 @@ define void @s_shuffle_v4bf16_v4bf16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12175,6 +12228,7 @@ define void @s_shuffle_v4bf16_v4bf16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12193,6 +12247,7 @@ define void @s_shuffle_v4bf16_v4bf16__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12205,6 +12260,7 @@ define void @s_shuffle_v4bf16_v4bf16__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12217,6 +12273,7 @@ define void @s_shuffle_v4bf16_v4bf16__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12235,6 +12292,7 @@ define void @s_shuffle_v4bf16_v4bf16__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12247,6 +12305,7 @@ define void @s_shuffle_v4bf16_v4bf16__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12259,6 +12318,7 @@ define void @s_shuffle_v4bf16_v4bf16__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12291,6 +12351,7 @@ define void @s_shuffle_v4bf16_v4bf16__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12303,6 +12364,7 @@ define void @s_shuffle_v4bf16_v4bf16__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12315,6 +12377,7 @@ define void @s_shuffle_v4bf16_v4bf16__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12334,6 +12397,7 @@ define void @s_shuffle_v4bf16_v4bf16__6_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12346,6 +12410,7 @@ define void @s_shuffle_v4bf16_v4bf16__6_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12358,6 +12423,7 @@ define void @s_shuffle_v4bf16_v4bf16__6_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12377,6 +12443,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12389,6 +12456,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12401,6 +12469,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12425,6 +12494,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12441,6 +12511,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12457,6 +12528,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12481,6 +12553,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_1_u_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12498,6 +12571,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_1_u_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12515,6 +12589,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_1_u_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12538,6 +12613,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12554,6 +12630,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12570,6 +12647,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12594,6 +12672,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_3_u_u() {
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12611,6 +12690,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_3_u_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12628,6 +12708,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_3_u_u() {
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12647,6 +12728,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_4_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12660,6 +12742,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_4_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12673,6 +12756,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_4_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12695,6 +12779,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_5_u_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12709,6 +12794,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_5_u_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12723,6 +12809,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_5_u_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12742,6 +12829,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_6_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12755,6 +12843,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_6_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12768,6 +12857,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_6_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12788,6 +12878,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_7_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12801,6 +12892,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_7_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12814,6 +12906,7 @@ define void @s_shuffle_v4bf16_v4bf16__7_7_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19170,6 +19263,7 @@ define void @s_shuffle_v4bf16_v4bf16__1_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19182,6 +19276,7 @@ define void @s_shuffle_v4bf16_v4bf16__1_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19194,6 +19289,7 @@ define void @s_shuffle_v4bf16_v4bf16__1_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19212,6 +19308,7 @@ define void @s_shuffle_v4bf16_v4bf16__2_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19224,6 +19321,7 @@ define void @s_shuffle_v4bf16_v4bf16__2_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19236,6 +19334,7 @@ define void @s_shuffle_v4bf16_v4bf16__2_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19254,6 +19353,7 @@ define void @s_shuffle_v4bf16_v4bf16__3_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19266,6 +19366,7 @@ define void @s_shuffle_v4bf16_v4bf16__3_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19278,6 +19379,7 @@ define void @s_shuffle_v4bf16_v4bf16__3_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
index c7a6f4359494a..19ee22077dcfa 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v2f16.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v4f16_v2f16__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f16_v2f16__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f16_v2f16__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f16_v2f16__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -61,9 +64,10 @@ define void @v_shuffle_v4f16_v2f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -73,9 +77,10 @@ define void @v_shuffle_v4f16_v2f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -85,9 +90,10 @@ define void @v_shuffle_v4f16_v2f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -114,9 +120,10 @@ define void @v_shuffle_v4f16_v2f16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -126,9 +133,10 @@ define void @v_shuffle_v4f16_v2f16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -138,9 +146,10 @@ define void @v_shuffle_v4f16_v2f16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -157,12 +166,13 @@ define void @v_shuffle_v4f16_v2f16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v2
+; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -172,12 +182,13 @@ define void @v_shuffle_v4f16_v2f16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v2
+; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -187,13 +198,14 @@ define void @v_shuffle_v4f16_v2f16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v2
+; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -211,12 +223,13 @@ define void @v_shuffle_v4f16_v2f16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v2
+; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -227,12 +240,13 @@ define void @v_shuffle_v4f16_v2f16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v2
+; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -243,13 +257,14 @@ define void @v_shuffle_v4f16_v2f16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v2
+; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_perm_b32 v0, v0, v2, s2
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -266,9 +281,10 @@ define void @v_shuffle_v4f16_v2f16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -278,9 +294,10 @@ define void @v_shuffle_v4f16_v2f16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -290,9 +307,10 @@ define void @v_shuffle_v4f16_v2f16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -310,9 +328,10 @@ define void @v_shuffle_v4f16_v2f16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v0, s4
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -323,9 +342,10 @@ define void @v_shuffle_v4f16_v2f16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v0, s4
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -336,9 +356,10 @@ define void @v_shuffle_v4f16_v2f16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v0, s2
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -2100,33 +2121,36 @@ define void @v_shuffle_v4f16_v2f16__0_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f16_v2f16__0_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f16_v2f16__0_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f16_v2f16__0_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -2142,9 +2166,10 @@ define void @v_shuffle_v4f16_v2f16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2154,9 +2179,10 @@ define void @v_shuffle_v4f16_v2f16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2166,9 +2192,10 @@ define void @v_shuffle_v4f16_v2f16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x half> asm "; def $0", "=v"()
@@ -3290,6 +3317,7 @@ define void @s_shuffle_v4f16_v2f16__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3301,6 +3329,7 @@ define void @s_shuffle_v4f16_v2f16__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3312,6 +3341,7 @@ define void @s_shuffle_v4f16_v2f16__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3330,6 +3360,7 @@ define void @s_shuffle_v4f16_v2f16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3342,6 +3373,7 @@ define void @s_shuffle_v4f16_v2f16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3354,6 +3386,7 @@ define void @s_shuffle_v4f16_v2f16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3386,6 +3419,7 @@ define void @s_shuffle_v4f16_v2f16__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3398,6 +3432,7 @@ define void @s_shuffle_v4f16_v2f16__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3410,6 +3445,7 @@ define void @s_shuffle_v4f16_v2f16__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3434,6 +3470,7 @@ define void @s_shuffle_v4f16_v2f16__3_0_u_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3450,6 +3487,7 @@ define void @s_shuffle_v4f16_v2f16__3_0_u_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3466,6 +3504,7 @@ define void @s_shuffle_v4f16_v2f16__3_0_u_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -3490,6 +3529,7 @@ define void @s_shuffle_v4f16_v2f16__3_1_u_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3507,6 +3547,7 @@ define void @s_shuffle_v4f16_v2f16__3_1_u_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3524,6 +3565,7 @@ define void @s_shuffle_v4f16_v2f16__3_1_u_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -3543,6 +3585,7 @@ define void @s_shuffle_v4f16_v2f16__3_2_u_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3556,6 +3599,7 @@ define void @s_shuffle_v4f16_v2f16__3_2_u_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3569,6 +3613,7 @@ define void @s_shuffle_v4f16_v2f16__3_2_u_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3589,6 +3634,7 @@ define void @s_shuffle_v4f16_v2f16__3_3_u_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3602,6 +3648,7 @@ define void @s_shuffle_v4f16_v2f16__3_3_u_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3615,6 +3662,7 @@ define void @s_shuffle_v4f16_v2f16__3_3_u_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5376,6 +5424,7 @@ define void @s_shuffle_v4f16_v2f16__0_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5387,6 +5436,7 @@ define void @s_shuffle_v4f16_v2f16__0_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5398,6 +5448,7 @@ define void @s_shuffle_v4f16_v2f16__0_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5416,6 +5467,7 @@ define void @s_shuffle_v4f16_v2f16__1_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5428,6 +5480,7 @@ define void @s_shuffle_v4f16_v2f16__1_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5440,6 +5493,7 @@ define void @s_shuffle_v4f16_v2f16__1_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
index d1ff8c658c77d..ec9384552b8ce 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v3f16.ll
@@ -65,6 +65,7 @@ define void @v_shuffle_v4f16_v3f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -77,6 +78,7 @@ define void @v_shuffle_v4f16_v3f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -89,6 +91,7 @@ define void @v_shuffle_v4f16_v3f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -103,11 +106,12 @@ define void @v_shuffle_v4f16_v3f16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f16_v3f16__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -119,6 +123,7 @@ define void @v_shuffle_v4f16_v3f16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -131,6 +136,7 @@ define void @v_shuffle_v4f16_v3f16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -162,6 +168,7 @@ define void @v_shuffle_v4f16_v3f16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -174,6 +181,7 @@ define void @v_shuffle_v4f16_v3f16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -186,6 +194,7 @@ define void @v_shuffle_v4f16_v3f16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -202,11 +211,12 @@ define void @v_shuffle_v4f16_v3f16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f16_v3f16__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -218,6 +228,7 @@ define void @v_shuffle_v4f16_v3f16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -230,6 +241,7 @@ define void @v_shuffle_v4f16_v3f16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -255,6 +267,7 @@ define void @v_shuffle_v4f16_v3f16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -271,6 +284,7 @@ define void @v_shuffle_v4f16_v3f16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -286,6 +300,7 @@ define void @v_shuffle_v4f16_v3f16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v0, v3, s2
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -313,6 +328,7 @@ define void @v_shuffle_v4f16_v3f16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -329,6 +345,7 @@ define void @v_shuffle_v4f16_v3f16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_bfi_b32 v0, s4, v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -344,6 +361,7 @@ define void @v_shuffle_v4f16_v3f16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_bfi_b32 v0, s2, v3, v0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -371,6 +389,7 @@ define void @v_shuffle_v4f16_v3f16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -387,6 +406,7 @@ define void @v_shuffle_v4f16_v3f16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -404,6 +424,7 @@ define void @v_shuffle_v4f16_v3f16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v1, v3, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -426,6 +447,7 @@ define void @v_shuffle_v4f16_v3f16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -439,6 +461,7 @@ define void @v_shuffle_v4f16_v3f16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x5040100
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -452,6 +475,7 @@ define void @v_shuffle_v4f16_v3f16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x5040100
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -474,6 +498,7 @@ define void @v_shuffle_v4f16_v3f16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0xffff
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -487,6 +512,7 @@ define void @v_shuffle_v4f16_v3f16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0xffff
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -500,6 +526,7 @@ define void @v_shuffle_v4f16_v3f16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0xffff
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_bfi_b32 v0, s2, v1, v0
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -522,6 +549,7 @@ define void @v_shuffle_v4f16_v3f16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -535,6 +563,7 @@ define void @v_shuffle_v4f16_v3f16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x5040100
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -548,6 +577,7 @@ define void @v_shuffle_v4f16_v3f16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x5040100
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v1, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4412,6 +4442,7 @@ define void @v_shuffle_v4f16_v3f16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4424,6 +4455,7 @@ define void @v_shuffle_v4f16_v3f16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4436,6 +4468,7 @@ define void @v_shuffle_v4f16_v3f16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4450,11 +4483,12 @@ define void @v_shuffle_v4f16_v3f16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f16_v3f16__2_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -4466,6 +4500,7 @@ define void @v_shuffle_v4f16_v3f16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4478,6 +4513,7 @@ define void @v_shuffle_v4f16_v3f16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7339,6 +7375,7 @@ define void @s_shuffle_v4f16_v3f16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7351,6 +7388,7 @@ define void @s_shuffle_v4f16_v3f16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7363,6 +7401,7 @@ define void @s_shuffle_v4f16_v3f16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7382,6 +7421,7 @@ define void @s_shuffle_v4f16_v3f16__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7394,6 +7434,7 @@ define void @s_shuffle_v4f16_v3f16__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7406,6 +7447,7 @@ define void @s_shuffle_v4f16_v3f16__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7440,6 +7482,7 @@ define void @s_shuffle_v4f16_v3f16__4_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7452,6 +7495,7 @@ define void @s_shuffle_v4f16_v3f16__4_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7464,6 +7508,7 @@ define void @s_shuffle_v4f16_v3f16__4_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7485,6 +7530,7 @@ define void @s_shuffle_v4f16_v3f16__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7497,6 +7543,7 @@ define void @s_shuffle_v4f16_v3f16__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7509,6 +7556,7 @@ define void @s_shuffle_v4f16_v3f16__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7534,6 +7582,7 @@ define void @s_shuffle_v4f16_v3f16__5_0_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7549,6 +7598,7 @@ define void @s_shuffle_v4f16_v3f16__5_0_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7564,6 +7614,7 @@ define void @s_shuffle_v4f16_v3f16__5_0_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7589,6 +7640,7 @@ define void @s_shuffle_v4f16_v3f16__5_1_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7605,6 +7657,7 @@ define void @s_shuffle_v4f16_v3f16__5_1_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7621,6 +7674,7 @@ define void @s_shuffle_v4f16_v3f16__5_1_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7645,6 +7699,7 @@ define void @s_shuffle_v4f16_v3f16__5_2_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7660,6 +7715,7 @@ define void @s_shuffle_v4f16_v3f16__5_2_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7675,6 +7731,7 @@ define void @s_shuffle_v4f16_v3f16__5_2_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7695,6 +7752,7 @@ define void @s_shuffle_v4f16_v3f16__5_3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7707,6 +7765,7 @@ define void @s_shuffle_v4f16_v3f16__5_3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7719,6 +7778,7 @@ define void @s_shuffle_v4f16_v3f16__5_3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7741,6 +7801,7 @@ define void @s_shuffle_v4f16_v3f16__5_4_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7754,6 +7815,7 @@ define void @s_shuffle_v4f16_v3f16__5_4_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7767,6 +7829,7 @@ define void @s_shuffle_v4f16_v3f16__5_4_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7788,6 +7851,7 @@ define void @s_shuffle_v4f16_v3f16__5_5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7800,6 +7864,7 @@ define void @s_shuffle_v4f16_v3f16__5_5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7812,6 +7877,7 @@ define void @s_shuffle_v4f16_v3f16__5_5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -11492,6 +11558,7 @@ define void @s_shuffle_v4f16_v3f16__1_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -11504,6 +11571,7 @@ define void @s_shuffle_v4f16_v3f16__1_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -11516,6 +11584,7 @@ define void @s_shuffle_v4f16_v3f16__1_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -11535,6 +11604,7 @@ define void @s_shuffle_v4f16_v3f16__2_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -11547,6 +11617,7 @@ define void @s_shuffle_v4f16_v3f16__2_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -11559,6 +11630,7 @@ define void @s_shuffle_v4f16_v3f16__2_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
index 8a9a0d1a7ef5d..398d5e3edaf97 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f16.v4f16.ll
@@ -63,6 +63,7 @@ define void @v_shuffle_v4f16_v4f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -75,6 +76,7 @@ define void @v_shuffle_v4f16_v4f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +89,7 @@ define void @v_shuffle_v4f16_v4f16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -100,11 +103,12 @@ define void @v_shuffle_v4f16_v4f16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f16_v4f16__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -116,6 +120,7 @@ define void @v_shuffle_v4f16_v4f16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -128,6 +133,7 @@ define void @v_shuffle_v4f16_v4f16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -146,6 +152,7 @@ define void @v_shuffle_v4f16_v4f16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -158,6 +165,7 @@ define void @v_shuffle_v4f16_v4f16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -170,6 +178,7 @@ define void @v_shuffle_v4f16_v4f16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -199,6 +208,7 @@ define void @v_shuffle_v4f16_v4f16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -211,6 +221,7 @@ define void @v_shuffle_v4f16_v4f16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -223,6 +234,7 @@ define void @v_shuffle_v4f16_v4f16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -237,11 +249,12 @@ define void @v_shuffle_v4f16_v4f16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f16_v4f16__6_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -253,6 +266,7 @@ define void @v_shuffle_v4f16_v4f16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -265,6 +279,7 @@ define void @v_shuffle_v4f16_v4f16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -284,6 +299,7 @@ define void @v_shuffle_v4f16_v4f16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -296,6 +312,7 @@ define void @v_shuffle_v4f16_v4f16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -308,6 +325,7 @@ define void @v_shuffle_v4f16_v4f16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -330,6 +348,7 @@ define void @v_shuffle_v4f16_v4f16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -345,6 +364,7 @@ define void @v_shuffle_v4f16_v4f16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -359,6 +379,7 @@ define void @v_shuffle_v4f16_v4f16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -384,6 +405,7 @@ define void @v_shuffle_v4f16_v4f16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -400,6 +422,7 @@ define void @v_shuffle_v4f16_v4f16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -415,6 +438,7 @@ define void @v_shuffle_v4f16_v4f16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v0, v3, s2
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -439,6 +463,7 @@ define void @v_shuffle_v4f16_v4f16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -454,6 +479,7 @@ define void @v_shuffle_v4f16_v4f16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -470,6 +496,7 @@ define void @v_shuffle_v4f16_v4f16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -493,6 +520,7 @@ define void @v_shuffle_v4f16_v4f16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -509,6 +537,7 @@ define void @v_shuffle_v4f16_v4f16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -526,6 +555,7 @@ define void @v_shuffle_v4f16_v4f16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v1, v3, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -545,6 +575,7 @@ define void @v_shuffle_v4f16_v4f16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -557,6 +588,7 @@ define void @v_shuffle_v4f16_v4f16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -569,6 +601,7 @@ define void @v_shuffle_v4f16_v4f16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -589,6 +622,7 @@ define void @v_shuffle_v4f16_v4f16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -602,6 +636,7 @@ define void @v_shuffle_v4f16_v4f16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -615,6 +650,7 @@ define void @v_shuffle_v4f16_v4f16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -634,6 +670,7 @@ define void @v_shuffle_v4f16_v4f16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -646,6 +683,7 @@ define void @v_shuffle_v4f16_v4f16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -658,6 +696,7 @@ define void @v_shuffle_v4f16_v4f16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -678,6 +717,7 @@ define void @v_shuffle_v4f16_v4f16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -691,6 +731,7 @@ define void @v_shuffle_v4f16_v4f16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -704,6 +745,7 @@ define void @v_shuffle_v4f16_v4f16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v1, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7045,6 +7087,7 @@ define void @v_shuffle_v4f16_v4f16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7057,6 +7100,7 @@ define void @v_shuffle_v4f16_v4f16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7069,6 +7113,7 @@ define void @v_shuffle_v4f16_v4f16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7082,11 +7127,12 @@ define void @v_shuffle_v4f16_v4f16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f16_v4f16__2_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -7098,6 +7144,7 @@ define void @v_shuffle_v4f16_v4f16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7110,6 +7157,7 @@ define void @v_shuffle_v4f16_v4f16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7128,6 +7176,7 @@ define void @v_shuffle_v4f16_v4f16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7140,6 +7189,7 @@ define void @v_shuffle_v4f16_v4f16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7152,6 +7202,7 @@ define void @v_shuffle_v4f16_v4f16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -12151,6 +12202,7 @@ define void @s_shuffle_v4f16_v4f16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12163,6 +12215,7 @@ define void @s_shuffle_v4f16_v4f16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12175,6 +12228,7 @@ define void @s_shuffle_v4f16_v4f16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12193,6 +12247,7 @@ define void @s_shuffle_v4f16_v4f16__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12205,6 +12260,7 @@ define void @s_shuffle_v4f16_v4f16__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12217,6 +12273,7 @@ define void @s_shuffle_v4f16_v4f16__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12235,6 +12292,7 @@ define void @s_shuffle_v4f16_v4f16__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12247,6 +12305,7 @@ define void @s_shuffle_v4f16_v4f16__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12259,6 +12318,7 @@ define void @s_shuffle_v4f16_v4f16__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12291,6 +12351,7 @@ define void @s_shuffle_v4f16_v4f16__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12303,6 +12364,7 @@ define void @s_shuffle_v4f16_v4f16__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12315,6 +12377,7 @@ define void @s_shuffle_v4f16_v4f16__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12334,6 +12397,7 @@ define void @s_shuffle_v4f16_v4f16__6_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12346,6 +12410,7 @@ define void @s_shuffle_v4f16_v4f16__6_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12358,6 +12423,7 @@ define void @s_shuffle_v4f16_v4f16__6_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12377,6 +12443,7 @@ define void @s_shuffle_v4f16_v4f16__7_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12389,6 +12456,7 @@ define void @s_shuffle_v4f16_v4f16__7_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12401,6 +12469,7 @@ define void @s_shuffle_v4f16_v4f16__7_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12425,6 +12494,7 @@ define void @s_shuffle_v4f16_v4f16__7_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12441,6 +12511,7 @@ define void @s_shuffle_v4f16_v4f16__7_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12457,6 +12528,7 @@ define void @s_shuffle_v4f16_v4f16__7_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12481,6 +12553,7 @@ define void @s_shuffle_v4f16_v4f16__7_1_u_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12498,6 +12571,7 @@ define void @s_shuffle_v4f16_v4f16__7_1_u_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12515,6 +12589,7 @@ define void @s_shuffle_v4f16_v4f16__7_1_u_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12538,6 +12613,7 @@ define void @s_shuffle_v4f16_v4f16__7_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12554,6 +12630,7 @@ define void @s_shuffle_v4f16_v4f16__7_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12570,6 +12647,7 @@ define void @s_shuffle_v4f16_v4f16__7_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12594,6 +12672,7 @@ define void @s_shuffle_v4f16_v4f16__7_3_u_u() {
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12611,6 +12690,7 @@ define void @s_shuffle_v4f16_v4f16__7_3_u_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12628,6 +12708,7 @@ define void @s_shuffle_v4f16_v4f16__7_3_u_u() {
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12647,6 +12728,7 @@ define void @s_shuffle_v4f16_v4f16__7_4_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12660,6 +12742,7 @@ define void @s_shuffle_v4f16_v4f16__7_4_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12673,6 +12756,7 @@ define void @s_shuffle_v4f16_v4f16__7_4_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12695,6 +12779,7 @@ define void @s_shuffle_v4f16_v4f16__7_5_u_u() {
; GFX900-NEXT: s_lshr_b32 s4, s4, 16
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12709,6 +12794,7 @@ define void @s_shuffle_v4f16_v4f16__7_5_u_u() {
; GFX90A-NEXT: s_lshr_b32 s4, s4, 16
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12723,6 +12809,7 @@ define void @s_shuffle_v4f16_v4f16__7_5_u_u() {
; GFX942-NEXT: s_lshr_b32 s0, s0, 16
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12742,6 +12829,7 @@ define void @s_shuffle_v4f16_v4f16__7_6_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12755,6 +12843,7 @@ define void @s_shuffle_v4f16_v4f16__7_6_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12768,6 +12857,7 @@ define void @s_shuffle_v4f16_v4f16__7_6_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12788,6 +12878,7 @@ define void @s_shuffle_v4f16_v4f16__7_7_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12801,6 +12892,7 @@ define void @s_shuffle_v4f16_v4f16__7_7_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12814,6 +12906,7 @@ define void @s_shuffle_v4f16_v4f16__7_7_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19170,6 +19263,7 @@ define void @s_shuffle_v4f16_v4f16__1_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19182,6 +19276,7 @@ define void @s_shuffle_v4f16_v4f16__1_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19194,6 +19289,7 @@ define void @s_shuffle_v4f16_v4f16__1_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19212,6 +19308,7 @@ define void @s_shuffle_v4f16_v4f16__2_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19224,6 +19321,7 @@ define void @s_shuffle_v4f16_v4f16__2_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19236,6 +19334,7 @@ define void @s_shuffle_v4f16_v4f16__2_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -19254,6 +19353,7 @@ define void @s_shuffle_v4f16_v4f16__3_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -19266,6 +19366,7 @@ define void @s_shuffle_v4f16_v4f16__3_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -19278,6 +19379,7 @@ define void @s_shuffle_v4f16_v4f16__3_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
index 2a0344fce9f44..16744c24961cd 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v2f32.ll
@@ -19,33 +19,39 @@ define void @v_shuffle_v4f32_v2f32__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v2f32__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v2f32__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -58,35 +64,45 @@ define void @v_shuffle_v4f32_v2f32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v2f32__1_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v2f32__1_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -110,35 +126,45 @@ define void @v_shuffle_v4f32_v2f32__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v2f32__3_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v2f32__3_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -152,14 +178,16 @@ define void @v_shuffle_v4f32_v2f32__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__3_0_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -169,11 +197,14 @@ define void @v_shuffle_v4f32_v2f32__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -184,12 +215,15 @@ define void @v_shuffle_v4f32_v2f32__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -204,14 +238,16 @@ define void @v_shuffle_v4f32_v2f32__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__3_1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -226,6 +262,8 @@ define void @v_shuffle_v4f32_v2f32__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -240,8 +278,10 @@ define void @v_shuffle_v4f32_v2f32__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -256,12 +296,14 @@ define void @v_shuffle_v4f32_v2f32__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__3_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v0
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -274,6 +316,8 @@ define void @v_shuffle_v4f32_v2f32__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -285,6 +329,8 @@ define void @v_shuffle_v4f32_v2f32__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v0
@@ -302,12 +348,14 @@ define void @v_shuffle_v4f32_v2f32__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__3_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -317,9 +365,11 @@ define void @v_shuffle_v4f32_v2f32__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -329,9 +379,11 @@ define void @v_shuffle_v4f32_v2f32__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -347,12 +399,13 @@ define void @v_shuffle_v4f32_v2f32__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:1]
+; GFX900-NEXT: ; def v[3:4]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[3:4]
+; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v2, v1
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -364,10 +417,11 @@ define void @v_shuffle_v4f32_v2f32__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -379,10 +433,11 @@ define void @v_shuffle_v4f32_v2f32__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -400,12 +455,13 @@ define void @v_shuffle_v4f32_v2f32__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -421,6 +477,7 @@ define void @v_shuffle_v4f32_v2f32__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -437,6 +494,7 @@ define void @v_shuffle_v4f32_v2f32__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -451,13 +509,14 @@ define void @v_shuffle_v4f32_v2f32__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__3_3_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -470,6 +529,7 @@ define void @v_shuffle_v4f32_v2f32__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -484,6 +544,7 @@ define void @v_shuffle_v4f32_v2f32__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -498,13 +559,14 @@ define void @v_shuffle_v4f32_v2f32__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__3_3_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -514,10 +576,11 @@ define void @v_shuffle_v4f32_v2f32__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -527,10 +590,11 @@ define void @v_shuffle_v4f32_v2f32__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -566,6 +630,7 @@ define void @v_shuffle_v4f32_v2f32__3_3_3_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
@@ -582,6 +647,7 @@ define void @v_shuffle_v4f32_v2f32__3_3_3_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[2:3], v[0:1], v[2:3] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v0, v1
@@ -1226,15 +1292,16 @@ define void @v_shuffle_v4f32_v2f32__3_3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:1]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1242,15 +1309,16 @@ define void @v_shuffle_v4f32_v2f32__3_3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:3]
+; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:1]
+; GFX942-NEXT: ; def v[4:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -2009,33 +2077,39 @@ define void @v_shuffle_v4f32_v2f32__0_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__0_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v2f32__0_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v2f32__0_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -2048,35 +2122,45 @@ define void @v_shuffle_v4f32_v2f32__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v2f32__1_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v2f32__1_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v2f32__1_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x float> asm "; def $0", "=v"()
@@ -2215,6 +2299,7 @@ define void @v_shuffle_v4f32_v2f32__3_0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
@@ -2231,6 +2316,7 @@ define void @v_shuffle_v4f32_v2f32__3_0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v3, v2
@@ -2372,6 +2458,7 @@ define void @v_shuffle_v4f32_v2f32__3_3_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v1
; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2383,6 +2470,7 @@ define void @v_shuffle_v4f32_v2f32__3_3_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v1
@@ -2788,6 +2876,7 @@ define void @v_shuffle_v4f32_v2f32__3_0_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -2804,6 +2893,7 @@ define void @v_shuffle_v4f32_v2f32__3_0_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -3146,6 +3236,8 @@ define void @s_shuffle_v4f32_v2f32__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3157,6 +3249,8 @@ define void @s_shuffle_v4f32_v2f32__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3168,6 +3262,8 @@ define void @s_shuffle_v4f32_v2f32__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3186,6 +3282,9 @@ define void @s_shuffle_v4f32_v2f32__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -3198,6 +3297,9 @@ define void @s_shuffle_v4f32_v2f32__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -3210,6 +3312,9 @@ define void @s_shuffle_v4f32_v2f32__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3242,6 +3347,9 @@ define void @s_shuffle_v4f32_v2f32__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -3254,6 +3362,9 @@ define void @s_shuffle_v4f32_v2f32__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -3266,6 +3377,9 @@ define void @s_shuffle_v4f32_v2f32__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3290,6 +3404,8 @@ define void @s_shuffle_v4f32_v2f32__3_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3306,6 +3422,8 @@ define void @s_shuffle_v4f32_v2f32__3_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3322,6 +3440,8 @@ define void @s_shuffle_v4f32_v2f32__3_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3344,6 +3464,8 @@ define void @s_shuffle_v4f32_v2f32__3_1_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3359,6 +3481,8 @@ define void @s_shuffle_v4f32_v2f32__3_1_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3374,6 +3498,8 @@ define void @s_shuffle_v4f32_v2f32__3_1_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3394,6 +3520,8 @@ define void @s_shuffle_v4f32_v2f32__3_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3407,6 +3535,8 @@ define void @s_shuffle_v4f32_v2f32__3_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3420,6 +3550,8 @@ define void @s_shuffle_v4f32_v2f32__3_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3438,6 +3570,8 @@ define void @s_shuffle_v4f32_v2f32__3_3_u_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
@@ -3455,12 +3589,13 @@ define void @s_shuffle_v4f32_v2f32__3_3_0_u() {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[8:9]
+; GFX9-NEXT: ; def s[10:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[10:11]
+; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s9
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -3484,6 +3619,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s9
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3500,6 +3636,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s9
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3516,6 +3653,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s9
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3536,6 +3674,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_2_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -3556,6 +3695,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_3_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: s_mov_b32 s10, s9
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -4062,6 +4202,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_u_0() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4078,6 +4219,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_u_0() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4094,6 +4236,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_u_0() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4674,6 +4817,8 @@ define void @s_shuffle_v4f32_v2f32__0_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -4685,6 +4830,8 @@ define void @s_shuffle_v4f32_v2f32__0_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -4696,6 +4843,8 @@ define void @s_shuffle_v4f32_v2f32__0_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4714,6 +4863,9 @@ define void @s_shuffle_v4f32_v2f32__1_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4726,6 +4878,9 @@ define void @s_shuffle_v4f32_v2f32__1_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4738,6 +4893,9 @@ define void @s_shuffle_v4f32_v2f32__1_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4915,6 +5073,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4929,6 +5088,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4943,6 +5103,7 @@ define void @s_shuffle_v4f32_v2f32__3_3_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
index 504f4aad7e682..be68cc327c9e6 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v3f32.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v4f32_v3f32__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -58,35 +61,45 @@ define void @v_shuffle_v4f32_v3f32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__1_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__1_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -99,33 +112,42 @@ define void @v_shuffle_v4f32_v3f32__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__2_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__2_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -149,35 +171,45 @@ define void @v_shuffle_v4f32_v3f32__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__4_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__4_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__4_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -191,33 +223,42 @@ define void @v_shuffle_v4f32_v3f32__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -238,6 +279,8 @@ define void @v_shuffle_v4f32_v3f32__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -253,6 +296,8 @@ define void @v_shuffle_v4f32_v3f32__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -267,8 +312,10 @@ define void @v_shuffle_v4f32_v3f32__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -283,43 +330,49 @@ define void @v_shuffle_v4f32_v3f32__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_1_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_1_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -333,14 +386,16 @@ define void @v_shuffle_v4f32_v3f32__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -350,12 +405,14 @@ define void @v_shuffle_v4f32_v3f32__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v3, v4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -365,12 +422,14 @@ define void @v_shuffle_v4f32_v3f32__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -384,37 +443,43 @@ define void @v_shuffle_v4f32_v3f32__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -428,37 +493,43 @@ define void @v_shuffle_v4f32_v3f32__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_4_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_4_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -472,37 +543,43 @@ define void @v_shuffle_v4f32_v3f32__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_5_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_5_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -518,12 +595,13 @@ define void @v_shuffle_v4f32_v3f32__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:2]
+; GFX900-NEXT: ; def v[4:6]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[4:6]
+; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v3, v2
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -533,12 +611,13 @@ define void @v_shuffle_v4f32_v3f32__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:2]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:6]
+; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v3, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -548,11 +627,12 @@ define void @v_shuffle_v4f32_v3f32__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:2]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:6]
+; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
@@ -577,6 +657,7 @@ define void @v_shuffle_v4f32_v3f32__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -593,6 +674,7 @@ define void @v_shuffle_v4f32_v3f32__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -609,6 +691,7 @@ define void @v_shuffle_v4f32_v3f32__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v3, v2
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -626,12 +709,13 @@ define void @v_shuffle_v4f32_v3f32__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:4]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -641,12 +725,13 @@ define void @v_shuffle_v4f32_v3f32__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -656,13 +741,14 @@ define void @v_shuffle_v4f32_v3f32__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -676,40 +762,43 @@ define void @v_shuffle_v4f32_v3f32__5_5_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_5_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_5_3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v0
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_5_3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v0
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -723,40 +812,43 @@ define void @v_shuffle_v4f32_v3f32__5_5_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_5_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_5_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_5_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v1
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -770,40 +862,43 @@ define void @v_shuffle_v4f32_v3f32__5_5_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__5_5_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_5_5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_5_5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v2
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -1824,32 +1919,35 @@ define void @v_shuffle_v4f32_v3f32__5_5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__5_5_u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v9, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:6]
+; GFX90A-NEXT: ; def v[6:8]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v9, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__5_5_u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v9, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:6]
+; GFX942-NEXT: ; def v[6:8]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: global_store_dwordx4 v9, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -2053,6 +2151,7 @@ define void @v_shuffle_v4f32_v3f32__5_5_4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
@@ -2069,6 +2168,7 @@ define void @v_shuffle_v4f32_v3f32__5_5_4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -3717,15 +3817,16 @@ define void @v_shuffle_v4f32_v3f32__5_5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:4]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -3733,15 +3834,16 @@ define void @v_shuffle_v4f32_v3f32__5_5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:4]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -3941,6 +4043,7 @@ define void @v_shuffle_v4f32_v3f32__5_5_4_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
@@ -3957,6 +4060,7 @@ define void @v_shuffle_v4f32_v3f32__5_5_4_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -3989,33 +4093,36 @@ define void @v_shuffle_v4f32_v3f32__0_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__0_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__0_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__0_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -4028,35 +4135,45 @@ define void @v_shuffle_v4f32_v3f32__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__1_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__1_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__1_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -4069,33 +4186,42 @@ define void @v_shuffle_v4f32_v3f32__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v3f32__2_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v3f32__2_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v3f32__2_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x float> asm "; def $0", "=v"()
@@ -6695,6 +6821,7 @@ define void @s_shuffle_v4f32_v3f32__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:10]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6706,6 +6833,7 @@ define void @s_shuffle_v4f32_v3f32__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:10]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -6717,6 +6845,7 @@ define void @s_shuffle_v4f32_v3f32__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:10]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6735,6 +6864,9 @@ define void @s_shuffle_v4f32_v3f32__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6747,6 +6879,9 @@ define void @s_shuffle_v4f32_v3f32__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6759,6 +6894,9 @@ define void @s_shuffle_v4f32_v3f32__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6777,6 +6915,9 @@ define void @s_shuffle_v4f32_v3f32__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6789,6 +6930,9 @@ define void @s_shuffle_v4f32_v3f32__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6801,6 +6945,9 @@ define void @s_shuffle_v4f32_v3f32__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6833,6 +6980,9 @@ define void @s_shuffle_v4f32_v3f32__4_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6845,6 +6995,9 @@ define void @s_shuffle_v4f32_v3f32__4_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6857,6 +7010,9 @@ define void @s_shuffle_v4f32_v3f32__4_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6876,6 +7032,9 @@ define void @s_shuffle_v4f32_v3f32__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6888,6 +7047,9 @@ define void @s_shuffle_v4f32_v3f32__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6900,6 +7062,9 @@ define void @s_shuffle_v4f32_v3f32__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6924,6 +7089,8 @@ define void @s_shuffle_v4f32_v3f32__5_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6940,6 +7107,8 @@ define void @s_shuffle_v4f32_v3f32__5_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -6956,6 +7125,8 @@ define void @s_shuffle_v4f32_v3f32__5_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -6978,6 +7149,8 @@ define void @s_shuffle_v4f32_v3f32__5_1_u_u() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6993,6 +7166,8 @@ define void @s_shuffle_v4f32_v3f32__5_1_u_u() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7008,6 +7183,8 @@ define void @s_shuffle_v4f32_v3f32__5_1_u_u() {
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7031,6 +7208,8 @@ define void @s_shuffle_v4f32_v3f32__5_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7047,6 +7226,8 @@ define void @s_shuffle_v4f32_v3f32__5_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7063,6 +7244,8 @@ define void @s_shuffle_v4f32_v3f32__5_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7083,6 +7266,8 @@ define void @s_shuffle_v4f32_v3f32__5_3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7096,6 +7281,8 @@ define void @s_shuffle_v4f32_v3f32__5_3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7109,6 +7296,8 @@ define void @s_shuffle_v4f32_v3f32__5_3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7127,7 +7316,9 @@ define void @s_shuffle_v4f32_v3f32__5_4_u_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:10]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: s_mov_b32 s8, s10
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -7148,6 +7339,8 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7161,6 +7354,8 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7174,6 +7369,8 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7198,6 +7395,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_0_u() {
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7215,6 +7413,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_0_u() {
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7232,6 +7431,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_0_u() {
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7256,6 +7456,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_1_u() {
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7273,6 +7474,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_1_u() {
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7290,6 +7492,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_1_u() {
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7313,6 +7516,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7329,6 +7533,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7345,6 +7550,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7366,6 +7572,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_3_u() {
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7380,6 +7587,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_3_u() {
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7394,6 +7602,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_3_u() {
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7415,6 +7624,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_4_u() {
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7429,6 +7639,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_4_u() {
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7443,6 +7654,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_4_u() {
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7463,6 +7675,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_5_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -7780,6 +7993,7 @@ define void @s_shuffle_v4f32_v3f32__u_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -7794,6 +8008,7 @@ define void @s_shuffle_v4f32_v3f32__u_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -7808,6 +8023,7 @@ define void @s_shuffle_v4f32_v3f32__u_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -7950,6 +8166,7 @@ define void @s_shuffle_v4f32_v3f32__3_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -7964,6 +8181,7 @@ define void @s_shuffle_v4f32_v3f32__3_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -7978,6 +8196,7 @@ define void @s_shuffle_v4f32_v3f32__3_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -8124,6 +8343,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_0_0() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8141,6 +8361,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_0_0() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8158,6 +8379,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_0_0() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8485,6 +8707,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_0() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -8502,6 +8725,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_0() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -8519,6 +8743,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_0() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -8999,6 +9224,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_1_1() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -9016,6 +9242,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_1_1() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -9033,6 +9260,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_1_1() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -9360,6 +9588,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -9377,6 +9606,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -9394,6 +9624,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10220,6 +10451,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10237,6 +10469,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10254,6 +10487,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10531,6 +10765,7 @@ define void @s_shuffle_v4f32_v3f32__0_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:10]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -10542,6 +10777,7 @@ define void @s_shuffle_v4f32_v3f32__0_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:10]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -10553,6 +10789,7 @@ define void @s_shuffle_v4f32_v3f32__0_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:10]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10571,6 +10808,9 @@ define void @s_shuffle_v4f32_v3f32__1_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10583,6 +10823,9 @@ define void @s_shuffle_v4f32_v3f32__1_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10595,6 +10838,9 @@ define void @s_shuffle_v4f32_v3f32__1_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10613,6 +10859,9 @@ define void @s_shuffle_v4f32_v3f32__2_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10625,6 +10874,9 @@ define void @s_shuffle_v4f32_v3f32__2_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10637,6 +10889,9 @@ define void @s_shuffle_v4f32_v3f32__2_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10773,6 +11028,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -10787,6 +11043,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -10801,6 +11058,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -11108,6 +11366,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11122,6 +11381,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11136,6 +11396,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11643,6 +11904,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
@@ -11657,6 +11919,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
@@ -11671,6 +11934,7 @@ define void @s_shuffle_v4f32_v3f32__5_u_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
@@ -11978,6 +12242,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11992,6 +12257,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -12006,6 +12272,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -12760,6 +13027,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_5() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -12774,6 +13042,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_5() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -12788,6 +13057,7 @@ define void @s_shuffle_v4f32_v3f32__5_5_u_5() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
index 5fdd57da3dab7..80e767fa049c2 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4f32.v4f32.ll
@@ -58,11 +58,14 @@ define void @v_shuffle_v4f32_v4f32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +77,9 @@ define void @v_shuffle_v4f32_v4f32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +92,9 @@ define void @v_shuffle_v4f32_v4f32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +108,42 @@ define void @v_shuffle_v4f32_v4f32__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v4f32__2_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v4f32__2_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -138,11 +156,14 @@ define void @v_shuffle_v4f32_v4f32__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +175,9 @@ define void @v_shuffle_v4f32_v4f32__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +190,9 @@ define void @v_shuffle_v4f32_v4f32__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -190,11 +217,14 @@ define void @v_shuffle_v4f32_v4f32__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -206,6 +236,9 @@ define void @v_shuffle_v4f32_v4f32__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +251,9 @@ define void @v_shuffle_v4f32_v4f32__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -232,33 +268,42 @@ define void @v_shuffle_v4f32_v4f32__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__6_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v4f32__6_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v4f32__6_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -272,11 +317,14 @@ define void @v_shuffle_v4f32_v4f32__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +336,9 @@ define void @v_shuffle_v4f32_v4f32__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +351,9 @@ define void @v_shuffle_v4f32_v4f32__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -321,6 +375,8 @@ define void @v_shuffle_v4f32_v4f32__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v8, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -331,11 +387,14 @@ define void @v_shuffle_v4f32_v4f32__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -346,10 +405,13 @@ define void @v_shuffle_v4f32_v4f32__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
@@ -373,6 +435,8 @@ define void @v_shuffle_v4f32_v4f32__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -388,6 +452,8 @@ define void @v_shuffle_v4f32_v4f32__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -402,6 +468,8 @@ define void @v_shuffle_v4f32_v4f32__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
@@ -418,14 +486,16 @@ define void @v_shuffle_v4f32_v4f32__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -439,7 +509,10 @@ define void @v_shuffle_v4f32_v4f32__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -454,8 +527,11 @@ define void @v_shuffle_v4f32_v4f32__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -470,14 +546,16 @@ define void @v_shuffle_v4f32_v4f32__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -492,6 +570,8 @@ define void @v_shuffle_v4f32_v4f32__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -506,6 +586,8 @@ define void @v_shuffle_v4f32_v4f32__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v7
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
@@ -522,12 +604,14 @@ define void @v_shuffle_v4f32_v4f32__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -539,6 +623,8 @@ define void @v_shuffle_v4f32_v4f32__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -551,6 +637,8 @@ define void @v_shuffle_v4f32_v4f32__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -565,12 +653,14 @@ define void @v_shuffle_v4f32_v4f32__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -582,6 +672,8 @@ define void @v_shuffle_v4f32_v4f32__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -594,6 +686,8 @@ define void @v_shuffle_v4f32_v4f32__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -608,12 +702,14 @@ define void @v_shuffle_v4f32_v4f32__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_6_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -625,6 +721,8 @@ define void @v_shuffle_v4f32_v4f32__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[2:3] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -637,6 +735,8 @@ define void @v_shuffle_v4f32_v4f32__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[2:3] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -651,12 +751,14 @@ define void @v_shuffle_v4f32_v4f32__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_7_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -666,9 +768,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -678,9 +782,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -696,12 +802,13 @@ define void @v_shuffle_v4f32_v4f32__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:3]
+; GFX900-NEXT: ; def v[5:8]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[5:8]
+; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v9, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -713,10 +820,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -728,10 +836,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -754,6 +863,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v8, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -770,6 +880,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -786,6 +897,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v5
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -808,6 +920,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -823,6 +936,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -837,6 +951,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
@@ -856,12 +971,13 @@ define void @v_shuffle_v4f32_v4f32__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -877,6 +993,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -893,6 +1010,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -907,13 +1025,14 @@ define void @v_shuffle_v4f32_v4f32__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_7_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v0
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -923,10 +1042,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v0
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -936,10 +1056,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v0
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -953,13 +1074,14 @@ define void @v_shuffle_v4f32_v4f32__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_7_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v1
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -969,10 +1091,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -982,10 +1105,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v1
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -999,13 +1123,14 @@ define void @v_shuffle_v4f32_v4f32__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_7_6_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v2
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -1018,6 +1143,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1031,6 +1157,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1045,13 +1172,14 @@ define void @v_shuffle_v4f32_v4f32__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__7_7_7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -1061,10 +1189,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v3
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1074,10 +1203,11 @@ define void @v_shuffle_v4f32_v4f32__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v3
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -1113,6 +1243,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_7_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -1129,6 +1260,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_7_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -1223,6 +1355,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_7_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -1236,6 +1369,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_7_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
@@ -2412,15 +2546,16 @@ define void @v_shuffle_v4f32_v4f32__7_7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[6:9]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2428,15 +2563,16 @@ define void @v_shuffle_v4f32_v4f32__7_7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[6:9]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -2696,6 +2832,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_5_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -2712,6 +2849,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_5_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -4961,15 +5099,16 @@ define void @v_shuffle_v4f32_v4f32__7_7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:5]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -4977,15 +5116,16 @@ define void @v_shuffle_v4f32_v4f32__7_7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:5]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -5242,6 +5382,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_5_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -5255,6 +5396,7 @@ define void @v_shuffle_v4f32_v4f32__7_7_5_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
@@ -6657,11 +6799,14 @@ define void @v_shuffle_v4f32_v4f32__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__1_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -6673,6 +6818,9 @@ define void @v_shuffle_v4f32_v4f32__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6685,6 +6833,9 @@ define void @v_shuffle_v4f32_v4f32__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6698,33 +6849,42 @@ define void @v_shuffle_v4f32_v4f32__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__2_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4f32_v4f32__2_4_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v4f32__2_4_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -6737,11 +6897,14 @@ define void @v_shuffle_v4f32_v4f32__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4f32_v4f32__3_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -6753,6 +6916,9 @@ define void @v_shuffle_v4f32_v4f32__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6765,6 +6931,9 @@ define void @v_shuffle_v4f32_v4f32__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7000,6 +7169,7 @@ define void @v_shuffle_v4f32_v4f32__7_0_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
@@ -7013,6 +7183,7 @@ define void @v_shuffle_v4f32_v4f32__7_0_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -7113,6 +7284,7 @@ define void @v_shuffle_v4f32_v4f32__7_2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
@@ -7129,6 +7301,7 @@ define void @v_shuffle_v4f32_v4f32__7_2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v3, v2
@@ -8246,6 +8419,7 @@ define void @v_shuffle_v4f32_v4f32__7_0_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -8259,6 +8433,7 @@ define void @v_shuffle_v4f32_v4f32__7_0_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -8359,6 +8534,7 @@ define void @v_shuffle_v4f32_v4f32__7_2_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
@@ -8375,6 +8551,7 @@ define void @v_shuffle_v4f32_v4f32__7_2_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -9489,6 +9666,7 @@ define void @v_shuffle_v4f32_v4f32__7_0_6_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v5, v4
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
@@ -9505,6 +9683,7 @@ define void @v_shuffle_v4f32_v4f32__7_0_6_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v5, v4
@@ -9597,12 +9776,13 @@ define void @v_shuffle_v4f32_v4f32__7_2_6_6(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v7, v6
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
@@ -9613,13 +9793,13 @@ define void @v_shuffle_v4f32_v4f32__7_2_6_6(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v7, v6
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
@@ -9849,28 +10029,31 @@ define void @v_shuffle_v4f32_v4f32__7_7_u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v4f32_v4f32__7_7_u_6:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v1, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v3
+; GFX90A-NEXT: v_mov_b32_e32 v9, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx4 v4, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4f32_v4f32__7_7_u_6:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v1, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v3
+; GFX942-NEXT: v_mov_b32_e32 v9, v2
+; GFX942-NEXT: global_store_dwordx4 v4, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x float> asm "; def $0", "=v"()
@@ -10698,6 +10881,7 @@ define void @v_shuffle_v4f32_v4f32__7_0_7_7(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
@@ -10714,6 +10898,7 @@ define void @v_shuffle_v4f32_v4f32__7_0_7_7(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v4, v5
@@ -10806,12 +10991,13 @@ define void @v_shuffle_v4f32_v4f32__7_2_7_7(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v6, v7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
@@ -10822,13 +11008,13 @@ define void @v_shuffle_v4f32_v4f32__7_2_7_7(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v6, v7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
@@ -11516,6 +11702,9 @@ define void @s_shuffle_v4f32_v4f32__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11528,6 +11717,9 @@ define void @s_shuffle_v4f32_v4f32__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11540,6 +11732,9 @@ define void @s_shuffle_v4f32_v4f32__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11558,6 +11753,9 @@ define void @s_shuffle_v4f32_v4f32__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11570,6 +11768,9 @@ define void @s_shuffle_v4f32_v4f32__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11582,6 +11783,9 @@ define void @s_shuffle_v4f32_v4f32__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11600,6 +11804,9 @@ define void @s_shuffle_v4f32_v4f32__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11612,6 +11819,9 @@ define void @s_shuffle_v4f32_v4f32__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11624,6 +11834,9 @@ define void @s_shuffle_v4f32_v4f32__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11656,6 +11869,9 @@ define void @s_shuffle_v4f32_v4f32__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11668,6 +11884,9 @@ define void @s_shuffle_v4f32_v4f32__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11680,6 +11899,9 @@ define void @s_shuffle_v4f32_v4f32__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11699,6 +11921,9 @@ define void @s_shuffle_v4f32_v4f32__6_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11711,6 +11936,9 @@ define void @s_shuffle_v4f32_v4f32__6_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11723,6 +11951,9 @@ define void @s_shuffle_v4f32_v4f32__6_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11742,6 +11973,9 @@ define void @s_shuffle_v4f32_v4f32__7_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11754,6 +11988,9 @@ define void @s_shuffle_v4f32_v4f32__7_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11766,6 +12003,9 @@ define void @s_shuffle_v4f32_v4f32__7_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11790,6 +12030,8 @@ define void @s_shuffle_v4f32_v4f32__7_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11806,6 +12048,8 @@ define void @s_shuffle_v4f32_v4f32__7_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11822,6 +12066,8 @@ define void @s_shuffle_v4f32_v4f32__7_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11844,6 +12090,8 @@ define void @s_shuffle_v4f32_v4f32__7_1_u_u() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11859,6 +12107,8 @@ define void @s_shuffle_v4f32_v4f32__7_1_u_u() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11874,6 +12124,8 @@ define void @s_shuffle_v4f32_v4f32__7_1_u_u() {
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11897,6 +12149,8 @@ define void @s_shuffle_v4f32_v4f32__7_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11913,6 +12167,8 @@ define void @s_shuffle_v4f32_v4f32__7_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11929,6 +12185,8 @@ define void @s_shuffle_v4f32_v4f32__7_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11952,6 +12210,8 @@ define void @s_shuffle_v4f32_v4f32__7_3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11968,6 +12228,8 @@ define void @s_shuffle_v4f32_v4f32__7_3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11984,6 +12246,8 @@ define void @s_shuffle_v4f32_v4f32__7_3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12004,6 +12268,8 @@ define void @s_shuffle_v4f32_v4f32__7_4_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12017,6 +12283,8 @@ define void @s_shuffle_v4f32_v4f32__7_4_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12030,6 +12298,8 @@ define void @s_shuffle_v4f32_v4f32__7_4_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12049,6 +12319,8 @@ define void @s_shuffle_v4f32_v4f32__7_5_u_u() {
; GFX9-NEXT: ; def s[8:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
+; GFX9-NEXT: ; implicit-def: $sgpr10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -12069,6 +12341,8 @@ define void @s_shuffle_v4f32_v4f32__7_6_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12082,6 +12356,8 @@ define void @s_shuffle_v4f32_v4f32__7_6_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12095,6 +12371,8 @@ define void @s_shuffle_v4f32_v4f32__7_6_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12115,6 +12393,8 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12128,6 +12408,8 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12141,6 +12423,8 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12165,6 +12449,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_0_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12182,6 +12467,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_0_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12199,6 +12485,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_0_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12223,6 +12510,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_1_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12240,6 +12528,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_1_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12257,6 +12546,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_1_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12280,6 +12570,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12296,6 +12587,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12312,6 +12604,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12336,6 +12629,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_3_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12353,6 +12647,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_3_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12370,6 +12665,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_3_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12391,6 +12687,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_4_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12405,6 +12702,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_4_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12419,6 +12717,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_4_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12440,6 +12739,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_5_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12454,6 +12754,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_5_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12468,6 +12769,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_5_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12488,6 +12790,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_6_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -12509,6 +12812,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_7_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12523,6 +12827,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_7_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12537,6 +12842,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_7_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12973,6 +13279,7 @@ define void @s_shuffle_v4f32_v4f32__u_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -12987,6 +13294,7 @@ define void @s_shuffle_v4f32_v4f32__u_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -13001,6 +13309,7 @@ define void @s_shuffle_v4f32_v4f32__u_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -13194,6 +13503,7 @@ define void @s_shuffle_v4f32_v4f32__4_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -13208,6 +13518,7 @@ define void @s_shuffle_v4f32_v4f32__4_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -13222,6 +13533,7 @@ define void @s_shuffle_v4f32_v4f32__4_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -13429,6 +13741,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_0_0() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -13446,6 +13759,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_0_0() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -13463,6 +13777,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_0_0() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -13912,6 +14227,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_0() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -13929,6 +14245,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_0() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -13946,6 +14263,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_0() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -14623,6 +14941,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_1_1() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -14640,6 +14959,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_1_1() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -14657,6 +14977,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_1_1() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -15106,6 +15427,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -15123,6 +15445,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -15140,6 +15463,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -16279,6 +16603,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -16296,6 +16621,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -16313,6 +16639,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17907,6 +18234,9 @@ define void @s_shuffle_v4f32_v4f32__1_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -17919,6 +18249,9 @@ define void @s_shuffle_v4f32_v4f32__1_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -17931,6 +18264,9 @@ define void @s_shuffle_v4f32_v4f32__1_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17949,6 +18285,9 @@ define void @s_shuffle_v4f32_v4f32__2_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -17961,6 +18300,9 @@ define void @s_shuffle_v4f32_v4f32__2_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -17973,6 +18315,9 @@ define void @s_shuffle_v4f32_v4f32__2_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17991,6 +18336,9 @@ define void @s_shuffle_v4f32_v4f32__3_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -18003,6 +18351,9 @@ define void @s_shuffle_v4f32_v4f32__3_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -18015,6 +18366,9 @@ define void @s_shuffle_v4f32_v4f32__3_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -18203,6 +18557,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -18217,6 +18572,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -18231,6 +18587,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -18651,6 +19008,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -18665,6 +19023,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -18679,6 +19038,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -19378,6 +19738,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_5_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
@@ -19392,6 +19753,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_5_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
@@ -19406,6 +19768,7 @@ define void @s_shuffle_v4f32_v4f32__7_u_5_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
@@ -19826,6 +20189,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_5() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -19840,6 +20204,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_5() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -19854,6 +20219,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_5() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -20900,6 +21266,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_6() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -20914,6 +21281,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_6() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -20928,6 +21296,7 @@ define void @s_shuffle_v4f32_v4f32__7_7_u_6() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
index c985c06900ff8..5d74f7f761db6 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v2i16.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v4i16_v2i16__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i16_v2i16__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i16_v2i16__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i16_v2i16__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -61,9 +64,10 @@ define void @v_shuffle_v4i16_v2i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -73,9 +77,10 @@ define void @v_shuffle_v4i16_v2i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -85,9 +90,10 @@ define void @v_shuffle_v4i16_v2i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -114,9 +120,10 @@ define void @v_shuffle_v4i16_v2i16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -126,9 +133,10 @@ define void @v_shuffle_v4i16_v2i16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -138,9 +146,10 @@ define void @v_shuffle_v4i16_v2i16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -157,12 +166,13 @@ define void @v_shuffle_v4i16_v2i16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v2
+; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -172,12 +182,13 @@ define void @v_shuffle_v4i16_v2i16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v2
+; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -187,13 +198,14 @@ define void @v_shuffle_v4i16_v2i16__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v2
+; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_alignbit_b32 v0, v0, v2, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -211,12 +223,13 @@ define void @v_shuffle_v4i16_v2i16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v2
+; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -227,12 +240,13 @@ define void @v_shuffle_v4i16_v2i16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v2
+; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -243,13 +257,14 @@ define void @v_shuffle_v4i16_v2i16__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v2
+; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_perm_b32 v0, v0, v2, s2
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -266,9 +281,10 @@ define void @v_shuffle_v4i16_v2i16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -278,9 +294,10 @@ define void @v_shuffle_v4i16_v2i16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -290,9 +307,10 @@ define void @v_shuffle_v4i16_v2i16__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -310,9 +328,10 @@ define void @v_shuffle_v4i16_v2i16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v0, s4
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -323,9 +342,10 @@ define void @v_shuffle_v4i16_v2i16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v0, s4
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -336,9 +356,10 @@ define void @v_shuffle_v4i16_v2i16__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v0, s2
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -2100,33 +2121,36 @@ define void @v_shuffle_v4i16_v2i16__0_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i16_v2i16__0_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i16_v2i16__0_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i16_v2i16__0_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -2142,9 +2166,10 @@ define void @v_shuffle_v4i16_v2i16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v0
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX900-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr1
+; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -2154,9 +2179,10 @@ define void @v_shuffle_v4i16_v2i16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v0
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
-; GFX90A-NEXT: global_store_dwordx2 v1, v[0:1], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2166,9 +2192,10 @@ define void @v_shuffle_v4i16_v2i16__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
-; GFX942-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i16> asm "; def $0", "=v"()
@@ -3290,6 +3317,7 @@ define void @s_shuffle_v4i16_v2i16__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3301,6 +3329,7 @@ define void @s_shuffle_v4i16_v2i16__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3312,6 +3341,7 @@ define void @s_shuffle_v4i16_v2i16__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3330,6 +3360,7 @@ define void @s_shuffle_v4i16_v2i16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3342,6 +3373,7 @@ define void @s_shuffle_v4i16_v2i16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3354,6 +3386,7 @@ define void @s_shuffle_v4i16_v2i16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3386,6 +3419,7 @@ define void @s_shuffle_v4i16_v2i16__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3398,6 +3432,7 @@ define void @s_shuffle_v4i16_v2i16__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3410,6 +3445,7 @@ define void @s_shuffle_v4i16_v2i16__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3434,6 +3470,7 @@ define void @s_shuffle_v4i16_v2i16__3_0_u_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3450,6 +3487,7 @@ define void @s_shuffle_v4i16_v2i16__3_0_u_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3466,6 +3504,7 @@ define void @s_shuffle_v4i16_v2i16__3_0_u_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -3488,6 +3527,7 @@ define void @s_shuffle_v4i16_v2i16__3_1_u_u() {
; GFX900-NEXT: ; def s5
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -3503,6 +3543,7 @@ define void @s_shuffle_v4i16_v2i16__3_1_u_u() {
; GFX90A-NEXT: ; def s5
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -3518,6 +3559,7 @@ define void @s_shuffle_v4i16_v2i16__3_1_u_u() {
; GFX942-NEXT: ; def s1
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -3537,6 +3579,7 @@ define void @s_shuffle_v4i16_v2i16__3_2_u_u() {
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s4, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3550,6 +3593,7 @@ define void @s_shuffle_v4i16_v2i16__3_2_u_u() {
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s4, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3563,6 +3607,7 @@ define void @s_shuffle_v4i16_v2i16__3_2_u_u() {
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s0, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -3582,6 +3627,7 @@ define void @s_shuffle_v4i16_v2i16__3_3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s4, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -3594,6 +3640,7 @@ define void @s_shuffle_v4i16_v2i16__3_3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s4, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -3606,6 +3653,7 @@ define void @s_shuffle_v4i16_v2i16__3_3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5190,6 +5238,7 @@ define void @s_shuffle_v4i16_v2i16__0_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s8
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -5201,6 +5250,7 @@ define void @s_shuffle_v4i16_v2i16__0_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s8
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -5212,6 +5262,7 @@ define void @s_shuffle_v4i16_v2i16__0_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s8
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -5230,6 +5281,7 @@ define void @s_shuffle_v4i16_v2i16__1_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s4
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -5242,6 +5294,7 @@ define void @s_shuffle_v4i16_v2i16__1_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s4
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -5254,6 +5307,7 @@ define void @s_shuffle_v4i16_v2i16__1_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
index 1a7e281e7e138..8fed3a21e60bc 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v3i16.ll
@@ -65,6 +65,7 @@ define void @v_shuffle_v4i16_v3i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -77,6 +78,7 @@ define void @v_shuffle_v4i16_v3i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -89,6 +91,7 @@ define void @v_shuffle_v4i16_v3i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -103,11 +106,12 @@ define void @v_shuffle_v4i16_v3i16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i16_v3i16__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -119,6 +123,7 @@ define void @v_shuffle_v4i16_v3i16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -131,6 +136,7 @@ define void @v_shuffle_v4i16_v3i16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -162,6 +168,7 @@ define void @v_shuffle_v4i16_v3i16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -174,6 +181,7 @@ define void @v_shuffle_v4i16_v3i16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -186,6 +194,7 @@ define void @v_shuffle_v4i16_v3i16__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -202,11 +211,12 @@ define void @v_shuffle_v4i16_v3i16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i16_v3i16__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -218,6 +228,7 @@ define void @v_shuffle_v4i16_v3i16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -230,6 +241,7 @@ define void @v_shuffle_v4i16_v3i16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -255,6 +267,7 @@ define void @v_shuffle_v4i16_v3i16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -271,6 +284,7 @@ define void @v_shuffle_v4i16_v3i16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -286,6 +300,7 @@ define void @v_shuffle_v4i16_v3i16__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v0, v3, s2
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -313,6 +328,7 @@ define void @v_shuffle_v4i16_v3i16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -329,6 +345,7 @@ define void @v_shuffle_v4i16_v3i16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_bfi_b32 v0, s4, v3, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -344,6 +361,7 @@ define void @v_shuffle_v4i16_v3i16__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_bfi_b32 v0, s2, v3, v0
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -371,6 +389,7 @@ define void @v_shuffle_v4i16_v3i16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -387,6 +406,7 @@ define void @v_shuffle_v4i16_v3i16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -404,6 +424,7 @@ define void @v_shuffle_v4i16_v3i16__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v1, v3, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -426,6 +447,7 @@ define void @v_shuffle_v4i16_v3i16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -439,6 +461,7 @@ define void @v_shuffle_v4i16_v3i16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x5040100
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -452,6 +475,7 @@ define void @v_shuffle_v4i16_v3i16__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x5040100
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -474,6 +498,7 @@ define void @v_shuffle_v4i16_v3i16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0xffff
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -487,6 +512,7 @@ define void @v_shuffle_v4i16_v3i16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0xffff
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_bfi_b32 v0, s4, v1, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -500,6 +526,7 @@ define void @v_shuffle_v4i16_v3i16__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0xffff
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_bfi_b32 v0, s2, v1, v0
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -522,6 +549,7 @@ define void @v_shuffle_v4i16_v3i16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -535,6 +563,7 @@ define void @v_shuffle_v4i16_v3i16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x5040100
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -548,6 +577,7 @@ define void @v_shuffle_v4i16_v3i16__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x5040100
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v1, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4412,6 +4442,7 @@ define void @v_shuffle_v4i16_v3i16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4424,6 +4455,7 @@ define void @v_shuffle_v4i16_v3i16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4436,6 +4468,7 @@ define void @v_shuffle_v4i16_v3i16__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4450,11 +4483,12 @@ define void @v_shuffle_v4i16_v3i16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i16_v3i16__2_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -4466,6 +4500,7 @@ define void @v_shuffle_v4i16_v3i16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4478,6 +4513,7 @@ define void @v_shuffle_v4i16_v3i16__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7339,6 +7375,7 @@ define void @s_shuffle_v4i16_v3i16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7351,6 +7388,7 @@ define void @s_shuffle_v4i16_v3i16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7363,6 +7401,7 @@ define void @s_shuffle_v4i16_v3i16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7382,6 +7421,7 @@ define void @s_shuffle_v4i16_v3i16__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7394,6 +7434,7 @@ define void @s_shuffle_v4i16_v3i16__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7406,6 +7447,7 @@ define void @s_shuffle_v4i16_v3i16__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7440,6 +7482,7 @@ define void @s_shuffle_v4i16_v3i16__4_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7452,6 +7495,7 @@ define void @s_shuffle_v4i16_v3i16__4_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7464,6 +7508,7 @@ define void @s_shuffle_v4i16_v3i16__4_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7485,6 +7530,7 @@ define void @s_shuffle_v4i16_v3i16__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7497,6 +7543,7 @@ define void @s_shuffle_v4i16_v3i16__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7509,6 +7556,7 @@ define void @s_shuffle_v4i16_v3i16__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7534,6 +7582,7 @@ define void @s_shuffle_v4i16_v3i16__5_0_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7549,6 +7598,7 @@ define void @s_shuffle_v4i16_v3i16__5_0_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7564,6 +7614,7 @@ define void @s_shuffle_v4i16_v3i16__5_0_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7588,6 +7639,7 @@ define void @s_shuffle_v4i16_v3i16__5_1_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_lh_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7603,6 +7655,7 @@ define void @s_shuffle_v4i16_v3i16__5_1_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_lh_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7618,6 +7671,7 @@ define void @s_shuffle_v4i16_v3i16__5_1_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_lh_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7642,6 +7696,7 @@ define void @s_shuffle_v4i16_v3i16__5_2_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -7657,6 +7712,7 @@ define void @s_shuffle_v4i16_v3i16__5_2_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s7, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -7672,6 +7728,7 @@ define void @s_shuffle_v4i16_v3i16__5_2_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s3, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -7692,6 +7749,7 @@ define void @s_shuffle_v4i16_v3i16__5_3_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7704,6 +7762,7 @@ define void @s_shuffle_v4i16_v3i16__5_3_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7716,6 +7775,7 @@ define void @s_shuffle_v4i16_v3i16__5_3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7737,6 +7797,7 @@ define void @s_shuffle_v4i16_v3i16__5_4_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_lh_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7749,6 +7810,7 @@ define void @s_shuffle_v4i16_v3i16__5_4_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_lh_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7761,6 +7823,7 @@ define void @s_shuffle_v4i16_v3i16__5_4_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_lh_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -7782,6 +7845,7 @@ define void @s_shuffle_v4i16_v3i16__5_5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -7794,6 +7858,7 @@ define void @s_shuffle_v4i16_v3i16__5_5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -7806,6 +7871,7 @@ define void @s_shuffle_v4i16_v3i16__5_5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -11339,6 +11405,7 @@ define void @s_shuffle_v4i16_v3i16__1_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -11351,6 +11418,7 @@ define void @s_shuffle_v4i16_v3i16__1_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -11363,6 +11431,7 @@ define void @s_shuffle_v4i16_v3i16__1_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -11382,6 +11451,7 @@ define void @s_shuffle_v4i16_v3i16__2_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -11394,6 +11464,7 @@ define void @s_shuffle_v4i16_v3i16__2_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -11406,6 +11477,7 @@ define void @s_shuffle_v4i16_v3i16__2_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
index 05ebf49b997eb..0cede6383db5d 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i16.v4i16.ll
@@ -63,6 +63,7 @@ define void @v_shuffle_v4i16_v4i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -75,6 +76,7 @@ define void @v_shuffle_v4i16_v4i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +89,7 @@ define void @v_shuffle_v4i16_v4i16__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -100,11 +103,12 @@ define void @v_shuffle_v4i16_v4i16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i16_v4i16__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -116,6 +120,7 @@ define void @v_shuffle_v4i16_v4i16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -128,6 +133,7 @@ define void @v_shuffle_v4i16_v4i16__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -146,6 +152,7 @@ define void @v_shuffle_v4i16_v4i16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -158,6 +165,7 @@ define void @v_shuffle_v4i16_v4i16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -170,6 +178,7 @@ define void @v_shuffle_v4i16_v4i16__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -199,6 +208,7 @@ define void @v_shuffle_v4i16_v4i16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -211,6 +221,7 @@ define void @v_shuffle_v4i16_v4i16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -223,6 +234,7 @@ define void @v_shuffle_v4i16_v4i16__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -237,11 +249,12 @@ define void @v_shuffle_v4i16_v4i16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i16_v4i16__6_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -253,6 +266,7 @@ define void @v_shuffle_v4i16_v4i16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -265,6 +279,7 @@ define void @v_shuffle_v4i16_v4i16__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -284,6 +299,7 @@ define void @v_shuffle_v4i16_v4i16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -296,6 +312,7 @@ define void @v_shuffle_v4i16_v4i16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -308,6 +325,7 @@ define void @v_shuffle_v4i16_v4i16__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -330,6 +348,7 @@ define void @v_shuffle_v4i16_v4i16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_alignbit_b32 v0, v0, v2, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -345,6 +364,7 @@ define void @v_shuffle_v4i16_v4i16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -359,6 +379,7 @@ define void @v_shuffle_v4i16_v4i16__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -384,6 +405,7 @@ define void @v_shuffle_v4i16_v4i16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v3, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -400,6 +422,7 @@ define void @v_shuffle_v4i16_v4i16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -415,6 +438,7 @@ define void @v_shuffle_v4i16_v4i16__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v0, v3, s2
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
@@ -439,6 +463,7 @@ define void @v_shuffle_v4i16_v4i16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -454,6 +479,7 @@ define void @v_shuffle_v4i16_v4i16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -470,6 +496,7 @@ define void @v_shuffle_v4i16_v4i16__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_alignbit_b32 v0, v1, v3, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -493,6 +520,7 @@ define void @v_shuffle_v4i16_v4i16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -509,6 +537,7 @@ define void @v_shuffle_v4i16_v4i16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_perm_b32 v0, v1, v3, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v4, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -526,6 +555,7 @@ define void @v_shuffle_v4i16_v4i16__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_perm_b32 v0, v1, v3, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -545,6 +575,7 @@ define void @v_shuffle_v4i16_v4i16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -557,6 +588,7 @@ define void @v_shuffle_v4i16_v4i16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -569,6 +601,7 @@ define void @v_shuffle_v4i16_v4i16__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -589,6 +622,7 @@ define void @v_shuffle_v4i16_v4i16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -602,6 +636,7 @@ define void @v_shuffle_v4i16_v4i16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -615,6 +650,7 @@ define void @v_shuffle_v4i16_v4i16__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v0, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -634,6 +670,7 @@ define void @v_shuffle_v4i16_v4i16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -646,6 +683,7 @@ define void @v_shuffle_v4i16_v4i16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -658,6 +696,7 @@ define void @v_shuffle_v4i16_v4i16__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, v1, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -678,6 +717,7 @@ define void @v_shuffle_v4i16_v4i16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_mov_b32 s4, 0x7060302
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -691,6 +731,7 @@ define void @v_shuffle_v4i16_v4i16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_mov_b32 s4, 0x7060302
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_perm_b32 v0, v1, v1, s4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -704,6 +745,7 @@ define void @v_shuffle_v4i16_v4i16__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_mov_b32 s2, 0x7060302
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_perm_b32 v0, v1, v1, s2
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7045,6 +7087,7 @@ define void @v_shuffle_v4i16_v4i16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7057,6 +7100,7 @@ define void @v_shuffle_v4i16_v4i16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v0, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7069,6 +7113,7 @@ define void @v_shuffle_v4i16_v4i16__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7082,11 +7127,12 @@ define void @v_shuffle_v4i16_v4i16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i16_v4i16__2_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx2 v2, v[1:2], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: global_store_dwordx2 v3, v[1:2], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -7098,6 +7144,7 @@ define void @v_shuffle_v4i16_v4i16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7110,6 +7157,7 @@ define void @v_shuffle_v4i16_v4i16__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7128,6 +7176,7 @@ define void @v_shuffle_v4i16_v4i16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX900-NEXT: ; implicit-def: $vgpr1
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7140,6 +7189,7 @@ define void @v_shuffle_v4i16_v4i16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_alignbit_b32 v0, s4, v1, 16
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7152,6 +7202,7 @@ define void @v_shuffle_v4i16_v4i16__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_alignbit_b32 v0, s0, v1, 16
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -12151,6 +12202,7 @@ define void @s_shuffle_v4i16_v4i16__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12163,6 +12215,7 @@ define void @s_shuffle_v4i16_v4i16__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12175,6 +12228,7 @@ define void @s_shuffle_v4i16_v4i16__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12193,6 +12247,7 @@ define void @s_shuffle_v4i16_v4i16__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12205,6 +12260,7 @@ define void @s_shuffle_v4i16_v4i16__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12217,6 +12273,7 @@ define void @s_shuffle_v4i16_v4i16__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12235,6 +12292,7 @@ define void @s_shuffle_v4i16_v4i16__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12247,6 +12305,7 @@ define void @s_shuffle_v4i16_v4i16__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12259,6 +12318,7 @@ define void @s_shuffle_v4i16_v4i16__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12291,6 +12351,7 @@ define void @s_shuffle_v4i16_v4i16__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12303,6 +12364,7 @@ define void @s_shuffle_v4i16_v4i16__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12315,6 +12377,7 @@ define void @s_shuffle_v4i16_v4i16__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12334,6 +12397,7 @@ define void @s_shuffle_v4i16_v4i16__6_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12346,6 +12410,7 @@ define void @s_shuffle_v4i16_v4i16__6_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12358,6 +12423,7 @@ define void @s_shuffle_v4i16_v4i16__6_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12377,6 +12443,7 @@ define void @s_shuffle_v4i16_v4i16__7_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12389,6 +12456,7 @@ define void @s_shuffle_v4i16_v4i16__7_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12401,6 +12469,7 @@ define void @s_shuffle_v4i16_v4i16__7_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12425,6 +12494,7 @@ define void @s_shuffle_v4i16_v4i16__7_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12441,6 +12511,7 @@ define void @s_shuffle_v4i16_v4i16__7_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12457,6 +12528,7 @@ define void @s_shuffle_v4i16_v4i16__7_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12479,6 +12551,7 @@ define void @s_shuffle_v4i16_v4i16__7_1_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s7, s4
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12494,6 +12567,7 @@ define void @s_shuffle_v4i16_v4i16__7_1_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s7, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12509,6 +12583,7 @@ define void @s_shuffle_v4i16_v4i16__7_1_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s3, s0
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12532,6 +12607,7 @@ define void @s_shuffle_v4i16_v4i16__7_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s7, 16
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12548,6 +12624,7 @@ define void @s_shuffle_v4i16_v4i16__7_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s7, 16
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12564,6 +12641,7 @@ define void @s_shuffle_v4i16_v4i16__7_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s3, 16
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12586,6 +12664,7 @@ define void @s_shuffle_v4i16_v4i16__7_3_u_u() {
; GFX900-NEXT: ; def s[6:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s7, s5
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
; GFX900-NEXT: ;;#ASMEND
@@ -12601,6 +12680,7 @@ define void @s_shuffle_v4i16_v4i16__7_3_u_u() {
; GFX90A-NEXT: ; def s[6:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s7, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
; GFX90A-NEXT: ;;#ASMEND
@@ -12616,6 +12696,7 @@ define void @s_shuffle_v4i16_v4i16__7_3_u_u() {
; GFX942-NEXT: ; def s[2:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s3, s1
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
; GFX942-NEXT: ;;#ASMEND
@@ -12635,6 +12716,7 @@ define void @s_shuffle_v4i16_v4i16__7_4_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s5, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12648,6 +12730,7 @@ define void @s_shuffle_v4i16_v4i16__7_4_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s5, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12661,6 +12744,7 @@ define void @s_shuffle_v4i16_v4i16__7_4_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s1, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12680,6 +12764,7 @@ define void @s_shuffle_v4i16_v4i16__7_5_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s5, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12692,6 +12777,7 @@ define void @s_shuffle_v4i16_v4i16__7_5_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s5, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12704,6 +12790,7 @@ define void @s_shuffle_v4i16_v4i16__7_5_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s1, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12724,6 +12811,7 @@ define void @s_shuffle_v4i16_v4i16__7_6_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_lshr_b32 s4, s5, 16
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12737,6 +12825,7 @@ define void @s_shuffle_v4i16_v4i16__7_6_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_lshr_b32 s4, s5, 16
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_ll_b32_b16 s8, s4, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12750,6 +12839,7 @@ define void @s_shuffle_v4i16_v4i16__7_6_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_lshr_b32 s0, s1, 16
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_ll_b32_b16 s8, s0, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -12769,6 +12859,7 @@ define void @s_shuffle_v4i16_v4i16__7_7_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_pack_hh_b32_b16 s8, s5, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -12781,6 +12872,7 @@ define void @s_shuffle_v4i16_v4i16__7_7_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_pack_hh_b32_b16 s8, s5, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -12793,6 +12885,7 @@ define void @s_shuffle_v4i16_v4i16__7_7_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_pack_hh_b32_b16 s8, s1, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -18693,6 +18786,7 @@ define void @s_shuffle_v4i16_v4i16__1_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s4, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -18705,6 +18799,7 @@ define void @s_shuffle_v4i16_v4i16__1_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s4, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -18717,6 +18812,7 @@ define void @s_shuffle_v4i16_v4i16__1_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s0, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -18735,6 +18831,7 @@ define void @s_shuffle_v4i16_v4i16__2_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -18747,6 +18844,7 @@ define void @s_shuffle_v4i16_v4i16__2_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -18759,6 +18857,7 @@ define void @s_shuffle_v4i16_v4i16__2_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
@@ -18777,6 +18876,7 @@ define void @s_shuffle_v4i16_v4i16__3_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_lshr_b32 s8, s5, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:9]
@@ -18789,6 +18889,7 @@ define void @s_shuffle_v4i16_v4i16__3_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_lshr_b32 s8, s5, 16
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:9]
@@ -18801,6 +18902,7 @@ define void @s_shuffle_v4i16_v4i16__3_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_lshr_b32 s8, s1, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
index ad2dd3a8f8073..8f8087ffa2e05 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v2i32.ll
@@ -19,33 +19,39 @@ define void @v_shuffle_v4i32_v2i32__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v2i32__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v2i32__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -58,35 +64,45 @@ define void @v_shuffle_v4i32_v2i32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v2i32__1_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v2i32__1_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -110,35 +126,45 @@ define void @v_shuffle_v4i32_v2i32__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v2i32__3_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v2i32__3_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -152,14 +178,16 @@ define void @v_shuffle_v4i32_v2i32__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__3_0_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -174,6 +202,8 @@ define void @v_shuffle_v4i32_v2i32__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -190,6 +220,8 @@ define void @v_shuffle_v4i32_v2i32__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -204,14 +236,16 @@ define void @v_shuffle_v4i32_v2i32__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__3_1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -226,6 +260,8 @@ define void @v_shuffle_v4i32_v2i32__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -240,8 +276,10 @@ define void @v_shuffle_v4i32_v2i32__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -256,12 +294,14 @@ define void @v_shuffle_v4i32_v2i32__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__3_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v0
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -274,6 +314,8 @@ define void @v_shuffle_v4i32_v2i32__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -285,6 +327,8 @@ define void @v_shuffle_v4i32_v2i32__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v0
@@ -302,12 +346,14 @@ define void @v_shuffle_v4i32_v2i32__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__3_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -317,9 +363,11 @@ define void @v_shuffle_v4i32_v2i32__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -329,9 +377,11 @@ define void @v_shuffle_v4i32_v2i32__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -347,12 +397,13 @@ define void @v_shuffle_v4i32_v2i32__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:1]
+; GFX900-NEXT: ; def v[3:4]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[3:4]
+; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v2, v1
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -364,10 +415,11 @@ define void @v_shuffle_v4i32_v2i32__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -379,10 +431,11 @@ define void @v_shuffle_v4i32_v2i32__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -400,12 +453,13 @@ define void @v_shuffle_v4i32_v2i32__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -421,6 +475,7 @@ define void @v_shuffle_v4i32_v2i32__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -437,6 +492,7 @@ define void @v_shuffle_v4i32_v2i32__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -451,13 +507,14 @@ define void @v_shuffle_v4i32_v2i32__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__3_3_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -470,6 +527,7 @@ define void @v_shuffle_v4i32_v2i32__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -484,6 +542,7 @@ define void @v_shuffle_v4i32_v2i32__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -498,13 +557,14 @@ define void @v_shuffle_v4i32_v2i32__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__3_3_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -514,10 +574,11 @@ define void @v_shuffle_v4i32_v2i32__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -527,10 +588,11 @@ define void @v_shuffle_v4i32_v2i32__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -1232,15 +1294,16 @@ define void @v_shuffle_v4i32_v2i32__3_3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:1]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1248,15 +1311,16 @@ define void @v_shuffle_v4i32_v2i32__3_3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:3]
+; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:1]
+; GFX942-NEXT: ; def v[4:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -2015,33 +2079,39 @@ define void @v_shuffle_v4i32_v2i32__0_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__0_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v2i32__0_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v2i32__0_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -2054,35 +2124,45 @@ define void @v_shuffle_v4i32_v2i32__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v2i32__1_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v2i32__1_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v2i32__1_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i32> asm "; def $0", "=v"()
@@ -2378,6 +2458,7 @@ define void @v_shuffle_v4i32_v2i32__3_3_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v1
; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2389,6 +2470,7 @@ define void @v_shuffle_v4i32_v2i32__3_3_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v1
@@ -3152,6 +3234,8 @@ define void @s_shuffle_v4i32_v2i32__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3163,6 +3247,8 @@ define void @s_shuffle_v4i32_v2i32__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3174,6 +3260,8 @@ define void @s_shuffle_v4i32_v2i32__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3192,6 +3280,9 @@ define void @s_shuffle_v4i32_v2i32__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -3204,6 +3295,9 @@ define void @s_shuffle_v4i32_v2i32__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -3216,6 +3310,9 @@ define void @s_shuffle_v4i32_v2i32__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3248,6 +3345,9 @@ define void @s_shuffle_v4i32_v2i32__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -3260,6 +3360,9 @@ define void @s_shuffle_v4i32_v2i32__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -3272,6 +3375,9 @@ define void @s_shuffle_v4i32_v2i32__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3296,6 +3402,8 @@ define void @s_shuffle_v4i32_v2i32__3_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3312,6 +3420,8 @@ define void @s_shuffle_v4i32_v2i32__3_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3328,6 +3438,8 @@ define void @s_shuffle_v4i32_v2i32__3_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3350,6 +3462,8 @@ define void @s_shuffle_v4i32_v2i32__3_1_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3365,6 +3479,8 @@ define void @s_shuffle_v4i32_v2i32__3_1_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3380,6 +3496,8 @@ define void @s_shuffle_v4i32_v2i32__3_1_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3400,6 +3518,8 @@ define void @s_shuffle_v4i32_v2i32__3_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3413,6 +3533,8 @@ define void @s_shuffle_v4i32_v2i32__3_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3426,6 +3548,8 @@ define void @s_shuffle_v4i32_v2i32__3_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3444,6 +3568,8 @@ define void @s_shuffle_v4i32_v2i32__3_3_u_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
@@ -3461,12 +3587,13 @@ define void @s_shuffle_v4i32_v2i32__3_3_0_u() {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[8:9]
+; GFX9-NEXT: ; def s[10:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[10:11]
+; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s9
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -3490,6 +3617,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s9
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3506,6 +3634,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s9
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3522,6 +3651,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s9
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3542,6 +3672,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_2_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -3562,6 +3693,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_3_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: s_mov_b32 s10, s9
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -4070,6 +4202,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_u_0() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4086,6 +4219,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_u_0() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4102,6 +4236,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_u_0() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4682,6 +4817,8 @@ define void @s_shuffle_v4i32_v2i32__0_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -4693,6 +4830,8 @@ define void @s_shuffle_v4i32_v2i32__0_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -4704,6 +4843,8 @@ define void @s_shuffle_v4i32_v2i32__0_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4722,6 +4863,9 @@ define void @s_shuffle_v4i32_v2i32__1_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4734,6 +4878,9 @@ define void @s_shuffle_v4i32_v2i32__1_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4746,6 +4893,9 @@ define void @s_shuffle_v4i32_v2i32__1_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4923,6 +5073,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4937,6 +5088,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4951,6 +5103,7 @@ define void @s_shuffle_v4i32_v2i32__3_3_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
index 2cf0f5c030d74..a4c74fca3c068 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v3i32.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v4i32_v3i32__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -58,35 +61,45 @@ define void @v_shuffle_v4i32_v3i32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__1_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__1_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -99,33 +112,42 @@ define void @v_shuffle_v4i32_v3i32__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__2_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__2_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -149,35 +171,45 @@ define void @v_shuffle_v4i32_v3i32__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__4_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__4_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__4_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -191,33 +223,42 @@ define void @v_shuffle_v4i32_v3i32__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -238,6 +279,8 @@ define void @v_shuffle_v4i32_v3i32__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -253,6 +296,8 @@ define void @v_shuffle_v4i32_v3i32__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -267,8 +312,10 @@ define void @v_shuffle_v4i32_v3i32__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -283,43 +330,49 @@ define void @v_shuffle_v4i32_v3i32__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_1_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_1_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -333,14 +386,16 @@ define void @v_shuffle_v4i32_v3i32__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -350,12 +405,14 @@ define void @v_shuffle_v4i32_v3i32__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v3, v4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -365,12 +422,14 @@ define void @v_shuffle_v4i32_v3i32__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -384,37 +443,43 @@ define void @v_shuffle_v4i32_v3i32__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -428,37 +493,43 @@ define void @v_shuffle_v4i32_v3i32__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_4_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_4_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -472,37 +543,43 @@ define void @v_shuffle_v4i32_v3i32__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_5_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_5_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -518,12 +595,13 @@ define void @v_shuffle_v4i32_v3i32__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:2]
+; GFX900-NEXT: ; def v[4:6]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[4:6]
+; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v3, v2
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -533,12 +611,13 @@ define void @v_shuffle_v4i32_v3i32__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:2]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:6]
+; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v3, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -548,11 +627,12 @@ define void @v_shuffle_v4i32_v3i32__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:2]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:6]
+; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
@@ -577,6 +657,7 @@ define void @v_shuffle_v4i32_v3i32__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -593,6 +674,7 @@ define void @v_shuffle_v4i32_v3i32__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -609,6 +691,7 @@ define void @v_shuffle_v4i32_v3i32__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v3, v2
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -626,12 +709,13 @@ define void @v_shuffle_v4i32_v3i32__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:4]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -641,12 +725,13 @@ define void @v_shuffle_v4i32_v3i32__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -656,13 +741,14 @@ define void @v_shuffle_v4i32_v3i32__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -676,40 +762,43 @@ define void @v_shuffle_v4i32_v3i32__5_5_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_5_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_5_3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v0
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_5_3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v0
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -723,40 +812,43 @@ define void @v_shuffle_v4i32_v3i32__5_5_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_5_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_5_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_5_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v1
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -770,40 +862,43 @@ define void @v_shuffle_v4i32_v3i32__5_5_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__5_5_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_5_5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_5_5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v2
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -1824,32 +1919,35 @@ define void @v_shuffle_v4i32_v3i32__5_5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__5_5_u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v9, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:6]
+; GFX90A-NEXT: ; def v[6:8]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v9, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__5_5_u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v9, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:6]
+; GFX942-NEXT: ; def v[6:8]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: global_store_dwordx4 v9, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -2053,6 +2151,7 @@ define void @v_shuffle_v4i32_v3i32__5_5_4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
@@ -2069,6 +2168,7 @@ define void @v_shuffle_v4i32_v3i32__5_5_4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -3717,15 +3817,16 @@ define void @v_shuffle_v4i32_v3i32__5_5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:4]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -3733,15 +3834,16 @@ define void @v_shuffle_v4i32_v3i32__5_5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:4]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -3941,6 +4043,7 @@ define void @v_shuffle_v4i32_v3i32__5_5_4_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
@@ -3957,6 +4060,7 @@ define void @v_shuffle_v4i32_v3i32__5_5_4_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -3989,33 +4093,36 @@ define void @v_shuffle_v4i32_v3i32__0_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__0_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__0_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__0_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -4028,35 +4135,45 @@ define void @v_shuffle_v4i32_v3i32__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__1_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__1_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__1_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -4069,33 +4186,42 @@ define void @v_shuffle_v4i32_v3i32__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v3i32__2_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v3i32__2_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v3i32__2_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i32> asm "; def $0", "=v"()
@@ -6695,6 +6821,7 @@ define void @s_shuffle_v4i32_v3i32__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:10]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6706,6 +6833,7 @@ define void @s_shuffle_v4i32_v3i32__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:10]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -6717,6 +6845,7 @@ define void @s_shuffle_v4i32_v3i32__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:10]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6735,6 +6864,9 @@ define void @s_shuffle_v4i32_v3i32__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6747,6 +6879,9 @@ define void @s_shuffle_v4i32_v3i32__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6759,6 +6894,9 @@ define void @s_shuffle_v4i32_v3i32__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6777,6 +6915,9 @@ define void @s_shuffle_v4i32_v3i32__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6789,6 +6930,9 @@ define void @s_shuffle_v4i32_v3i32__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6801,6 +6945,9 @@ define void @s_shuffle_v4i32_v3i32__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6833,6 +6980,9 @@ define void @s_shuffle_v4i32_v3i32__4_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6845,6 +6995,9 @@ define void @s_shuffle_v4i32_v3i32__4_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6857,6 +7010,9 @@ define void @s_shuffle_v4i32_v3i32__4_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6876,6 +7032,9 @@ define void @s_shuffle_v4i32_v3i32__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6888,6 +7047,9 @@ define void @s_shuffle_v4i32_v3i32__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6900,6 +7062,9 @@ define void @s_shuffle_v4i32_v3i32__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6924,6 +7089,8 @@ define void @s_shuffle_v4i32_v3i32__5_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6940,6 +7107,8 @@ define void @s_shuffle_v4i32_v3i32__5_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -6956,6 +7125,8 @@ define void @s_shuffle_v4i32_v3i32__5_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -6978,6 +7149,8 @@ define void @s_shuffle_v4i32_v3i32__5_1_u_u() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6993,6 +7166,8 @@ define void @s_shuffle_v4i32_v3i32__5_1_u_u() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7008,6 +7183,8 @@ define void @s_shuffle_v4i32_v3i32__5_1_u_u() {
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7031,6 +7208,8 @@ define void @s_shuffle_v4i32_v3i32__5_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7047,6 +7226,8 @@ define void @s_shuffle_v4i32_v3i32__5_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7063,6 +7244,8 @@ define void @s_shuffle_v4i32_v3i32__5_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7083,6 +7266,8 @@ define void @s_shuffle_v4i32_v3i32__5_3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7096,6 +7281,8 @@ define void @s_shuffle_v4i32_v3i32__5_3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7109,6 +7296,8 @@ define void @s_shuffle_v4i32_v3i32__5_3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7127,7 +7316,9 @@ define void @s_shuffle_v4i32_v3i32__5_4_u_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:10]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: s_mov_b32 s8, s10
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -7148,6 +7339,8 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7161,6 +7354,8 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7174,6 +7369,8 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7198,6 +7395,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_0_u() {
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7215,6 +7413,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_0_u() {
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7232,6 +7431,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_0_u() {
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7256,6 +7456,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_1_u() {
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7273,6 +7474,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_1_u() {
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7290,6 +7492,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_1_u() {
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7313,6 +7516,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7329,6 +7533,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7345,6 +7550,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7366,6 +7572,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_3_u() {
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7380,6 +7587,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_3_u() {
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7394,6 +7602,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_3_u() {
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7415,6 +7624,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_4_u() {
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7429,6 +7639,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_4_u() {
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7443,6 +7654,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_4_u() {
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7463,6 +7675,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_5_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -7780,6 +7993,7 @@ define void @s_shuffle_v4i32_v3i32__u_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -7794,6 +8008,7 @@ define void @s_shuffle_v4i32_v3i32__u_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -7808,6 +8023,7 @@ define void @s_shuffle_v4i32_v3i32__u_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -7950,6 +8166,7 @@ define void @s_shuffle_v4i32_v3i32__3_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -7964,6 +8181,7 @@ define void @s_shuffle_v4i32_v3i32__3_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -7978,6 +8196,7 @@ define void @s_shuffle_v4i32_v3i32__3_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -8124,6 +8343,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_0_0() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8141,6 +8361,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_0_0() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8158,6 +8379,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_0_0() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8485,6 +8707,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_0() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -8502,6 +8725,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_0() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -8519,6 +8743,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_0() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -8999,6 +9224,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_1_1() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -9016,6 +9242,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_1_1() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -9033,6 +9260,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_1_1() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -9360,6 +9588,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -9377,6 +9606,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -9394,6 +9624,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10220,6 +10451,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10237,6 +10469,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10254,6 +10487,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10531,6 +10765,7 @@ define void @s_shuffle_v4i32_v3i32__0_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:10]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -10542,6 +10777,7 @@ define void @s_shuffle_v4i32_v3i32__0_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:10]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -10553,6 +10789,7 @@ define void @s_shuffle_v4i32_v3i32__0_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:10]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10571,6 +10808,9 @@ define void @s_shuffle_v4i32_v3i32__1_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10583,6 +10823,9 @@ define void @s_shuffle_v4i32_v3i32__1_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10595,6 +10838,9 @@ define void @s_shuffle_v4i32_v3i32__1_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10613,6 +10859,9 @@ define void @s_shuffle_v4i32_v3i32__2_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10625,6 +10874,9 @@ define void @s_shuffle_v4i32_v3i32__2_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10637,6 +10889,9 @@ define void @s_shuffle_v4i32_v3i32__2_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10773,6 +11028,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -10787,6 +11043,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -10801,6 +11058,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -11108,6 +11366,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11122,6 +11381,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11136,6 +11396,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11643,6 +11904,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
@@ -11657,6 +11919,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
@@ -11671,6 +11934,7 @@ define void @s_shuffle_v4i32_v3i32__5_u_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
@@ -11978,6 +12242,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11992,6 +12257,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -12006,6 +12272,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -12760,6 +13027,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_5() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -12774,6 +13042,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_5() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -12788,6 +13057,7 @@ define void @s_shuffle_v4i32_v3i32__5_5_u_5() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
index c7d7bf9fa1623..c598afc28b4ec 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i32.v4i32.ll
@@ -58,11 +58,14 @@ define void @v_shuffle_v4i32_v4i32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +77,9 @@ define void @v_shuffle_v4i32_v4i32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +92,9 @@ define void @v_shuffle_v4i32_v4i32__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +108,42 @@ define void @v_shuffle_v4i32_v4i32__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v4i32__2_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v4i32__2_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -138,11 +156,14 @@ define void @v_shuffle_v4i32_v4i32__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +175,9 @@ define void @v_shuffle_v4i32_v4i32__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +190,9 @@ define void @v_shuffle_v4i32_v4i32__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -190,11 +217,14 @@ define void @v_shuffle_v4i32_v4i32__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -206,6 +236,9 @@ define void @v_shuffle_v4i32_v4i32__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +251,9 @@ define void @v_shuffle_v4i32_v4i32__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -232,33 +268,42 @@ define void @v_shuffle_v4i32_v4i32__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__6_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v4i32__6_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v4i32__6_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -272,11 +317,14 @@ define void @v_shuffle_v4i32_v4i32__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +336,9 @@ define void @v_shuffle_v4i32_v4i32__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +351,9 @@ define void @v_shuffle_v4i32_v4i32__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -321,6 +375,8 @@ define void @v_shuffle_v4i32_v4i32__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v8, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -331,11 +387,14 @@ define void @v_shuffle_v4i32_v4i32__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -346,10 +405,13 @@ define void @v_shuffle_v4i32_v4i32__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
@@ -373,6 +435,8 @@ define void @v_shuffle_v4i32_v4i32__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -388,6 +452,8 @@ define void @v_shuffle_v4i32_v4i32__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -402,6 +468,8 @@ define void @v_shuffle_v4i32_v4i32__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
@@ -418,14 +486,16 @@ define void @v_shuffle_v4i32_v4i32__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -439,7 +509,10 @@ define void @v_shuffle_v4i32_v4i32__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -454,8 +527,11 @@ define void @v_shuffle_v4i32_v4i32__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -470,14 +546,16 @@ define void @v_shuffle_v4i32_v4i32__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -492,6 +570,8 @@ define void @v_shuffle_v4i32_v4i32__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -506,6 +586,8 @@ define void @v_shuffle_v4i32_v4i32__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v7
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
@@ -522,12 +604,14 @@ define void @v_shuffle_v4i32_v4i32__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -539,6 +623,8 @@ define void @v_shuffle_v4i32_v4i32__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -551,6 +637,8 @@ define void @v_shuffle_v4i32_v4i32__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -565,12 +653,14 @@ define void @v_shuffle_v4i32_v4i32__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -582,6 +672,8 @@ define void @v_shuffle_v4i32_v4i32__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -594,6 +686,8 @@ define void @v_shuffle_v4i32_v4i32__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -608,12 +702,14 @@ define void @v_shuffle_v4i32_v4i32__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_6_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -625,6 +721,8 @@ define void @v_shuffle_v4i32_v4i32__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[2:3] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -637,6 +735,8 @@ define void @v_shuffle_v4i32_v4i32__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[2:3] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -651,12 +751,14 @@ define void @v_shuffle_v4i32_v4i32__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_7_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -666,9 +768,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -678,9 +782,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -696,12 +802,13 @@ define void @v_shuffle_v4i32_v4i32__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:3]
+; GFX900-NEXT: ; def v[5:8]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[5:8]
+; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v9, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -713,10 +820,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -728,10 +836,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -754,6 +863,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v8, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -770,6 +880,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -786,6 +897,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v5
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -808,6 +920,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -823,6 +936,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -837,6 +951,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
@@ -856,12 +971,13 @@ define void @v_shuffle_v4i32_v4i32__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -877,6 +993,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -893,6 +1010,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -907,13 +1025,14 @@ define void @v_shuffle_v4i32_v4i32__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_7_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v0
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -923,10 +1042,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v0
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -936,10 +1056,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v0
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -953,13 +1074,14 @@ define void @v_shuffle_v4i32_v4i32__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_7_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v1
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -969,10 +1091,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -982,10 +1105,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v1
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -999,13 +1123,14 @@ define void @v_shuffle_v4i32_v4i32__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_7_6_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v2
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -1018,6 +1143,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1031,6 +1157,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1045,13 +1172,14 @@ define void @v_shuffle_v4i32_v4i32__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__7_7_7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -1061,10 +1189,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v3
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1074,10 +1203,11 @@ define void @v_shuffle_v4i32_v4i32__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v3
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -1113,6 +1243,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_7_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -1129,6 +1260,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_7_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -1223,6 +1355,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_7_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -1236,6 +1369,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_7_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
@@ -2412,15 +2546,16 @@ define void @v_shuffle_v4i32_v4i32__7_7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[6:9]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2428,15 +2563,16 @@ define void @v_shuffle_v4i32_v4i32__7_7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[6:9]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -2696,6 +2832,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_5_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -2712,6 +2849,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_5_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -4961,15 +5099,16 @@ define void @v_shuffle_v4i32_v4i32__7_7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:5]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -4977,15 +5116,16 @@ define void @v_shuffle_v4i32_v4i32__7_7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:5]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -5242,6 +5382,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_5_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -5255,6 +5396,7 @@ define void @v_shuffle_v4i32_v4i32__7_7_5_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
@@ -6657,11 +6799,14 @@ define void @v_shuffle_v4i32_v4i32__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__1_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -6673,6 +6818,9 @@ define void @v_shuffle_v4i32_v4i32__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6685,6 +6833,9 @@ define void @v_shuffle_v4i32_v4i32__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6698,33 +6849,42 @@ define void @v_shuffle_v4i32_v4i32__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__2_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i32_v4i32__2_4_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v4i32__2_4_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -6737,11 +6897,14 @@ define void @v_shuffle_v4i32_v4i32__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i32_v4i32__3_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -6753,6 +6916,9 @@ define void @v_shuffle_v4i32_v4i32__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6765,6 +6931,9 @@ define void @v_shuffle_v4i32_v4i32__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7000,6 +7169,7 @@ define void @v_shuffle_v4i32_v4i32__7_0_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
@@ -7013,6 +7183,7 @@ define void @v_shuffle_v4i32_v4i32__7_0_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -7113,6 +7284,7 @@ define void @v_shuffle_v4i32_v4i32__7_2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
@@ -7129,6 +7301,7 @@ define void @v_shuffle_v4i32_v4i32__7_2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v3, v2
@@ -8246,6 +8419,7 @@ define void @v_shuffle_v4i32_v4i32__7_0_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -8259,6 +8433,7 @@ define void @v_shuffle_v4i32_v4i32__7_0_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -8359,6 +8534,7 @@ define void @v_shuffle_v4i32_v4i32__7_2_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
@@ -8375,6 +8551,7 @@ define void @v_shuffle_v4i32_v4i32__7_2_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -9489,6 +9666,7 @@ define void @v_shuffle_v4i32_v4i32__7_0_6_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v5, v4
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
@@ -9505,6 +9683,7 @@ define void @v_shuffle_v4i32_v4i32__7_0_6_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v5, v4
@@ -9597,12 +9776,13 @@ define void @v_shuffle_v4i32_v4i32__7_2_6_6(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v7, v6
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
@@ -9613,13 +9793,13 @@ define void @v_shuffle_v4i32_v4i32__7_2_6_6(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v7, v6
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
@@ -9849,28 +10029,31 @@ define void @v_shuffle_v4i32_v4i32__7_7_u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v4i32_v4i32__7_7_u_6:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v1, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v3
+; GFX90A-NEXT: v_mov_b32_e32 v9, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx4 v4, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i32_v4i32__7_7_u_6:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v1, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v3
+; GFX942-NEXT: v_mov_b32_e32 v9, v2
+; GFX942-NEXT: global_store_dwordx4 v4, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i32> asm "; def $0", "=v"()
@@ -10698,6 +10881,7 @@ define void @v_shuffle_v4i32_v4i32__7_0_7_7(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
@@ -10714,6 +10898,7 @@ define void @v_shuffle_v4i32_v4i32__7_0_7_7(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v4, v5
@@ -10806,12 +10991,13 @@ define void @v_shuffle_v4i32_v4i32__7_2_7_7(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v6, v7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
@@ -10822,13 +11008,13 @@ define void @v_shuffle_v4i32_v4i32__7_2_7_7(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v6, v7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
@@ -11516,6 +11702,9 @@ define void @s_shuffle_v4i32_v4i32__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11528,6 +11717,9 @@ define void @s_shuffle_v4i32_v4i32__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11540,6 +11732,9 @@ define void @s_shuffle_v4i32_v4i32__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11558,6 +11753,9 @@ define void @s_shuffle_v4i32_v4i32__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11570,6 +11768,9 @@ define void @s_shuffle_v4i32_v4i32__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11582,6 +11783,9 @@ define void @s_shuffle_v4i32_v4i32__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11600,6 +11804,9 @@ define void @s_shuffle_v4i32_v4i32__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11612,6 +11819,9 @@ define void @s_shuffle_v4i32_v4i32__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11624,6 +11834,9 @@ define void @s_shuffle_v4i32_v4i32__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11656,6 +11869,9 @@ define void @s_shuffle_v4i32_v4i32__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11668,6 +11884,9 @@ define void @s_shuffle_v4i32_v4i32__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11680,6 +11899,9 @@ define void @s_shuffle_v4i32_v4i32__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11699,6 +11921,9 @@ define void @s_shuffle_v4i32_v4i32__6_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11711,6 +11936,9 @@ define void @s_shuffle_v4i32_v4i32__6_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11723,6 +11951,9 @@ define void @s_shuffle_v4i32_v4i32__6_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11742,6 +11973,9 @@ define void @s_shuffle_v4i32_v4i32__7_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11754,6 +11988,9 @@ define void @s_shuffle_v4i32_v4i32__7_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11766,6 +12003,9 @@ define void @s_shuffle_v4i32_v4i32__7_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11790,6 +12030,8 @@ define void @s_shuffle_v4i32_v4i32__7_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11806,6 +12048,8 @@ define void @s_shuffle_v4i32_v4i32__7_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11822,6 +12066,8 @@ define void @s_shuffle_v4i32_v4i32__7_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11844,6 +12090,8 @@ define void @s_shuffle_v4i32_v4i32__7_1_u_u() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11859,6 +12107,8 @@ define void @s_shuffle_v4i32_v4i32__7_1_u_u() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11874,6 +12124,8 @@ define void @s_shuffle_v4i32_v4i32__7_1_u_u() {
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11897,6 +12149,8 @@ define void @s_shuffle_v4i32_v4i32__7_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11913,6 +12167,8 @@ define void @s_shuffle_v4i32_v4i32__7_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11929,6 +12185,8 @@ define void @s_shuffle_v4i32_v4i32__7_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11952,6 +12210,8 @@ define void @s_shuffle_v4i32_v4i32__7_3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11968,6 +12228,8 @@ define void @s_shuffle_v4i32_v4i32__7_3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11984,6 +12246,8 @@ define void @s_shuffle_v4i32_v4i32__7_3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12004,6 +12268,8 @@ define void @s_shuffle_v4i32_v4i32__7_4_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12017,6 +12283,8 @@ define void @s_shuffle_v4i32_v4i32__7_4_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12030,6 +12298,8 @@ define void @s_shuffle_v4i32_v4i32__7_4_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12049,6 +12319,8 @@ define void @s_shuffle_v4i32_v4i32__7_5_u_u() {
; GFX9-NEXT: ; def s[8:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
+; GFX9-NEXT: ; implicit-def: $sgpr10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -12069,6 +12341,8 @@ define void @s_shuffle_v4i32_v4i32__7_6_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12082,6 +12356,8 @@ define void @s_shuffle_v4i32_v4i32__7_6_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12095,6 +12371,8 @@ define void @s_shuffle_v4i32_v4i32__7_6_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12115,6 +12393,8 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12128,6 +12408,8 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12141,6 +12423,8 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12165,6 +12449,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_0_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12182,6 +12467,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_0_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12199,6 +12485,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_0_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12223,6 +12510,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_1_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12240,6 +12528,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_1_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12257,6 +12546,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_1_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12280,6 +12570,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12296,6 +12587,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12312,6 +12604,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12336,6 +12629,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_3_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12353,6 +12647,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_3_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12370,6 +12665,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_3_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12391,6 +12687,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_4_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12405,6 +12702,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_4_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12419,6 +12717,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_4_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12440,6 +12739,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_5_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12454,6 +12754,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_5_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12468,6 +12769,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_5_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12488,6 +12790,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_6_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -12509,6 +12812,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_7_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12523,6 +12827,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_7_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12537,6 +12842,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_7_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12973,6 +13279,7 @@ define void @s_shuffle_v4i32_v4i32__u_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -12987,6 +13294,7 @@ define void @s_shuffle_v4i32_v4i32__u_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -13001,6 +13309,7 @@ define void @s_shuffle_v4i32_v4i32__u_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -13194,6 +13503,7 @@ define void @s_shuffle_v4i32_v4i32__4_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -13208,6 +13518,7 @@ define void @s_shuffle_v4i32_v4i32__4_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -13222,6 +13533,7 @@ define void @s_shuffle_v4i32_v4i32__4_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -13429,6 +13741,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_0_0() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -13446,6 +13759,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_0_0() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -13463,6 +13777,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_0_0() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -13912,6 +14227,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_0() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -13929,6 +14245,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_0() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -13946,6 +14263,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_0() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -14623,6 +14941,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_1_1() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -14640,6 +14959,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_1_1() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -14657,6 +14977,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_1_1() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -15106,6 +15427,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -15123,6 +15445,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -15140,6 +15463,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -16279,6 +16603,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -16296,6 +16621,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -16313,6 +16639,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17907,6 +18234,9 @@ define void @s_shuffle_v4i32_v4i32__1_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -17919,6 +18249,9 @@ define void @s_shuffle_v4i32_v4i32__1_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -17931,6 +18264,9 @@ define void @s_shuffle_v4i32_v4i32__1_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17949,6 +18285,9 @@ define void @s_shuffle_v4i32_v4i32__2_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -17961,6 +18300,9 @@ define void @s_shuffle_v4i32_v4i32__2_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -17973,6 +18315,9 @@ define void @s_shuffle_v4i32_v4i32__2_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17991,6 +18336,9 @@ define void @s_shuffle_v4i32_v4i32__3_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -18003,6 +18351,9 @@ define void @s_shuffle_v4i32_v4i32__3_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -18015,6 +18366,9 @@ define void @s_shuffle_v4i32_v4i32__3_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -18203,6 +18557,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -18217,6 +18572,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -18231,6 +18587,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -18651,6 +19008,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -18665,6 +19023,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -18679,6 +19038,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -19378,6 +19738,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_5_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
@@ -19392,6 +19753,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_5_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
@@ -19406,6 +19768,7 @@ define void @s_shuffle_v4i32_v4i32__7_u_5_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
@@ -19826,6 +20189,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_5() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -19840,6 +20204,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_5() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -19854,6 +20219,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_5() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -20900,6 +21266,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_6() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -20914,6 +21281,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_6() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -20928,6 +21296,7 @@ define void @s_shuffle_v4i32_v4i32__7_7_u_6() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
index 190137de6eef8..6a62b59bc9c0b 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v2i64.ll
@@ -58,33 +58,39 @@ define void @v_shuffle_v4i64_v2i64__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v2i64__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v2i64__1_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v2i64__1_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -108,33 +114,39 @@ define void @v_shuffle_v4i64_v2i64__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v2i64__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v2i64__3_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v2i64__3_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -348,6 +360,8 @@ define void @v_shuffle_v4i64_v2i64__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v4, v2
@@ -366,6 +380,8 @@ define void @v_shuffle_v4i64_v2i64__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
@@ -384,6 +400,8 @@ define void @v_shuffle_v4i64_v2i64__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mov_b32_e32 v4, v2
@@ -411,6 +429,8 @@ define void @v_shuffle_v4i64_v2i64__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
@@ -428,6 +448,8 @@ define void @v_shuffle_v4i64_v2i64__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -443,6 +465,8 @@ define void @v_shuffle_v4i64_v2i64__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1] offset:16
; GFX942-NEXT: v_mov_b32_e32 v8, v6
; GFX942-NEXT: v_mov_b32_e32 v9, v7
@@ -1060,6 +1084,8 @@ define void @v_shuffle_v4i64_v2i64__3_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1077,6 +1103,8 @@ define void @v_shuffle_v4i64_v2i64__3_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1094,6 +1122,8 @@ define void @v_shuffle_v4i64_v2i64__3_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1752,14 +1782,16 @@ define void @v_shuffle_v4i64_v2i64__3_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[4:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v3
-; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -1769,14 +1801,16 @@ define void @v_shuffle_v4i64_v2i64__3_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
; GFX90A-NEXT: v_mov_b32_e32 v5, v3
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1786,15 +1820,17 @@ define void @v_shuffle_v4i64_v2i64__3_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v2
; GFX942-NEXT: v_mov_b32_e32 v5, v3
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -2237,33 +2273,39 @@ define void @v_shuffle_v4i64_v2i64__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v2i64__1_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v2i64__1_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v2i64__1_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -2343,43 +2385,49 @@ define void @v_shuffle_v4i64_v2i64__3_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v2i64__3_u_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v0, v2
; GFX900-NEXT: v_mov_b32_e32 v1, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v2i64__3_u_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
-; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v2i64__3_u_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v2
; GFX942-NEXT: v_mov_b32_e32 v1, v3
-; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x i64> asm "; def $0", "=v"()
@@ -2968,6 +3016,8 @@ define void @v_shuffle_v4i64_v2i64__3_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: v_mov_b32_e32 v4, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v3
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2982,6 +3032,8 @@ define void @v_shuffle_v4i64_v2i64__3_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
; GFX90A-NEXT: v_mov_b32_e32 v5, v3
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2997,6 +3049,8 @@ define void @v_shuffle_v4i64_v2i64__3_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, v2
; GFX942-NEXT: v_mov_b32_e32 v5, v3
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3453,6 +3507,10 @@ define void @s_shuffle_v4i64_v2i64__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3464,6 +3522,10 @@ define void @s_shuffle_v4i64_v2i64__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3475,6 +3537,10 @@ define void @s_shuffle_v4i64_v2i64__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -3495,6 +3561,12 @@ define void @s_shuffle_v4i64_v2i64__1_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3508,6 +3580,12 @@ define void @s_shuffle_v4i64_v2i64__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3521,6 +3599,12 @@ define void @s_shuffle_v4i64_v2i64__1_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3554,6 +3638,12 @@ define void @s_shuffle_v4i64_v2i64__3_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3567,6 +3657,12 @@ define void @s_shuffle_v4i64_v2i64__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3580,6 +3676,12 @@ define void @s_shuffle_v4i64_v2i64__3_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3605,6 +3707,10 @@ define void @s_shuffle_v4i64_v2i64__3_0_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3623,6 +3729,10 @@ define void @s_shuffle_v4i64_v2i64__3_0_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3641,6 +3751,10 @@ define void @s_shuffle_v4i64_v2i64__3_0_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3664,6 +3778,10 @@ define void @s_shuffle_v4i64_v2i64__3_1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3680,6 +3798,10 @@ define void @s_shuffle_v4i64_v2i64__3_1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3696,6 +3818,10 @@ define void @s_shuffle_v4i64_v2i64__3_1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3718,6 +3844,10 @@ define void @s_shuffle_v4i64_v2i64__3_2_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3733,6 +3863,10 @@ define void @s_shuffle_v4i64_v2i64__3_2_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3748,6 +3882,10 @@ define void @s_shuffle_v4i64_v2i64__3_2_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3768,6 +3906,10 @@ define void @s_shuffle_v4i64_v2i64__3_3_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -3784,13 +3926,15 @@ define void @s_shuffle_v4i64_v2i64__3_3_0_u() {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[8:11]
+; GFX9-NEXT: ; def s[12:15]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[12:15]
+; GFX9-NEXT: ; def s[8:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -3816,6 +3960,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_1_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3834,6 +3980,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_1_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3852,6 +4000,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_1_u() {
; GFX942-NEXT: s_mov_b32 s9, s11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: s_mov_b32 s13, s3
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3874,6 +4024,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_2_u() {
; GFX9-NEXT: s_mov_b32 s9, s15
; GFX9-NEXT: s_mov_b32 s10, s14
; GFX9-NEXT: s_mov_b32 s11, s15
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -3896,6 +4048,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_3_u() {
; GFX9-NEXT: s_mov_b32 s9, s11
; GFX9-NEXT: s_mov_b32 s12, s10
; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -4474,6 +4628,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_u_0() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: s_mov_b32 s14, s4
; GFX900-NEXT: s_mov_b32 s15, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -4492,6 +4648,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_u_0() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: s_mov_b32 s14, s4
; GFX90A-NEXT: s_mov_b32 s15, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -4510,6 +4668,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_u_0() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s0
; GFX942-NEXT: s_mov_b32 s15, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -5164,6 +5324,10 @@ define void @s_shuffle_v4i64_v2i64__0_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -5175,6 +5339,10 @@ define void @s_shuffle_v4i64_v2i64__0_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -5186,6 +5354,10 @@ define void @s_shuffle_v4i64_v2i64__0_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -5206,6 +5378,12 @@ define void @s_shuffle_v4i64_v2i64__1_2_2_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -5219,6 +5397,12 @@ define void @s_shuffle_v4i64_v2i64__1_2_2_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -5232,6 +5416,12 @@ define void @s_shuffle_v4i64_v2i64__1_2_2_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -5429,6 +5619,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_u_2() {
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s6
; GFX900-NEXT: s_mov_b32 s11, s7
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: s_mov_b32 s14, s4
; GFX900-NEXT: s_mov_b32 s15, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -5446,6 +5638,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_u_2() {
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s6
; GFX90A-NEXT: s_mov_b32 s11, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: s_mov_b32 s14, s4
; GFX90A-NEXT: s_mov_b32 s15, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -5463,6 +5657,8 @@ define void @s_shuffle_v4i64_v2i64__3_3_u_2() {
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s2
; GFX942-NEXT: s_mov_b32 s11, s3
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s0
; GFX942-NEXT: s_mov_b32 s15, s1
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
index c8797d5dba427..f48d76d7ba326 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v3i64.ll
@@ -65,6 +65,8 @@ define void @v_shuffle_v4i64_v3i64__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -76,6 +78,8 @@ define void @v_shuffle_v4i64_v3i64__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +91,8 @@ define void @v_shuffle_v4i64_v3i64__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -100,33 +106,39 @@ define void @v_shuffle_v4i64_v3i64__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v3i64__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v3i64__2_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v3i64__2_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -154,6 +166,8 @@ define void @v_shuffle_v4i64_v3i64__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -165,6 +179,8 @@ define void @v_shuffle_v4i64_v3i64__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -176,6 +192,8 @@ define void @v_shuffle_v4i64_v3i64__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -190,33 +208,39 @@ define void @v_shuffle_v4i64_v3i64__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v3i64__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v3i64__5_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v3i64__5_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -527,6 +551,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v6, v4
@@ -545,6 +571,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v6, v4
@@ -563,6 +591,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v12, v[6:9], s[0:1] offset:16
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mov_b32_e32 v6, v4
@@ -588,6 +618,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v6, v4
@@ -606,6 +638,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v6, v4
@@ -621,6 +655,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1] offset:16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
@@ -651,6 +687,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v14, v[4:7], s[16:17] offset:16
; GFX900-NEXT: global_store_dwordx4 v14, v[10:13], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
@@ -668,6 +706,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v14, v[4:7], s[16:17] offset:16
; GFX90A-NEXT: global_store_dwordx4 v14, v[10:13], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -683,6 +723,8 @@ define void @v_shuffle_v4i64_v3i64__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v14, v[4:7], s[0:1] offset:16
; GFX942-NEXT: v_mov_b32_e32 v12, v10
; GFX942-NEXT: v_mov_b32_e32 v13, v11
@@ -1588,6 +1630,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1605,6 +1649,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1622,6 +1668,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v12, v[6:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v12, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2663,6 +2711,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v10, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2680,6 +2730,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v10, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2697,6 +2749,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v10, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3734,14 +3788,16 @@ define void @v_shuffle_v4i64_v3i64__5_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[6:11]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v12, 0
+; GFX900-NEXT: v_mov_b32_e32 v14, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v6, v4
; GFX900-NEXT: v_mov_b32_e32 v7, v5
-; GFX900-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v12, v[10:13], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v14, v[4:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr12
+; GFX900-NEXT: ; implicit-def: $vgpr13
+; GFX900-NEXT: global_store_dwordx4 v14, v[10:13], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -3751,14 +3807,16 @@ define void @v_shuffle_v4i64_v3i64__5_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:11]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, v4
; GFX90A-NEXT: v_mov_b32_e32 v7, v5
-; GFX90A-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v12, v[10:13], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v14, v[4:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr12
+; GFX90A-NEXT: ; implicit-def: $vgpr13
+; GFX90A-NEXT: global_store_dwordx4 v14, v[10:13], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -3768,15 +3826,17 @@ define void @v_shuffle_v4i64_v3i64__5_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:11]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v12, 0
+; GFX942-NEXT: v_mov_b32_e32 v14, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v6, v4
; GFX942-NEXT: v_mov_b32_e32 v7, v5
-; GFX942-NEXT: global_store_dwordx4 v12, v[4:7], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v12, v[10:13], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v14, v[4:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr12
+; GFX942-NEXT: ; implicit-def: $vgpr13
+; GFX942-NEXT: global_store_dwordx4 v14, v[10:13], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -4481,6 +4541,8 @@ define void @v_shuffle_v4i64_v3i64__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4492,6 +4554,8 @@ define void @v_shuffle_v4i64_v3i64__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4503,6 +4567,8 @@ define void @v_shuffle_v4i64_v3i64__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4516,33 +4582,39 @@ define void @v_shuffle_v4i64_v3i64__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v3i64__2_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v3i64__2_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v3i64__2_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -4679,11 +4751,13 @@ define void @v_shuffle_v4i64_v3i64__5_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: v_mov_b32_e32 v2, v0
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -4693,11 +4767,13 @@ define void @v_shuffle_v4i64_v3i64__5_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v0
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -4707,11 +4783,13 @@ define void @v_shuffle_v4i64_v3i64__5_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -5690,11 +5768,13 @@ define void @v_shuffle_v4i64_v3i64__5_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: v_mov_b32_e32 v0, v2
; GFX900-NEXT: v_mov_b32_e32 v1, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -5704,11 +5784,13 @@ define void @v_shuffle_v4i64_v3i64__5_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
-; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -5718,11 +5800,13 @@ define void @v_shuffle_v4i64_v3i64__5_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v2
; GFX942-NEXT: v_mov_b32_e32 v1, v3
-; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=v"()
@@ -6684,6 +6768,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: v_mov_b32_e32 v6, v4
; GFX900-NEXT: v_mov_b32_e32 v7, v5
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -6698,6 +6784,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v6, v4
; GFX90A-NEXT: v_mov_b32_e32 v7, v5
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6713,6 +6801,8 @@ define void @v_shuffle_v4i64_v3i64__5_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v6, v4
; GFX942-NEXT: v_mov_b32_e32 v7, v5
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7419,6 +7509,8 @@ define void @s_shuffle_v4i64_v3i64__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7430,6 +7522,8 @@ define void @s_shuffle_v4i64_v3i64__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7441,6 +7535,8 @@ define void @s_shuffle_v4i64_v3i64__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -7461,6 +7557,12 @@ define void @s_shuffle_v4i64_v3i64__1_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7474,6 +7576,12 @@ define void @s_shuffle_v4i64_v3i64__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7487,6 +7595,12 @@ define void @s_shuffle_v4i64_v3i64__1_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7504,6 +7618,12 @@ define void @s_shuffle_v4i64_v3i64__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7515,6 +7635,12 @@ define void @s_shuffle_v4i64_v3i64__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7526,6 +7652,12 @@ define void @s_shuffle_v4i64_v3i64__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -7560,6 +7692,12 @@ define void @s_shuffle_v4i64_v3i64__4_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7573,6 +7711,12 @@ define void @s_shuffle_v4i64_v3i64__4_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7586,6 +7730,12 @@ define void @s_shuffle_v4i64_v3i64__4_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7604,6 +7754,12 @@ define void @s_shuffle_v4i64_v3i64__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7615,6 +7771,12 @@ define void @s_shuffle_v4i64_v3i64__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7626,6 +7788,12 @@ define void @s_shuffle_v4i64_v3i64__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -7650,6 +7818,10 @@ define void @s_shuffle_v4i64_v3i64__5_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7666,6 +7838,10 @@ define void @s_shuffle_v4i64_v3i64__5_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7682,6 +7858,10 @@ define void @s_shuffle_v4i64_v3i64__5_0_u_u() {
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7700,9 +7880,13 @@ define void @s_shuffle_v4i64_v3i64__5_1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7714,9 +7898,13 @@ define void @s_shuffle_v4i64_v3i64__5_1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7728,6 +7916,10 @@ define void @s_shuffle_v4i64_v3i64__5_1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -7756,6 +7948,10 @@ define void @s_shuffle_v4i64_v3i64__5_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7772,6 +7968,10 @@ define void @s_shuffle_v4i64_v3i64__5_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7788,6 +7988,10 @@ define void @s_shuffle_v4i64_v3i64__5_2_u_u() {
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7808,6 +8012,10 @@ define void @s_shuffle_v4i64_v3i64__5_3_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s4
; GFX9-NEXT: s_mov_b32 s11, s5
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -7828,6 +8036,10 @@ define void @s_shuffle_v4i64_v3i64__5_4_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s6
; GFX9-NEXT: s_mov_b32 s11, s7
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -7848,6 +8060,10 @@ define void @s_shuffle_v4i64_v3i64__5_5_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s8
; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -7871,6 +8087,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_0_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s8
; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -7896,6 +8114,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_1_u() {
; GFX900-NEXT: s_mov_b32 s11, s9
; GFX900-NEXT: s_mov_b32 s12, s14
; GFX900-NEXT: s_mov_b32 s13, s15
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7914,6 +8134,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_1_u() {
; GFX90A-NEXT: s_mov_b32 s11, s9
; GFX90A-NEXT: s_mov_b32 s12, s14
; GFX90A-NEXT: s_mov_b32 s13, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7932,6 +8154,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_1_u() {
; GFX942-NEXT: s_mov_b32 s10, s8
; GFX942-NEXT: s_mov_b32 s11, s9
; GFX942-NEXT: s_mov_b32 s13, s3
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7955,6 +8179,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s8
; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7971,6 +8197,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s8
; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7982,6 +8210,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -8010,6 +8240,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_3_u() {
; GFX9-NEXT: s_mov_b32 s11, s9
; GFX9-NEXT: s_mov_b32 s12, s4
; GFX9-NEXT: s_mov_b32 s13, s5
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -8032,6 +8264,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_4_u() {
; GFX9-NEXT: s_mov_b32 s11, s9
; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s13, s7
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -8054,6 +8288,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_5_u() {
; GFX9-NEXT: s_mov_b32 s11, s9
; GFX9-NEXT: s_mov_b32 s12, s8
; GFX9-NEXT: s_mov_b32 s13, s9
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -8612,15 +8848,17 @@ define void @s_shuffle_v4i64_v3i64__5_5_u_0() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[12:17]
+; GFX900-NEXT: ; def s[16:21]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s8
; GFX900-NEXT: s_mov_b32 s11, s9
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: s_mov_b32 s14, s16
+; GFX900-NEXT: s_mov_b32 s15, s17
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -8630,15 +8868,17 @@ define void @s_shuffle_v4i64_v3i64__5_5_u_0() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[12:17]
+; GFX90A-NEXT: ; def s[16:21]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s8
; GFX90A-NEXT: s_mov_b32 s11, s9
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: s_mov_b32 s14, s16
+; GFX90A-NEXT: s_mov_b32 s15, s17
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -8650,6 +8890,8 @@ define void @s_shuffle_v4i64_v3i64__5_5_u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -9960,59 +10202,25 @@ define void @s_shuffle_v4i64_v3i64__5_5_2_2() {
}
define void @s_shuffle_v4i64_v3i64__5_5_u_2() {
-; GFX900-LABEL: s_shuffle_v4i64_v3i64__5_5_u_2:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[8:13]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:9]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use s[8:15]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX90A-LABEL: s_shuffle_v4i64_v3i64__5_5_u_2:
-; GFX90A: ; %bb.0:
-; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[8:13]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:9]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; use s[8:15]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX942-LABEL: s_shuffle_v4i64_v3i64__5_5_u_2:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[8:13]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s14, s12
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[4:9]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s8
-; GFX942-NEXT: s_mov_b32 s11, s9
-; GFX942-NEXT: s_mov_b32 s15, s13
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; use s[8:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: s_shuffle_v4i64_v3i64__5_5_u_2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[12:17]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[4:9]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: s_mov_b32 s14, s16
+; GFX9-NEXT: s_mov_b32 s15, s17
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use s[8:15]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x i64> asm "; def $0", "=s"()
%vec1 = call <3 x i64> asm "; def $0", "=s"()
%shuf = shufflevector <3 x i64> %vec0, <3 x i64> %vec1, <4 x i32> <i32 5, i32 5, i32 poison, i32 2>
@@ -10147,6 +10355,8 @@ define void @s_shuffle_v4i64_v3i64__0_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -10158,6 +10368,8 @@ define void @s_shuffle_v4i64_v3i64__0_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -10169,6 +10381,8 @@ define void @s_shuffle_v4i64_v3i64__0_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -10189,6 +10403,12 @@ define void @s_shuffle_v4i64_v3i64__1_3_3_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -10202,6 +10422,12 @@ define void @s_shuffle_v4i64_v3i64__1_3_3_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -10215,6 +10441,12 @@ define void @s_shuffle_v4i64_v3i64__1_3_3_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -10232,6 +10464,12 @@ define void @s_shuffle_v4i64_v3i64__2_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -10243,6 +10481,12 @@ define void @s_shuffle_v4i64_v3i64__2_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -10254,6 +10498,12 @@ define void @s_shuffle_v4i64_v3i64__2_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
index 32e0f5fd3e57b..b29bf933a6929 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
@@ -65,6 +65,8 @@ define void @v_shuffle_v4i64_v4i64__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -76,6 +78,8 @@ define void @v_shuffle_v4i64_v4i64__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +91,8 @@ define void @v_shuffle_v4i64_v4i64__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -104,6 +110,8 @@ define void @v_shuffle_v4i64_v4i64__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -115,6 +123,8 @@ define void @v_shuffle_v4i64_v4i64__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -126,6 +136,8 @@ define void @v_shuffle_v4i64_v4i64__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -139,33 +151,39 @@ define void @v_shuffle_v4i64_v4i64__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v4i64__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v4i64__3_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v4i64__3_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -193,6 +211,8 @@ define void @v_shuffle_v4i64_v4i64__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -204,6 +224,8 @@ define void @v_shuffle_v4i64_v4i64__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -215,6 +237,8 @@ define void @v_shuffle_v4i64_v4i64__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -233,6 +257,8 @@ define void @v_shuffle_v4i64_v4i64__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -244,6 +270,8 @@ define void @v_shuffle_v4i64_v4i64__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -255,6 +283,8 @@ define void @v_shuffle_v4i64_v4i64__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -269,33 +299,39 @@ define void @v_shuffle_v4i64_v4i64__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v4i64__7_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v4i64__7_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v4i64__7_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -703,6 +739,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr10
+; GFX900-NEXT: ; implicit-def: $vgpr11
; GFX900-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v8, v6
@@ -721,6 +759,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr10
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
@@ -739,6 +779,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr10
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:16
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mov_b32_e32 v8, v6
@@ -764,6 +806,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr10
+; GFX900-NEXT: ; implicit-def: $vgpr11
; GFX900-NEXT: global_store_dwordx4 v14, v[8:11], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v8, v6
@@ -782,6 +826,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr10
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: global_store_dwordx4 v14, v[8:11], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
@@ -797,6 +843,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr10
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: global_store_dwordx4 v14, v[8:11], s[0:1] offset:16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
@@ -825,6 +873,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr10
+; GFX900-NEXT: ; implicit-def: $vgpr11
; GFX900-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v8, v6
@@ -843,6 +893,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr10
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
@@ -858,6 +910,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr10
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: global_store_dwordx4 v12, v[8:11], s[0:1] offset:16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
@@ -883,6 +937,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: ;;#ASMSTART
@@ -906,6 +962,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v18, v[6:9], s[16:17] offset:16
; GFX90A-NEXT: global_store_dwordx4 v18, v[14:17], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -921,6 +979,8 @@ define void @v_shuffle_v4i64_v4i64__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v18, v[6:9], s[0:1] offset:16
; GFX942-NEXT: v_mov_b32_e32 v16, v14
; GFX942-NEXT: v_mov_b32_e32 v17, v15
@@ -2115,6 +2175,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2132,6 +2194,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2149,6 +2213,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3574,6 +3640,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v14, v[8:11], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v14, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -3591,6 +3659,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v14, v[8:11], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v14, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3608,6 +3678,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v14, v[8:11], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v14, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -5030,6 +5102,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -5047,6 +5121,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -5064,6 +5140,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v12, v[8:11], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v12, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6482,6 +6560,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: v_mov_b32_e32 v8, v6
; GFX900-NEXT: v_mov_b32_e32 v9, v7
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
@@ -6496,14 +6576,16 @@ define void @v_shuffle_v4i64_v4i64__7_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: v_mov_b32_e32 v18, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
; GFX90A-NEXT: v_mov_b32_e32 v9, v7
-; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v16, v[14:17], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v18, v[6:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr16
+; GFX90A-NEXT: ; implicit-def: $vgpr17
+; GFX90A-NEXT: global_store_dwordx4 v18, v[14:17], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -6513,15 +6595,17 @@ define void @v_shuffle_v4i64_v4i64__7_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: v_mov_b32_e32 v18, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v8, v6
; GFX942-NEXT: v_mov_b32_e32 v9, v7
-; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v16, v[14:17], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v18, v[6:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr16
+; GFX942-NEXT: ; implicit-def: $vgpr17
+; GFX942-NEXT: global_store_dwordx4 v18, v[14:17], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -7485,6 +7569,8 @@ define void @v_shuffle_v4i64_v4i64__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7496,6 +7582,8 @@ define void @v_shuffle_v4i64_v4i64__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7507,6 +7595,8 @@ define void @v_shuffle_v4i64_v4i64__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7524,6 +7614,8 @@ define void @v_shuffle_v4i64_v4i64__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7535,6 +7627,8 @@ define void @v_shuffle_v4i64_v4i64__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7546,6 +7640,8 @@ define void @v_shuffle_v4i64_v4i64__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7559,33 +7655,39 @@ define void @v_shuffle_v4i64_v4i64__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4i64_v4i64__3_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4i64_v4i64__3_4_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4i64_v4i64__3_4_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -7777,11 +7879,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: v_mov_b32_e32 v2, v0
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v10, v[0:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -7791,11 +7895,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v0
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v10, v[0:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -7805,11 +7911,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v10, v[0:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -9135,11 +9243,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: v_mov_b32_e32 v4, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v3
-; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -9149,11 +9259,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
; GFX90A-NEXT: v_mov_b32_e32 v5, v3
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -9163,11 +9275,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: v_mov_b32_e32 v4, v2
; GFX942-NEXT: v_mov_b32_e32 v5, v3
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -10521,11 +10635,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_6_6(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: v_mov_b32_e32 v2, v4
; GFX900-NEXT: v_mov_b32_e32 v3, v5
-; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -10535,11 +10651,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_6_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v4
; GFX90A-NEXT: v_mov_b32_e32 v3, v5
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -10549,11 +10667,13 @@ define void @v_shuffle_v4i64_v4i64__7_u_6_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v4
; GFX942-NEXT: v_mov_b32_e32 v3, v5
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=v"()
@@ -11871,6 +11991,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_7_7(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: v_mov_b32_e32 v8, v6
; GFX900-NEXT: v_mov_b32_e32 v9, v7
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -11885,6 +12007,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_7_7(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
; GFX90A-NEXT: v_mov_b32_e32 v9, v7
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -11900,6 +12024,8 @@ define void @v_shuffle_v4i64_v4i64__7_u_7_7(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v8, v6
; GFX942-NEXT: v_mov_b32_e32 v9, v7
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -12898,6 +13024,12 @@ define void @s_shuffle_v4i64_v4i64__1_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -12911,6 +13043,12 @@ define void @s_shuffle_v4i64_v4i64__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -12924,6 +13062,12 @@ define void @s_shuffle_v4i64_v4i64__1_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -12941,6 +13085,12 @@ define void @s_shuffle_v4i64_v4i64__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -12952,6 +13102,12 @@ define void @s_shuffle_v4i64_v4i64__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -12963,6 +13119,12 @@ define void @s_shuffle_v4i64_v4i64__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -12983,6 +13145,12 @@ define void @s_shuffle_v4i64_v4i64__3_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -12996,6 +13164,12 @@ define void @s_shuffle_v4i64_v4i64__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13009,6 +13183,12 @@ define void @s_shuffle_v4i64_v4i64__3_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13042,6 +13222,12 @@ define void @s_shuffle_v4i64_v4i64__5_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13055,6 +13241,12 @@ define void @s_shuffle_v4i64_v4i64__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13068,6 +13260,12 @@ define void @s_shuffle_v4i64_v4i64__5_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13086,6 +13284,12 @@ define void @s_shuffle_v4i64_v4i64__6_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13097,6 +13301,12 @@ define void @s_shuffle_v4i64_v4i64__6_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13108,6 +13318,12 @@ define void @s_shuffle_v4i64_v4i64__6_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -13129,6 +13345,12 @@ define void @s_shuffle_v4i64_v4i64__7_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13142,6 +13364,12 @@ define void @s_shuffle_v4i64_v4i64__7_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13155,6 +13383,12 @@ define void @s_shuffle_v4i64_v4i64__7_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13180,6 +13414,10 @@ define void @s_shuffle_v4i64_v4i64__7_0_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13198,6 +13436,10 @@ define void @s_shuffle_v4i64_v4i64__7_0_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13209,6 +13451,10 @@ define void @s_shuffle_v4i64_v4i64__7_0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
@@ -13240,6 +13486,10 @@ define void @s_shuffle_v4i64_v4i64__7_1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13256,6 +13506,10 @@ define void @s_shuffle_v4i64_v4i64__7_1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13272,6 +13526,10 @@ define void @s_shuffle_v4i64_v4i64__7_1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13297,6 +13555,10 @@ define void @s_shuffle_v4i64_v4i64__7_2_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13315,6 +13577,10 @@ define void @s_shuffle_v4i64_v4i64__7_2_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13333,6 +13599,10 @@ define void @s_shuffle_v4i64_v4i64__7_2_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s15
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13356,6 +13626,10 @@ define void @s_shuffle_v4i64_v4i64__7_3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13372,6 +13646,10 @@ define void @s_shuffle_v4i64_v4i64__7_3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13383,6 +13661,10 @@ define void @s_shuffle_v4i64_v4i64__7_3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
@@ -13411,6 +13693,10 @@ define void @s_shuffle_v4i64_v4i64__7_4_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13426,6 +13712,10 @@ define void @s_shuffle_v4i64_v4i64__7_4_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13441,6 +13731,10 @@ define void @s_shuffle_v4i64_v4i64__7_4_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13461,6 +13755,10 @@ define void @s_shuffle_v4i64_v4i64__7_5_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s14
; GFX9-NEXT: s_mov_b32 s9, s15
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13483,6 +13781,10 @@ define void @s_shuffle_v4i64_v4i64__7_6_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13498,6 +13800,10 @@ define void @s_shuffle_v4i64_v4i64__7_6_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13513,6 +13819,10 @@ define void @s_shuffle_v4i64_v4i64__7_6_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13533,6 +13843,10 @@ define void @s_shuffle_v4i64_v4i64__7_7_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13549,13 +13863,15 @@ define void @s_shuffle_v4i64_v4i64__7_7_0_u() {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[4:11]
+; GFX9-NEXT: ; def s[12:19]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[12:19]
+; GFX9-NEXT: ; def s[4:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13581,6 +13897,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_1_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s12, s14
; GFX900-NEXT: s_mov_b32 s13, s15
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13599,6 +13917,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_1_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s12, s14
; GFX90A-NEXT: s_mov_b32 s13, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13617,6 +13937,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_1_u() {
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
; GFX942-NEXT: s_mov_b32 s13, s3
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13640,6 +13962,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13656,6 +13980,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13667,6 +13993,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
@@ -13698,6 +14026,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_3_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s12, s14
; GFX900-NEXT: s_mov_b32 s13, s15
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13716,6 +14046,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_3_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s12, s14
; GFX90A-NEXT: s_mov_b32 s13, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13734,6 +14066,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_3_u() {
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
; GFX942-NEXT: s_mov_b32 s13, s15
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13756,6 +14090,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_4_u() {
; GFX9-NEXT: s_mov_b32 s9, s11
; GFX9-NEXT: s_mov_b32 s12, s4
; GFX9-NEXT: s_mov_b32 s13, s5
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13778,6 +14114,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_5_u() {
; GFX9-NEXT: s_mov_b32 s9, s11
; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s13, s7
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13800,6 +14138,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_6_u() {
; GFX9-NEXT: s_mov_b32 s9, s15
; GFX9-NEXT: s_mov_b32 s10, s14
; GFX9-NEXT: s_mov_b32 s11, s15
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13822,6 +14162,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_7_u() {
; GFX9-NEXT: s_mov_b32 s9, s11
; GFX9-NEXT: s_mov_b32 s12, s10
; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -14896,15 +15238,17 @@ define void @s_shuffle_v4i64_v4i64__7_7_u_0() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[12:19]
+; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[16:23]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: s_mov_b32 s14, s16
+; GFX900-NEXT: s_mov_b32 s15, s17
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -14914,15 +15258,17 @@ define void @s_shuffle_v4i64_v4i64__7_7_u_0() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[12:19]
+; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[16:23]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: s_mov_b32 s14, s16
+; GFX90A-NEXT: s_mov_b32 s15, s17
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -14934,6 +15280,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
@@ -17078,59 +17426,25 @@ define void @s_shuffle_v4i64_v4i64__7_7_2_2() {
}
define void @s_shuffle_v4i64_v4i64__7_7_u_2() {
-; GFX900-LABEL: s_shuffle_v4i64_v4i64__7_7_u_2:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[8:15]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s10
-; GFX900-NEXT: s_mov_b32 s9, s11
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use s[8:15]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX90A-LABEL: s_shuffle_v4i64_v4i64__7_7_u_2:
-; GFX90A: ; %bb.0:
-; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[8:15]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s10
-; GFX90A-NEXT: s_mov_b32 s9, s11
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; use s[8:15]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX942-LABEL: s_shuffle_v4i64_v4i64__7_7_u_2:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[8:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s14, s12
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[4:11]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s8, s10
-; GFX942-NEXT: s_mov_b32 s9, s11
-; GFX942-NEXT: s_mov_b32 s15, s13
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; use s[8:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: s_shuffle_v4i64_v4i64__7_7_u_2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[12:19]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[4:11]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_mov_b32 s8, s10
+; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: s_mov_b32 s14, s16
+; GFX9-NEXT: s_mov_b32 s15, s17
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use s[8:15]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x i64> asm "; def $0", "=s"()
%vec1 = call <4 x i64> asm "; def $0", "=s"()
%shuf = shufflevector <4 x i64> %vec0, <4 x i64> %vec1, <4 x i32> <i32 7, i32 7, i32 poison, i32 2>
@@ -18605,6 +18919,12 @@ define void @s_shuffle_v4i64_v4i64__1_4_4_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -18618,6 +18938,12 @@ define void @s_shuffle_v4i64_v4i64__1_4_4_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -18631,6 +18957,12 @@ define void @s_shuffle_v4i64_v4i64__1_4_4_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -18648,6 +18980,12 @@ define void @s_shuffle_v4i64_v4i64__2_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -18659,6 +18997,12 @@ define void @s_shuffle_v4i64_v4i64__2_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -18670,6 +19014,12 @@ define void @s_shuffle_v4i64_v4i64__2_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -18690,6 +19040,12 @@ define void @s_shuffle_v4i64_v4i64__3_4_4_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -18703,6 +19059,12 @@ define void @s_shuffle_v4i64_v4i64__3_4_4_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -18716,6 +19078,12 @@ define void @s_shuffle_v4i64_v4i64__3_4_4_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -21192,14 +21560,16 @@ define void @s_shuffle_v4i64_v4i64__7_7_u_6() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[8:15]
+; GFX900-NEXT: ; def s[12:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s14
-; GFX900-NEXT: s_mov_b32 s9, s15
-; GFX900-NEXT: s_mov_b32 s10, s14
-; GFX900-NEXT: s_mov_b32 s11, s15
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
+; GFX900-NEXT: s_mov_b32 s8, s18
+; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: s_mov_b32 s10, s18
+; GFX900-NEXT: s_mov_b32 s11, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: s_mov_b32 s14, s16
+; GFX900-NEXT: s_mov_b32 s15, s17
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -21209,14 +21579,16 @@ define void @s_shuffle_v4i64_v4i64__7_7_u_6() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[8:15]
+; GFX90A-NEXT: ; def s[12:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s14
-; GFX90A-NEXT: s_mov_b32 s9, s15
-; GFX90A-NEXT: s_mov_b32 s10, s14
-; GFX90A-NEXT: s_mov_b32 s11, s15
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
+; GFX90A-NEXT: s_mov_b32 s8, s18
+; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: s_mov_b32 s10, s18
+; GFX90A-NEXT: s_mov_b32 s11, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: s_mov_b32 s14, s16
+; GFX90A-NEXT: s_mov_b32 s15, s17
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -21232,6 +21604,8 @@ define void @s_shuffle_v4i64_v4i64__7_7_u_6() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s6
; GFX942-NEXT: s_mov_b32 s11, s7
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s4
; GFX942-NEXT: s_mov_b32 s15, s5
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
index ce30d041acd8a..5a8cf81df7086 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v2p0.ll
@@ -58,33 +58,39 @@ define void @v_shuffle_v4p0_v2p0__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v2p0__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v2p0__1_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v2p0__1_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -108,33 +114,39 @@ define void @v_shuffle_v4p0_v2p0__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v2p0__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v2p0__3_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v2p0__3_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -348,6 +360,8 @@ define void @v_shuffle_v4p0_v2p0__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v4, v2
@@ -366,6 +380,8 @@ define void @v_shuffle_v4p0_v2p0__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
@@ -384,6 +400,8 @@ define void @v_shuffle_v4p0_v2p0__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mov_b32_e32 v4, v2
@@ -411,6 +429,8 @@ define void @v_shuffle_v4p0_v2p0__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
@@ -428,6 +448,8 @@ define void @v_shuffle_v4p0_v2p0__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -443,6 +465,8 @@ define void @v_shuffle_v4p0_v2p0__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1] offset:16
; GFX942-NEXT: v_mov_b32_e32 v8, v6
; GFX942-NEXT: v_mov_b32_e32 v9, v7
@@ -1060,6 +1084,8 @@ define void @v_shuffle_v4p0_v2p0__3_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1077,6 +1103,8 @@ define void @v_shuffle_v4p0_v2p0__3_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1094,6 +1122,8 @@ define void @v_shuffle_v4p0_v2p0__3_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1752,14 +1782,16 @@ define void @v_shuffle_v4p0_v2p0__3_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[4:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v3
-; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -1769,14 +1801,16 @@ define void @v_shuffle_v4p0_v2p0__3_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
; GFX90A-NEXT: v_mov_b32_e32 v5, v3
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1786,15 +1820,17 @@ define void @v_shuffle_v4p0_v2p0__3_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v2
; GFX942-NEXT: v_mov_b32_e32 v5, v3
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -2237,33 +2273,39 @@ define void @v_shuffle_v4p0_v2p0__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v2p0__1_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v2p0__1_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v2p0__1_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -2343,43 +2385,49 @@ define void @v_shuffle_v4p0_v2p0__3_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v2p0__3_u_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v0, v2
; GFX900-NEXT: v_mov_b32_e32 v1, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v2p0__3_u_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
-; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v2p0__3_u_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v2
; GFX942-NEXT: v_mov_b32_e32 v1, v3
-; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr> asm "; def $0", "=v"()
@@ -2968,6 +3016,8 @@ define void @v_shuffle_v4p0_v2p0__3_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: v_mov_b32_e32 v4, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v3
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2982,6 +3032,8 @@ define void @v_shuffle_v4p0_v2p0__3_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
; GFX90A-NEXT: v_mov_b32_e32 v5, v3
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2997,6 +3049,8 @@ define void @v_shuffle_v4p0_v2p0__3_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, v2
; GFX942-NEXT: v_mov_b32_e32 v5, v3
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3453,6 +3507,10 @@ define void @s_shuffle_v4p0_v2p0__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3464,6 +3522,10 @@ define void @s_shuffle_v4p0_v2p0__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3475,6 +3537,10 @@ define void @s_shuffle_v4p0_v2p0__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -3495,6 +3561,12 @@ define void @s_shuffle_v4p0_v2p0__1_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3508,6 +3580,12 @@ define void @s_shuffle_v4p0_v2p0__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3521,6 +3599,12 @@ define void @s_shuffle_v4p0_v2p0__1_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3554,6 +3638,12 @@ define void @s_shuffle_v4p0_v2p0__3_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3567,6 +3657,12 @@ define void @s_shuffle_v4p0_v2p0__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3580,6 +3676,12 @@ define void @s_shuffle_v4p0_v2p0__3_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3605,6 +3707,10 @@ define void @s_shuffle_v4p0_v2p0__3_0_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3623,6 +3729,10 @@ define void @s_shuffle_v4p0_v2p0__3_0_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3641,6 +3751,10 @@ define void @s_shuffle_v4p0_v2p0__3_0_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3664,6 +3778,10 @@ define void @s_shuffle_v4p0_v2p0__3_1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3680,6 +3798,10 @@ define void @s_shuffle_v4p0_v2p0__3_1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3696,6 +3818,10 @@ define void @s_shuffle_v4p0_v2p0__3_1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3718,6 +3844,10 @@ define void @s_shuffle_v4p0_v2p0__3_2_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3733,6 +3863,10 @@ define void @s_shuffle_v4p0_v2p0__3_2_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3748,6 +3882,10 @@ define void @s_shuffle_v4p0_v2p0__3_2_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3768,6 +3906,10 @@ define void @s_shuffle_v4p0_v2p0__3_3_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -3784,13 +3926,15 @@ define void @s_shuffle_v4p0_v2p0__3_3_0_u() {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[8:11]
+; GFX9-NEXT: ; def s[12:15]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[12:15]
+; GFX9-NEXT: ; def s[8:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -3816,6 +3960,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_1_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s12, s6
; GFX900-NEXT: s_mov_b32 s13, s7
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -3834,6 +3980,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_1_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s12, s6
; GFX90A-NEXT: s_mov_b32 s13, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -3852,6 +4000,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_1_u() {
; GFX942-NEXT: s_mov_b32 s9, s11
; GFX942-NEXT: s_mov_b32 s12, s2
; GFX942-NEXT: s_mov_b32 s13, s3
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -3874,6 +4024,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_2_u() {
; GFX9-NEXT: s_mov_b32 s9, s15
; GFX9-NEXT: s_mov_b32 s10, s14
; GFX9-NEXT: s_mov_b32 s11, s15
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -3896,6 +4048,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_3_u() {
; GFX9-NEXT: s_mov_b32 s9, s11
; GFX9-NEXT: s_mov_b32 s12, s10
; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -4474,6 +4628,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_u_0() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: s_mov_b32 s14, s4
; GFX900-NEXT: s_mov_b32 s15, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -4492,6 +4648,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_u_0() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: s_mov_b32 s14, s4
; GFX90A-NEXT: s_mov_b32 s15, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -4510,6 +4668,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_u_0() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s0
; GFX942-NEXT: s_mov_b32 s15, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -5164,6 +5324,10 @@ define void @s_shuffle_v4p0_v2p0__0_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -5175,6 +5339,10 @@ define void @s_shuffle_v4p0_v2p0__0_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -5186,6 +5354,10 @@ define void @s_shuffle_v4p0_v2p0__0_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -5206,6 +5378,12 @@ define void @s_shuffle_v4p0_v2p0__1_2_2_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -5219,6 +5397,12 @@ define void @s_shuffle_v4p0_v2p0__1_2_2_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -5232,6 +5416,12 @@ define void @s_shuffle_v4p0_v2p0__1_2_2_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -5429,6 +5619,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_u_2() {
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s6
; GFX900-NEXT: s_mov_b32 s11, s7
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: s_mov_b32 s14, s4
; GFX900-NEXT: s_mov_b32 s15, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -5446,6 +5638,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_u_2() {
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s6
; GFX90A-NEXT: s_mov_b32 s11, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: s_mov_b32 s14, s4
; GFX90A-NEXT: s_mov_b32 s15, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -5463,6 +5657,8 @@ define void @s_shuffle_v4p0_v2p0__3_3_u_2() {
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s2
; GFX942-NEXT: s_mov_b32 s11, s3
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s0
; GFX942-NEXT: s_mov_b32 s15, s1
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
index 206c09eb78f44..77b3d00165a56 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
@@ -65,6 +65,8 @@ define void @v_shuffle_v4p0_v3p0__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -76,6 +78,8 @@ define void @v_shuffle_v4p0_v3p0__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +91,8 @@ define void @v_shuffle_v4p0_v3p0__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -100,33 +106,39 @@ define void @v_shuffle_v4p0_v3p0__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v3p0__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v3p0__2_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v3p0__2_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -154,6 +166,8 @@ define void @v_shuffle_v4p0_v3p0__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -165,6 +179,8 @@ define void @v_shuffle_v4p0_v3p0__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -176,6 +192,8 @@ define void @v_shuffle_v4p0_v3p0__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -190,33 +208,39 @@ define void @v_shuffle_v4p0_v3p0__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v3p0__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v3p0__5_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v3p0__5_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -527,6 +551,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v6, v4
@@ -545,6 +571,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v6, v4
@@ -563,6 +591,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v12, v[6:9], s[0:1] offset:16
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mov_b32_e32 v6, v4
@@ -588,6 +618,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v6, v4
@@ -606,6 +638,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v6, v4
@@ -621,6 +655,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1] offset:16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
@@ -651,6 +687,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v14, v[4:7], s[16:17] offset:16
; GFX900-NEXT: global_store_dwordx4 v14, v[10:13], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
@@ -668,6 +706,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v14, v[4:7], s[16:17] offset:16
; GFX90A-NEXT: global_store_dwordx4 v14, v[10:13], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -683,6 +723,8 @@ define void @v_shuffle_v4p0_v3p0__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v14, v[4:7], s[0:1] offset:16
; GFX942-NEXT: v_mov_b32_e32 v12, v10
; GFX942-NEXT: v_mov_b32_e32 v13, v11
@@ -1588,6 +1630,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1605,6 +1649,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1622,6 +1668,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v12, v[6:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v12, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -2663,6 +2711,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v10, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2680,6 +2730,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v10, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2697,6 +2749,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v10, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3734,14 +3788,16 @@ define void @v_shuffle_v4p0_v3p0__5_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[6:11]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v12, 0
+; GFX900-NEXT: v_mov_b32_e32 v14, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v6, v4
; GFX900-NEXT: v_mov_b32_e32 v7, v5
-; GFX900-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v12, v[10:13], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v14, v[4:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr12
+; GFX900-NEXT: ; implicit-def: $vgpr13
+; GFX900-NEXT: global_store_dwordx4 v14, v[10:13], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -3751,14 +3807,16 @@ define void @v_shuffle_v4p0_v3p0__5_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[6:11]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v12, 0
+; GFX90A-NEXT: v_mov_b32_e32 v14, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, v4
; GFX90A-NEXT: v_mov_b32_e32 v7, v5
-; GFX90A-NEXT: global_store_dwordx4 v12, v[4:7], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v12, v[10:13], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v14, v[4:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr12
+; GFX90A-NEXT: ; implicit-def: $vgpr13
+; GFX90A-NEXT: global_store_dwordx4 v14, v[10:13], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -3768,15 +3826,17 @@ define void @v_shuffle_v4p0_v3p0__5_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:11]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v12, 0
+; GFX942-NEXT: v_mov_b32_e32 v14, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v6, v4
; GFX942-NEXT: v_mov_b32_e32 v7, v5
-; GFX942-NEXT: global_store_dwordx4 v12, v[4:7], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v12, v[10:13], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v14, v[4:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr12
+; GFX942-NEXT: ; implicit-def: $vgpr13
+; GFX942-NEXT: global_store_dwordx4 v14, v[10:13], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -4481,6 +4541,8 @@ define void @v_shuffle_v4p0_v3p0__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -4492,6 +4554,8 @@ define void @v_shuffle_v4p0_v3p0__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -4503,6 +4567,8 @@ define void @v_shuffle_v4p0_v3p0__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -4516,33 +4582,39 @@ define void @v_shuffle_v4p0_v3p0__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v3p0__2_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v3p0__2_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v3p0__2_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -4679,11 +4751,13 @@ define void @v_shuffle_v4p0_v3p0__5_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: v_mov_b32_e32 v2, v0
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -4693,11 +4767,13 @@ define void @v_shuffle_v4p0_v3p0__5_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v0
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -4707,11 +4783,13 @@ define void @v_shuffle_v4p0_v3p0__5_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -5690,11 +5768,13 @@ define void @v_shuffle_v4p0_v3p0__5_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v8, 0
; GFX900-NEXT: v_mov_b32_e32 v0, v2
; GFX900-NEXT: v_mov_b32_e32 v1, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
+; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -5704,11 +5784,13 @@ define void @v_shuffle_v4p0_v3p0__5_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v2
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
-; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v6, v[4:7], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -5718,11 +5800,13 @@ define void @v_shuffle_v4p0_v3p0__5_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v2
; GFX942-NEXT: v_mov_b32_e32 v1, v3
-; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v6, v[4:7], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=v"()
@@ -6684,6 +6768,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: v_mov_b32_e32 v6, v4
; GFX900-NEXT: v_mov_b32_e32 v7, v5
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -6698,6 +6784,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v6, v4
; GFX90A-NEXT: v_mov_b32_e32 v7, v5
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6713,6 +6801,8 @@ define void @v_shuffle_v4p0_v3p0__5_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v6, v4
; GFX942-NEXT: v_mov_b32_e32 v7, v5
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7419,6 +7509,8 @@ define void @s_shuffle_v4p0_v3p0__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7430,6 +7522,8 @@ define void @s_shuffle_v4p0_v3p0__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7441,6 +7535,8 @@ define void @s_shuffle_v4p0_v3p0__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -7461,6 +7557,12 @@ define void @s_shuffle_v4p0_v3p0__1_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7474,6 +7576,12 @@ define void @s_shuffle_v4p0_v3p0__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7487,6 +7595,12 @@ define void @s_shuffle_v4p0_v3p0__1_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7504,6 +7618,12 @@ define void @s_shuffle_v4p0_v3p0__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7515,6 +7635,12 @@ define void @s_shuffle_v4p0_v3p0__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7526,6 +7652,12 @@ define void @s_shuffle_v4p0_v3p0__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -7560,6 +7692,12 @@ define void @s_shuffle_v4p0_v3p0__4_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7573,6 +7711,12 @@ define void @s_shuffle_v4p0_v3p0__4_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7586,6 +7730,12 @@ define void @s_shuffle_v4p0_v3p0__4_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7604,6 +7754,12 @@ define void @s_shuffle_v4p0_v3p0__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7615,6 +7771,12 @@ define void @s_shuffle_v4p0_v3p0__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7626,6 +7788,12 @@ define void @s_shuffle_v4p0_v3p0__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -7650,6 +7818,10 @@ define void @s_shuffle_v4p0_v3p0__5_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7666,6 +7838,10 @@ define void @s_shuffle_v4p0_v3p0__5_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7682,6 +7858,10 @@ define void @s_shuffle_v4p0_v3p0__5_0_u_u() {
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7700,9 +7880,13 @@ define void @s_shuffle_v4p0_v3p0__5_1_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7714,9 +7898,13 @@ define void @s_shuffle_v4p0_v3p0__5_1_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7728,6 +7916,10 @@ define void @s_shuffle_v4p0_v3p0__5_1_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -7756,6 +7948,10 @@ define void @s_shuffle_v4p0_v3p0__5_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7772,6 +7968,10 @@ define void @s_shuffle_v4p0_v3p0__5_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7788,6 +7988,10 @@ define void @s_shuffle_v4p0_v3p0__5_2_u_u() {
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7808,6 +8012,10 @@ define void @s_shuffle_v4p0_v3p0__5_3_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s4
; GFX9-NEXT: s_mov_b32 s11, s5
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -7828,6 +8036,10 @@ define void @s_shuffle_v4p0_v3p0__5_4_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s6
; GFX9-NEXT: s_mov_b32 s11, s7
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -7848,6 +8060,10 @@ define void @s_shuffle_v4p0_v3p0__5_5_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s8
; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -7871,6 +8087,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_0_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s10, s8
; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -7896,6 +8114,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_1_u() {
; GFX900-NEXT: s_mov_b32 s11, s9
; GFX900-NEXT: s_mov_b32 s12, s14
; GFX900-NEXT: s_mov_b32 s13, s15
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7914,6 +8134,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_1_u() {
; GFX90A-NEXT: s_mov_b32 s11, s9
; GFX90A-NEXT: s_mov_b32 s12, s14
; GFX90A-NEXT: s_mov_b32 s13, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7932,6 +8154,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_1_u() {
; GFX942-NEXT: s_mov_b32 s10, s8
; GFX942-NEXT: s_mov_b32 s11, s9
; GFX942-NEXT: s_mov_b32 s13, s3
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -7955,6 +8179,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s8
; GFX900-NEXT: s_mov_b32 s11, s9
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -7971,6 +8197,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s8
; GFX90A-NEXT: s_mov_b32 s11, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -7982,6 +8210,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -8010,6 +8240,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_3_u() {
; GFX9-NEXT: s_mov_b32 s11, s9
; GFX9-NEXT: s_mov_b32 s12, s4
; GFX9-NEXT: s_mov_b32 s13, s5
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -8032,6 +8264,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_4_u() {
; GFX9-NEXT: s_mov_b32 s11, s9
; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s13, s7
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -8054,6 +8288,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_5_u() {
; GFX9-NEXT: s_mov_b32 s11, s9
; GFX9-NEXT: s_mov_b32 s12, s8
; GFX9-NEXT: s_mov_b32 s13, s9
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -8612,15 +8848,17 @@ define void @s_shuffle_v4p0_v3p0__5_5_u_0() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[12:17]
+; GFX900-NEXT: ; def s[16:21]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s10, s8
; GFX900-NEXT: s_mov_b32 s11, s9
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: s_mov_b32 s14, s16
+; GFX900-NEXT: s_mov_b32 s15, s17
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -8630,15 +8868,17 @@ define void @s_shuffle_v4p0_v3p0__5_5_u_0() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[12:17]
+; GFX90A-NEXT: ; def s[16:21]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s10, s8
; GFX90A-NEXT: s_mov_b32 s11, s9
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: s_mov_b32 s14, s16
+; GFX90A-NEXT: s_mov_b32 s15, s17
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -8650,6 +8890,8 @@ define void @s_shuffle_v4p0_v3p0__5_5_u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
@@ -9960,59 +10202,25 @@ define void @s_shuffle_v4p0_v3p0__5_5_2_2() {
}
define void @s_shuffle_v4p0_v3p0__5_5_u_2() {
-; GFX900-LABEL: s_shuffle_v4p0_v3p0__5_5_u_2:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[8:13]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:9]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s10, s8
-; GFX900-NEXT: s_mov_b32 s11, s9
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use s[8:15]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX90A-LABEL: s_shuffle_v4p0_v3p0__5_5_u_2:
-; GFX90A: ; %bb.0:
-; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[8:13]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:9]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s10, s8
-; GFX90A-NEXT: s_mov_b32 s11, s9
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; use s[8:15]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX942-LABEL: s_shuffle_v4p0_v3p0__5_5_u_2:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[8:13]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s14, s12
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[4:9]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s8
-; GFX942-NEXT: s_mov_b32 s11, s9
-; GFX942-NEXT: s_mov_b32 s15, s13
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; use s[8:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: s_shuffle_v4p0_v3p0__5_5_u_2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[12:17]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[4:9]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_mov_b32 s10, s8
+; GFX9-NEXT: s_mov_b32 s11, s9
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: s_mov_b32 s14, s16
+; GFX9-NEXT: s_mov_b32 s15, s17
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use s[8:15]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr> asm "; def $0", "=s"()
%vec1 = call <3 x ptr> asm "; def $0", "=s"()
%shuf = shufflevector <3 x ptr> %vec0, <3 x ptr> %vec1, <4 x i32> <i32 5, i32 5, i32 poison, i32 2>
@@ -10147,6 +10355,8 @@ define void @s_shuffle_v4p0_v3p0__0_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:13]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -10158,6 +10368,8 @@ define void @s_shuffle_v4p0_v3p0__0_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:13]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -10169,6 +10381,8 @@ define void @s_shuffle_v4p0_v3p0__0_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -10189,6 +10403,12 @@ define void @s_shuffle_v4p0_v3p0__1_3_3_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -10202,6 +10422,12 @@ define void @s_shuffle_v4p0_v3p0__1_3_3_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -10215,6 +10441,12 @@ define void @s_shuffle_v4p0_v3p0__1_3_3_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -10232,6 +10464,12 @@ define void @s_shuffle_v4p0_v3p0__2_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -10243,6 +10481,12 @@ define void @s_shuffle_v4p0_v3p0__2_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -10254,6 +10498,12 @@ define void @s_shuffle_v4p0_v3p0__2_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
index 8e905b09c5fdc..3257a4cf58a7f 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
@@ -65,6 +65,8 @@ define void @v_shuffle_v4p0_v4p0__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -76,6 +78,8 @@ define void @v_shuffle_v4p0_v4p0__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -87,6 +91,8 @@ define void @v_shuffle_v4p0_v4p0__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -104,6 +110,8 @@ define void @v_shuffle_v4p0_v4p0__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -115,6 +123,8 @@ define void @v_shuffle_v4p0_v4p0__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -126,6 +136,8 @@ define void @v_shuffle_v4p0_v4p0__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -139,33 +151,39 @@ define void @v_shuffle_v4p0_v4p0__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v4p0__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v4p0__3_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v4p0__3_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -193,6 +211,8 @@ define void @v_shuffle_v4p0_v4p0__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -204,6 +224,8 @@ define void @v_shuffle_v4p0_v4p0__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -215,6 +237,8 @@ define void @v_shuffle_v4p0_v4p0__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -233,6 +257,8 @@ define void @v_shuffle_v4p0_v4p0__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -244,6 +270,8 @@ define void @v_shuffle_v4p0_v4p0__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -255,6 +283,8 @@ define void @v_shuffle_v4p0_v4p0__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -269,33 +299,39 @@ define void @v_shuffle_v4p0_v4p0__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v4p0__7_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v4p0__7_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v4p0__7_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -703,6 +739,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr10
+; GFX900-NEXT: ; implicit-def: $vgpr11
; GFX900-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v8, v6
@@ -721,6 +759,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr10
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
@@ -739,6 +779,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr10
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:16
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_mov_b32_e32 v8, v6
@@ -764,6 +806,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr10
+; GFX900-NEXT: ; implicit-def: $vgpr11
; GFX900-NEXT: global_store_dwordx4 v14, v[8:11], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v8, v6
@@ -782,6 +826,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr10
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: global_store_dwordx4 v14, v[8:11], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
@@ -797,6 +843,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[6:13]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr10
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: global_store_dwordx4 v14, v[8:11], s[0:1] offset:16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
@@ -825,6 +873,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr10
+; GFX900-NEXT: ; implicit-def: $vgpr11
; GFX900-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: v_mov_b32_e32 v8, v6
@@ -843,6 +893,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr10
+; GFX90A-NEXT: ; implicit-def: $vgpr11
; GFX90A-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:16
; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
@@ -858,6 +910,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr10
+; GFX942-NEXT: ; implicit-def: $vgpr11
; GFX942-NEXT: global_store_dwordx4 v12, v[8:11], s[0:1] offset:16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
@@ -883,6 +937,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: ;;#ASMSTART
@@ -906,6 +962,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v18, v[6:9], s[16:17] offset:16
; GFX90A-NEXT: global_store_dwordx4 v18, v[14:17], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
@@ -921,6 +979,8 @@ define void @v_shuffle_v4p0_v4p0__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v18, v[6:9], s[0:1] offset:16
; GFX942-NEXT: v_mov_b32_e32 v16, v14
; GFX942-NEXT: v_mov_b32_e32 v17, v15
@@ -2115,6 +2175,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -2132,6 +2194,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2149,6 +2213,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_0_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -3574,6 +3640,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v14, v[8:11], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v14, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -3591,6 +3659,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v14, v[8:11], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v14, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -3608,6 +3678,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_1_1(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v14, v[8:11], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v14, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -5030,6 +5102,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -5047,6 +5121,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: global_store_dwordx4 v12, v[8:11], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v12, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -5064,6 +5140,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: global_store_dwordx4 v12, v[8:11], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v12, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6482,6 +6560,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: v_mov_b32_e32 v8, v6
; GFX900-NEXT: v_mov_b32_e32 v9, v7
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: s_nop 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
@@ -6496,14 +6576,16 @@ define void @v_shuffle_v4p0_v4p0__7_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[8:15]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v16, 0
+; GFX90A-NEXT: v_mov_b32_e32 v18, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
; GFX90A-NEXT: v_mov_b32_e32 v9, v7
-; GFX90A-NEXT: global_store_dwordx4 v16, v[6:9], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v16, v[14:17], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v18, v[6:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr16
+; GFX90A-NEXT: ; implicit-def: $vgpr17
+; GFX90A-NEXT: global_store_dwordx4 v18, v[14:17], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -6513,15 +6595,17 @@ define void @v_shuffle_v4p0_v4p0__7_u_3_3(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[8:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v16, 0
+; GFX942-NEXT: v_mov_b32_e32 v18, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v8, v6
; GFX942-NEXT: v_mov_b32_e32 v9, v7
-; GFX942-NEXT: global_store_dwordx4 v16, v[6:9], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v16, v[14:17], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v18, v[6:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr16
+; GFX942-NEXT: ; implicit-def: $vgpr17
+; GFX942-NEXT: global_store_dwordx4 v18, v[14:17], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -7485,6 +7569,8 @@ define void @v_shuffle_v4p0_v4p0__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7496,6 +7582,8 @@ define void @v_shuffle_v4p0_v4p0__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7507,6 +7595,8 @@ define void @v_shuffle_v4p0_v4p0__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7524,6 +7614,8 @@ define void @v_shuffle_v4p0_v4p0__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: ; implicit-def: $vgpr7
; GFX900-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -7535,6 +7627,8 @@ define void @v_shuffle_v4p0_v4p0__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -7546,6 +7640,8 @@ define void @v_shuffle_v4p0_v4p0__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7559,33 +7655,39 @@ define void @v_shuffle_v4p0_v4p0__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p0_v4p0__3_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p0_v4p0__3_4_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p0_v4p0__3_4_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -7777,11 +7879,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: v_mov_b32_e32 v2, v0
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v10, v[0:3], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -7791,11 +7895,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v0
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v10, v[0:3], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -7805,11 +7911,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v10, v[0:3], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -9135,11 +9243,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: v_mov_b32_e32 v4, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v3
-; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -9149,11 +9259,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
; GFX90A-NEXT: v_mov_b32_e32 v5, v3
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -9163,11 +9275,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: v_mov_b32_e32 v4, v2
; GFX942-NEXT: v_mov_b32_e32 v5, v3
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -10521,11 +10635,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_6_6(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:7]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v8, 0
+; GFX900-NEXT: v_mov_b32_e32 v10, 0
; GFX900-NEXT: v_mov_b32_e32 v2, v4
; GFX900-NEXT: v_mov_b32_e32 v3, v5
-; GFX900-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX900-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX900-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
+; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -10535,11 +10651,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_6_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:7]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v4
; GFX90A-NEXT: v_mov_b32_e32 v3, v5
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17] offset:16
-; GFX90A-NEXT: global_store_dwordx4 v8, v[6:9], s[16:17]
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
+; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -10549,11 +10667,13 @@ define void @v_shuffle_v4p0_v4p0__7_u_6_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v4
; GFX942-NEXT: v_mov_b32_e32 v3, v5
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1] offset:16
-; GFX942-NEXT: global_store_dwordx4 v8, v[6:9], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
+; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=v"()
@@ -11871,6 +11991,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_7_7(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: v_mov_b32_e32 v8, v6
; GFX900-NEXT: v_mov_b32_e32 v9, v7
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX900-NEXT: ; implicit-def: $vgpr8
+; GFX900-NEXT: ; implicit-def: $vgpr9
; GFX900-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -11885,6 +12007,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_7_7(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v8, v6
; GFX90A-NEXT: v_mov_b32_e32 v9, v7
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17] offset:16
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: ; implicit-def: $vgpr9
; GFX90A-NEXT: global_store_dwordx4 v10, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -11900,6 +12024,8 @@ define void @v_shuffle_v4p0_v4p0__7_u_7_7(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v8, v6
; GFX942-NEXT: v_mov_b32_e32 v9, v7
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1] offset:16
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: ; implicit-def: $vgpr9
; GFX942-NEXT: global_store_dwordx4 v10, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -12898,6 +13024,12 @@ define void @s_shuffle_v4p0_v4p0__1_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -12911,6 +13043,12 @@ define void @s_shuffle_v4p0_v4p0__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -12924,6 +13062,12 @@ define void @s_shuffle_v4p0_v4p0__1_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -12941,6 +13085,12 @@ define void @s_shuffle_v4p0_v4p0__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -12952,6 +13102,12 @@ define void @s_shuffle_v4p0_v4p0__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -12963,6 +13119,12 @@ define void @s_shuffle_v4p0_v4p0__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -12983,6 +13145,12 @@ define void @s_shuffle_v4p0_v4p0__3_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -12996,6 +13164,12 @@ define void @s_shuffle_v4p0_v4p0__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13009,6 +13183,12 @@ define void @s_shuffle_v4p0_v4p0__3_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13042,6 +13222,12 @@ define void @s_shuffle_v4p0_v4p0__5_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13055,6 +13241,12 @@ define void @s_shuffle_v4p0_v4p0__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13068,6 +13260,12 @@ define void @s_shuffle_v4p0_v4p0__5_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13086,6 +13284,12 @@ define void @s_shuffle_v4p0_v4p0__6_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13097,6 +13301,12 @@ define void @s_shuffle_v4p0_v4p0__6_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13108,6 +13318,12 @@ define void @s_shuffle_v4p0_v4p0__6_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -13129,6 +13345,12 @@ define void @s_shuffle_v4p0_v4p0__7_u_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13142,6 +13364,12 @@ define void @s_shuffle_v4p0_v4p0__7_u_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13155,6 +13383,12 @@ define void @s_shuffle_v4p0_v4p0__7_u_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13180,6 +13414,10 @@ define void @s_shuffle_v4p0_v4p0__7_0_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13198,6 +13436,10 @@ define void @s_shuffle_v4p0_v4p0__7_0_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13209,6 +13451,10 @@ define void @s_shuffle_v4p0_v4p0__7_0_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
@@ -13240,6 +13486,10 @@ define void @s_shuffle_v4p0_v4p0__7_1_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13256,6 +13506,10 @@ define void @s_shuffle_v4p0_v4p0__7_1_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13272,6 +13526,10 @@ define void @s_shuffle_v4p0_v4p0__7_1_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13297,6 +13555,10 @@ define void @s_shuffle_v4p0_v4p0__7_2_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13315,6 +13577,10 @@ define void @s_shuffle_v4p0_v4p0__7_2_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13333,6 +13599,10 @@ define void @s_shuffle_v4p0_v4p0__7_2_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s15
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13356,6 +13626,10 @@ define void @s_shuffle_v4p0_v4p0__7_3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13372,6 +13646,10 @@ define void @s_shuffle_v4p0_v4p0__7_3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13383,6 +13661,10 @@ define void @s_shuffle_v4p0_v4p0__7_3_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
@@ -13411,6 +13693,10 @@ define void @s_shuffle_v4p0_v4p0__7_4_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s5
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13426,6 +13712,10 @@ define void @s_shuffle_v4p0_v4p0__7_4_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13441,6 +13731,10 @@ define void @s_shuffle_v4p0_v4p0__7_4_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s1
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13461,6 +13755,10 @@ define void @s_shuffle_v4p0_v4p0__7_5_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s14
; GFX9-NEXT: s_mov_b32 s9, s15
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13483,6 +13781,10 @@ define void @s_shuffle_v4p0_v4p0__7_6_u_u() {
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13498,6 +13800,10 @@ define void @s_shuffle_v4p0_v4p0__7_6_u_u() {
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13513,6 +13819,10 @@ define void @s_shuffle_v4p0_v4p0__7_6_u_u() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s4
; GFX942-NEXT: s_mov_b32 s11, s5
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13533,6 +13843,10 @@ define void @s_shuffle_v4p0_v4p0__7_7_u_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13549,13 +13863,15 @@ define void @s_shuffle_v4p0_v4p0__7_7_0_u() {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[4:11]
+; GFX9-NEXT: ; def s[12:19]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[12:19]
+; GFX9-NEXT: ; def s[4:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13581,6 +13897,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_1_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s12, s14
; GFX900-NEXT: s_mov_b32 s13, s15
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13599,6 +13917,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_1_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s12, s14
; GFX90A-NEXT: s_mov_b32 s13, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13617,6 +13937,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_1_u() {
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
; GFX942-NEXT: s_mov_b32 s13, s3
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13640,6 +13962,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13656,6 +13980,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13667,6 +13993,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_2_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
@@ -13698,6 +14026,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_3_u() {
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s12, s14
; GFX900-NEXT: s_mov_b32 s13, s15
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -13716,6 +14046,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_3_u() {
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s12, s14
; GFX90A-NEXT: s_mov_b32 s13, s15
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -13734,6 +14066,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_3_u() {
; GFX942-NEXT: s_mov_b32 s8, s10
; GFX942-NEXT: s_mov_b32 s9, s11
; GFX942-NEXT: s_mov_b32 s13, s15
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -13756,6 +14090,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_4_u() {
; GFX9-NEXT: s_mov_b32 s9, s11
; GFX9-NEXT: s_mov_b32 s12, s4
; GFX9-NEXT: s_mov_b32 s13, s5
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13778,6 +14114,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_5_u() {
; GFX9-NEXT: s_mov_b32 s9, s11
; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s13, s7
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13800,6 +14138,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_6_u() {
; GFX9-NEXT: s_mov_b32 s9, s15
; GFX9-NEXT: s_mov_b32 s10, s14
; GFX9-NEXT: s_mov_b32 s11, s15
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -13822,6 +14162,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_7_u() {
; GFX9-NEXT: s_mov_b32 s9, s11
; GFX9-NEXT: s_mov_b32 s12, s10
; GFX9-NEXT: s_mov_b32 s13, s11
+; GFX9-NEXT: ; implicit-def: $sgpr14
+; GFX9-NEXT: ; implicit-def: $sgpr15
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:15]
; GFX9-NEXT: ;;#ASMEND
@@ -14896,15 +15238,17 @@ define void @s_shuffle_v4p0_v4p0__7_7_u_0() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[12:19]
+; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
+; GFX900-NEXT: ; def s[16:23]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: s_mov_b32 s14, s16
+; GFX900-NEXT: s_mov_b32 s15, s17
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -14914,15 +15258,17 @@ define void @s_shuffle_v4p0_v4p0__7_7_u_0() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[12:19]
+; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
+; GFX90A-NEXT: ; def s[16:23]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: s_mov_b32 s14, s16
+; GFX90A-NEXT: s_mov_b32 s15, s17
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -14934,6 +15280,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_u_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
@@ -17078,59 +17426,25 @@ define void @s_shuffle_v4p0_v4p0__7_7_2_2() {
}
define void @s_shuffle_v4p0_v4p0__7_7_u_2() {
-; GFX900-LABEL: s_shuffle_v4p0_v4p0__7_7_u_2:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[8:15]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[4:11]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s10
-; GFX900-NEXT: s_mov_b32 s9, s11
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
-; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; use s[8:15]
-; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX90A-LABEL: s_shuffle_v4p0_v4p0__7_7_u_2:
-; GFX90A: ; %bb.0:
-; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[8:15]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[4:11]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s10
-; GFX90A-NEXT: s_mov_b32 s9, s11
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
-; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; use s[8:15]
-; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX942-LABEL: s_shuffle_v4p0_v4p0__7_7_u_2:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[8:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s14, s12
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[4:11]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s8, s10
-; GFX942-NEXT: s_mov_b32 s9, s11
-; GFX942-NEXT: s_mov_b32 s15, s13
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; use s[8:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: s_shuffle_v4p0_v4p0__7_7_u_2:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[12:19]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; def s[4:11]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_mov_b32 s8, s10
+; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr12
+; GFX9-NEXT: ; implicit-def: $sgpr13
+; GFX9-NEXT: s_mov_b32 s14, s16
+; GFX9-NEXT: s_mov_b32 s15, s17
+; GFX9-NEXT: ;;#ASMSTART
+; GFX9-NEXT: ; use s[8:15]
+; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr> asm "; def $0", "=s"()
%vec1 = call <4 x ptr> asm "; def $0", "=s"()
%shuf = shufflevector <4 x ptr> %vec0, <4 x ptr> %vec1, <4 x i32> <i32 7, i32 7, i32 poison, i32 2>
@@ -18605,6 +18919,12 @@ define void @s_shuffle_v4p0_v4p0__1_4_4_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -18618,6 +18938,12 @@ define void @s_shuffle_v4p0_v4p0__1_4_4_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -18631,6 +18957,12 @@ define void @s_shuffle_v4p0_v4p0__1_4_4_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -18648,6 +18980,12 @@ define void @s_shuffle_v4p0_v4p0__2_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:11]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -18659,6 +18997,12 @@ define void @s_shuffle_v4p0_v4p0__2_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:11]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -18670,6 +19014,12 @@ define void @s_shuffle_v4p0_v4p0__2_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:11]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
@@ -18690,6 +19040,12 @@ define void @s_shuffle_v4p0_v4p0__3_4_4_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: ; implicit-def: $sgpr14
+; GFX900-NEXT: ; implicit-def: $sgpr15
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -18703,6 +19059,12 @@ define void @s_shuffle_v4p0_v4p0__3_4_4_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: ; implicit-def: $sgpr14
+; GFX90A-NEXT: ; implicit-def: $sgpr15
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -18716,6 +19078,12 @@ define void @s_shuffle_v4p0_v4p0__3_4_4_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
+; GFX942-NEXT: ; implicit-def: $sgpr14
+; GFX942-NEXT: ; implicit-def: $sgpr15
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:15]
; GFX942-NEXT: ;;#ASMEND
@@ -21192,14 +21560,16 @@ define void @s_shuffle_v4p0_v4p0__7_7_u_6() {
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def s[8:15]
+; GFX900-NEXT: ; def s[12:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: s_mov_b32 s8, s14
-; GFX900-NEXT: s_mov_b32 s9, s15
-; GFX900-NEXT: s_mov_b32 s10, s14
-; GFX900-NEXT: s_mov_b32 s11, s15
-; GFX900-NEXT: s_mov_b32 s14, s12
-; GFX900-NEXT: s_mov_b32 s15, s13
+; GFX900-NEXT: s_mov_b32 s8, s18
+; GFX900-NEXT: s_mov_b32 s9, s19
+; GFX900-NEXT: s_mov_b32 s10, s18
+; GFX900-NEXT: s_mov_b32 s11, s19
+; GFX900-NEXT: ; implicit-def: $sgpr12
+; GFX900-NEXT: ; implicit-def: $sgpr13
+; GFX900-NEXT: s_mov_b32 s14, s16
+; GFX900-NEXT: s_mov_b32 s15, s17
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:15]
; GFX900-NEXT: ;;#ASMEND
@@ -21209,14 +21579,16 @@ define void @s_shuffle_v4p0_v4p0__7_7_u_6() {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def s[8:15]
+; GFX90A-NEXT: ; def s[12:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: s_mov_b32 s8, s14
-; GFX90A-NEXT: s_mov_b32 s9, s15
-; GFX90A-NEXT: s_mov_b32 s10, s14
-; GFX90A-NEXT: s_mov_b32 s11, s15
-; GFX90A-NEXT: s_mov_b32 s14, s12
-; GFX90A-NEXT: s_mov_b32 s15, s13
+; GFX90A-NEXT: s_mov_b32 s8, s18
+; GFX90A-NEXT: s_mov_b32 s9, s19
+; GFX90A-NEXT: s_mov_b32 s10, s18
+; GFX90A-NEXT: s_mov_b32 s11, s19
+; GFX90A-NEXT: ; implicit-def: $sgpr12
+; GFX90A-NEXT: ; implicit-def: $sgpr13
+; GFX90A-NEXT: s_mov_b32 s14, s16
+; GFX90A-NEXT: s_mov_b32 s15, s17
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:15]
; GFX90A-NEXT: ;;#ASMEND
@@ -21232,6 +21604,8 @@ define void @s_shuffle_v4p0_v4p0__7_7_u_6() {
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s6
; GFX942-NEXT: s_mov_b32 s11, s7
+; GFX942-NEXT: ; implicit-def: $sgpr12
+; GFX942-NEXT: ; implicit-def: $sgpr13
; GFX942-NEXT: s_mov_b32 s14, s4
; GFX942-NEXT: s_mov_b32 s15, s5
; GFX942-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
index 1cf5c6cd3f286..64768ac160013 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v2p3.ll
@@ -19,33 +19,39 @@ define void @v_shuffle_v4p3_v2p3__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v2p3__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v2p3__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -58,35 +64,45 @@ define void @v_shuffle_v4p3_v2p3__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v2p3__1_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v2p3__1_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -110,35 +126,45 @@ define void @v_shuffle_v4p3_v2p3__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v2p3__3_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v2p3__3_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -152,14 +178,16 @@ define void @v_shuffle_v4p3_v2p3__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__3_0_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -174,6 +202,8 @@ define void @v_shuffle_v4p3_v2p3__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -190,6 +220,8 @@ define void @v_shuffle_v4p3_v2p3__3_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -204,14 +236,16 @@ define void @v_shuffle_v4p3_v2p3__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__3_1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -226,6 +260,8 @@ define void @v_shuffle_v4p3_v2p3__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -240,8 +276,10 @@ define void @v_shuffle_v4p3_v2p3__3_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -256,12 +294,14 @@ define void @v_shuffle_v4p3_v2p3__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__3_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v0
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -274,6 +314,8 @@ define void @v_shuffle_v4p3_v2p3__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -285,6 +327,8 @@ define void @v_shuffle_v4p3_v2p3__3_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v0
@@ -302,12 +346,14 @@ define void @v_shuffle_v4p3_v2p3__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__3_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -317,9 +363,11 @@ define void @v_shuffle_v4p3_v2p3__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -329,9 +377,11 @@ define void @v_shuffle_v4p3_v2p3__3_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -347,12 +397,13 @@ define void @v_shuffle_v4p3_v2p3__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:1]
+; GFX900-NEXT: ; def v[3:4]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[3:4]
+; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v2, v1
+; GFX900-NEXT: ; implicit-def: $vgpr4
; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -364,10 +415,11 @@ define void @v_shuffle_v4p3_v2p3__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -379,10 +431,11 @@ define void @v_shuffle_v4p3_v2p3__3_3_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -400,12 +453,13 @@ define void @v_shuffle_v4p3_v2p3__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -421,6 +475,7 @@ define void @v_shuffle_v4p3_v2p3__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -437,6 +492,7 @@ define void @v_shuffle_v4p3_v2p3__3_3_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -451,13 +507,14 @@ define void @v_shuffle_v4p3_v2p3__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__3_3_2_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -470,6 +527,7 @@ define void @v_shuffle_v4p3_v2p3__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -484,6 +542,7 @@ define void @v_shuffle_v4p3_v2p3__3_3_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -498,13 +557,14 @@ define void @v_shuffle_v4p3_v2p3__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__3_3_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v2, v1
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -514,10 +574,11 @@ define void @v_shuffle_v4p3_v2p3__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
; GFX90A-NEXT: v_mov_b32_e32 v2, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -527,10 +588,11 @@ define void @v_shuffle_v4p3_v2p3__3_3_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
; GFX942-NEXT: v_mov_b32_e32 v2, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1232,15 +1294,16 @@ define void @v_shuffle_v4p3_v2p3__3_3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:3]
+; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:1]
+; GFX90A-NEXT: ; def v[4:5]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v3, v4
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1248,15 +1311,16 @@ define void @v_shuffle_v4p3_v2p3__3_3_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:3]
+; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:1]
+; GFX942-NEXT: ; def v[4:5]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -2015,33 +2079,39 @@ define void @v_shuffle_v4p3_v2p3__0_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__0_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v2p3__0_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v2p3__0_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -2054,35 +2124,45 @@ define void @v_shuffle_v4p3_v2p3__1_2_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v2p3__1_2_2_2:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:1]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v2, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v2p3__1_2_2_2:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:1]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v2, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v2p3__1_2_2_2:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v2, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v2, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <2 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -2378,6 +2458,7 @@ define void @v_shuffle_v4p3_v2p3__3_3_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
; GFX90A-NEXT: v_mov_b32_e32 v5, v1
; GFX90A-NEXT: v_mov_b32_e32 v7, v0
+; GFX90A-NEXT: ; implicit-def: $vgpr6
; GFX90A-NEXT: global_store_dwordx4 v2, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -2389,6 +2470,7 @@ define void @v_shuffle_v4p3_v2p3__3_3_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr6
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, v1
; GFX942-NEXT: v_mov_b32_e32 v5, v1
@@ -3152,6 +3234,8 @@ define void @s_shuffle_v4p3_v2p3__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3163,6 +3247,8 @@ define void @s_shuffle_v4p3_v2p3__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3174,6 +3260,8 @@ define void @s_shuffle_v4p3_v2p3__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3192,6 +3280,9 @@ define void @s_shuffle_v4p3_v2p3__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -3204,6 +3295,9 @@ define void @s_shuffle_v4p3_v2p3__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -3216,6 +3310,9 @@ define void @s_shuffle_v4p3_v2p3__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3248,6 +3345,9 @@ define void @s_shuffle_v4p3_v2p3__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -3260,6 +3360,9 @@ define void @s_shuffle_v4p3_v2p3__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -3272,6 +3375,9 @@ define void @s_shuffle_v4p3_v2p3__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -3296,6 +3402,8 @@ define void @s_shuffle_v4p3_v2p3__3_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3312,6 +3420,8 @@ define void @s_shuffle_v4p3_v2p3__3_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3328,6 +3438,8 @@ define void @s_shuffle_v4p3_v2p3__3_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3350,6 +3462,8 @@ define void @s_shuffle_v4p3_v2p3__3_1_u_u() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3365,6 +3479,8 @@ define void @s_shuffle_v4p3_v2p3__3_1_u_u() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3380,6 +3496,8 @@ define void @s_shuffle_v4p3_v2p3__3_1_u_u() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3400,6 +3518,8 @@ define void @s_shuffle_v4p3_v2p3__3_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3413,6 +3533,8 @@ define void @s_shuffle_v4p3_v2p3__3_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3426,6 +3548,8 @@ define void @s_shuffle_v4p3_v2p3__3_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3444,6 +3568,8 @@ define void @s_shuffle_v4p3_v2p3__3_3_u_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
@@ -3461,12 +3587,13 @@ define void @s_shuffle_v4p3_v2p3__3_3_0_u() {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[8:9]
+; GFX9-NEXT: ; def s[10:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
-; GFX9-NEXT: ; def s[10:11]
+; GFX9-NEXT: ; def s[8:9]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s9
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -3490,6 +3617,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_1_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s9
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -3506,6 +3634,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_1_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s9
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -3522,6 +3651,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_1_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s9
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -3542,6 +3672,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_2_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -3562,6 +3693,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_3_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s9
; GFX9-NEXT: s_mov_b32 s10, s9
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -4070,6 +4202,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_u_0() {
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s9
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4086,6 +4219,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_u_0() {
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4102,6 +4236,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_u_0() {
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s9
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4682,6 +4817,8 @@ define void @s_shuffle_v4p3_v2p3__0_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:9]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -4693,6 +4830,8 @@ define void @s_shuffle_v4p3_v2p3__0_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:9]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -4704,6 +4843,8 @@ define void @s_shuffle_v4p3_v2p3__0_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:9]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4722,6 +4863,9 @@ define void @s_shuffle_v4p3_v2p3__1_2_2_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:5]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4734,6 +4878,9 @@ define void @s_shuffle_v4p3_v2p3__1_2_2_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4746,6 +4893,9 @@ define void @s_shuffle_v4p3_v2p3__1_2_2_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:1]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -4923,6 +5073,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: s_mov_b32 s9, s5
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -4937,6 +5088,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: s_mov_b32 s9, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -4951,6 +5103,7 @@ define void @s_shuffle_v4p3_v2p3__3_3_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: s_mov_b32 s9, s1
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
index 3253b4914420f..dd708b3878192 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v3p3.ll
@@ -19,33 +19,36 @@ define void @v_shuffle_v4p3_v3p3__0_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__0_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__0_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__0_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -58,35 +61,45 @@ define void @v_shuffle_v4p3_v3p3__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__1_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__1_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -99,33 +112,42 @@ define void @v_shuffle_v4p3_v3p3__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__2_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__2_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -149,35 +171,45 @@ define void @v_shuffle_v4p3_v3p3__4_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__4_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__4_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__4_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -191,33 +223,42 @@ define void @v_shuffle_v4p3_v3p3__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -238,6 +279,8 @@ define void @v_shuffle_v4p3_v3p3__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -253,6 +296,8 @@ define void @v_shuffle_v4p3_v3p3__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -267,8 +312,10 @@ define void @v_shuffle_v4p3_v3p3__5_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -283,43 +330,49 @@ define void @v_shuffle_v4p3_v3p3__5_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_1_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_1_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_1_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -333,14 +386,16 @@ define void @v_shuffle_v4p3_v3p3__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -350,12 +405,14 @@ define void @v_shuffle_v4p3_v3p3__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v3, v4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -365,12 +422,14 @@ define void @v_shuffle_v4p3_v3p3__5_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v3, v4
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -384,37 +443,43 @@ define void @v_shuffle_v4p3_v3p3__5_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_3_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v0
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_3_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v0
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -428,37 +493,43 @@ define void @v_shuffle_v4p3_v3p3__5_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v1
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_4_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v1
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_4_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v1
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -472,37 +543,43 @@ define void @v_shuffle_v4p3_v3p3__5_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_5_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_5_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -518,12 +595,13 @@ define void @v_shuffle_v4p3_v3p3__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:2]
+; GFX900-NEXT: ; def v[4:6]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[4:6]
+; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v3, v2
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -533,12 +611,13 @@ define void @v_shuffle_v4p3_v3p3__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:2]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:6]
+; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v3, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -548,11 +627,12 @@ define void @v_shuffle_v4p3_v3p3__5_5_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:2]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:6]
+; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
@@ -577,6 +657,7 @@ define void @v_shuffle_v4p3_v3p3__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
+; GFX900-NEXT: ; implicit-def: $vgpr5
; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -593,6 +674,7 @@ define void @v_shuffle_v4p3_v3p3__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -609,6 +691,7 @@ define void @v_shuffle_v4p3_v3p3__5_5_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v3, v2
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -626,12 +709,13 @@ define void @v_shuffle_v4p3_v3p3__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:4]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -641,12 +725,13 @@ define void @v_shuffle_v4p3_v3p3__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -656,13 +741,14 @@ define void @v_shuffle_v4p3_v3p3__5_5_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -676,40 +762,43 @@ define void @v_shuffle_v4p3_v3p3__5_5_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_5_3_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_5_3_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v0
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_5_3_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v0
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -723,40 +812,43 @@ define void @v_shuffle_v4p3_v3p3__5_5_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_5_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_5_4_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_5_4_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v1
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -770,40 +862,43 @@ define void @v_shuffle_v4p3_v3p3__5_5_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__5_5_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v3, v2
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_5_5_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: v_mov_b32_e32 v4, v2
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_5_5_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
; GFX942-NEXT: v_mov_b32_e32 v4, v2
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1824,32 +1919,35 @@ define void @v_shuffle_v4p3_v3p3__5_5_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__5_5_u_0:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v9, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:6]
+; GFX90A-NEXT: ; def v[6:8]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v9, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__5_5_u_0:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v9, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:6]
+; GFX942-NEXT: ; def v[6:8]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: global_store_dwordx4 v9, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -2053,6 +2151,7 @@ define void @v_shuffle_v4p3_v3p3__5_5_4_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
@@ -2069,6 +2168,7 @@ define void @v_shuffle_v4p3_v3p3__5_5_4_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -3717,15 +3817,16 @@ define void @v_shuffle_v4p3_v3p3__5_5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:4]
+; GFX90A-NEXT: ; def v[4:6]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v7, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v7, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -3733,15 +3834,16 @@ define void @v_shuffle_v4p3_v3p3__5_5_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:4]
+; GFX942-NEXT: ; def v[4:6]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
+; GFX942-NEXT: v_mov_b32_e32 v7, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v7, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -3941,6 +4043,7 @@ define void @v_shuffle_v4p3_v3p3__5_5_4_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:4]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
@@ -3957,6 +4060,7 @@ define void @v_shuffle_v4p3_v3p3__5_5_4_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:4]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
@@ -3989,33 +4093,36 @@ define void @v_shuffle_v4p3_v3p3__0_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__0_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v4, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__0_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__0_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -4028,35 +4135,45 @@ define void @v_shuffle_v4p3_v3p3__1_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__1_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__1_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v3, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v1
-; GFX90A-NEXT: global_store_dwordx4 v3, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v4, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6
+; GFX90A-NEXT: ; implicit-def: $vgpr7
+; GFX90A-NEXT: global_store_dwordx4 v3, v[4:7], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__1_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v3, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v1
-; GFX942-NEXT: global_store_dwordx4 v3, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: ; implicit-def: $vgpr6
+; GFX942-NEXT: ; implicit-def: $vgpr7
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v1
+; GFX942-NEXT: global_store_dwordx4 v3, v[4:7], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -4069,33 +4186,42 @@ define void @v_shuffle_v4p3_v3p3__2_3_3_3(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v3p3__2_3_3_3:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:2]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v3p3__2_3_3_3:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:2]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v3, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v3p3__2_3_3_3:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:2]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v3, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <3 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -6695,6 +6821,7 @@ define void @s_shuffle_v4p3_v3p3__0_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:10]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6706,6 +6833,7 @@ define void @s_shuffle_v4p3_v3p3__0_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:10]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -6717,6 +6845,7 @@ define void @s_shuffle_v4p3_v3p3__0_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:10]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6735,6 +6864,9 @@ define void @s_shuffle_v4p3_v3p3__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6747,6 +6879,9 @@ define void @s_shuffle_v4p3_v3p3__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6759,6 +6894,9 @@ define void @s_shuffle_v4p3_v3p3__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6777,6 +6915,9 @@ define void @s_shuffle_v4p3_v3p3__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6789,6 +6930,9 @@ define void @s_shuffle_v4p3_v3p3__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6801,6 +6945,9 @@ define void @s_shuffle_v4p3_v3p3__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6833,6 +6980,9 @@ define void @s_shuffle_v4p3_v3p3__4_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6845,6 +6995,9 @@ define void @s_shuffle_v4p3_v3p3__4_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6857,6 +7010,9 @@ define void @s_shuffle_v4p3_v3p3__4_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6876,6 +7032,9 @@ define void @s_shuffle_v4p3_v3p3__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -6888,6 +7047,9 @@ define void @s_shuffle_v4p3_v3p3__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -6900,6 +7062,9 @@ define void @s_shuffle_v4p3_v3p3__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -6924,6 +7089,8 @@ define void @s_shuffle_v4p3_v3p3__5_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6940,6 +7107,8 @@ define void @s_shuffle_v4p3_v3p3__5_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -6956,6 +7125,8 @@ define void @s_shuffle_v4p3_v3p3__5_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -6978,6 +7149,8 @@ define void @s_shuffle_v4p3_v3p3__5_1_u_u() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -6993,6 +7166,8 @@ define void @s_shuffle_v4p3_v3p3__5_1_u_u() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7008,6 +7183,8 @@ define void @s_shuffle_v4p3_v3p3__5_1_u_u() {
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7031,6 +7208,8 @@ define void @s_shuffle_v4p3_v3p3__5_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7047,6 +7226,8 @@ define void @s_shuffle_v4p3_v3p3__5_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7063,6 +7244,8 @@ define void @s_shuffle_v4p3_v3p3__5_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7083,6 +7266,8 @@ define void @s_shuffle_v4p3_v3p3__5_3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7096,6 +7281,8 @@ define void @s_shuffle_v4p3_v3p3__5_3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7109,6 +7296,8 @@ define void @s_shuffle_v4p3_v3p3__5_3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7127,7 +7316,9 @@ define void @s_shuffle_v4p3_v3p3__5_4_u_u() {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s[8:10]
; GFX9-NEXT: ;;#ASMEND
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: s_mov_b32 s8, s10
+; GFX9-NEXT: ; implicit-def: $sgpr10
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -7148,6 +7339,8 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7161,6 +7354,8 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7174,6 +7369,8 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7198,6 +7395,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_0_u() {
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7215,6 +7413,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_0_u() {
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7232,6 +7431,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_0_u() {
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7256,6 +7456,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_1_u() {
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7273,6 +7474,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_1_u() {
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7290,6 +7492,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_1_u() {
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7313,6 +7516,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7329,6 +7533,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7345,6 +7550,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7366,6 +7572,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_3_u() {
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7380,6 +7587,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_3_u() {
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7394,6 +7602,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_3_u() {
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7415,6 +7624,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_4_u() {
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -7429,6 +7639,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_4_u() {
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -7443,6 +7654,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_4_u() {
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -7463,6 +7675,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_5_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s10
; GFX9-NEXT: s_mov_b32 s9, s10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -7780,6 +7993,7 @@ define void @s_shuffle_v4p3_v3p3__u_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -7794,6 +8008,7 @@ define void @s_shuffle_v4p3_v3p3__u_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -7808,6 +8023,7 @@ define void @s_shuffle_v4p3_v3p3__u_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -7950,6 +8166,7 @@ define void @s_shuffle_v4p3_v3p3__3_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -7964,6 +8181,7 @@ define void @s_shuffle_v4p3_v3p3__3_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -7978,6 +8196,7 @@ define void @s_shuffle_v4p3_v3p3__3_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -8124,6 +8343,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_0_0() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -8141,6 +8361,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_0_0() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -8158,6 +8379,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_0_0() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -8485,6 +8707,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_0() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -8502,6 +8725,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_0() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -8519,6 +8743,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_0() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -8999,6 +9224,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_1_1() {
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -9016,6 +9242,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_1_1() {
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -9033,6 +9260,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_1_1() {
; GFX942-NEXT: ; def s[4:6]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -9360,6 +9588,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -9377,6 +9606,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -9394,6 +9624,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10220,6 +10451,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s10
; GFX900-NEXT: s_mov_b32 s9, s10
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10237,6 +10469,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s10
; GFX90A-NEXT: s_mov_b32 s9, s10
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10254,6 +10487,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s6
; GFX942-NEXT: s_mov_b32 s9, s6
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10531,6 +10765,7 @@ define void @s_shuffle_v4p3_v3p3__0_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:10]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -10542,6 +10777,7 @@ define void @s_shuffle_v4p3_v3p3__0_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:10]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -10553,6 +10789,7 @@ define void @s_shuffle_v4p3_v3p3__0_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:10]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10571,6 +10808,9 @@ define void @s_shuffle_v4p3_v3p3__1_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10583,6 +10823,9 @@ define void @s_shuffle_v4p3_v3p3__1_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10595,6 +10838,9 @@ define void @s_shuffle_v4p3_v3p3__1_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10613,6 +10859,9 @@ define void @s_shuffle_v4p3_v3p3__2_3_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -10625,6 +10874,9 @@ define void @s_shuffle_v4p3_v3p3__2_3_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -10637,6 +10889,9 @@ define void @s_shuffle_v4p3_v3p3__2_3_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -10773,6 +11028,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_3_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -10787,6 +11043,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_3_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -10801,6 +11058,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_3_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -11108,6 +11366,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_3() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11122,6 +11381,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_3() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11136,6 +11396,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_3() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11643,6 +11904,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:6]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
@@ -11657,6 +11919,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:6]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
@@ -11671,6 +11934,7 @@ define void @s_shuffle_v4p3_v3p3__5_u_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:2]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
@@ -11978,6 +12242,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11992,6 +12257,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -12006,6 +12272,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -12760,6 +13027,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_5() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -12774,6 +13042,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_5() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -12788,6 +13057,7 @@ define void @s_shuffle_v4p3_v3p3__5_5_u_5() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
index 9672a7d0c0e8e..b50fcb744360f 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v4p3.v4p3.ll
@@ -58,11 +58,14 @@ define void @v_shuffle_v4p3_v4p3__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__1_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -74,6 +77,9 @@ define void @v_shuffle_v4p3_v4p3__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -86,6 +92,9 @@ define void @v_shuffle_v4p3_v4p3__1_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -99,33 +108,42 @@ define void @v_shuffle_v4p3_v4p3__2_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__2_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v4p3__2_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v4p3__2_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -138,11 +156,14 @@ define void @v_shuffle_v4p3_v4p3__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__3_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -154,6 +175,9 @@ define void @v_shuffle_v4p3_v4p3__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -166,6 +190,9 @@ define void @v_shuffle_v4p3_v4p3__3_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -190,11 +217,14 @@ define void @v_shuffle_v4p3_v4p3__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__5_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -206,6 +236,9 @@ define void @v_shuffle_v4p3_v4p3__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -218,6 +251,9 @@ define void @v_shuffle_v4p3_v4p3__5_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -232,33 +268,42 @@ define void @v_shuffle_v4p3_v4p3__6_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__6_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v4p3__6_u_u_u:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v4p3__6_u_u_u:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -272,11 +317,14 @@ define void @v_shuffle_v4p3_v4p3__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_u_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -288,6 +336,9 @@ define void @v_shuffle_v4p3_v4p3__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -300,6 +351,9 @@ define void @v_shuffle_v4p3_v4p3__7_u_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -321,6 +375,8 @@ define void @v_shuffle_v4p3_v4p3__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v8, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -331,11 +387,14 @@ define void @v_shuffle_v4p3_v4p3__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -346,10 +405,13 @@ define void @v_shuffle_v4p3_v4p3__7_0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
@@ -373,6 +435,8 @@ define void @v_shuffle_v4p3_v4p3__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -388,6 +452,8 @@ define void @v_shuffle_v4p3_v4p3__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v0, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v6, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -402,6 +468,8 @@ define void @v_shuffle_v4p3_v4p3__7_1_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v0, v5
; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
@@ -418,14 +486,16 @@ define void @v_shuffle_v4p3_v4p3__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_2_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:5]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -439,7 +509,10 @@ define void @v_shuffle_v4p3_v4p3__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -454,8 +527,11 @@ define void @v_shuffle_v4p3_v4p3__7_2_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[6:7], v[2:3] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -470,14 +546,16 @@ define void @v_shuffle_v4p3_v4p3__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_3_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[1:4]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -492,6 +570,8 @@ define void @v_shuffle_v4p3_v4p3__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v2, v7
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -506,6 +586,8 @@ define void @v_shuffle_v4p3_v4p3__7_3_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v7
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
@@ -522,12 +604,14 @@ define void @v_shuffle_v4p3_v4p3__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_4_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v0
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -539,6 +623,8 @@ define void @v_shuffle_v4p3_v4p3__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -551,6 +637,8 @@ define void @v_shuffle_v4p3_v4p3__7_4_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[0:1] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -565,12 +653,14 @@ define void @v_shuffle_v4p3_v4p3__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_5_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v1
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -582,6 +672,8 @@ define void @v_shuffle_v4p3_v4p3__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -594,6 +686,8 @@ define void @v_shuffle_v4p3_v4p3__7_5_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -608,12 +702,14 @@ define void @v_shuffle_v4p3_v4p3__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_6_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v2
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -625,6 +721,8 @@ define void @v_shuffle_v4p3_v4p3__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[2:3] op_sel:[1,0]
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -637,6 +735,8 @@ define void @v_shuffle_v4p3_v4p3__7_6_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[2:3], v[2:3] op_sel:[1,0]
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -651,12 +751,14 @@ define void @v_shuffle_v4p3_v4p3__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_7_u_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx4 v5, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -666,9 +768,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -678,9 +782,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -696,12 +802,13 @@ define void @v_shuffle_v4p3_v4p3__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v9, 0
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[0:3]
+; GFX900-NEXT: ; def v[5:8]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: ;;#ASMSTART
-; GFX900-NEXT: ; def v[5:8]
+; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v9, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -713,10 +820,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -728,10 +836,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_0_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v8, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -754,6 +863,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v8, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -770,6 +880,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -786,6 +897,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_1_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v5
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -808,6 +920,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
+; GFX900-NEXT: ; implicit-def: $vgpr6
; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -823,6 +936,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -837,6 +951,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_2_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
@@ -856,12 +971,13 @@ define void @v_shuffle_v4p3_v4p3__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[2:5]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -877,6 +993,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -893,6 +1010,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_3_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v2, v3
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -907,13 +1025,14 @@ define void @v_shuffle_v4p3_v4p3__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_7_4_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v0
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -923,10 +1042,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v0
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -936,10 +1056,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_4_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v0
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -953,13 +1074,14 @@ define void @v_shuffle_v4p3_v4p3__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_7_5_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v1
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -969,10 +1091,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v1
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -982,10 +1105,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_5_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v1
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -999,13 +1123,14 @@ define void @v_shuffle_v4p3_v4p3__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_7_6_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v2
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -1018,6 +1143,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
; GFX90A-NEXT: v_mov_b32_e32 v1, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1031,6 +1157,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_6_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
; GFX942-NEXT: v_mov_b32_e32 v1, v3
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1045,13 +1172,14 @@ define void @v_shuffle_v4p3_v4p3__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__7_7_7_u:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_mov_b32_e32 v4, v3
; GFX900-NEXT: v_mov_b32_e32 v5, v3
-; GFX900-NEXT: global_store_dwordx4 v6, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -1061,10 +1189,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v5, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: v_mov_b32_e32 v4, v3
-; GFX90A-NEXT: global_store_dwordx4 v5, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -1074,10 +1203,11 @@ define void @v_shuffle_v4p3_v4p3__7_7_7_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
; GFX942-NEXT: v_mov_b32_e32 v4, v3
-; GFX942-NEXT: global_store_dwordx4 v5, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -1113,6 +1243,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_7_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -1129,6 +1260,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_7_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -1223,6 +1355,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_7_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[2:3], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -1236,6 +1369,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_7_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
@@ -2412,15 +2546,16 @@ define void @v_shuffle_v4p3_v4p3__7_7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v10, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[6:9]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v10, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -2428,15 +2563,16 @@ define void @v_shuffle_v4p3_v4p3__7_7_u_0(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_mov_b32_e32 v10, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[6:9]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
-; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v10, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -2696,6 +2832,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_5_0(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -2712,6 +2849,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_5_0(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -4961,15 +5099,16 @@ define void @v_shuffle_v4p3_v4p3__7_7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[2:5]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
-; GFX90A-NEXT: v_mov_b32_e32 v5, v4
-; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v5, v6
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: global_store_dwordx4 v8, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
@@ -4977,15 +5116,16 @@ define void @v_shuffle_v4p3_v4p3__7_7_u_2(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[2:5]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v5, v4
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: v_mov_b32_e32 v2, v3
-; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
+; GFX942-NEXT: v_mov_b32_e32 v5, v6
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: global_store_dwordx4 v8, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -5242,6 +5382,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_5_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr5
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[0:1], v[4:5] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -5255,6 +5396,7 @@ define void @v_shuffle_v4p3_v4p3__7_7_5_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr5
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
@@ -6657,11 +6799,14 @@ define void @v_shuffle_v4p3_v4p3__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__1_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v5, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[1:4], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr2
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: global_store_dwordx4 v5, v[1:4], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -6673,6 +6818,9 @@ define void @v_shuffle_v4p3_v4p3__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v1
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6685,6 +6833,9 @@ define void @v_shuffle_v4p3_v4p3__1_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v1
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -6698,33 +6849,42 @@ define void @v_shuffle_v4p3_v4p3__2_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__2_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v6, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr3
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GFX90A-LABEL: v_shuffle_v4p3_v4p3__2_4_4_4:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_dwordx4 v4, v[2:5], s[16:17]
+; GFX90A-NEXT: ; implicit-def: $vgpr3
+; GFX90A-NEXT: ; implicit-def: $vgpr4
+; GFX90A-NEXT: ; implicit-def: $vgpr5
+; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v4p3__2_4_4_4:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_dwordx4 v4, v[2:5], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr3
+; GFX942-NEXT: ; implicit-def: $vgpr4
+; GFX942-NEXT: ; implicit-def: $vgpr5
+; GFX942-NEXT: global_store_dwordx4 v6, v[2:5], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -6737,11 +6897,14 @@ define void @v_shuffle_v4p3_v4p3__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX900-LABEL: v_shuffle_v4p3_v4p3__3_4_4_4:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-NEXT: v_mov_b32_e32 v7, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v[0:3]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_dwordx4 v4, v[3:6], s[16:17]
+; GFX900-NEXT: ; implicit-def: $vgpr4
+; GFX900-NEXT: ; implicit-def: $vgpr5
+; GFX900-NEXT: ; implicit-def: $vgpr6
+; GFX900-NEXT: global_store_dwordx4 v7, v[3:6], s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
;
@@ -6753,6 +6916,9 @@ define void @v_shuffle_v4p3_v4p3__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mov_b32_e32 v0, v3
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -6765,6 +6931,9 @@ define void @v_shuffle_v4p3_v4p3__3_4_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: v_mov_b32_e32 v0, v3
+; GFX942-NEXT: ; implicit-def: $vgpr1
+; GFX942-NEXT: ; implicit-def: $vgpr2
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -7000,6 +7169,7 @@ define void @v_shuffle_v4p3_v4p3__7_0_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
@@ -7013,6 +7183,7 @@ define void @v_shuffle_v4p3_v4p3__7_0_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -7113,6 +7284,7 @@ define void @v_shuffle_v4p3_v4p3__7_2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v3, v2
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
@@ -7129,6 +7301,7 @@ define void @v_shuffle_v4p3_v4p3__7_2_4_4(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v3, v2
@@ -8246,6 +8419,7 @@ define void @v_shuffle_v4p3_v4p3__7_0_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
@@ -8259,6 +8433,7 @@ define void @v_shuffle_v4p3_v4p3__7_0_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: v_mov_b32_e32 v6, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
@@ -8359,6 +8534,7 @@ define void @v_shuffle_v4p3_v4p3__7_2_5_5(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr7
; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v2, v3
; GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
@@ -8375,6 +8551,7 @@ define void @v_shuffle_v4p3_v4p3__7_2_5_5(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr7
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[6:7] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v2, v3
@@ -9489,6 +9666,7 @@ define void @v_shuffle_v4p3_v4p3__7_0_6_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v5, v4
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
@@ -9505,6 +9683,7 @@ define void @v_shuffle_v4p3_v4p3__7_0_6_6(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v5, v4
@@ -9597,12 +9776,13 @@ define void @v_shuffle_v4p3_v4p3__7_2_6_6(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v7, v6
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
@@ -9613,13 +9793,13 @@ define void @v_shuffle_v4p3_v4p3__7_2_6_6(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v7, v6
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
@@ -9849,28 +10029,31 @@ define void @v_shuffle_v4p3_v4p3__7_7_u_6(ptr addrspace(1) inreg %ptr) {
; GFX90A-LABEL: v_shuffle_v4p3_v4p3__7_7_u_6:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GFX90A-NEXT: v_mov_b32_e32 v0, v3
-; GFX90A-NEXT: v_mov_b32_e32 v1, v3
-; GFX90A-NEXT: v_mov_b32_e32 v3, v2
-; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
+; GFX90A-NEXT: v_mov_b32_e32 v6, v3
+; GFX90A-NEXT: v_mov_b32_e32 v7, v3
+; GFX90A-NEXT: v_mov_b32_e32 v9, v2
+; GFX90A-NEXT: ; implicit-def: $vgpr8
+; GFX90A-NEXT: global_store_dwordx4 v4, v[6:9], s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: v_shuffle_v4p3_v4p3__7_7_u_6:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT: v_mov_b32_e32 v4, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, v3
-; GFX942-NEXT: v_mov_b32_e32 v1, v3
-; GFX942-NEXT: v_mov_b32_e32 v3, v2
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX942-NEXT: ; implicit-def: $vgpr8
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v6, v3
+; GFX942-NEXT: v_mov_b32_e32 v7, v3
+; GFX942-NEXT: v_mov_b32_e32 v9, v2
+; GFX942-NEXT: global_store_dwordx4 v4, v[6:9], s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
%vec0 = call <4 x ptr addrspace(3)> asm "; def $0", "=v"()
@@ -10698,6 +10881,7 @@ define void @v_shuffle_v4p3_v4p3__7_0_7_7(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ; def v[2:5]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_mov_b32_e32 v6, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr1
; GFX90A-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v4, v5
; GFX90A-NEXT: global_store_dwordx4 v6, v[2:5], s[16:17]
@@ -10714,6 +10898,7 @@ define void @v_shuffle_v4p3_v4p3__7_0_7_7(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v[2:5]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $vgpr1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_pk_mov_b32 v[2:3], v[4:5], v[0:1] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v4, v5
@@ -10806,12 +10991,13 @@ define void @v_shuffle_v4p3_v4p3__7_2_7_7(ptr addrspace(1) inreg %ptr) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[4:7]
+; GFX90A-NEXT: ; def v[0:3]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: ;;#ASMSTART
-; GFX90A-NEXT: ; def v[0:3]
+; GFX90A-NEXT: ; def v[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GFX90A-NEXT: ; implicit-def: $vgpr3
; GFX90A-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX90A-NEXT: v_mov_b32_e32 v6, v7
; GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17]
@@ -10822,13 +11008,13 @@ define void @v_shuffle_v4p3_v4p3__7_2_7_7(ptr addrspace(1) inreg %ptr) {
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[4:7]
+; GFX942-NEXT: ; def v[0:3]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_mov_b32_e32 v8, 0
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def v[0:3]
+; GFX942-NEXT: ; def v[4:7]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-NEXT: ; implicit-def: $vgpr3
; GFX942-NEXT: v_pk_mov_b32 v[4:5], v[6:7], v[2:3] op_sel:[1,0]
; GFX942-NEXT: v_mov_b32_e32 v6, v7
; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
@@ -11516,6 +11702,9 @@ define void @s_shuffle_v4p3_v4p3__1_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11528,6 +11717,9 @@ define void @s_shuffle_v4p3_v4p3__1_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11540,6 +11732,9 @@ define void @s_shuffle_v4p3_v4p3__1_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11558,6 +11753,9 @@ define void @s_shuffle_v4p3_v4p3__2_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11570,6 +11768,9 @@ define void @s_shuffle_v4p3_v4p3__2_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11582,6 +11783,9 @@ define void @s_shuffle_v4p3_v4p3__2_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11600,6 +11804,9 @@ define void @s_shuffle_v4p3_v4p3__3_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11612,6 +11819,9 @@ define void @s_shuffle_v4p3_v4p3__3_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11624,6 +11834,9 @@ define void @s_shuffle_v4p3_v4p3__3_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11656,6 +11869,9 @@ define void @s_shuffle_v4p3_v4p3__5_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11668,6 +11884,9 @@ define void @s_shuffle_v4p3_v4p3__5_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11680,6 +11899,9 @@ define void @s_shuffle_v4p3_v4p3__5_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11699,6 +11921,9 @@ define void @s_shuffle_v4p3_v4p3__6_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11711,6 +11936,9 @@ define void @s_shuffle_v4p3_v4p3__6_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11723,6 +11951,9 @@ define void @s_shuffle_v4p3_v4p3__6_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11742,6 +11973,9 @@ define void @s_shuffle_v4p3_v4p3__7_u_u_u() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -11754,6 +11988,9 @@ define void @s_shuffle_v4p3_v4p3__7_u_u_u() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -11766,6 +12003,9 @@ define void @s_shuffle_v4p3_v4p3__7_u_u_u() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -11790,6 +12030,8 @@ define void @s_shuffle_v4p3_v4p3__7_0_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11806,6 +12048,8 @@ define void @s_shuffle_v4p3_v4p3__7_0_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11822,6 +12066,8 @@ define void @s_shuffle_v4p3_v4p3__7_0_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11844,6 +12090,8 @@ define void @s_shuffle_v4p3_v4p3__7_1_u_u() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11859,6 +12107,8 @@ define void @s_shuffle_v4p3_v4p3__7_1_u_u() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11874,6 +12124,8 @@ define void @s_shuffle_v4p3_v4p3__7_1_u_u() {
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11897,6 +12149,8 @@ define void @s_shuffle_v4p3_v4p3__7_2_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11913,6 +12167,8 @@ define void @s_shuffle_v4p3_v4p3__7_2_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11929,6 +12185,8 @@ define void @s_shuffle_v4p3_v4p3__7_2_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -11952,6 +12210,8 @@ define void @s_shuffle_v4p3_v4p3__7_3_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -11968,6 +12228,8 @@ define void @s_shuffle_v4p3_v4p3__7_3_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -11984,6 +12246,8 @@ define void @s_shuffle_v4p3_v4p3__7_3_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12004,6 +12268,8 @@ define void @s_shuffle_v4p3_v4p3__7_4_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s4
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12017,6 +12283,8 @@ define void @s_shuffle_v4p3_v4p3__7_4_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12030,6 +12298,8 @@ define void @s_shuffle_v4p3_v4p3__7_4_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s0
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12049,6 +12319,8 @@ define void @s_shuffle_v4p3_v4p3__7_5_u_u() {
; GFX9-NEXT: ; def s[8:11]
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
+; GFX9-NEXT: ; implicit-def: $sgpr10
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -12069,6 +12341,8 @@ define void @s_shuffle_v4p3_v4p3__7_6_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s6
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12082,6 +12356,8 @@ define void @s_shuffle_v4p3_v4p3__7_6_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12095,6 +12371,8 @@ define void @s_shuffle_v4p3_v4p3__7_6_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s2
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12115,6 +12393,8 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12128,6 +12408,8 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12141,6 +12423,8 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12165,6 +12449,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_0_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12182,6 +12467,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_0_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12199,6 +12485,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_0_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12223,6 +12510,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_1_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12240,6 +12528,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_1_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12257,6 +12546,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_1_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12280,6 +12570,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_2_u() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12296,6 +12587,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_2_u() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12312,6 +12604,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_2_u() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12336,6 +12629,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_3_u() {
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
; GFX900-NEXT: s_mov_b32 s10, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12353,6 +12647,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_3_u() {
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
; GFX90A-NEXT: s_mov_b32 s10, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12370,6 +12665,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_3_u() {
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
; GFX942-NEXT: s_mov_b32 s10, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12391,6 +12687,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_4_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s4
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12405,6 +12702,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_4_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12419,6 +12717,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_4_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s0
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12440,6 +12739,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_5_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s5
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12454,6 +12754,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_5_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12468,6 +12769,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_5_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s1
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12488,6 +12790,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_6_u() {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s8, s11
; GFX9-NEXT: s_mov_b32 s9, s11
+; GFX9-NEXT: ; implicit-def: $sgpr11
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s[8:11]
; GFX9-NEXT: ;;#ASMEND
@@ -12509,6 +12812,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_7_u() {
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
; GFX900-NEXT: s_mov_b32 s10, s7
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
@@ -12523,6 +12827,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_7_u() {
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
; GFX90A-NEXT: s_mov_b32 s10, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
@@ -12537,6 +12842,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_7_u() {
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
; GFX942-NEXT: s_mov_b32 s10, s3
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -12973,6 +13279,7 @@ define void @s_shuffle_v4p3_v4p3__u_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -12987,6 +13294,7 @@ define void @s_shuffle_v4p3_v4p3__u_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -13001,6 +13309,7 @@ define void @s_shuffle_v4p3_v4p3__u_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -13194,6 +13503,7 @@ define void @s_shuffle_v4p3_v4p3__4_0_0_0() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr8
; GFX900-NEXT: s_mov_b32 s9, s4
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -13208,6 +13518,7 @@ define void @s_shuffle_v4p3_v4p3__4_0_0_0() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr8
; GFX90A-NEXT: s_mov_b32 s9, s4
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -13222,6 +13533,7 @@ define void @s_shuffle_v4p3_v4p3__4_0_0_0() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr8
; GFX942-NEXT: s_mov_b32 s9, s0
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -13429,6 +13741,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_0_0() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
@@ -13446,6 +13759,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_0_0() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
@@ -13463,6 +13777,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_0_0() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
@@ -13912,6 +14227,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_0() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -13929,6 +14245,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_0() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -13946,6 +14263,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_0() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -14623,6 +14941,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_1_1() {
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
@@ -14640,6 +14959,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_1_1() {
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
@@ -14657,6 +14977,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_1_1() {
; GFX942-NEXT: ; def s[4:7]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
@@ -15106,6 +15427,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_1() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -15123,6 +15445,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_1() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -15140,6 +15463,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_1() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -16279,6 +16603,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s11
; GFX900-NEXT: s_mov_b32 s9, s11
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -16296,6 +16621,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s11
; GFX90A-NEXT: s_mov_b32 s9, s11
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -16313,6 +16639,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_2() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s7
; GFX942-NEXT: s_mov_b32 s9, s7
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17907,6 +18234,9 @@ define void @s_shuffle_v4p3_v4p3__1_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -17919,6 +18249,9 @@ define void @s_shuffle_v4p3_v4p3__1_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -17931,6 +18264,9 @@ define void @s_shuffle_v4p3_v4p3__1_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17949,6 +18285,9 @@ define void @s_shuffle_v4p3_v4p3__2_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -17961,6 +18300,9 @@ define void @s_shuffle_v4p3_v4p3__2_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -17973,6 +18315,9 @@ define void @s_shuffle_v4p3_v4p3__2_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -17991,6 +18336,9 @@ define void @s_shuffle_v4p3_v4p3__3_4_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
+; GFX900-NEXT: ; implicit-def: $sgpr10
+; GFX900-NEXT: ; implicit-def: $sgpr11
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -18003,6 +18351,9 @@ define void @s_shuffle_v4p3_v4p3__3_4_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
+; GFX90A-NEXT: ; implicit-def: $sgpr10
+; GFX90A-NEXT: ; implicit-def: $sgpr11
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -18015,6 +18366,9 @@ define void @s_shuffle_v4p3_v4p3__3_4_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
+; GFX942-NEXT: ; implicit-def: $sgpr10
+; GFX942-NEXT: ; implicit-def: $sgpr11
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -18203,6 +18557,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_4_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s4
; GFX900-NEXT: s_mov_b32 s11, s4
@@ -18217,6 +18572,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_4_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s4
; GFX90A-NEXT: s_mov_b32 s11, s4
@@ -18231,6 +18587,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_4_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s0
; GFX942-NEXT: s_mov_b32 s11, s0
@@ -18651,6 +19008,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s4
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -18665,6 +19023,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s4
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -18679,6 +19038,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_4() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -19378,6 +19738,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_5_5() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:7]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: ; implicit-def: $sgpr9
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s10, s5
; GFX900-NEXT: s_mov_b32 s11, s5
@@ -19392,6 +19753,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_5_5() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:7]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: ; implicit-def: $sgpr9
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s10, s5
; GFX90A-NEXT: s_mov_b32 s11, s5
@@ -19406,6 +19768,7 @@ define void @s_shuffle_v4p3_v4p3__7_u_5_5() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:3]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ; implicit-def: $sgpr9
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s10, s1
; GFX942-NEXT: s_mov_b32 s11, s1
@@ -19826,6 +20189,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_5() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s5
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -19840,6 +20204,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_5() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s5
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -19854,6 +20219,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_5() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -20900,6 +21266,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_6() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s7
; GFX900-NEXT: s_mov_b32 s9, s7
+; GFX900-NEXT: ; implicit-def: $sgpr10
; GFX900-NEXT: s_mov_b32 s11, s6
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
@@ -20914,6 +21281,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_6() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s7
; GFX90A-NEXT: s_mov_b32 s9, s7
+; GFX90A-NEXT: ; implicit-def: $sgpr10
; GFX90A-NEXT: s_mov_b32 s11, s6
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
@@ -20928,6 +21296,7 @@ define void @s_shuffle_v4p3_v4p3__7_7_u_6() {
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s3
; GFX942-NEXT: s_mov_b32 s9, s3
+; GFX942-NEXT: ; implicit-def: $sgpr10
; GFX942-NEXT: s_mov_b32 s11, s2
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
diff --git a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
index fb336f4558a63..343b7d2f43239 100644
--- a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
@@ -623,34 +623,40 @@ define amdgpu_kernel void @reorder_global_offsets_addr64_soffset0(ptr addrspace(
define amdgpu_vs void @reorder_local_load_tbuffer_store_local_load(ptr addrspace(1) %out, i32 %a1, i32 %vaddr) #0 {
; CI-LABEL: reorder_local_load_tbuffer_store_local_load:
; CI: ; %bb.0:
-; CI-NEXT: v_mov_b32_e32 v4, stored_lds_ptr at abs32@lo
+; CI-NEXT: v_mov_b32_e32 v6, v3
+; CI-NEXT: v_mov_b32_e32 v3, stored_lds_ptr at abs32@lo
; CI-NEXT: s_mov_b32 m0, -1
-; CI-NEXT: ds_read_b32 v4, v4
+; CI-NEXT: ds_read_b32 v3, v3
; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s0, s2
; CI-NEXT: s_mov_b32 s1, s2
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: ds_read2_b32 v[4:5], v4 offset0:1 offset1:2
-; CI-NEXT: v_add_i32_e32 v3, vcc, 32, v3
+; CI-NEXT: ds_read2_b32 v[7:8], v3 offset0:1 offset1:2
+; CI-NEXT: v_add_i32_e32 v6, vcc, 32, v6
+; CI-NEXT: ; implicit-def: $vgpr3
+; CI-NEXT: ; implicit-def: $vgpr4
+; CI-NEXT: ; implicit-def: $vgpr5
+; CI-NEXT: tbuffer_store_format_xyzw v[2:5], v6, s[0:3], 0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_SNORM_OGL] idxen glc slc
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: tbuffer_store_format_xyzw v[2:5], v3, s[0:3], 0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_SNORM_OGL] idxen glc slc
-; CI-NEXT: s_nop 0
-; CI-NEXT: v_add_i32_e32 v2, vcc, v4, v5
+; CI-NEXT: v_add_i32_e32 v2, vcc, v7, v8
; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_endpgm
;
; GFX9-LABEL: reorder_local_load_tbuffer_store_local_load:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v4, stored_lds_ptr at abs32@lo
-; GFX9-NEXT: ds_read_b32 v4, v4
-; GFX9-NEXT: v_add_u32_e32 v3, 32, v3
+; GFX9-NEXT: v_mov_b32_e32 v6, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, stored_lds_ptr at abs32@lo
+; GFX9-NEXT: ds_read_b32 v3, v3
+; GFX9-NEXT: v_add_u32_e32 v6, 32, v6
+; GFX9-NEXT: ; implicit-def: $vgpr4
+; GFX9-NEXT: ; implicit-def: $vgpr5
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: ds_read2_b32 v[4:5], v4 offset0:1 offset1:2
+; GFX9-NEXT: ds_read2_b32 v[7:8], v3 offset0:1 offset1:2
+; GFX9-NEXT: ; implicit-def: $vgpr3
+; GFX9-NEXT: tbuffer_store_format_xyzw v[2:5], v6, s[0:3], 0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_RESERVED_6] idxen glc slc
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: tbuffer_store_format_xyzw v[2:5], v3, s[0:3], 0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_RESERVED_6] idxen glc slc
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: v_add_u32_e32 v2, v4, v5
+; GFX9-NEXT: v_add_u32_e32 v2, v7, v8
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_endpgm
%ptr0 = load ptr addrspace(3), ptr addrspace(3) @stored_lds_ptr, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/sign_extend.ll b/llvm/test/CodeGen/AMDGPU/sign_extend.ll
index 373618f3da1b8..1ce46c7d91895 100644
--- a/llvm/test/CodeGen/AMDGPU/sign_extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/sign_extend.ll
@@ -184,6 +184,7 @@ define amdgpu_kernel void @s_sext_i16_to_i64(ptr addrspace(1) %out, i16 %a) noun
; SI: ; %bb.0:
; SI-NEXT: s_load_dword s6, s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: ; implicit-def: $sgpr7
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
@@ -197,6 +198,7 @@ define amdgpu_kernel void @s_sext_i16_to_i64(ptr addrspace(1) %out, i16 %a) noun
; VI: ; %bb.0:
; VI-NEXT: s_load_dword s6, s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: ; implicit-def: $sgpr7
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
index bfd2dd9946301..5bbabebd310dc 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
@@ -12,10 +12,11 @@ define amdgpu_kernel void @test_spill_av_class(<4 x i32> %arg) #0 {
; GCN-NEXT: [[AV_MOV_:%[0-9]+]]:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 1, implicit $exec
; GCN-NEXT: [[AV_MOV_1:%[0-9]+]]:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 2, implicit $exec
; GCN-NEXT: [[V_MFMA_I32_4X4X4I8_e64_:%[0-9]+]]:areg_128 = V_MFMA_I32_4X4X4I8_e64 [[AV_MOV_]], [[AV_MOV_1]], [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: INLINEASM &"; def $0", sideeffect attdialect, regdef:VGPR_32, def undef %14.sub0
+ ; GCN-NEXT: INLINEASM &"; def $0", sideeffect attdialect, regdef:VGPR_32, def undef %16.sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[V_MFMA_I32_4X4X4I8_e64_]]
; GCN-NEXT: GLOBAL_STORE_DWORDX4 undef %24:vreg_64, [[COPY1]], 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
- ; GCN-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VReg_64, %14
+ ; GCN-NEXT: [[DEF:%[0-9]+]].sub1:vreg_64 = IMPLICIT_DEF
+ ; GCN-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VReg_64, [[DEF]]
; GCN-NEXT: S_ENDPGM 0
%v0 = call i32 asm sideeffect "; def $0", "=v"()
%tmp = insertelement <2 x i32> poison, i32 %v0, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
index f08b68f9b8c38..17690cd07d964 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
@@ -10,23 +10,22 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_or_saveexec_b64 s[4:5], -1
-; CHECK-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:1632 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:2452 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:980 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:976 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:972 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:976 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:972 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a33, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a34, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
@@ -59,95 +58,102 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_store_dword a61, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a62, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a63, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v63, s34, 0
-; CHECK-NEXT: v_writelane_b32 v63, s35, 1
-; CHECK-NEXT: v_writelane_b32 v63, s36, 2
-; CHECK-NEXT: v_writelane_b32 v63, s37, 3
-; CHECK-NEXT: v_writelane_b32 v63, s38, 4
-; CHECK-NEXT: v_writelane_b32 v63, s39, 5
-; CHECK-NEXT: v_writelane_b32 v63, s48, 6
-; CHECK-NEXT: v_writelane_b32 v63, s49, 7
-; CHECK-NEXT: v_writelane_b32 v63, s50, 8
-; CHECK-NEXT: v_writelane_b32 v63, s51, 9
-; CHECK-NEXT: v_writelane_b32 v63, s52, 10
-; CHECK-NEXT: v_writelane_b32 v63, s53, 11
-; CHECK-NEXT: v_writelane_b32 v63, s54, 12
-; CHECK-NEXT: v_writelane_b32 v63, s55, 13
-; CHECK-NEXT: v_writelane_b32 v63, s30, 14
-; CHECK-NEXT: v_writelane_b32 v63, s31, 15
-; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1264 ; 4-byte Folded Spill
+; CHECK-NEXT: v_writelane_b32 v62, s34, 0
+; CHECK-NEXT: v_writelane_b32 v62, s35, 1
+; CHECK-NEXT: v_writelane_b32 v62, s36, 2
+; CHECK-NEXT: v_writelane_b32 v62, s37, 3
+; CHECK-NEXT: v_writelane_b32 v62, s38, 4
+; CHECK-NEXT: v_writelane_b32 v62, s39, 5
+; CHECK-NEXT: v_writelane_b32 v62, s48, 6
+; CHECK-NEXT: v_writelane_b32 v62, s49, 7
+; CHECK-NEXT: v_writelane_b32 v62, s50, 8
+; CHECK-NEXT: v_writelane_b32 v62, s51, 9
+; CHECK-NEXT: v_writelane_b32 v62, s52, 10
+; CHECK-NEXT: v_writelane_b32 v62, s53, 11
+; CHECK-NEXT: v_writelane_b32 v62, s54, 12
+; CHECK-NEXT: v_writelane_b32 v62, s55, 13
+; CHECK-NEXT: v_writelane_b32 v62, s30, 14
+; CHECK-NEXT: v_writelane_b32 v62, s31, 15
+; CHECK-NEXT: v_mov_b32_e32 v32, v29
+; CHECK-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:1508 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1268 ; 4-byte Folded Spill
-; CHECK-NEXT: v_mov_b32_e32 v30, v29
-; CHECK-NEXT: buffer_load_dword a43, off, s[0:3], s32 offset:368
-; CHECK-NEXT: buffer_load_dword a42, off, s[0:3], s32 offset:364
-; CHECK-NEXT: buffer_load_dword a41, off, s[0:3], s32 offset:360
-; CHECK-NEXT: buffer_load_dword a40, off, s[0:3], s32 offset:356
-; CHECK-NEXT: buffer_load_dword a39, off, s[0:3], s32 offset:352
-; CHECK-NEXT: buffer_load_dword a38, off, s[0:3], s32 offset:348
-; CHECK-NEXT: buffer_load_dword a37, off, s[0:3], s32 offset:344
-; CHECK-NEXT: buffer_load_dword a36, off, s[0:3], s32 offset:340
-; CHECK-NEXT: buffer_load_dword a35, off, s[0:3], s32 offset:336
-; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:332
-; CHECK-NEXT: buffer_load_dword a33, off, s[0:3], s32 offset:328
-; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:324
-; CHECK-NEXT: buffer_load_dword a31, off, s[0:3], s32 offset:320
-; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:316
-; CHECK-NEXT: buffer_load_dword a29, off, s[0:3], s32 offset:312
-; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:308
-; CHECK-NEXT: buffer_load_dword a27, off, s[0:3], s32 offset:304
-; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:300
-; CHECK-NEXT: buffer_load_dword a25, off, s[0:3], s32 offset:296
-; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:292
-; CHECK-NEXT: buffer_load_dword a23, off, s[0:3], s32 offset:288
-; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:284
-; CHECK-NEXT: buffer_load_dword a21, off, s[0:3], s32 offset:280
-; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:276
-; CHECK-NEXT: buffer_load_dword a19, off, s[0:3], s32 offset:272
-; CHECK-NEXT: buffer_load_dword a18, off, s[0:3], s32 offset:268
+; CHECK-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:1512 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:1572 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:1576 ; 4-byte Folded Spill
+; CHECK-NEXT: v_mov_b32_e32 v32, v27
+; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1564 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1568 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a29, off, s[0:3], s32 offset:368
+; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:364
+; CHECK-NEXT: buffer_load_dword a27, off, s[0:3], s32 offset:360
+; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:356
+; CHECK-NEXT: buffer_load_dword a25, off, s[0:3], s32 offset:352
+; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:348
+; CHECK-NEXT: buffer_load_dword a23, off, s[0:3], s32 offset:344
+; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:340
+; CHECK-NEXT: buffer_load_dword a21, off, s[0:3], s32 offset:336
+; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:332
+; CHECK-NEXT: buffer_load_dword a19, off, s[0:3], s32 offset:328
+; CHECK-NEXT: buffer_load_dword a18, off, s[0:3], s32 offset:324
+; CHECK-NEXT: buffer_load_dword a17, off, s[0:3], s32 offset:320
+; CHECK-NEXT: buffer_load_dword a16, off, s[0:3], s32 offset:316
+; CHECK-NEXT: buffer_load_dword a15, off, s[0:3], s32 offset:312
+; CHECK-NEXT: buffer_load_dword a14, off, s[0:3], s32 offset:308
+; CHECK-NEXT: buffer_load_dword a13, off, s[0:3], s32 offset:304
+; CHECK-NEXT: buffer_load_dword a12, off, s[0:3], s32 offset:300
+; CHECK-NEXT: buffer_load_dword a11, off, s[0:3], s32 offset:296
+; CHECK-NEXT: buffer_load_dword a10, off, s[0:3], s32 offset:292
+; CHECK-NEXT: buffer_load_dword a9, off, s[0:3], s32 offset:288
+; CHECK-NEXT: buffer_load_dword a8, off, s[0:3], s32 offset:284
+; CHECK-NEXT: buffer_load_dword a7, off, s[0:3], s32 offset:280
+; CHECK-NEXT: buffer_load_dword a6, off, s[0:3], s32 offset:276
+; CHECK-NEXT: buffer_load_dword a5, off, s[0:3], s32 offset:272
+; CHECK-NEXT: buffer_load_dword a4, off, s[0:3], s32 offset:268
; CHECK-NEXT: v_and_b32_e32 v17, 1, v17
-; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
; CHECK-NEXT: v_and_b32_e32 v16, 1, v16
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17
; CHECK-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v16
; CHECK-NEXT: s_mov_b64 s[48:49], 0
; CHECK-NEXT: s_mov_b64 s[52:53], 0
-; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1400 ; 4-byte Folded Spill
+; CHECK-NEXT: ; implicit-def: $vgpr61
+; CHECK-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:1516 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1404 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:1496 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:1520 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1580 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:1500 ; 4-byte Folded Spill
-; CHECK-NEXT: v_mov_b32_e32 v30, v27
-; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1408 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1584 ; 4-byte Folded Spill
+; CHECK-NEXT: v_mov_b32_e32 v32, v25
+; CHECK-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:1524 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1412 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1416 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:1528 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:1540 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1420 ; 4-byte Folded Spill
-; CHECK-NEXT: v_mov_b32_e32 v26, v25
-; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1432 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:1544 ; 4-byte Folded Spill
+; CHECK-NEXT: v_mov_b32_e32 v32, v21
+; CHECK-NEXT: v_mov_b32_e32 v24, v23
+; CHECK-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:1532 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1436 ; 4-byte Folded Spill
-; CHECK-NEXT: v_mov_b32_e32 v26, v23
-; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1424 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:1536 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:1556 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1428 ; 4-byte Folded Spill
-; CHECK-NEXT: v_mov_b32_e32 v26, v21
-; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1440 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:1560 ; 4-byte Folded Spill
+; CHECK-NEXT: v_mov_b32_e32 v20, v19
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:1548 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1444 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:1448 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:1552 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:1588 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:1452 ; 4-byte Folded Spill
-; CHECK-NEXT: v_mov_b32_e32 v20, v19
-; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:1456 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:1592 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:1748 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:1460 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:1464 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:1468 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:992 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:1752 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:1756 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:1760 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:996 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:136
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:132
@@ -158,13 +164,13 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:112
; CHECK-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:108
; CHECK-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:104
-; CHECK-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:100
-; CHECK-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:96
-; CHECK-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:92
-; CHECK-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:88
+; CHECK-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:100
+; CHECK-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:96
+; CHECK-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:92
+; CHECK-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:88
; CHECK-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:84
; CHECK-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:80
-; CHECK-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:76
+; CHECK-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:76
; CHECK-NEXT: s_waitcnt vmcnt(15)
; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
; CHECK-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v0
@@ -199,323 +205,540 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_and_b32_e32 v0, 1, v2
; CHECK-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v1
; CHECK-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0
-; CHECK-NEXT: buffer_load_dword a49, off, s[0:3], s32 offset:392
-; CHECK-NEXT: buffer_load_dword a48, off, s[0:3], s32 offset:388
-; CHECK-NEXT: buffer_load_dword a47, off, s[0:3], s32 offset:384
-; CHECK-NEXT: buffer_load_dword a46, off, s[0:3], s32 offset:380
-; CHECK-NEXT: buffer_load_dword a45, off, s[0:3], s32 offset:376
-; CHECK-NEXT: buffer_load_dword a44, off, s[0:3], s32 offset:372
+; CHECK-NEXT: buffer_load_dword a35, off, s[0:3], s32 offset:392
+; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:388
+; CHECK-NEXT: buffer_load_dword a33, off, s[0:3], s32 offset:384
+; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:380
+; CHECK-NEXT: buffer_load_dword a31, off, s[0:3], s32 offset:376
+; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:372
; CHECK-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:792
; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788
-; CHECK-NEXT: s_waitcnt vmcnt(21)
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:784
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:780
+; CHECK-NEXT: s_waitcnt vmcnt(23)
; CHECK-NEXT: v_and_b32_e32 v17, 1, v18
-; CHECK-NEXT: s_waitcnt vmcnt(20)
+; CHECK-NEXT: s_waitcnt vmcnt(22)
; CHECK-NEXT: v_and_b32_e32 v18, 1, v19
-; CHECK-NEXT: s_waitcnt vmcnt(19)
+; CHECK-NEXT: s_waitcnt vmcnt(21)
; CHECK-NEXT: v_and_b32_e32 v19, 1, v20
-; CHECK-NEXT: s_waitcnt vmcnt(18)
+; CHECK-NEXT: s_waitcnt vmcnt(20)
; CHECK-NEXT: v_and_b32_e32 v20, 1, v21
-; CHECK-NEXT: s_waitcnt vmcnt(17)
+; CHECK-NEXT: s_waitcnt vmcnt(19)
; CHECK-NEXT: v_and_b32_e32 v21, 1, v23
-; CHECK-NEXT: s_waitcnt vmcnt(16)
+; CHECK-NEXT: s_waitcnt vmcnt(18)
; CHECK-NEXT: v_and_b32_e32 v23, 1, v32
-; CHECK-NEXT: s_waitcnt vmcnt(15)
+; CHECK-NEXT: s_waitcnt vmcnt(17)
; CHECK-NEXT: v_and_b32_e32 v32, 1, v25
+; CHECK-NEXT: s_waitcnt vmcnt(16)
+; CHECK-NEXT: v_and_b32_e32 v25, 1, v27
+; CHECK-NEXT: s_waitcnt vmcnt(15)
+; CHECK-NEXT: v_and_b32_e32 v27, 1, v36
; CHECK-NEXT: s_waitcnt vmcnt(14)
-; CHECK-NEXT: v_and_b32_e32 v25, 1, v33
+; CHECK-NEXT: v_and_b32_e32 v36, 1, v37
; CHECK-NEXT: s_waitcnt vmcnt(13)
-; CHECK-NEXT: v_and_b32_e32 v33, 1, v27
+; CHECK-NEXT: v_and_b32_e32 v37, 1, v38
; CHECK-NEXT: s_waitcnt vmcnt(12)
-; CHECK-NEXT: v_and_b32_e32 v27, 1, v34
+; CHECK-NEXT: v_and_b32_e32 v38, 1, v29
; CHECK-NEXT: s_waitcnt vmcnt(11)
-; CHECK-NEXT: v_and_b32_e32 v34, 1, v26
-; CHECK-NEXT: s_waitcnt vmcnt(10)
-; CHECK-NEXT: v_and_b32_e32 v26, 1, v29
-; CHECK-NEXT: s_waitcnt vmcnt(9)
; CHECK-NEXT: v_and_b32_e32 v29, 1, v31
-; CHECK-NEXT: s_waitcnt vmcnt(8)
-; CHECK-NEXT: v_and_b32_e32 v31, 1, v35
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v32
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v33
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v34
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v31
-; CHECK-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:264
-; CHECK-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:260
-; CHECK-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:256
-; CHECK-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:252
-; CHECK-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:248
-; CHECK-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:244
-; CHECK-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:240
-; CHECK-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:236
-; CHECK-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:232
-; CHECK-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:228
-; CHECK-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:224
-; CHECK-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:220
-; CHECK-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:216
-; CHECK-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:212
-; CHECK-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:208
-; CHECK-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:204
-; CHECK-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:200
-; CHECK-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:196
-; CHECK-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:192
-; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188
-; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:184
-; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:180
-; CHECK-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:176
-; CHECK-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:172
-; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:168
-; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:164
-; CHECK-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:160
-; CHECK-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:156
-; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:152
-; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148
-; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144
-; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:140
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v18
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v20
+; CHECK-NEXT: s_waitcnt vmcnt(10)
+; CHECK-NEXT: v_and_b32_e32 v31, 1, v33
; CHECK-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v17
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v18
; CHECK-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v19
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v20
; CHECK-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v21
; CHECK-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v23
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v32
; CHECK-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v25
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v27
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v26
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v27
; CHECK-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v29
-; CHECK-NEXT: buffer_store_dword a18, off, s[0:3], s32 offset:1136 ; 4-byte Folded Spill
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v31
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v36
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v37
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v38
+; CHECK-NEXT: buffer_store_dword a4, off, s[0:3], s32 offset:1252 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword a19, off, s[0:3], s32 offset:1140 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a20, off, s[0:3], s32 offset:1144 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a21, off, s[0:3], s32 offset:1148 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a22, off, s[0:3], s32 offset:1152 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a23, off, s[0:3], s32 offset:1156 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a24, off, s[0:3], s32 offset:1160 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a25, off, s[0:3], s32 offset:1164 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a26, off, s[0:3], s32 offset:1168 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a27, off, s[0:3], s32 offset:1172 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a28, off, s[0:3], s32 offset:1176 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a29, off, s[0:3], s32 offset:1180 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a30, off, s[0:3], s32 offset:1184 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a31, off, s[0:3], s32 offset:1188 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:1192 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a33, off, s[0:3], s32 offset:1196 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a34, off, s[0:3], s32 offset:1200 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a35, off, s[0:3], s32 offset:1204 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a36, off, s[0:3], s32 offset:1208 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a37, off, s[0:3], s32 offset:1212 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a38, off, s[0:3], s32 offset:1216 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a39, off, s[0:3], s32 offset:1220 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a40, off, s[0:3], s32 offset:1224 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a41, off, s[0:3], s32 offset:1228 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a42, off, s[0:3], s32 offset:1232 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a43, off, s[0:3], s32 offset:1236 ; 4-byte Folded Spill
-; CHECK-NEXT: s_waitcnt vmcnt(60)
-; CHECK-NEXT: buffer_store_dword a44, off, s[0:3], s32 offset:1240 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a45, off, s[0:3], s32 offset:1244 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a46, off, s[0:3], s32 offset:1248 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a47, off, s[0:3], s32 offset:1252 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a48, off, s[0:3], s32 offset:1256 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a49, off, s[0:3], s32 offset:1260 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:712
+; CHECK-NEXT: buffer_store_dword a5, off, s[0:3], s32 offset:1256 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a6, off, s[0:3], s32 offset:1260 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a7, off, s[0:3], s32 offset:1264 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a8, off, s[0:3], s32 offset:1268 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a9, off, s[0:3], s32 offset:1272 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a10, off, s[0:3], s32 offset:1276 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a11, off, s[0:3], s32 offset:1280 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a12, off, s[0:3], s32 offset:1284 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a13, off, s[0:3], s32 offset:1288 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a14, off, s[0:3], s32 offset:1292 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a15, off, s[0:3], s32 offset:1296 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a16, off, s[0:3], s32 offset:1300 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a17, off, s[0:3], s32 offset:1304 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a18, off, s[0:3], s32 offset:1308 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a19, off, s[0:3], s32 offset:1312 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a20, off, s[0:3], s32 offset:1316 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a21, off, s[0:3], s32 offset:1320 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a22, off, s[0:3], s32 offset:1324 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a23, off, s[0:3], s32 offset:1328 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a24, off, s[0:3], s32 offset:1332 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a25, off, s[0:3], s32 offset:1336 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a26, off, s[0:3], s32 offset:1340 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a27, off, s[0:3], s32 offset:1344 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a28, off, s[0:3], s32 offset:1348 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a29, off, s[0:3], s32 offset:1352 ; 4-byte Folded Spill
+; CHECK-NEXT: s_waitcnt vmcnt(30)
+; CHECK-NEXT: buffer_store_dword a30, off, s[0:3], s32 offset:1356 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a31, off, s[0:3], s32 offset:1360 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:1364 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a33, off, s[0:3], s32 offset:1368 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a34, off, s[0:3], s32 offset:1372 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a35, off, s[0:3], s32 offset:1376 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a35, off, s[0:3], s32 offset:264
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:708
-; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:704
-; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:700
-; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:696
-; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:692
-; CHECK-NEXT: buffer_load_dword a18, off, s[0:3], s32 offset:688
-; CHECK-NEXT: buffer_load_dword a16, off, s[0:3], s32 offset:684
-; CHECK-NEXT: buffer_load_dword a14, off, s[0:3], s32 offset:680
-; CHECK-NEXT: buffer_load_dword a12, off, s[0:3], s32 offset:676
-; CHECK-NEXT: buffer_load_dword a10, off, s[0:3], s32 offset:672
-; CHECK-NEXT: buffer_load_dword a8, off, s[0:3], s32 offset:668
-; CHECK-NEXT: buffer_load_dword a6, off, s[0:3], s32 offset:664
-; CHECK-NEXT: buffer_load_dword a4, off, s[0:3], s32 offset:660
-; CHECK-NEXT: ; kill: def $agpr1 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr3 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr5 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr7 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr9 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr11 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr13 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr15 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr17 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr19 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr21 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr23 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr25 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr27 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr29 killed $sgpr4 killed $exec
-; CHECK-NEXT: ; kill: def $agpr31 killed $sgpr4 killed $exec
-; CHECK-NEXT: buffer_load_dword a2, off, s[0:3], s32 offset:656
-; CHECK-NEXT: buffer_load_dword a0, off, s[0:3], s32 offset:652
-; CHECK-NEXT: s_waitcnt vmcnt(48)
-; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1272 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:260
+; CHECK-NEXT: buffer_load_dword a33, off, s[0:3], s32 offset:256
+; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:252
+; CHECK-NEXT: buffer_load_dword a31, off, s[0:3], s32 offset:248
+; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:244
+; CHECK-NEXT: buffer_load_dword a29, off, s[0:3], s32 offset:240
+; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:236
+; CHECK-NEXT: buffer_load_dword a27, off, s[0:3], s32 offset:232
+; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:228
+; CHECK-NEXT: buffer_load_dword a25, off, s[0:3], s32 offset:224
+; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:220
+; CHECK-NEXT: buffer_load_dword a23, off, s[0:3], s32 offset:216
+; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:212
+; CHECK-NEXT: buffer_load_dword a21, off, s[0:3], s32 offset:208
+; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:204
+; CHECK-NEXT: buffer_load_dword a19, off, s[0:3], s32 offset:200
+; CHECK-NEXT: buffer_load_dword a18, off, s[0:3], s32 offset:196
+; CHECK-NEXT: buffer_load_dword a17, off, s[0:3], s32 offset:192
+; CHECK-NEXT: buffer_load_dword a16, off, s[0:3], s32 offset:188
+; CHECK-NEXT: buffer_load_dword a15, off, s[0:3], s32 offset:184
+; CHECK-NEXT: buffer_load_dword a14, off, s[0:3], s32 offset:180
+; CHECK-NEXT: buffer_load_dword a13, off, s[0:3], s32 offset:176
+; CHECK-NEXT: buffer_load_dword a12, off, s[0:3], s32 offset:172
+; CHECK-NEXT: buffer_load_dword a11, off, s[0:3], s32 offset:168
+; CHECK-NEXT: buffer_load_dword a10, off, s[0:3], s32 offset:164
+; CHECK-NEXT: buffer_load_dword a9, off, s[0:3], s32 offset:160
+; CHECK-NEXT: buffer_load_dword a8, off, s[0:3], s32 offset:156
+; CHECK-NEXT: buffer_load_dword a7, off, s[0:3], s32 offset:152
+; CHECK-NEXT: buffer_load_dword a6, off, s[0:3], s32 offset:148
+; CHECK-NEXT: buffer_load_dword a5, off, s[0:3], s32 offset:144
+; CHECK-NEXT: buffer_load_dword a4, off, s[0:3], s32 offset:140
+; CHECK-NEXT: s_waitcnt vmcnt(62)
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:988 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1276 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:1280 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:1284 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:1288 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:1292 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:1296 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:1300 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:1304 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:1308 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:1312 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:1316 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:1320 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:1324 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:1328 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:1332 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:1336 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:1340 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:1344 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:1348 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:1352 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:1356 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:1360 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:1364 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:1368 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:1372 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:1376 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:1380 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:1384 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:1388 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:1392 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:1396 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:992 ; 4-byte Folded Spill
; CHECK-NEXT: v_and_b32_e32 v1, 1, v1
; CHECK-NEXT: v_cmp_ne_u32_e64 s[46:47], 1, v1
-; CHECK-NEXT: s_waitcnt vmcnt(32)
-; CHECK-NEXT: buffer_store_dword a0, off, s[0:3], s32 offset:1000 ; 4-byte Folded Spill
+; CHECK-NEXT: s_waitcnt vmcnt(2)
+; CHECK-NEXT: buffer_store_dword a4, off, s[0:3], s32 offset:1380 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword a1, off, s[0:3], s32 offset:1004 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a2, off, s[0:3], s32 offset:1008 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a3, off, s[0:3], s32 offset:1012 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a4, off, s[0:3], s32 offset:1016 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a5, off, s[0:3], s32 offset:1020 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a6, off, s[0:3], s32 offset:1024 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a7, off, s[0:3], s32 offset:1028 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a8, off, s[0:3], s32 offset:1032 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a9, off, s[0:3], s32 offset:1036 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a10, off, s[0:3], s32 offset:1040 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a11, off, s[0:3], s32 offset:1044 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a12, off, s[0:3], s32 offset:1048 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a13, off, s[0:3], s32 offset:1052 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a14, off, s[0:3], s32 offset:1056 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a15, off, s[0:3], s32 offset:1060 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a16, off, s[0:3], s32 offset:1064 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a17, off, s[0:3], s32 offset:1068 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a18, off, s[0:3], s32 offset:1072 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a19, off, s[0:3], s32 offset:1076 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a20, off, s[0:3], s32 offset:1080 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a21, off, s[0:3], s32 offset:1084 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a22, off, s[0:3], s32 offset:1088 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a23, off, s[0:3], s32 offset:1092 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a24, off, s[0:3], s32 offset:1096 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a25, off, s[0:3], s32 offset:1100 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a26, off, s[0:3], s32 offset:1104 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a27, off, s[0:3], s32 offset:1108 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a28, off, s[0:3], s32 offset:1112 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a29, off, s[0:3], s32 offset:1116 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a30, off, s[0:3], s32 offset:1120 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword a31, off, s[0:3], s32 offset:1124 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:412
+; CHECK-NEXT: buffer_store_dword a5, off, s[0:3], s32 offset:1384 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a6, off, s[0:3], s32 offset:1388 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a7, off, s[0:3], s32 offset:1392 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a8, off, s[0:3], s32 offset:1396 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a9, off, s[0:3], s32 offset:1400 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a10, off, s[0:3], s32 offset:1404 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a11, off, s[0:3], s32 offset:1408 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a12, off, s[0:3], s32 offset:1412 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a13, off, s[0:3], s32 offset:1416 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a14, off, s[0:3], s32 offset:1420 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a15, off, s[0:3], s32 offset:1424 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a16, off, s[0:3], s32 offset:1428 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a17, off, s[0:3], s32 offset:1432 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a18, off, s[0:3], s32 offset:1436 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a19, off, s[0:3], s32 offset:1440 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a20, off, s[0:3], s32 offset:1444 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a21, off, s[0:3], s32 offset:1448 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a22, off, s[0:3], s32 offset:1452 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a23, off, s[0:3], s32 offset:1456 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a24, off, s[0:3], s32 offset:1460 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a25, off, s[0:3], s32 offset:1464 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a26, off, s[0:3], s32 offset:1468 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a27, off, s[0:3], s32 offset:1472 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a28, off, s[0:3], s32 offset:1476 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a29, off, s[0:3], s32 offset:1480 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a30, off, s[0:3], s32 offset:1484 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a31, off, s[0:3], s32 offset:1488 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:1492 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a33, off, s[0:3], s32 offset:1496 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a34, off, s[0:3], s32 offset:1500 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a35, off, s[0:3], s32 offset:1504 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:712
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_load_dword a6, off, s[0:3], s32 offset:408
-; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:416
-; CHECK-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:404
-; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:420
-; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:400
-; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:396
-; CHECK-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:424
-; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:440
-; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:436
-; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:444
+; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:708
+; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:704
+; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:700
+; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:696
+; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:692
+; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:688
+; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:684
+; CHECK-NEXT: buffer_load_dword a18, off, s[0:3], s32 offset:680
+; CHECK-NEXT: buffer_load_dword a16, off, s[0:3], s32 offset:676
+; CHECK-NEXT: buffer_load_dword a14, off, s[0:3], s32 offset:672
+; CHECK-NEXT: buffer_load_dword a12, off, s[0:3], s32 offset:668
+; CHECK-NEXT: buffer_load_dword a10, off, s[0:3], s32 offset:664
+; CHECK-NEXT: buffer_load_dword a8, off, s[0:3], s32 offset:660
+; CHECK-NEXT: ; implicit-def: $agpr35
+; CHECK-NEXT: buffer_load_dword a6, off, s[0:3], s32 offset:656
+; CHECK-NEXT: buffer_load_dword a4, off, s[0:3], s32 offset:652
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1472 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a4, off, s[0:3], s32 offset:996 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1476 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:432
+; CHECK-NEXT: buffer_store_dword a5, off, s[0:3], s32 offset:1000 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a6, off, s[0:3], s32 offset:1004 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a7, off, s[0:3], s32 offset:1008 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a8, off, s[0:3], s32 offset:1012 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a9, off, s[0:3], s32 offset:1016 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a10, off, s[0:3], s32 offset:1020 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a11, off, s[0:3], s32 offset:1024 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a12, off, s[0:3], s32 offset:1028 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a13, off, s[0:3], s32 offset:1032 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a14, off, s[0:3], s32 offset:1036 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a15, off, s[0:3], s32 offset:1040 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a16, off, s[0:3], s32 offset:1044 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a17, off, s[0:3], s32 offset:1048 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a18, off, s[0:3], s32 offset:1052 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a19, off, s[0:3], s32 offset:1056 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a20, off, s[0:3], s32 offset:1060 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a21, off, s[0:3], s32 offset:1064 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a22, off, s[0:3], s32 offset:1068 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a23, off, s[0:3], s32 offset:1072 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a24, off, s[0:3], s32 offset:1076 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a25, off, s[0:3], s32 offset:1080 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a26, off, s[0:3], s32 offset:1084 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a27, off, s[0:3], s32 offset:1088 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a28, off, s[0:3], s32 offset:1092 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a29, off, s[0:3], s32 offset:1096 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a30, off, s[0:3], s32 offset:1100 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a31, off, s[0:3], s32 offset:1104 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:1108 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a33, off, s[0:3], s32 offset:1112 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a34, off, s[0:3], s32 offset:1116 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword a35, off, s[0:3], s32 offset:1120 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a8, off, s[0:3], s32 offset:8
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:448
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:400
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:396
+; CHECK-NEXT: ; implicit-def: $agpr9
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1124 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1128 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:1132 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:1136 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:1140 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:1144 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:1148 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:1152 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:1156 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:1160 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:1164 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:1168 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:1172 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:1176 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:1180 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:1184 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:1188 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:1192 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:1196 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:1200 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:1204 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:1208 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:1212 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:1216 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1220 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1224 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:1228 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:1232 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1236 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1240 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:1244 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:1248 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:424
+; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:420
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:416
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1932 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1936 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a14, off, s[0:3], s32 offset:412
+; CHECK-NEXT: buffer_load_dword a12, off, s[0:3], s32 offset:408
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:404
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1480 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1740 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1484 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:428
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1744 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a6, off, s[0:3], s32 offset:4
+; CHECK-NEXT: buffer_load_dword a0, off, s[0:3], s32
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:452
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1488 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1596 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1492 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:784
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1600 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:448
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1604 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:780
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1608 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:444
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:984 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1796 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:988 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:8
-; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:4
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1800 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:440
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1788 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1792 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:436
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1128 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1780 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1784 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:432
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1772 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1776 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:428
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:456
+; CHECK-NEXT: s_waitcnt vmcnt(1)
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1764 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1768 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:1804 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:1808 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1812 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1816 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:1820 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:1824 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:1828 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:1832 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:1836 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:1840 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:1844 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:1848 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:1852 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:1856 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:1860 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:1864 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:1868 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:1872 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:1876 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:1880 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:1884 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:1888 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:1892 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:1896 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:1900 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:1904 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1908 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1912 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:1916 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:1920 ; 4-byte Folded Spill
+; CHECK-NEXT: s_waitcnt vmcnt(32)
+; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1924 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1928 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:584
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:580
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:1612 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:1616 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1620 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1624 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:1628 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:1632 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:1636 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:1640 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:1644 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:1648 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:1652 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:1656 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:1660 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:1664 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:1668 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:1672 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:1676 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:1680 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:1684 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:1688 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:1692 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:1696 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:1700 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:1704 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:1708 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:1712 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1716 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1720 ; 4-byte Folded Spill
+; CHECK-NEXT: s_waitcnt vmcnt(28)
+; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:1724 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:1728 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1732 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1736 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:576
+; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:572
+; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:568
+; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:564
+; CHECK-NEXT: buffer_load_dword a18, off, s[0:3], s32 offset:560
+; CHECK-NEXT: buffer_load_dword a16, off, s[0:3], s32 offset:556
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1132 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:456
-; CHECK-NEXT: buffer_load_dword a36, off, s[0:3], s32 offset:584
-; CHECK-NEXT: buffer_load_dword a40, off, s[0:3], s32 offset:580
-; CHECK-NEXT: buffer_load_dword a38, off, s[0:3], s32 offset:576
-; CHECK-NEXT: buffer_load_dword a42, off, s[0:3], s32 offset:572
-; CHECK-NEXT: buffer_load_dword a44, off, s[0:3], s32 offset:568
-; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:564
-; CHECK-NEXT: buffer_load_dword a46, off, s[0:3], s32 offset:560
-; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:556
; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:552
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:2068 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:2072 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:2076 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:2080 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:2084 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:2088 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:2092 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:2096 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:2100 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:2104 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:2108 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:2112 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:2116 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:2120 ; 4-byte Folded Spill
+; CHECK-NEXT: s_waitcnt vmcnt(14)
+; CHECK-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:2124 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:2128 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:2132 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:2136 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:2140 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:2144 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:2148 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:2152 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:2156 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:2160 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:2164 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:2168 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:2172 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:2176 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:2180 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:2184 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:2188 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:2192 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:548
-; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:544
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:2196 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:2200 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:2204 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:2208 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:2212 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:2216 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:2220 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:2224 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:2228 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:2232 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:2236 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:2240 ; 4-byte Folded Spill
+; CHECK-NEXT: s_waitcnt vmcnt(12)
+; CHECK-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:2244 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:2248 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:2252 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:2256 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:2260 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:2264 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:2268 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:2272 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:2276 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:2280 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:2284 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:2288 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:2292 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:2296 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:2300 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:2304 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:2308 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:2312 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:2316 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:2320 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_load_dword a10, off, s[0:3], s32 offset:544
+; CHECK-NEXT: s_nop 0
; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:540
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:2324 ; 4-byte Folded Spill
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:2328 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:2332 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:2336 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:2340 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:2344 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:2348 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:2352 ; 4-byte Folded Spill
+; CHECK-NEXT: s_waitcnt vmcnt(8)
+; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:2356 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:2360 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:2364 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:2368 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:2372 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:2376 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:2380 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:2384 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:2388 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:2392 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:2396 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:2400 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:2404 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:2408 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:2412 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:2416 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:2420 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:2424 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:2428 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:2432 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:2436 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:2440 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:2444 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:2448 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:536
-; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:532
-; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:528
; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_load_dword a4, off, s[0:3], s32 offset:532
+; CHECK-NEXT: buffer_load_dword a2, off, s[0:3], s32 offset:528
; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:524
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1940 ; 4-byte Folded Spill
; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:1504 ; 4-byte Folded Spill
-; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:1508 ; 4-byte Folded Spill
-; CHECK-NEXT: s_waitcnt vmcnt(2)
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1512 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1516 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:1520 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:1524 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:1528 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:1532 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:1536 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:1540 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:1544 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:1548 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:1552 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:1556 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:1560 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:1564 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:1568 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:1572 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:1576 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:1580 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:1584 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:1588 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:1592 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:1596 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:1600 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:1604 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:1608 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:1612 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:1616 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:1620 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:1624 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:1628 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1944 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:1948 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:1952 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:1956 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:1960 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:1964 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:1968 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:1972 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:1976 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:1980 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:1984 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:1988 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:1992 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:1996 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:2000 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:2004 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:2008 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:2012 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:2016 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:2020 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:2024 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:2028 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:2032 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:2036 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:2040 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:2044 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:2048 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:2052 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:2056 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:2060 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:2064 ; 4-byte Folded Spill
; CHECK-NEXT: v_cmp_lt_i32_e64 s[38:39], 2, v0
; CHECK-NEXT: s_and_saveexec_b64 s[50:51], s[38:39]
; CHECK-NEXT: s_xor_b64 s[50:51], exec, s[50:51]
@@ -526,213 +749,372 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[52:53], s[38:39]
; CHECK-NEXT: s_cbranch_execz .LBB0_3
; CHECK-NEXT: ; %bb.2: ; %bb2
-; CHECK-NEXT: v_accvgpr_write_b32 a10, v42
-; CHECK-NEXT: v_accvgpr_write_b32 a14, v48
-; CHECK-NEXT: v_accvgpr_write_b32 a4, v56
-; CHECK-NEXT: v_accvgpr_write_b32 a2, v50
-; CHECK-NEXT: v_accvgpr_write_b32 a11, v43
-; CHECK-NEXT: v_accvgpr_write_b32 a8, v40
-; CHECK-NEXT: v_accvgpr_write_b32 a15, v49
-; CHECK-NEXT: v_accvgpr_write_b32 a5, v57
-; CHECK-NEXT: v_accvgpr_write_b32 a3, v51
-; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1000 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1004 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1008 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1012 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1016 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1020 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1024 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:1028 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:1032 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:1036 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:1040 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:1044 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:1048 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:1052 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:1056 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:1060 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:1064 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:1068 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:1072 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:1076 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:1080 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:1084 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:1088 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:1092 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:1096 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:1100 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:1104 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:1108 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:1112 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:1116 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:1120 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:1124 ; 4-byte Folded Reload
-; CHECK-NEXT: v_accvgpr_write_b32 a16, v58
-; CHECK-NEXT: v_accvgpr_write_b32 a17, v59
-; CHECK-NEXT: v_accvgpr_read_b32 v60, a36
-; CHECK-NEXT: v_accvgpr_read_b32 v58, a40
+; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:996 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a33, off, s[0:3], s32 offset:1000 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:1004 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a35, off, s[0:3], s32 offset:1008 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a36, off, s[0:3], s32 offset:1012 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a37, off, s[0:3], s32 offset:1016 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a38, off, s[0:3], s32 offset:1020 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a39, off, s[0:3], s32 offset:1024 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a40, off, s[0:3], s32 offset:1028 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a41, off, s[0:3], s32 offset:1032 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a42, off, s[0:3], s32 offset:1036 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a43, off, s[0:3], s32 offset:1040 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a44, off, s[0:3], s32 offset:1044 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a45, off, s[0:3], s32 offset:1048 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a46, off, s[0:3], s32 offset:1052 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a47, off, s[0:3], s32 offset:1056 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a48, off, s[0:3], s32 offset:1060 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a49, off, s[0:3], s32 offset:1064 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a50, off, s[0:3], s32 offset:1068 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a51, off, s[0:3], s32 offset:1072 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a52, off, s[0:3], s32 offset:1076 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a53, off, s[0:3], s32 offset:1080 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a54, off, s[0:3], s32 offset:1084 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a55, off, s[0:3], s32 offset:1088 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a56, off, s[0:3], s32 offset:1092 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a57, off, s[0:3], s32 offset:1096 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a58, off, s[0:3], s32 offset:1100 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a59, off, s[0:3], s32 offset:1104 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a60, off, s[0:3], s32 offset:1108 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a61, off, s[0:3], s32 offset:1112 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a62, off, s[0:3], s32 offset:1116 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a63, off, s[0:3], s32 offset:1120 ; 4-byte Folded Reload
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a2
+; CHECK-NEXT: ; implicit-def: $vgpr31
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v52, a22
; CHECK-NEXT: s_xor_b64 s[54:55], exec, -1
; CHECK-NEXT: s_waitcnt vmcnt(29)
-; CHECK-NEXT: v_xor_b32_e32 v28, v28, v18
-; CHECK-NEXT: s_waitcnt vmcnt(28)
-; CHECK-NEXT: v_xor_b32_e32 v0, v29, v3
-; CHECK-NEXT: v_accvgpr_write_b32 a9, v0
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a27
-; CHECK-NEXT: s_waitcnt vmcnt(26)
-; CHECK-NEXT: v_xor_b32_e32 v29, v31, v29
-; CHECK-NEXT: s_waitcnt vmcnt(24)
-; CHECK-NEXT: v_xor_b32_e32 v0, v33, v7
-; CHECK-NEXT: v_accvgpr_write_b32 a27, v0
-; CHECK-NEXT: v_xor_b32_e32 v0, v30, v4
-; CHECK-NEXT: v_accvgpr_write_b32 a12, v0
-; CHECK-NEXT: s_waitcnt vmcnt(20)
-; CHECK-NEXT: v_xor_b32_e32 v62, v37, v11
-; CHECK-NEXT: v_xor_b32_e32 v0, v32, v6
-; CHECK-NEXT: v_xor_b32_e32 v32, v34, v8
-; CHECK-NEXT: v_xor_b32_e32 v34, v36, v10
-; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a39
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a46
-; CHECK-NEXT: v_xor_b32_e32 v33, v35, v9
-; CHECK-NEXT: s_waitcnt vmcnt(20)
-; CHECK-NEXT: v_xor_b32_e32 v35, v39, v13
-; CHECK-NEXT: s_waitcnt vmcnt(15)
-; CHECK-NEXT: v_xor_b32_e32 v10, v44, v30
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a44
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a34
+; CHECK-NEXT: s_waitcnt vmcnt(25)
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a38
+; CHECK-NEXT: v_xor_b32_e32 v46, v8, v6
+; CHECK-NEXT: s_waitcnt vmcnt(21)
+; CHECK-NEXT: v_accvgpr_mov_b32 a38, a42
+; CHECK-NEXT: s_waitcnt vmcnt(17)
+; CHECK-NEXT: v_accvgpr_mov_b32 a42, a46
+; CHECK-NEXT: s_waitcnt vmcnt(13)
+; CHECK-NEXT: v_accvgpr_mov_b32 a46, a50
+; CHECK-NEXT: s_waitcnt vmcnt(5)
+; CHECK-NEXT: v_accvgpr_read_b32 v36, a58
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_accvgpr_read_b32 v38, a62
+; CHECK-NEXT: v_accvgpr_read_b32 v39, a63
+; CHECK-NEXT: v_xor_b32_e32 v51, v39, v31
+; CHECK-NEXT: v_xor_b32_e32 v39, v38, v60
+; CHECK-NEXT: v_xor_b32_e32 v60, v32, v28
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a36
+; CHECK-NEXT: v_xor_b32_e32 v42, v32, v30
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:2324 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:2328 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:2332 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:2336 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:2340 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:2344 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:2348 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:2352 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:2356 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:2360 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:2364 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:2368 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:2372 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:2376 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:2380 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:2384 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:2388 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:2392 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:2396 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:2400 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:2404 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:2408 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:2412 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:2416 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:2420 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:2424 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:2428 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:2432 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:2436 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:2440 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:2444 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:2448 ; 4-byte Folded Reload
+; CHECK-NEXT: v_accvgpr_mov_b32 a36, a40
+; CHECK-NEXT: s_waitcnt vmcnt(13)
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a36
; CHECK-NEXT: s_waitcnt vmcnt(11)
-; CHECK-NEXT: v_xor_b32_e32 v6, v48, v30
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a42
-; CHECK-NEXT: v_xor_b32_e32 v9, v47, v21
-; CHECK-NEXT: s_waitcnt vmcnt(8)
-; CHECK-NEXT: v_xor_b32_e32 v21, v51, v25
-; CHECK-NEXT: v_accvgpr_write_b32 a36, v0
-; CHECK-NEXT: s_waitcnt vmcnt(6)
-; CHECK-NEXT: v_xor_b32_e32 v13, v53, v31
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a29
-; CHECK-NEXT: s_waitcnt vmcnt(4)
-; CHECK-NEXT: v_xor_b32_e32 v1, v55, v31
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a38
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a10
+; CHECK-NEXT: v_xor_b32_e32 v50, v20, v16
+; CHECK-NEXT: v_accvgpr_mov_b32 a40, a44
+; CHECK-NEXT: v_accvgpr_mov_b32 a44, a48
+; CHECK-NEXT: v_accvgpr_mov_b32 a48, a52
+; CHECK-NEXT: v_accvgpr_mov_b32 a52, a56
+; CHECK-NEXT: v_accvgpr_read_b32 v34, a52
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a26
+; CHECK-NEXT: v_xor_b32_e32 v36, v36, v32
+; CHECK-NEXT: v_xor_b32_e32 v40, v18, v8
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:2196 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:2200 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:2204 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:2208 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:2212 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:2216 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:2220 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:2224 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:2228 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:2232 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:2236 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:2240 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:2244 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:2248 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:2252 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:2256 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:2260 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:2264 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:2268 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:2272 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:2276 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:2280 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:2284 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:2288 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:2292 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:2296 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:2300 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:2304 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:2308 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:2312 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:2316 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:2320 ; 4-byte Folded Reload
+; CHECK-NEXT: s_waitcnt vmcnt(17)
+; CHECK-NEXT: v_accvgpr_read_b32 v14, a40
+; CHECK-NEXT: v_xor_b32_e32 v44, v14, v12
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:2068 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:2072 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:2076 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:2080 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:2084 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:2088 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:2092 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:2096 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:2100 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:2104 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:2108 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:2112 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:2116 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:2120 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:2124 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:2128 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:2132 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:2136 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:2140 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:2144 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:2148 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:2152 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:2156 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:2160 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:2164 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:2168 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:2172 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:2176 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:2180 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:2184 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:2188 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:2192 ; 4-byte Folded Reload
+; CHECK-NEXT: s_waitcnt vmcnt(11)
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a42
+; CHECK-NEXT: s_waitcnt vmcnt(9)
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a44
+; CHECK-NEXT: s_waitcnt vmcnt(7)
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a46
+; CHECK-NEXT: s_waitcnt vmcnt(5)
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a48
; CHECK-NEXT: s_waitcnt vmcnt(3)
-; CHECK-NEXT: v_xor_b32_e32 v25, v56, v60
-; CHECK-NEXT: v_xor_b32_e32 v8, v46, v20
-; CHECK-NEXT: v_xor_b32_e32 v20, v50, v30
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a38
-; CHECK-NEXT: v_xor_b32_e32 v0, v54, v58
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a54
+; CHECK-NEXT: v_xor_b32_e32 v52, v28, v52
+; CHECK-NEXT: v_xor_b32_e32 v56, v20, v14
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
+; CHECK-NEXT: v_xor_b32_e32 v58, v22, v20
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
+; CHECK-NEXT: v_xor_b32_e32 v54, v24, v22
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a20
+; CHECK-NEXT: v_xor_b32_e32 v48, v26, v24
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a24
+; CHECK-NEXT: v_xor_b32_e32 v34, v34, v24
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:1612 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:1616 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1620 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1624 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:1628 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:1632 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1636 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1640 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1644 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1648 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1652 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1656 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1660 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1664 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1668 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1672 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1676 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:1680 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:1684 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:1688 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:1692 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:1696 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:1700 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:1704 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:1708 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:1712 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1716 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1720 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1724 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1728 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1732 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1736 ; 4-byte Folded Reload
+; CHECK-NEXT: s_waitcnt vmcnt(1)
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a60
+; CHECK-NEXT: v_xor_b32_e32 v0, v30, v28
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1940 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1944 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:1948 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:1952 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1956 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1960 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1964 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1968 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1972 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1976 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1984 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1988 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1992 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1996 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:2000 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:2004 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:2008 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:2012 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:2016 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:2020 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:2024 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:2028 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:2032 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:2036 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:2040 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:2044 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:2048 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:2052 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:2056 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:2060 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:2064 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:992 ; 4-byte Folded Reload
+; CHECK-NEXT: s_waitcnt vmcnt(31)
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a32
+; CHECK-NEXT: s_waitcnt vmcnt(30)
+; CHECK-NEXT: v_lshlrev_b32_e32 v5, 17, v39
+; CHECK-NEXT: s_waitcnt vmcnt(27)
+; CHECK-NEXT: v_xor_b32_e32 v8, v4, v2
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 20, v34
+; CHECK-NEXT: s_waitcnt vmcnt(6)
+; CHECK-NEXT: v_xor_b32_e32 v1, v29, v29
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; CHECK-NEXT: v_xor_b32_e32 v11, v45, v19
-; CHECK-NEXT: v_xor_b32_e32 v19, v27, v5
-; CHECK-NEXT: v_xor_b32_e32 v4, v52, v30
-; CHECK-NEXT: v_xor_b32_e32 v30, v26, v2
-; CHECK-NEXT: v_lshlrev_b32_e32 v5, 17, v25
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 14, v[0:1]
+; CHECK-NEXT: v_xor_b32_e32 v1, v27, v27
+; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v1
; CHECK-NEXT: v_or_b32_e32 v3, v3, v5
-; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffffff, v13
-; CHECK-NEXT: v_xor_b32_e32 v18, v38, v12
-; CHECK-NEXT: v_lshlrev_b32_e32 v12, 18, v0
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 13, v[4:5]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v12
-; CHECK-NEXT: v_xor_b32_e32 v7, v49, v23
-; CHECK-NEXT: v_and_b32_e32 v21, 0x7fffffff, v21
-; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
-; CHECK-NEXT: v_and_b32_e32 v11, 0x7fffffff, v11
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a37
-; CHECK-NEXT: s_waitcnt vmcnt(2)
-; CHECK-NEXT: v_xor_b32_e32 v23, v57, v31
-; CHECK-NEXT: v_xor_b32_e32 v17, v43, v17
-; CHECK-NEXT: v_xor_b32_e32 v16, v42, v16
-; CHECK-NEXT: v_and_b32_e32 v17, 0x7fffffff, v17
-; CHECK-NEXT: v_xor_b32_e32 v15, v41, v15
-; CHECK-NEXT: v_xor_b32_e32 v14, v40, v14
-; CHECK-NEXT: v_and_b32_e32 v15, 0x7fffffff, v15
-; CHECK-NEXT: v_accvgpr_read_b32 v57, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v43, a11
-; CHECK-NEXT: v_accvgpr_read_b32 v49, a15
-; CHECK-NEXT: v_accvgpr_read_b32 v51, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v59, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v56, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v42, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v40, a8
-; CHECK-NEXT: v_accvgpr_read_b32 v48, a14
-; CHECK-NEXT: v_accvgpr_read_b32 v50, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v58, a16
+; CHECK-NEXT: v_lshlrev_b32_e32 v5, 18, v0
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 13, v[36:37]
; CHECK-NEXT: s_waitcnt vmcnt(1)
-; CHECK-NEXT: v_add_co_u32_e64 v12, s[38:39], 24, v36
+; CHECK-NEXT: v_add_co_u32_e64 v12, s[38:39], 24, v6
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v5
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_addc_co_u32_e64 v13, s[38:39], 0, v37, s[38:39]
+; CHECK-NEXT: v_addc_co_u32_e64 v13, s[38:39], 0, v7, s[38:39]
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:80
; CHECK-NEXT: s_movk_i32 s38, 0x7c
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 19, v4
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 12, v[20:21]
+; CHECK-NEXT: v_xor_b32_e32 v0, v25, v25
+; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v0
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 19, v36
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 12, v[34:35]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 20, v20
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 11, v[6:7]
+; CHECK-NEXT: v_xor_b32_e32 v0, v23, v23
+; CHECK-NEXT: v_and_b32_e32 v53, 0x7fffffff, v0
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 11, v[52:53]
; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 22, v8
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 21, v6
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 10, v[8:9]
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 22, v48
+; CHECK-NEXT: v_xor_b32_e32 v0, v21, v21
+; CHECK-NEXT: v_and_b32_e32 v49, 0x7fffffff, v0
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 21, v52
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 10, v[48:49]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 9, v[10:11]
+; CHECK-NEXT: v_xor_b32_e32 v0, v19, v19
+; CHECK-NEXT: v_and_b32_e32 v55, 0x7fffffff, v0
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 9, v[54:55]
; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:48
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 26, v18
-; CHECK-NEXT: v_add_co_u32_e64 v0, s[38:39], s38, v36
-; CHECK-NEXT: v_addc_co_u32_e64 v1, s[38:39], 0, v37, s[38:39]
-; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v23
+; CHECK-NEXT: v_xor_b32_e32 v4, v7, v7
+; CHECK-NEXT: v_add_co_u32_e64 v0, s[38:39], s38, v6
+; CHECK-NEXT: v_addc_co_u32_e64 v1, s[38:39], 0, v7, s[38:39]
+; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v51
; CHECK-NEXT: s_movk_i32 s38, 0x78
; CHECK-NEXT: flat_store_short v[0:1], v2
-; CHECK-NEXT: v_add_co_u32_e64 v0, s[38:39], s38, v36
-; CHECK-NEXT: v_alignbit_b32 v2, v23, v25, 15
-; CHECK-NEXT: v_addc_co_u32_e64 v1, s[38:39], 0, v37, s[38:39]
+; CHECK-NEXT: v_add_co_u32_e64 v0, s[38:39], s38, v6
+; CHECK-NEXT: v_alignbit_b32 v2, v51, v39, 15
+; CHECK-NEXT: v_addc_co_u32_e64 v1, s[38:39], 0, v7, s[38:39]
; CHECK-NEXT: flat_store_dword v[0:1], v2
-; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v19
-; CHECK-NEXT: v_lshlrev_b32_e32 v1, 31, v28
-; CHECK-NEXT: v_or_b32_e32 v31, v0, v1
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 23, v10
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 8, v[16:17]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
-; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 24, v16
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 7, v[14:15]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
-; CHECK-NEXT: v_and_b32_e32 v19, 0x7fffffff, v35
+; CHECK-NEXT: v_xor_b32_e32 v0, v1, v1
+; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; CHECK-NEXT: v_lshlrev_b32_e32 v1, 31, v60
+; CHECK-NEXT: v_or_b32_e32 v9, v0, v1
+; CHECK-NEXT: v_xor_b32_e32 v0, v17, v17
+; CHECK-NEXT: v_and_b32_e32 v59, 0x7fffffff, v0
+; CHECK-NEXT: v_xor_b32_e32 v2, v3, v3
+; CHECK-NEXT: v_lshlrev_b32_e32 v3, 23, v54
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 8, v[58:59]
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v3
+; CHECK-NEXT: flat_store_dwordx2 v[6:7], v[0:1] offset:64
+; CHECK-NEXT: v_xor_b32_e32 v0, v15, v15
+; CHECK-NEXT: v_and_b32_e32 v57, 0x7fffffff, v0
+; CHECK-NEXT: v_xor_b32_e32 v3, v5, v5
+; CHECK-NEXT: v_lshlrev_b32_e32 v5, 24, v58
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 7, v[56:57]
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v5
+; CHECK-NEXT: v_xor_b32_e32 v5, v13, v13
+; CHECK-NEXT: v_and_b32_e32 v45, 0x7fffffff, v5
; CHECK-NEXT: flat_store_dwordx2 v[12:13], v[0:1] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 25, v14
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 6, v[18:19]
-; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v62
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 5, v[34:35]
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 25, v56
+; CHECK-NEXT: v_lshrrev_b64 v[16:17], 6, v[44:45]
+; CHECK-NEXT: v_or_b32_e32 v17, v17, v0
+; CHECK-NEXT: v_xor_b32_e32 v0, v11, v11
+; CHECK-NEXT: v_and_b32_e32 v51, 0x7fffffff, v0
+; CHECK-NEXT: v_xor_b32_e32 v0, v9, v9
+; CHECK-NEXT: v_lshrrev_b64 v[14:15], 5, v[50:51]
+; CHECK-NEXT: v_lshlrev_b32_e32 v1, 26, v44
+; CHECK-NEXT: v_and_b32_e32 v41, 0x7fffffff, v0
+; CHECK-NEXT: v_or_b32_e32 v15, v15, v1
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 4, v[40:41]
+; CHECK-NEXT: v_lshlrev_b32_e32 v5, 27, v50
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v5
+; CHECK-NEXT: v_and_b32_e32 v47, 0x7fffffff, v4
+; CHECK-NEXT: flat_store_dwordx2 v[6:7], v[0:1] offset:32
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 3, v[46:47]
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v40
; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
-; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:16
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a36
-; CHECK-NEXT: v_mov_b32_e32 v0, v33
-; CHECK-NEXT: v_and_b32_e32 v33, 0x7fffffff, v0
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 4, v[32:33]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 27, v34
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
-; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:32
-; CHECK-NEXT: v_accvgpr_read_b32 v0, a27
-; CHECK-NEXT: v_accvgpr_read_b32 v2, a36
-; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 3, v[2:3]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 28, v32
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_and_b32_e32 v43, 0x7fffffff, v3
; CHECK-NEXT: flat_store_dwordx2 v[12:13], v[0:1]
-; CHECK-NEXT: v_mov_b32_e32 v0, v29
-; CHECK-NEXT: v_accvgpr_read_b32 v2, a12
-; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[2:3]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v6
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
-; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:16
-; CHECK-NEXT: v_accvgpr_read_b32 v0, a9
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a12
-; CHECK-NEXT: v_and_b32_e32 v29, 0x7fffffff, v0
-; CHECK-NEXT: v_lshrrev_b64 v[32:33], 1, v[28:29]
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v4
-; CHECK-NEXT: v_or_b32_e32 v33, v33, v0
-; CHECK-NEXT: flat_store_dwordx4 v[36:37], v[30:33]
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[42:43]
+; CHECK-NEXT: v_lshlrev_b32_e32 v3, 29, v46
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v3
+; CHECK-NEXT: v_mov_b32_e32 v44, v60
+; CHECK-NEXT: v_and_b32_e32 v45, 0x7fffffff, v2
+; CHECK-NEXT: flat_store_dwordx2 v[6:7], v[0:1] offset:16
+; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[44:45]
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v42
+; CHECK-NEXT: v_or_b32_e32 v11, v11, v0
+; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[14:17] offset:16
+; CHECK-NEXT: flat_store_dwordx4 v[6:7], v[8:11]
; CHECK-NEXT: .LBB0_3: ; %Flow52
; CHECK-NEXT: s_or_b64 exec, exec, s[52:53]
; CHECK-NEXT: s_and_b64 s[52:53], s[54:55], exec
@@ -741,17 +1123,13 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_andn2_saveexec_b64 s[50:51], s[50:51]
; CHECK-NEXT: ; %bb.5: ; %LeafBlock
; CHECK-NEXT: v_cmp_ne_u32_e64 s[38:39], 2, v0
-; CHECK-NEXT: s_andn2_b64 s[48:49], s[52:53], exec
+; CHECK-NEXT: s_andn2_b64 s[52:53], s[52:53], exec
; CHECK-NEXT: s_and_b64 s[38:39], s[38:39], exec
-; CHECK-NEXT: s_or_b64 s[52:53], s[48:49], s[38:39]
; CHECK-NEXT: s_mov_b64 s[48:49], exec
+; CHECK-NEXT: s_or_b64 s[52:53], s[52:53], s[38:39]
; CHECK-NEXT: ; %bb.6: ; %Flow53
; CHECK-NEXT: s_or_b64 exec, exec, s[50:51]
-; CHECK-NEXT: s_mov_b64 s[38:39], exec
-; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:992 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:996 ; 4-byte Folded Reload
-; CHECK-NEXT: s_and_b64 s[50:51], s[38:39], s[52:53]
-; CHECK-NEXT: s_mov_b64 exec, s[50:51]
+; CHECK-NEXT: s_and_saveexec_b64 s[38:39], s[52:53]
; CHECK-NEXT: s_cbranch_execz .LBB0_44
; CHECK-NEXT: ; %bb.7: ; %bb0
; CHECK-NEXT: s_and_saveexec_b64 s[50:51], s[46:47]
@@ -759,42 +1137,50 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_cbranch_execz .LBB0_41
; CHECK-NEXT: ; %bb.8: ; %bb0b
; CHECK-NEXT: s_mov_b64 s[52:53], exec
-; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1456 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1460 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1464 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1468 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1748 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1752 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1756 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1760 ; 4-byte Folded Reload
; CHECK-NEXT: s_and_b64 s[36:37], s[52:53], s[36:37]
; CHECK-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr9
; CHECK-NEXT: s_mov_b64 exec, s[36:37]
; CHECK-NEXT: s_cbranch_execz .LBB0_10
; CHECK-NEXT: ; %bb.9: ; %cond.load
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[8:9], v[0:1]
; CHECK-NEXT: .LBB0_10: ; %else
; CHECK-NEXT: s_or_b64 exec, exec, s[52:53]
; CHECK-NEXT: s_mov_b64 s[36:37], exec
-; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1448 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1452 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1440 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1444 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1424 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:1428 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:1432 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:1436 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1416 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1420 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:1408 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:1412 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1496 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1500 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1400 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:1404 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1264 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1268 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1556 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1560 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1532 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1536 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:1588 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:1592 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1548 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:1552 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:1540 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:1544 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:1524 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:1528 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1580 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1584 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:1516 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:1520 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1572 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1576 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1508 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:1512 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1564 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1568 ; 4-byte Folded Reload
; CHECK-NEXT: s_and_b64 s[34:35], s[36:37], s[34:35]
; CHECK-NEXT: s_mov_b64 exec, s[34:35]
; CHECK-NEXT: s_cbranch_execz .LBB0_12
; CHECK-NEXT: ; %bb.11: ; %cond.load1
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[10:11], v[0:1] offset:8
; CHECK-NEXT: .LBB0_12: ; %else2
@@ -802,6 +1188,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[34:35], s[30:31]
; CHECK-NEXT: s_cbranch_execz .LBB0_14
; CHECK-NEXT: ; %bb.13: ; %cond.load4
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[12:13], v[0:1] offset:16
; CHECK-NEXT: .LBB0_14: ; %else5
@@ -809,6 +1197,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[30:31], s[94:95]
; CHECK-NEXT: s_cbranch_execz .LBB0_16
; CHECK-NEXT: ; %bb.15: ; %cond.load7
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[14:15], v[0:1] offset:24
; CHECK-NEXT: .LBB0_16: ; %else8
@@ -816,6 +1206,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[94:95], s[92:93]
; CHECK-NEXT: s_cbranch_execz .LBB0_18
; CHECK-NEXT: ; %bb.17: ; %cond.load10
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[22:23], v[0:1] offset:32
; CHECK-NEXT: .LBB0_18: ; %else11
@@ -823,6 +1215,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[92:93], s[90:91]
; CHECK-NEXT: s_cbranch_execz .LBB0_20
; CHECK-NEXT: ; %bb.19: ; %cond.load13
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[16:17], v[0:1] offset:40
; CHECK-NEXT: .LBB0_20: ; %else14
@@ -830,6 +1224,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[90:91], s[88:89]
; CHECK-NEXT: s_cbranch_execz .LBB0_22
; CHECK-NEXT: ; %bb.21: ; %cond.load16
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[24:25], v[0:1] offset:48
; CHECK-NEXT: .LBB0_22: ; %else17
@@ -837,6 +1233,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[88:89], s[78:79]
; CHECK-NEXT: s_cbranch_execz .LBB0_24
; CHECK-NEXT: ; %bb.23: ; %cond.load19
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[18:19], v[0:1] offset:56
; CHECK-NEXT: .LBB0_24: ; %else20
@@ -844,6 +1242,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[78:79], s[76:77]
; CHECK-NEXT: s_cbranch_execz .LBB0_26
; CHECK-NEXT: ; %bb.25: ; %cond.load22
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[26:27], v[0:1] offset:64
; CHECK-NEXT: .LBB0_26: ; %else23
@@ -851,6 +1251,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[76:77], s[74:75]
; CHECK-NEXT: s_cbranch_execz .LBB0_28
; CHECK-NEXT: ; %bb.27: ; %cond.load25
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[20:21], v[0:1] offset:72
; CHECK-NEXT: .LBB0_28: ; %else26
@@ -858,6 +1260,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[74:75], s[72:73]
; CHECK-NEXT: s_cbranch_execz .LBB0_30
; CHECK-NEXT: ; %bb.29: ; %cond.load28
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[28:29], v[0:1] offset:80
; CHECK-NEXT: .LBB0_30: ; %else29
@@ -865,6 +1269,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[72:73], s[62:63]
; CHECK-NEXT: s_cbranch_execz .LBB0_32
; CHECK-NEXT: ; %bb.31: ; %cond.load31
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[32:33], v[0:1] offset:88
; CHECK-NEXT: .LBB0_32: ; %else32
@@ -872,6 +1278,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[62:63], s[60:61]
; CHECK-NEXT: s_cbranch_execz .LBB0_34
; CHECK-NEXT: ; %bb.33: ; %cond.load34
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: flat_load_dwordx2 v[30:31], v[0:1] offset:96
; CHECK-NEXT: .LBB0_34: ; %else35
@@ -879,36 +1287,39 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_and_saveexec_b64 s[60:61], s[58:59]
; CHECK-NEXT: s_cbranch_execz .LBB0_36
; CHECK-NEXT: ; %bb.35: ; %cond.load37
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: flat_load_dwordx2 v[2:3], v[0:1] offset:104
-; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:1128 ; 4-byte Folded Spill
-; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:1132 ; 4-byte Folded Spill
+; CHECK-NEXT: flat_load_dwordx2 a[0:1], v[0:1] offset:104
; CHECK-NEXT: .LBB0_36: ; %else38
; CHECK-NEXT: s_or_b64 exec, exec, s[60:61]
; CHECK-NEXT: s_and_saveexec_b64 s[58:59], s[56:57]
; CHECK-NEXT: s_cbranch_execz .LBB0_38
; CHECK-NEXT: ; %bb.37: ; %cond.load40
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: flat_load_dwordx2 a[26:27], v[0:1] offset:112
+; CHECK-NEXT: flat_load_dwordx2 a[6:7], v[0:1] offset:112
; CHECK-NEXT: .LBB0_38: ; %else41
; CHECK-NEXT: s_or_b64 exec, exec, s[58:59]
; CHECK-NEXT: s_and_saveexec_b64 s[56:57], vcc
; CHECK-NEXT: s_cbranch_execz .LBB0_40
; CHECK-NEXT: ; %bb.39: ; %cond.load43
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: flat_load_dwordx2 a[28:29], v[0:1] offset:120
+; CHECK-NEXT: flat_load_dwordx2 a[8:9], v[0:1] offset:120
; CHECK-NEXT: .LBB0_40: ; %else44
; CHECK-NEXT: s_or_b64 exec, exec, s[56:57]
-; CHECK-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:1128 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:1132 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:992 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a28
-; CHECK-NEXT: v_accvgpr_read_b32 v5, a29
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a9
; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v5
+; CHECK-NEXT: v_accvgpr_read_b32 v35, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v34, a0
+; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v35
; CHECK-NEXT: v_and_b32_e32 v31, 0x7fffffff, v31
; CHECK-NEXT: v_and_b32_e32 v33, 0x7fffffff, v33
; CHECK-NEXT: v_and_b32_e32 v29, 0x7fffffff, v29
@@ -921,31 +1332,30 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_and_b32_e32 v15, 0x7fffffff, v15
; CHECK-NEXT: v_and_b32_e32 v13, 0x7fffffff, v13
; CHECK-NEXT: v_and_b32_e32 v11, 0x7fffffff, v11
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v34
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v35, vcc
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v36
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v37, vcc
; CHECK-NEXT: flat_store_short v[0:1], v2
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v34
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v36
; CHECK-NEXT: v_alignbit_b32 v2, v5, v4, 15
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v35, vcc
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v37, vcc
; CHECK-NEXT: flat_store_dword v[0:1], v2
-; CHECK-NEXT: v_accvgpr_read_b32 v2, a26
-; CHECK-NEXT: v_accvgpr_read_b32 v3, a27
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a7
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v10
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
; CHECK-NEXT: v_or_b32_e32 v9, v1, v0
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 17, v4
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[2:3]
-; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v37
; CHECK-NEXT: v_or_b32_e32 v5, v5, v0
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v34
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v36
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 18, v2
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[36:37]
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v35, vcc
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[34:35]
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v37, vcc
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v30
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v36
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v34
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[30:31]
; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[32:33]
@@ -962,7 +1372,7 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v20
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[26:27]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
-; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[2:3] offset:64
+; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[2:3] offset:64
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v26
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[18:19]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
@@ -977,7 +1387,7 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v16
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[22:23]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
-; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[2:3] offset:32
+; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[2:3] offset:32
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v22
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[14:15]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
@@ -985,50 +1395,50 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v14
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[12:13]
; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
-; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[0:1] offset:16
+; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:16
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v12
; CHECK-NEXT: v_or_b32_e32 v11, v11, v0
-; CHECK-NEXT: flat_store_dwordx4 v[34:35], v[8:11]
+; CHECK-NEXT: flat_store_dwordx4 v[36:37], v[8:11]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; kill: killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: .LBB0_41: ; %Flow
; CHECK-NEXT: s_andn2_saveexec_b64 s[56:57], s[50:51]
; CHECK-NEXT: s_cbranch_execz .LBB0_43
; CHECK-NEXT: ; %bb.42: ; %bb0a
-; CHECK-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1000 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1004 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1008 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1012 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1016 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1020 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1024 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1028 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1032 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:1036 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:1040 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:1044 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:1048 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:1052 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:1056 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:1060 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:1064 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:1068 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1072 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1076 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1080 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1084 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1088 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1092 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1096 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:1100 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:1104 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:1108 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:1112 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:1116 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:1120 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:1124 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:992 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:996 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1000 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1004 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1008 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1012 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1016 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1020 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1024 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1028 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:1032 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:1036 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:1040 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:1044 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:1048 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:1052 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:1056 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:1060 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:1064 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1068 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1072 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1076 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1080 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1084 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1088 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1092 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:1096 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:1100 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:1104 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:1108 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:1112 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:1116 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:1120 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_and_b32_e32 v11, 0x7fffffff, v11
; CHECK-NEXT: v_and_b32_e32 v13, 0x7fffffff, v13
@@ -1044,24 +1454,25 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_and_b32_e32 v33, 0x7fffffff, v33
; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v35
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 18, v36
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v52
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v4
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v39
; CHECK-NEXT: flat_store_short v[0:1], v2
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v52
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v4
; CHECK-NEXT: v_alignbit_b32 v2, v39, v38, 15
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
; CHECK-NEXT: flat_store_dword v[0:1], v2
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v10
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v37
; CHECK-NEXT: v_or_b32_e32 v9, v1, v0
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 17, v38
+; CHECK-NEXT: v_pk_mov_b32 v[38:39], v[4:5], v[4:5] op_sel:[0,1]
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[36:37]
; CHECK-NEXT: v_or_b32_e32 v5, v5, v0
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v52
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v38
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[34:35]
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v39, vcc
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v32
@@ -1082,7 +1493,7 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v26
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[24:25]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
-; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[2:3] offset:64
+; CHECK-NEXT: flat_store_dwordx2 v[38:39], v[2:3] offset:64
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v24
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[22:23]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
@@ -1097,7 +1508,7 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v18
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[16:17]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
-; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[2:3] offset:32
+; CHECK-NEXT: flat_store_dwordx2 v[38:39], v[2:3] offset:32
; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v16
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[14:15]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
@@ -1105,10 +1516,10 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v14
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[12:13]
; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
-; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[0:1] offset:16
+; CHECK-NEXT: flat_store_dwordx2 v[38:39], v[0:1] offset:16
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v12
; CHECK-NEXT: v_or_b32_e32 v11, v11, v0
-; CHECK-NEXT: flat_store_dwordx4 v[52:53], v[8:11]
+; CHECK-NEXT: flat_store_dwordx4 v[38:39], v[8:11]
; CHECK-NEXT: .LBB0_43: ; %Flow48
; CHECK-NEXT: s_or_b64 exec, exec, s[56:57]
; CHECK-NEXT: s_andn2_b64 s[48:49], s[48:49], exec
@@ -1121,141 +1532,187 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_xor_b64 s[46:47], exec, s[58:59]
; CHECK-NEXT: s_cbranch_execz .LBB0_47
; CHECK-NEXT: ; %bb.46: ; %bb1b
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a31
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a30
-; CHECK-NEXT: v_lshrrev_b32_e32 v33, 15, v31
-; CHECK-NEXT: v_alignbit_b32 v36, v31, v32, 15
-; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:1504 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:1508 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1512 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1516 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:1520 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:1524 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1528 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1532 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1536 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1540 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1544 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1548 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1552 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1556 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1560 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1564 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1568 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:1572 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:1576 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:1580 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:1584 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:1588 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:1592 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:1596 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:1600 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:1604 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1608 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1612 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1616 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1620 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1624 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1628 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1488 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1492 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1480 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1484 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1804 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1808 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1812 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1816 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1820 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1824 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1828 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1832 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1836 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:1840 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:1844 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:1848 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:1852 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:1856 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:1860 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:1864 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:1868 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:1872 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1876 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1880 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1884 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1888 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1892 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1896 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1900 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:1904 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:1908 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:1912 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:1916 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:1920 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:1924 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:1928 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1596 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1600 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:1604 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:1608 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:992 ; 4-byte Folded Reload
+; CHECK-NEXT: v_lshrrev_b32_e32 v6, 15, v61
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 17, v32
-; CHECK-NEXT: v_and_b32_e32 v59, 0x7fffffff, v59
-; CHECK-NEXT: v_and_b32_e32 v51, 0x7fffffff, v51
-; CHECK-NEXT: v_and_b32_e32 v57, 0x7fffffff, v57
-; CHECK-NEXT: v_and_b32_e32 v49, 0x7fffffff, v49
-; CHECK-NEXT: v_and_b32_e32 v43, 0x7fffffff, v43
-; CHECK-NEXT: v_and_b32_e32 v4, 0x7fffffff, v1
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v10
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
-; CHECK-NEXT: flat_store_short v[0:1], v33
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v10
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
-; CHECK-NEXT: flat_store_dword v[0:1], v36
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v42
-; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; CHECK-NEXT: v_or_b32_e32 v41, v4, v0
+; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v27
+; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v29
+; CHECK-NEXT: v_mov_b32_e32 v30, v38
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 17, v30
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[2:3]
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v6
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 18, v2
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[8:9]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
-; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1472 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1476 ; 4-byte Folded Reload
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v10
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v0
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 18, v2
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[34:35]
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v36
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v37, vcc
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
-; CHECK-NEXT: v_lshrrev_b64 v[42:43], 1, v[42:43]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v8
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a32
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a33
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
+; CHECK-NEXT: v_alignbit_b32 v7, v61, v30, 15
+; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, 0x7c, v36
+; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v37, vcc
+; CHECK-NEXT: flat_store_short v[2:3], v6
+; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, 0x78, v36
+; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v37, vcc
+; CHECK-NEXT: flat_store_dword v[2:3], v7
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1124 ; 4-byte Folded Reload
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1128 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:1132 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:1136 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1140 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1144 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1148 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1152 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:1156 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:1160 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1164 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1168 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:1172 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:1176 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:1180 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:1184 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:1188 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:1192 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:1196 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:1200 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:1204 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:1208 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:1212 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:1216 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:1220 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:1224 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:1228 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1232 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1236 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1240 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1244 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:1248 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1796 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1800 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1788 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1792 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
+; CHECK-NEXT: v_mov_b32_e32 v8, v2
+; CHECK-NEXT: v_mov_b32_e32 v10, v4
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 31, v10
+; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v9
+; CHECK-NEXT: v_or_b32_e32 v9, v3, v2
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v34
+; CHECK-NEXT: v_and_b32_e32 v11, 0x7fffffff, v11
+; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; CHECK-NEXT: v_and_b32_e32 v13, 0x7fffffff, v31
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v33
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[6:7]
; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v6
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[8:9]
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[12:13]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a34
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1780 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1784 ; 4-byte Folded Reload
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v29
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a35
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v8
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a24
-; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a25
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v12
+; CHECK-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:1772 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:1776 ; 4-byte Folded Reload
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_and_b32_e32 v13, 0x7fffffff, v27
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[6:7]
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 22, v6
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[8:9]
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[12:13]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1764 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1768 ; 4-byte Folded Reload
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v25
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:48
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a22
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v8
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[58:59]
+; CHECK-NEXT: v_and_b32_e32 v13, 0x7fffffff, v19
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v12
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[6:7]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
-; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[2:3] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v58
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[50:51]
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a20
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v6
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a30
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v23
+; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[2:3] offset:64
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[6:7]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
-; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a21
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v50
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v6
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a28
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v21
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 6, v[6:7]
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
+; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1932 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1936 ; 4-byte Folded Reload
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 26, v6
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[8:9]
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v17
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v12, v2
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[12:13]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a14
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:16
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v8
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[56:57]
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v12
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[6:7]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
-; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
-; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[2:3] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v56
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v6
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a12
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v15
+; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[2:3] offset:32
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[6:7]
; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:1740 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:1744 ; 4-byte Folded Reload
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffffff, v13
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v6
-; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[48:49]
+; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[4:5]
; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
-; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[0:1] offset:16
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v48
-; CHECK-NEXT: v_or_b32_e32 v43, v43, v0
-; CHECK-NEXT: flat_store_dwordx4 v[10:11], v[40:43]
+; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:16
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v4
+; CHECK-NEXT: v_or_b32_e32 v11, v11, v0
+; CHECK-NEXT: flat_store_dwordx4 v[36:37], v[8:11]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; kill: killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
@@ -1266,150 +1723,173 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: s_andn2_saveexec_b64 s[46:47], s[46:47]
; CHECK-NEXT: s_cbranch_execz .LBB0_49
; CHECK-NEXT: ; %bb.48: ; %bb1a
-; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:1136 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a33, off, s[0:3], s32 offset:1140 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:1144 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a35, off, s[0:3], s32 offset:1148 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a36, off, s[0:3], s32 offset:1152 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a37, off, s[0:3], s32 offset:1156 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a38, off, s[0:3], s32 offset:1160 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a39, off, s[0:3], s32 offset:1164 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a40, off, s[0:3], s32 offset:1168 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a41, off, s[0:3], s32 offset:1172 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a42, off, s[0:3], s32 offset:1176 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a43, off, s[0:3], s32 offset:1180 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a44, off, s[0:3], s32 offset:1184 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a45, off, s[0:3], s32 offset:1188 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a46, off, s[0:3], s32 offset:1192 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a47, off, s[0:3], s32 offset:1196 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a48, off, s[0:3], s32 offset:1200 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a49, off, s[0:3], s32 offset:1204 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a50, off, s[0:3], s32 offset:1208 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a51, off, s[0:3], s32 offset:1212 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a52, off, s[0:3], s32 offset:1216 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a53, off, s[0:3], s32 offset:1220 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a54, off, s[0:3], s32 offset:1224 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a55, off, s[0:3], s32 offset:1228 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a56, off, s[0:3], s32 offset:1232 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a57, off, s[0:3], s32 offset:1236 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a58, off, s[0:3], s32 offset:1240 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a59, off, s[0:3], s32 offset:1244 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a60, off, s[0:3], s32 offset:1248 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a61, off, s[0:3], s32 offset:1252 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a62, off, s[0:3], s32 offset:1256 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a63, off, s[0:3], s32 offset:1260 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a0, off, s[0:3], s32 offset:1272 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a1, off, s[0:3], s32 offset:1276 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a2, off, s[0:3], s32 offset:1280 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a3, off, s[0:3], s32 offset:1284 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a4, off, s[0:3], s32 offset:1288 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a5, off, s[0:3], s32 offset:1292 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a6, off, s[0:3], s32 offset:1296 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a7, off, s[0:3], s32 offset:1300 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a8, off, s[0:3], s32 offset:1304 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a9, off, s[0:3], s32 offset:1308 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a10, off, s[0:3], s32 offset:1312 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a11, off, s[0:3], s32 offset:1316 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a12, off, s[0:3], s32 offset:1320 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a13, off, s[0:3], s32 offset:1324 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a14, off, s[0:3], s32 offset:1328 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a15, off, s[0:3], s32 offset:1332 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a16, off, s[0:3], s32 offset:1336 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a17, off, s[0:3], s32 offset:1340 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a18, off, s[0:3], s32 offset:1344 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a19, off, s[0:3], s32 offset:1348 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:1352 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a21, off, s[0:3], s32 offset:1356 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:1360 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a23, off, s[0:3], s32 offset:1364 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:1368 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a25, off, s[0:3], s32 offset:1372 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:1376 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a27, off, s[0:3], s32 offset:1380 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:1384 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a29, off, s[0:3], s32 offset:1388 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:1392 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword a31, off, s[0:3], s32 offset:1396 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:1252 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a33, off, s[0:3], s32 offset:1256 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:1260 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a35, off, s[0:3], s32 offset:1264 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a36, off, s[0:3], s32 offset:1268 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a37, off, s[0:3], s32 offset:1272 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a38, off, s[0:3], s32 offset:1276 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a39, off, s[0:3], s32 offset:1280 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a40, off, s[0:3], s32 offset:1284 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a41, off, s[0:3], s32 offset:1288 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a42, off, s[0:3], s32 offset:1292 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a43, off, s[0:3], s32 offset:1296 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a44, off, s[0:3], s32 offset:1300 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a45, off, s[0:3], s32 offset:1304 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a46, off, s[0:3], s32 offset:1308 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a47, off, s[0:3], s32 offset:1312 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a48, off, s[0:3], s32 offset:1316 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a49, off, s[0:3], s32 offset:1320 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a50, off, s[0:3], s32 offset:1324 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a51, off, s[0:3], s32 offset:1328 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a52, off, s[0:3], s32 offset:1332 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a53, off, s[0:3], s32 offset:1336 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a54, off, s[0:3], s32 offset:1340 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a55, off, s[0:3], s32 offset:1344 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a56, off, s[0:3], s32 offset:1348 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a57, off, s[0:3], s32 offset:1352 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a58, off, s[0:3], s32 offset:1356 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a59, off, s[0:3], s32 offset:1360 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a60, off, s[0:3], s32 offset:1364 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a61, off, s[0:3], s32 offset:1368 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a62, off, s[0:3], s32 offset:1372 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a63, off, s[0:3], s32 offset:1376 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a0, off, s[0:3], s32 offset:1380 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a1, off, s[0:3], s32 offset:1384 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a2, off, s[0:3], s32 offset:1388 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a3, off, s[0:3], s32 offset:1392 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a4, off, s[0:3], s32 offset:1396 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a5, off, s[0:3], s32 offset:1400 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a6, off, s[0:3], s32 offset:1404 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a7, off, s[0:3], s32 offset:1408 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a8, off, s[0:3], s32 offset:1412 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a9, off, s[0:3], s32 offset:1416 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a10, off, s[0:3], s32 offset:1420 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a11, off, s[0:3], s32 offset:1424 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a12, off, s[0:3], s32 offset:1428 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a13, off, s[0:3], s32 offset:1432 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a14, off, s[0:3], s32 offset:1436 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a15, off, s[0:3], s32 offset:1440 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a16, off, s[0:3], s32 offset:1444 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a17, off, s[0:3], s32 offset:1448 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a18, off, s[0:3], s32 offset:1452 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a19, off, s[0:3], s32 offset:1456 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a20, off, s[0:3], s32 offset:1460 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a21, off, s[0:3], s32 offset:1464 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a22, off, s[0:3], s32 offset:1468 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a23, off, s[0:3], s32 offset:1472 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a24, off, s[0:3], s32 offset:1476 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a25, off, s[0:3], s32 offset:1480 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a26, off, s[0:3], s32 offset:1484 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a27, off, s[0:3], s32 offset:1488 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a28, off, s[0:3], s32 offset:1492 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a29, off, s[0:3], s32 offset:1496 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a30, off, s[0:3], s32 offset:1500 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword a31, off, s[0:3], s32 offset:1504 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a32
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a33
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a34
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a35
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a36
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a37
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a38
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a39
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a40
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a41
+; CHECK-NEXT: v_accvgpr_read_b32 v10, a42
+; CHECK-NEXT: v_accvgpr_read_b32 v11, a43
+; CHECK-NEXT: v_accvgpr_read_b32 v12, a44
+; CHECK-NEXT: v_accvgpr_read_b32 v13, a45
+; CHECK-NEXT: v_accvgpr_read_b32 v14, a46
+; CHECK-NEXT: v_accvgpr_read_b32 v15, a47
; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a30
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a31
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a32
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a28
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a33
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a34
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a35
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a36
-; CHECK-NEXT: v_accvgpr_read_b32 v36, a38
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a28
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a9
+; CHECK-NEXT: v_accvgpr_read_b32 v10, a10
+; CHECK-NEXT: v_accvgpr_read_b32 v11, a11
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a62
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a63
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
+; CHECK-NEXT: v_accvgpr_read_b32 v61, a31
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
; CHECK-NEXT: v_accvgpr_read_b32 v28, a60
+; CHECK-NEXT: v_accvgpr_read_b32 v58, a28
; CHECK-NEXT: v_accvgpr_read_b32 v30, a62
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a21
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a24
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a25
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a26
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a27
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a29
-; CHECK-NEXT: v_accvgpr_read_b32 v37, a39
-; CHECK-NEXT: v_accvgpr_read_b32 v38, a40
-; CHECK-NEXT: v_accvgpr_read_b32 v39, a41
-; CHECK-NEXT: v_accvgpr_read_b32 v59, a61
-; CHECK-NEXT: v_cndmask_b32_e64 v36, v28, v32, s[44:45]
; CHECK-NEXT: v_accvgpr_read_b32 v33, a31
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a61
+; CHECK-NEXT: v_accvgpr_read_b32 v60, a30
+; CHECK-NEXT: v_accvgpr_read_b32 v59, a29
+; CHECK-NEXT: v_accvgpr_read_b32 v43, a13
+; CHECK-NEXT: v_accvgpr_read_b32 v42, a12
+; CHECK-NEXT: v_accvgpr_read_b32 v41, a11
+; CHECK-NEXT: v_accvgpr_read_b32 v40, a10
+; CHECK-NEXT: v_accvgpr_read_b32 v39, a9
+; CHECK-NEXT: v_accvgpr_read_b32 v38, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v37, a7
+; CHECK-NEXT: v_accvgpr_read_b32 v36, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v35, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v34, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a60
+; CHECK-NEXT: v_accvgpr_read_b32 v58, a28
; CHECK-NEXT: v_accvgpr_read_b32 v31, a63
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a30
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a62
-; CHECK-NEXT: v_cndmask_b32_e64 v37, v59, v29, s[44:45]
-; CHECK-NEXT: v_cndmask_b32_e64 v39, v31, v33, s[40:41]
-; CHECK-NEXT: v_cndmask_b32_e64 v38, v30, v34, s[40:41]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a27
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a21
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v49, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a25
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a24
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a53
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a56
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a57
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a58
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a59
-; CHECK-NEXT: v_cndmask_b32_e64 v49, v25, v29, s[42:43]
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a24
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
; CHECK-NEXT: v_accvgpr_read_b32 v32, a30
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a62
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
+; CHECK-NEXT: v_cndmask_b32_e64 v59, v29, v59, s[44:45]
+; CHECK-NEXT: v_cndmask_b32_e64 v58, v28, v58, s[44:45]
+; CHECK-NEXT: v_cndmask_b32_e64 v61, v31, v33, s[40:41]
+; CHECK-NEXT: v_cndmask_b32_e64 v60, v30, v32, s[40:41]
+; CHECK-NEXT: v_accvgpr_read_b32 v28, a32
+; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
+; CHECK-NEXT: v_accvgpr_read_b32 v29, a33
+; CHECK-NEXT: v_accvgpr_read_b32 v32, a36
+; CHECK-NEXT: v_accvgpr_read_b32 v33, a37
+; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
+; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
+; CHECK-NEXT: v_cndmask_b32_e64 v5, v33, v5, s[12:13]
+; CHECK-NEXT: v_cndmask_b32_e64 v4, v32, v4, s[12:13]
+; CHECK-NEXT: v_cndmask_b32_e64 v33, v29, v1, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v32, v28, v0, s[4:5]
+; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:992 ; 4-byte Folded Reload
; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a58
-; CHECK-NEXT: v_accvgpr_read_b32 v48, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v50, a52
-; CHECK-NEXT: v_accvgpr_read_b32 v51, a53
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a26
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a21
; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
@@ -1418,213 +1898,142 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
; CHECK-NEXT: v_accvgpr_read_b32 v24, a56
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a27
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a57
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a58
; CHECK-NEXT: v_accvgpr_read_b32 v27, a59
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a26
-; CHECK-NEXT: v_cndmask_b32_e64 v48, v24, v28, s[42:43]
-; CHECK-NEXT: v_cndmask_b32_e64 v51, v27, v33, s[26:27]
-; CHECK-NEXT: v_cndmask_b32_e64 v50, v26, v34, s[26:27]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v53, a55
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a21
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a53
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
-; CHECK-NEXT: v_cndmask_b32_e64 v53, v21, v29, s[28:29]
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a26
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a20
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v52, a54
-; CHECK-NEXT: v_accvgpr_read_b32 v54, a56
-; CHECK-NEXT: v_accvgpr_read_b32 v55, a57
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a52
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a55
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a22
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a50
-; CHECK-NEXT: v_accvgpr_read_b32 v40, a42
-; CHECK-NEXT: v_accvgpr_read_b32 v41, a43
-; CHECK-NEXT: v_accvgpr_read_b32 v42, a44
-; CHECK-NEXT: v_accvgpr_read_b32 v43, a45
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a49
-; CHECK-NEXT: v_cndmask_b32_e64 v52, v20, v24, s[28:29]
-; CHECK-NEXT: v_cndmask_b32_e64 v55, v23, v33, s[22:23]
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a17
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a16
-; CHECK-NEXT: v_cndmask_b32_e64 v54, v22, v34, s[22:23]
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a16
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a19
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a51
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v17, a17
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v19, a19
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a20
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a21
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a24
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v55, a25
+; CHECK-NEXT: v_accvgpr_read_b32 v54, a24
+; CHECK-NEXT: v_accvgpr_read_b32 v53, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v52, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v51, a21
+; CHECK-NEXT: v_accvgpr_read_b32 v50, a20
+; CHECK-NEXT: v_accvgpr_read_b32 v49, a19
+; CHECK-NEXT: v_accvgpr_read_b32 v48, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v47, a17
+; CHECK-NEXT: v_accvgpr_read_b32 v46, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v45, a15
+; CHECK-NEXT: v_accvgpr_read_b32 v44, a14
+; CHECK-NEXT: v_accvgpr_read_b32 v17, a17
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v19, a19
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a20
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a21
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v44, a48
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a16
; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a8
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a9
+; CHECK-NEXT: v_accvgpr_read_b32 v48, a52
+; CHECK-NEXT: v_accvgpr_read_b32 v20, a20
; CHECK-NEXT: v_accvgpr_read_b32 v10, a10
; CHECK-NEXT: v_accvgpr_read_b32 v11, a11
-; CHECK-NEXT: v_accvgpr_read_b32 v12, a12
-; CHECK-NEXT: v_accvgpr_read_b32 v13, a13
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a34
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a35
+; CHECK-NEXT: v_accvgpr_read_b32 v34, a38
+; CHECK-NEXT: v_accvgpr_read_b32 v35, a39
+; CHECK-NEXT: v_accvgpr_read_b32 v49, a53
; CHECK-NEXT: v_accvgpr_read_b32 v14, a14
; CHECK-NEXT: v_accvgpr_read_b32 v15, a15
-; CHECK-NEXT: v_cndmask_b32_e64 v41, v17, v29, s[24:25]
-; CHECK-NEXT: v_cndmask_b32_e64 v40, v16, v20, s[24:25]
-; CHECK-NEXT: v_cndmask_b32_e64 v43, v19, v33, s[18:19]
-; CHECK-NEXT: v_cndmask_b32_e64 v42, v18, v34, s[18:19]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a15
-; CHECK-NEXT: v_accvgpr_read_b32 v0, a32
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a14
-; CHECK-NEXT: v_accvgpr_read_b32 v12, a44
-; CHECK-NEXT: v_accvgpr_read_b32 v13, a45
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a13
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a12
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a11
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a9
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a8
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a6
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v17, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v16, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a12
-; CHECK-NEXT: v_cndmask_b32_e64 v17, v13, v29, s[20:21]
-; CHECK-NEXT: v_cndmask_b32_e64 v16, v12, v30, s[20:21]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a11
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a18
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a41
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a9
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a8
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a6
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v21, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a15
-; CHECK-NEXT: v_cndmask_b32_e64 v21, v9, v29, s[16:17]
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a8
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a40
-; CHECK-NEXT: v_accvgpr_read_b32 v15, a47
-; CHECK-NEXT: v_accvgpr_read_b32 v19, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a14
-; CHECK-NEXT: v_accvgpr_read_b32 v20, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a6
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a2
-; CHECK-NEXT: v_cndmask_b32_e64 v19, v15, v33, s[14:15]
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a11
-; CHECK-NEXT: v_cndmask_b32_e64 v20, v8, v30, s[16:17]
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v5, a37
-; CHECK-NEXT: v_accvgpr_read_b32 v11, a43
-; CHECK-NEXT: v_accvgpr_read_b32 v23, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a6
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a5
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v25, a1
-; CHECK-NEXT: v_cndmask_b32_e64 v23, v11, v33, s[10:11]
-; CHECK-NEXT: v_cndmask_b32_e64 v25, v5, v29, s[12:13]
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a4
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a7
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a36
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a39
-; CHECK-NEXT: v_accvgpr_read_b32 v24, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v27, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a6
-; CHECK-NEXT: v_cndmask_b32_e64 v24, v4, v30, s[12:13]
-; CHECK-NEXT: v_cndmask_b32_e64 v27, v7, v33, s[6:7]
-; CHECK-NEXT: v_accvgpr_read_b32 v33, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a3
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v29, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v1, a33
-; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
-; CHECK-NEXT: v_cndmask_b32_e64 v29, v1, v29, s[4:5]
-; CHECK-NEXT: v_cndmask_b32_e64 v28, v0, v28, s[4:5]
-; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
-; CHECK-NEXT: v_accvgpr_read_b32 v14, a46
-; CHECK-NEXT: v_accvgpr_read_b32 v18, a2
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a14
-; CHECK-NEXT: v_accvgpr_read_b32 v2, a34
-; CHECK-NEXT: v_accvgpr_read_b32 v3, a35
-; CHECK-NEXT: v_accvgpr_read_b32 v10, a42
-; CHECK-NEXT: v_cndmask_b32_e64 v18, v14, v34, s[14:15]
-; CHECK-NEXT: v_accvgpr_read_b32 v22, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a10
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a1
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a38
-; CHECK-NEXT: v_cndmask_b32_e64 v22, v10, v34, s[10:11]
-; CHECK-NEXT: v_accvgpr_read_b32 v26, a0
-; CHECK-NEXT: v_accvgpr_read_b32 v34, a6
-; CHECK-NEXT: v_cndmask_b32_e64 v31, v3, v33, s[8:9]
-; CHECK-NEXT: v_cndmask_b32_e64 v30, v2, v30, s[8:9]
-; CHECK-NEXT: v_cndmask_b32_e64 v26, v6, v34, s[6:7]
+; CHECK-NEXT: v_accvgpr_read_b32 v21, a21
+; CHECK-NEXT: v_cndmask_b32_e64 v48, v48, v20, s[28:29]
+; CHECK-NEXT: v_accvgpr_read_b32 v10, a10
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
+; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
+; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
+; CHECK-NEXT: v_accvgpr_read_b32 v36, a40
+; CHECK-NEXT: v_accvgpr_read_b32 v37, a41
+; CHECK-NEXT: v_accvgpr_read_b32 v38, a42
+; CHECK-NEXT: v_accvgpr_read_b32 v39, a43
+; CHECK-NEXT: v_accvgpr_read_b32 v12, a12
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a26
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a27
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v19, a19
+; CHECK-NEXT: v_cndmask_b32_e64 v49, v49, v21, s[28:29]
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a9
+; CHECK-NEXT: v_accvgpr_read_b32 v14, a14
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a8
+; CHECK-NEXT: v_accvgpr_read_b32 v11, a11
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[28:31]
-; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[24:27] offset:16
-; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[20:23] offset:32
-; CHECK-NEXT: v_accvgpr_read_b32 v35, a37
; CHECK-NEXT: v_add_co_u32_e32 v20, vcc, 48, v0
+; CHECK-NEXT: v_accvgpr_read_b32 v10, a10
+; CHECK-NEXT: v_cndmask_b32_e64 v7, v35, v7, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v6, v34, v6, s[6:7]
+; CHECK-NEXT: v_cndmask_b32_e64 v35, v31, v3, s[8:9]
+; CHECK-NEXT: v_cndmask_b32_e64 v34, v30, v2, s[8:9]
; CHECK-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v1, vcc
+; CHECK-NEXT: v_accvgpr_read_b32 v40, a44
+; CHECK-NEXT: v_accvgpr_read_b32 v41, a45
+; CHECK-NEXT: v_accvgpr_read_b32 v42, a46
+; CHECK-NEXT: v_accvgpr_read_b32 v43, a47
+; CHECK-NEXT: v_accvgpr_read_b32 v13, a13
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a26
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
+; CHECK-NEXT: v_accvgpr_read_b32 v12, a12
+; CHECK-NEXT: v_accvgpr_read_b32 v15, a15
+; CHECK-NEXT: v_accvgpr_read_b32 v14, a14
+; CHECK-NEXT: v_cndmask_b32_e64 v9, v37, v9, s[16:17]
+; CHECK-NEXT: v_cndmask_b32_e64 v8, v36, v8, s[16:17]
+; CHECK-NEXT: v_cndmask_b32_e64 v11, v39, v11, s[10:11]
+; CHECK-NEXT: v_cndmask_b32_e64 v10, v38, v10, s[10:11]
+; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[32:35]
+; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[4:7] offset:16
+; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[8:11] offset:32
; CHECK-NEXT: v_add_co_u32_e32 v4, vcc, 0x70, v0
+; CHECK-NEXT: v_accvgpr_read_b32 v45, a49
+; CHECK-NEXT: v_accvgpr_read_b32 v46, a50
+; CHECK-NEXT: v_accvgpr_read_b32 v47, a51
+; CHECK-NEXT: v_accvgpr_read_b32 v50, a54
+; CHECK-NEXT: v_accvgpr_read_b32 v51, a55
+; CHECK-NEXT: v_accvgpr_read_b32 v52, a56
+; CHECK-NEXT: v_accvgpr_read_b32 v53, a57
+; CHECK-NEXT: v_accvgpr_read_b32 v54, a58
+; CHECK-NEXT: v_accvgpr_read_b32 v55, a59
+; CHECK-NEXT: v_accvgpr_read_b32 v25, a25
+; CHECK-NEXT: v_accvgpr_read_b32 v24, a24
+; CHECK-NEXT: v_accvgpr_read_b32 v27, a27
+; CHECK-NEXT: v_accvgpr_read_b32 v17, a17
+; CHECK-NEXT: v_accvgpr_read_b32 v22, a22
+; CHECK-NEXT: v_accvgpr_read_b32 v23, a23
+; CHECK-NEXT: v_accvgpr_read_b32 v26, a26
+; CHECK-NEXT: v_accvgpr_read_b32 v16, a16
+; CHECK-NEXT: v_accvgpr_read_b32 v19, a19
+; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
+; CHECK-NEXT: v_cndmask_b32_e64 v13, v41, v13, s[20:21]
+; CHECK-NEXT: v_cndmask_b32_e64 v12, v40, v12, s[20:21]
+; CHECK-NEXT: v_cndmask_b32_e64 v15, v43, v15, s[14:15]
+; CHECK-NEXT: v_cndmask_b32_e64 v14, v42, v14, s[14:15]
; CHECK-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; CHECK-NEXT: v_accvgpr_read_b32 v44, a46
-; CHECK-NEXT: v_accvgpr_read_b32 v45, a47
-; CHECK-NEXT: v_accvgpr_read_b32 v46, a48
-; CHECK-NEXT: v_accvgpr_read_b32 v47, a49
-; CHECK-NEXT: v_accvgpr_read_b32 v56, a58
-; CHECK-NEXT: v_accvgpr_read_b32 v57, a59
-; CHECK-NEXT: v_accvgpr_read_b32 v58, a60
-; CHECK-NEXT: v_accvgpr_read_b32 v60, a62
-; CHECK-NEXT: v_accvgpr_read_b32 v61, a63
-; CHECK-NEXT: v_accvgpr_read_b32 v32, a2
-; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
-; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[40:43] offset:64
-; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[52:55] offset:32
-; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[48:51] offset:48
-; CHECK-NEXT: flat_store_dwordx4 v[4:5], v[36:39]
+; CHECK-NEXT: v_accvgpr_read_b32 v57, a27
+; CHECK-NEXT: v_accvgpr_read_b32 v56, a26
+; CHECK-NEXT: v_cndmask_b32_e64 v25, v53, v25, s[42:43]
+; CHECK-NEXT: v_cndmask_b32_e64 v24, v52, v24, s[42:43]
+; CHECK-NEXT: v_cndmask_b32_e64 v27, v55, v27, s[26:27]
+; CHECK-NEXT: v_cndmask_b32_e64 v26, v54, v26, s[26:27]
+; CHECK-NEXT: v_cndmask_b32_e64 v51, v51, v23, s[22:23]
+; CHECK-NEXT: v_cndmask_b32_e64 v50, v50, v22, s[22:23]
+; CHECK-NEXT: v_cndmask_b32_e64 v17, v45, v17, s[24:25]
+; CHECK-NEXT: v_cndmask_b32_e64 v16, v44, v16, s[24:25]
+; CHECK-NEXT: v_cndmask_b32_e64 v19, v47, v19, s[18:19]
+; CHECK-NEXT: v_cndmask_b32_e64 v18, v46, v18, s[18:19]
+; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[12:15]
+; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[16:19] offset:64
+; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[48:51] offset:32
+; CHECK-NEXT: flat_store_dwordx4 v[20:21], v[24:27] offset:48
+; CHECK-NEXT: flat_store_dwordx4 v[4:5], v[58:61]
; CHECK-NEXT: .LBB0_49: ; %UnifiedReturnBlock
; CHECK-NEXT: s_or_b64 exec, exec, s[56:57]
; CHECK-NEXT: buffer_load_dword a63, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
@@ -1659,39 +2068,38 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_dword a34, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword a33, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword a32, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:972 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:976 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:980 ; 4-byte Folded Reload
-; CHECK-NEXT: v_readlane_b32 s30, v63, 14
-; CHECK-NEXT: v_readlane_b32 s31, v63, 15
-; CHECK-NEXT: v_readlane_b32 s55, v63, 13
-; CHECK-NEXT: v_readlane_b32 s54, v63, 12
-; CHECK-NEXT: v_readlane_b32 s53, v63, 11
-; CHECK-NEXT: v_readlane_b32 s52, v63, 10
-; CHECK-NEXT: v_readlane_b32 s51, v63, 9
-; CHECK-NEXT: v_readlane_b32 s50, v63, 8
-; CHECK-NEXT: v_readlane_b32 s49, v63, 7
-; CHECK-NEXT: v_readlane_b32 s48, v63, 6
-; CHECK-NEXT: v_readlane_b32 s39, v63, 5
-; CHECK-NEXT: v_readlane_b32 s38, v63, 4
-; CHECK-NEXT: v_readlane_b32 s37, v63, 3
-; CHECK-NEXT: v_readlane_b32 s36, v63, 2
-; CHECK-NEXT: v_readlane_b32 s35, v63, 1
-; CHECK-NEXT: v_readlane_b32 s34, v63, 0
+; CHECK-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:972 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:976 ; 4-byte Folded Reload
+; CHECK-NEXT: v_readlane_b32 s30, v62, 14
+; CHECK-NEXT: v_readlane_b32 s31, v62, 15
+; CHECK-NEXT: v_readlane_b32 s55, v62, 13
+; CHECK-NEXT: v_readlane_b32 s54, v62, 12
+; CHECK-NEXT: v_readlane_b32 s53, v62, 11
+; CHECK-NEXT: v_readlane_b32 s52, v62, 10
+; CHECK-NEXT: v_readlane_b32 s51, v62, 9
+; CHECK-NEXT: v_readlane_b32 s50, v62, 8
+; CHECK-NEXT: v_readlane_b32 s49, v62, 7
+; CHECK-NEXT: v_readlane_b32 s48, v62, 6
+; CHECK-NEXT: v_readlane_b32 s39, v62, 5
+; CHECK-NEXT: v_readlane_b32 s38, v62, 4
+; CHECK-NEXT: v_readlane_b32 s37, v62, 3
+; CHECK-NEXT: v_readlane_b32 s36, v62, 2
+; CHECK-NEXT: v_readlane_b32 s35, v62, 1
+; CHECK-NEXT: v_readlane_b32 s34, v62, 0
; CHECK-NEXT: s_or_saveexec_b64 s[4:5], -1
-; CHECK-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:1632 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:2452 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
index eee29e20f96b1..bafc4899ab782 100644
--- a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
@@ -144,6 +144,7 @@ define amdgpu_kernel void @local_store_i55(ptr addrspace(3) %ptr, i55 %arg) #0 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
index 4c6b0201f7b78..3b2122f9a288b 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
@@ -35,17 +35,29 @@ define half @v_constained_fadd_f16_fpexcept_strict(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fadd_f16_fpexcept_strict:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fadd_f16_fpexcept_strict:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fadd_f16_fpexcept_strict:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call half @llvm.experimental.constrained.fadd.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret half %val
}
@@ -67,17 +79,29 @@ define half @v_constained_fadd_f16_fpexcept_ignore(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fadd_f16_fpexcept_ignore:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fadd_f16_fpexcept_ignore:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fadd_f16_fpexcept_ignore:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call half @llvm.experimental.constrained.fadd.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret half %val
}
@@ -99,17 +123,29 @@ define half @v_constained_fadd_f16_fpexcept_maytrap(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fadd_f16_fpexcept_maytrap:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call half @llvm.experimental.constrained.fadd.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
ret half %val
}
@@ -310,6 +346,7 @@ define <3 x half> @v_constained_fadd_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fadd_v3f16_fpexcept_strict:
@@ -335,6 +372,7 @@ define <3 x half> @v_constained_fadd_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_pk_add_f16 v0, v0, v2
; GFX12-SDAG-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fadd_v3f16_fpexcept_strict:
@@ -501,6 +539,7 @@ define amdgpu_ps half @s_constained_fadd_f16_fpexcept_strict(half inreg %x, half
; GFX11-GISEL-TRUE16-LABEL: s_constained_fadd_f16_fpexcept_strict:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e64 v0.l, s2, s3
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-FAKE16-LABEL: s_constained_fadd_f16_fpexcept_strict:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
index f695526737311..5f1958e5d5176 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
@@ -100,6 +100,7 @@ define <3 x half> @v_constained_fma_v3f16_fpexcept_strict(<3 x half> %x, <3 x ha
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v5.l, v1.l, v3.l
; GFX11-TRUE16-NEXT: v_pk_fma_f16 v0, v0, v2, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
index dbe7530c0334c..3096f5e6e82f1 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
@@ -47,6 +47,7 @@ define half @v_constained_fmul_f16_fpexcept_strict(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_constained_fmul_f16_fpexcept_strict:
@@ -55,15 +56,26 @@ define half @v_constained_fmul_f16_fpexcept_strict(half %x, half %y) #0 {
; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fmul_f16_fpexcept_strict:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fmul_f16_fpexcept_strict:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fmul_f16_fpexcept_strict:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX1-GISEL-TRUE16-LABEL: v_constained_fmul_f16_fpexcept_strict:
; GFX1-GISEL-TRUE16: ; %bb.0:
; GFX1-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -107,6 +119,7 @@ define half @v_constained_fmul_f16_fpexcept_ignore(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_constained_fmul_f16_fpexcept_ignore:
@@ -115,15 +128,26 @@ define half @v_constained_fmul_f16_fpexcept_ignore(half %x, half %y) #0 {
; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fmul_f16_fpexcept_ignore:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fmul_f16_fpexcept_ignore:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fmul_f16_fpexcept_ignore:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX1-GISEL-TRUE16-LABEL: v_constained_fmul_f16_fpexcept_ignore:
; GFX1-GISEL-TRUE16: ; %bb.0:
; GFX1-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -167,6 +191,7 @@ define half @v_constained_fmul_f16_fpexcept_maytrap(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_constained_fmul_f16_fpexcept_maytrap:
@@ -175,15 +200,26 @@ define half @v_constained_fmul_f16_fpexcept_maytrap(half %x, half %y) #0 {
; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fmul_f16_fpexcept_maytrap:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fmul_f16_fpexcept_maytrap:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fmul_f16_fpexcept_maytrap:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX1-GISEL-TRUE16-LABEL: v_constained_fmul_f16_fpexcept_maytrap:
; GFX1-GISEL-TRUE16: ; %bb.0:
; GFX1-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -376,6 +412,7 @@ define <3 x half> @v_constained_fmul_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
@@ -401,6 +438,7 @@ define <3 x half> @v_constained_fmul_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX12-SDAG-NEXT: v_mul_f16_e32 v1.l, v1.l, v3.l
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fmul_v3f16_fpexcept_strict:
@@ -573,6 +611,7 @@ define amdgpu_ps half @s_constained_fmul_f16_fpexcept_strict(half inreg %x, half
; GFX11-GISEL-TRUE16-LABEL: s_constained_fmul_f16_fpexcept_strict:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e64 v0.l, s2, s3
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-FAKE16-LABEL: s_constained_fmul_f16_fpexcept_strict:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll b/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
index 87b41815e36d5..c41826daa3d3d 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
@@ -142,6 +142,7 @@ define <3 x half> @v_constrained_fptrunc_v3f32_to_v3f16_fpexcept_strict(<3 x flo
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.h, v1
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v0
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
index c7da9b388442b..486b6372b5ebb 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
@@ -47,6 +47,7 @@ define half @v_constained_fsub_f16_fpexcept_strict(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_constained_fsub_f16_fpexcept_strict:
@@ -55,15 +56,26 @@ define half @v_constained_fsub_f16_fpexcept_strict(half %x, half %y) #0 {
; GFX11-GISEL-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fsub_f16_fpexcept_strict:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fsub_f16_fpexcept_strict:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fsub_f16_fpexcept_strict:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call half @llvm.experimental.constrained.fsub.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret half %val
}
@@ -97,6 +109,7 @@ define half @v_constained_fsub_f16_fpexcept_ignore(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_constained_fsub_f16_fpexcept_ignore:
@@ -105,15 +118,26 @@ define half @v_constained_fsub_f16_fpexcept_ignore(half %x, half %y) #0 {
; GFX11-GISEL-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fsub_f16_fpexcept_ignore:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fsub_f16_fpexcept_ignore:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fsub_f16_fpexcept_ignore:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call half @llvm.experimental.constrained.fsub.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
ret half %val
}
@@ -147,6 +171,7 @@ define half @v_constained_fsub_f16_fpexcept_maytrap(half %x, half %y) #0 {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_constained_fsub_f16_fpexcept_maytrap:
@@ -155,15 +180,26 @@ define half @v_constained_fsub_f16_fpexcept_maytrap(half %x, half %y) #0 {
; GFX11-GISEL-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_constained_fsub_f16_fpexcept_maytrap:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: v_constained_fsub_f16_fpexcept_maytrap:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: v_constained_fsub_f16_fpexcept_maytrap:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%val = call half @llvm.experimental.constrained.fsub.f16(half %x, half %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
ret half %val
}
@@ -554,6 +590,7 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
@@ -572,6 +609,7 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
@@ -593,6 +631,7 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v0.h, v2.h
; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
; GFX12-SDAG-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
+; GFX12-SDAG-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
@@ -604,6 +643,7 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_pk_add_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX12-GISEL-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
+; GFX12-GISEL-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX10PLUS-SDAG-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
; GFX10PLUS-SDAG: ; %bb.0:
@@ -806,6 +846,7 @@ define amdgpu_ps half @s_constained_fsub_f16_fpexcept_strict(half inreg %x, half
; GFX11-GISEL-TRUE16-LABEL: s_constained_fsub_f16_fpexcept_strict:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e64 v0.l, s2, s3
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-FAKE16-LABEL: s_constained_fsub_f16_fpexcept_strict:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
index 44715b4e9b2a9..28ca880e9da45 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
@@ -78,6 +78,7 @@ define half @test_ldexp_f16_i32(ptr addrspace(1) %out, half %a, i32 %b) #0 {
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v3, v0
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -243,6 +244,7 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a,
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, v4, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, v5, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v4, v6, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
@@ -303,6 +305,7 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a,
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v4, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v4, 0xffff8000, v5, v0
; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v5, 0xffff8000, v6, v0
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v4.l
@@ -538,6 +541,7 @@ define amdgpu_ps half @s_test_ldexp_f16_i32(half inreg %a, i32 inreg %b) #0 {
; GFX11-GISEL-TRUE16-LABEL: s_test_ldexp_f16_i32:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_max_i32 s1, s1, 0xffff8000
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-TRUE16-NEXT: s_min_i32 s1, s1, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, s0, s1
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
index 4621be5cab450..861c72abd972e 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
@@ -21,11 +21,14 @@ define amdgpu_kernel void @foobar(float %a0, float %a1, ptr addrspace(1) %out) #
; CHECK-NEXT: v_mov_b32_e32 v3, s7
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
; CHECK-NEXT: ; %bb.1: ; %ift
-; CHECK-NEXT: s_mov_b32 s4, s5
-; CHECK-NEXT: v_mov_b32_e32 v0, s4
-; CHECK-NEXT: v_mov_b32_e32 v1, s5
-; CHECK-NEXT: v_mov_b32_e32 v2, s6
-; CHECK-NEXT: v_mov_b32_e32 v3, s7
+; CHECK-NEXT: s_mov_b32 s8, s5
+; CHECK-NEXT: ; implicit-def: $sgpr9
+; CHECK-NEXT: ; implicit-def: $sgpr10
+; CHECK-NEXT: ; implicit-def: $sgpr11
+; CHECK-NEXT: v_mov_b32_e32 v0, s8
+; CHECK-NEXT: v_mov_b32_e32 v1, s9
+; CHECK-NEXT: v_mov_b32_e32 v2, s10
+; CHECK-NEXT: v_mov_b32_e32 v3, s11
; CHECK-NEXT: ; %bb.2: ; %ife
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
diff --git a/llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll b/llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll
index 1ea2a1884d924..7aa055bce367a 100644
--- a/llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll
+++ b/llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll
@@ -8,6 +8,8 @@ define i32 @mov16_bfi_fold_regression(half %arg, i32 %arg1) {
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_mov_b16_e32 v2.l, 0x3c00
+; CHECK-NEXT: ; implicit-def: $vgpr0_hi16
+; CHECK-NEXT: ; implicit-def: $vgpr2_hi16
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; CHECK-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
index d575be5cfd82c..7e73f34a6a92b 100644
--- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck -check-prefix=CHECK %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=liveintervals,twoaddressinstruction -o - %s | FileCheck -check-prefix=LIS %s
@@ -10,17 +11,18 @@ noPhis: true
body: |
bb.0:
+
+
; CHECK-LABEL: name: regsequence-undef-subreg-use
- ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
- ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
- ; CHECK-NEXT: [[DEF:%[0-9]+]].sub1:sreg_64 = COPY undef [[UND:%[0-9]+]]:sgpr_32
- ; CHECK-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[DEF]].sub1
-
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:sreg_64 = COPY [[S_MOV_B32_]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:sreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[COPY]].sub1, implicit $exec
+ ;
; LIS-LABEL: name: regsequence-undef-subreg-use
- ; LIS: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
- ; LIS-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
- ; LIS-NEXT: [[OTH:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[DEF]].sub1
-
+ ; LIS: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; LIS-NEXT: dead undef [[COPY:%[0-9]+]].sub0:sreg_64 = COPY [[S_MOV_B32_]]
+ ; LIS-NEXT: dead [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub1, implicit $exec
%0:sgpr_32 = S_MOV_B32 0, implicit $exec
%1:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
@@ -33,14 +35,15 @@ noPhis: true
body: |
bb.0:
+
+
; CHECK-LABEL: name: regsequence-undef-subreg-without-use
- ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
- ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
-
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:sreg_64 = COPY [[S_MOV_B32_]]
+ ;
; LIS-LABEL: name: regsequence-undef-subreg-without-use
- ; LIS: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
- ; LIS-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
-
+ ; LIS: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; LIS-NEXT: dead undef [[COPY:%[0-9]+]].sub0:sreg_64 = COPY [[S_MOV_B32_]]
%0:sgpr_32 = S_MOV_B32 0, implicit $exec
%1:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
@@ -52,16 +55,18 @@ noPhis: true
body: |
bb.0:
+
+
; CHECK-LABEL: name: regsequence-undef-subreg-full-reg-use
- ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
- ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
- ; CHECK-NEXT: [[OTH:%[0-9]+]]:vreg_64 = COPY [[DEF]], implicit $exec
-
+ ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:sreg_64 = COPY [[S_MOV_B32_]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:sreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]], implicit $exec
+ ;
; LIS-LABEL: name: regsequence-undef-subreg-full-reg-use
- ; LIS: [[COPY:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
- ; LIS-NEXT: undef [[DEF:%[0-9]+]].sub0:sreg_64 = COPY [[COPY]]
- ; LIS-NEXT: [[OTH:%[0-9]+]]:vreg_64 = COPY [[DEF]], implicit $exec
-
+ ; LIS: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0, implicit $exec
+ ; LIS-NEXT: undef [[COPY:%[0-9]+]].sub0:sreg_64 = COPY [[S_MOV_B32_]]
+ ; LIS-NEXT: dead [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]], implicit $exec
%0:sgpr_32 = S_MOV_B32 0, implicit $exec
%1:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, undef %2:sgpr_32, %subreg.sub1
diff --git a/llvm/test/CodeGen/AMDGPU/uaddo.ll b/llvm/test/CodeGen/AMDGPU/uaddo.ll
index d9a88b2ba2867..b470e7c1ed684 100644
--- a/llvm/test/CodeGen/AMDGPU/uaddo.ll
+++ b/llvm/test/CodeGen/AMDGPU/uaddo.ll
@@ -721,6 +721,7 @@ define amdgpu_kernel void @v_uaddo_i16(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX11-NEXT: global_load_u16 v2, v0, s[6:7]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_add_nc_u32_e32 v2, v1, v2
+; GFX11-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v2
diff --git a/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll b/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
index 485d7d3e75b62..3847eb1169546 100644
--- a/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
+++ b/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
@@ -103,6 +103,9 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
; CHECK-NEXT: ; %bb.6: ; %sw.bb.i.i.i.i
; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: ; implicit-def: $vgpr1
+; CHECK-NEXT: ; implicit-def: $vgpr2
+; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: ; %bb.7: ; %Flow7
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: v_mov_b32_e32 v4, 0
@@ -120,6 +123,11 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; CHECK-NEXT: ; %bb.11: ; %sw.bb7.i.i.i3.i.i
+; CHECK-NEXT: ; implicit-def: $vgpr1
+; CHECK-NEXT: ; implicit-def: $vgpr2
+; CHECK-NEXT: ; implicit-def: $vgpr3
+; CHECK-NEXT: ; %bb.12: ; %bb.4
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], 0
; CHECK-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
index 237ff114b50ab..ac5e4837df85b 100644
--- a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
+++ b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
@@ -44,31 +44,6 @@ B30.2:
; FIXME: Extra undef subregister copy should be removed before
; overwritten with defined copy
define amdgpu_ps float @valley_partially_undef_copy() #0 {
-; CHECK-LABEL: valley_partially_undef_copy:
-; CHECK: ; %bb.0: ; %bb
-; CHECK-NEXT: s_mov_b32 s3, 0xf000
-; CHECK-NEXT: s_mov_b32 s2, -1
-; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
-; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
-; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000
-; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT: s_waitcnt expcnt(1)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
-; CHECK-NEXT: .LBB1_1: ; %bb9
-; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
-; CHECK-NEXT: s_cbranch_vccnz .LBB1_1
-; CHECK-NEXT: ; %bb.2: ; %bb11
-; CHECK-NEXT: s_mov_b32 s3, 0xf000
-; CHECK-NEXT: s_mov_b32 s2, -1
-; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0)
-; CHECK-NEXT: ; return to shader part epilog
bb:
%tmp = load volatile i32, ptr addrspace(1) poison, align 4
%tmp1 = load volatile i32, ptr addrspace(1) poison, align 4
@@ -94,27 +69,6 @@ bb11: ; preds = %bb9
; FIXME: Should be able to remove the undef copies
define amdgpu_kernel void @partially_undef_copy() #0 {
-; CHECK-LABEL: partially_undef_copy:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: ;;#ASMSTART
-; CHECK-NEXT: v_mov_b32_e32 v5, 5
-; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: ;;#ASMSTART
-; CHECK-NEXT: v_mov_b32_e32 v6, 6
-; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: v_mov_b32_e32 v0, v5
-; CHECK-NEXT: v_mov_b32_e32 v1, v6
-; CHECK-NEXT: v_mov_b32_e32 v2, v7
-; CHECK-NEXT: v_mov_b32_e32 v3, v8
-; CHECK-NEXT: v_mov_b32_e32 v0, v6
-; CHECK-NEXT: s_mov_b32 s3, 0xf000
-; CHECK-NEXT: s_mov_b32 s2, -1
-; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: ;;#ASMSTART
-; CHECK-NEXT: v_nop
-; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: s_endpgm
%tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"()
%tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"()
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll b/llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
index d3f13893d6851..e45f3f94131f2 100644
--- a/llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
+++ b/llvm/test/CodeGen/AMDGPU/uniform-vgpr-to-sgpr-return.ll
@@ -109,6 +109,7 @@ define amdgpu_ps i16 @uniform_v_to_s_i16(half inreg %a, half inreg %b) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, s0, s1
; GFX11-TRUE16-NEXT: v_max_f16_e64 v0.l, s0, s1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/usubo.ll b/llvm/test/CodeGen/AMDGPU/usubo.ll
index 9286095352fe2..5f1298e545641 100644
--- a/llvm/test/CodeGen/AMDGPU/usubo.ll
+++ b/llvm/test/CodeGen/AMDGPU/usubo.ll
@@ -720,6 +720,7 @@ define amdgpu_kernel void @v_usubo_i16(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX11-NEXT: global_load_u16 v2, v0, s[6:7]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_sub_nc_u32_e32 v2, v1, v2
+; GFX11-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v2
diff --git a/llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll b/llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
index 4d6ff1083492a..f3b8f2761b65c 100644
--- a/llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll
@@ -30,6 +30,7 @@ define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i3
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-TRUE16-NEXT: v_ashr_pk_i8_i32 v0.l, s0, s1, v0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
; GFX1250-TRUE16-NEXT: s_endpgm
;
@@ -59,6 +60,7 @@ define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i3
; GFX1300-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1300-TRUE16-NEXT: v_ashr_pk_i8_i32 v0.l, s0, s1, v0
+; GFX1300-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1300-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GFX1300-TRUE16-NEXT: s_endpgm
;
@@ -115,6 +117,7 @@ define amdgpu_kernel void @v_ashr_pk_u8_i32(ptr addrspace(1) %out, i32 %src0, i3
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-TRUE16-NEXT: v_ashr_pk_u8_i32 v0.l, s0, s1, v0
+; GFX1250-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
; GFX1250-TRUE16-NEXT: s_endpgm
;
@@ -144,6 +147,7 @@ define amdgpu_kernel void @v_ashr_pk_u8_i32(ptr addrspace(1) %out, i32 %src0, i3
; GFX1300-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1300-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1300-TRUE16-NEXT: v_ashr_pk_u8_i32 v0.l, s0, s1, v0
+; GFX1300-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1300-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
; GFX1300-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/v_pack.ll b/llvm/test/CodeGen/AMDGPU/v_pack.ll
index 8b91e4b21eb95..15d44737e193a 100644
--- a/llvm/test/CodeGen/AMDGPU/v_pack.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_pack.ll
@@ -357,6 +357,8 @@ define amdgpu_kernel void @fptrunc(
; GFX11-GISEL-REAL16-LABEL: fptrunc:
; GFX11-GISEL-REAL16: ; %bb.0:
; GFX11-GISEL-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-REAL16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-GISEL-REAL16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-REAL16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-REAL16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX11-GISEL-REAL16-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 185f0bb0aa421..8c612d91d07ec 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -1015,6 +1015,7 @@ define i16 @basic_smax_smin_bit_or(i16 %src0, i16 %src1) {
; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GISEL-GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-FAKE16-LABEL: basic_smax_smin_bit_or:
@@ -1039,6 +1040,7 @@ define i16 @basic_smax_smin_bit_or(i16 %src0, i16 %src1) {
; GISEL-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GISEL-GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: basic_smax_smin_bit_or:
@@ -1157,6 +1159,7 @@ define i16 @basic_umax_umin_bit_or(i16 %src0, i16 %src1) {
; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GISEL-GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-FAKE16-LABEL: basic_umax_umin_bit_or:
@@ -1181,6 +1184,7 @@ define i16 @basic_umax_umin_bit_or(i16 %src0, i16 %src1) {
; GISEL-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GISEL-GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: basic_umax_umin_bit_or:
@@ -1313,6 +1317,7 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GISEL-GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-FAKE16-LABEL: basic_smax_smin_vec_cast:
@@ -1337,6 +1342,7 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
; GISEL-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GISEL-GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: basic_smax_smin_vec_cast:
@@ -1460,6 +1466,7 @@ define i16 @basic_smax_smin_bit_shl(i16 %src0, i16 %src1) {
; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GISEL-GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-FAKE16-LABEL: basic_smax_smin_bit_shl:
@@ -1484,6 +1491,7 @@ define i16 @basic_smax_smin_bit_shl(i16 %src0, i16 %src1) {
; GISEL-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GISEL-GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: basic_smax_smin_bit_shl:
@@ -1621,6 +1629,7 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-FAKE16-LABEL: basic_smax_smin_vec_input:
@@ -1654,6 +1663,7 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
; GISEL-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GISEL-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX12-FAKE16-LABEL: basic_smax_smin_vec_input:
@@ -1788,6 +1798,7 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
; GISEL-GFX11-TRUE16-NEXT: v_pk_max_i16 v0, 0, v0
; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX11-TRUE16-NEXT: v_pk_min_i16 v1, 0xff00ff, v0
+; GISEL-GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
@@ -1818,6 +1829,7 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
; GISEL-GFX12-TRUE16-NEXT: v_pk_max_i16 v0, 0, v0
; GISEL-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX12-TRUE16-NEXT: v_pk_min_i16 v1, 0xff00ff, v0
+; GISEL-GFX12-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GISEL-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
; GISEL-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-GFX12-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
index c52aa7980b55b..57140c49a042b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
@@ -57,6 +57,7 @@ define i8 @test_vector_reduce_add_v2i8(<2 x i8> %v) {
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_add_v2i8:
@@ -93,6 +94,7 @@ define i8 @test_vector_reduce_add_v2i8(<2 x i8> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_add_v2i8:
@@ -186,6 +188,7 @@ define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -230,6 +233,7 @@ define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -371,6 +375,7 @@ define i8 @test_vector_reduce_add_v4i8(<4 x i8> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.h, v1.l, v3.l
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -435,6 +440,7 @@ define i8 @test_vector_reduce_add_v4i8(<4 x i8> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.h, v1.l, v3.l
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -624,6 +630,7 @@ define i8 @test_vector_reduce_add_v8i8(<8 x i8> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.h, v0.h, v1.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -708,6 +715,7 @@ define i8 @test_vector_reduce_add_v8i8(<8 x i8> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.h, v0.h, v1.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -992,6 +1000,7 @@ define i8 @test_vector_reduce_add_v16i8(<16 x i8> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.h, v0.h, v1.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1112,6 +1121,7 @@ define i8 @test_vector_reduce_add_v16i8(<16 x i8> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.h, v0.h, v1.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: v_bfe_u32 v0, v0, 0, 8
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1224,6 +1234,7 @@ define i16 @test_vector_reduce_add_v2i16(<2 x i16> %v) {
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1266,6 +1277,7 @@ define i16 @test_vector_reduce_add_v2i16(<2 x i16> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1363,6 +1375,7 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1409,6 +1422,7 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1529,6 +1543,7 @@ define i16 @test_vector_reduce_add_v4i16(<4 x i16> %v) {
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
@@ -1576,6 +1591,7 @@ define i16 @test_vector_reduce_add_v4i16(<4 x i16> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
@@ -1735,6 +1751,7 @@ define i16 @test_vector_reduce_add_v8i16(<8 x i16> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v1, v1, v3
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
@@ -1793,6 +1810,7 @@ define i16 @test_vector_reduce_add_v8i16(<8 x i16> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v1, v1, v3
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
@@ -2026,6 +2044,7 @@ define i16 @test_vector_reduce_add_v16i16(<16 x i16> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v1, v1, v3
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
@@ -2104,6 +2123,7 @@ define i16 @test_vector_reduce_add_v16i16(<16 x i16> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v1, v1, v3
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
index 924851b5bfdac..aff858fe34f4b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
@@ -1004,6 +1004,7 @@ define i16 @test_vector_reduce_and_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, v0, v1
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1032,6 +1033,7 @@ define i16 @test_vector_reduce_and_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
index b3aed22579a61..ac0c41b5fc644 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
@@ -88,6 +88,7 @@ define half @test_vector_reduce_fadd_v2half(half %sp, <2 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -135,6 +136,7 @@ define half @test_vector_reduce_fadd_v2half(half %sp, <2 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -240,6 +242,7 @@ define half @test_vector_reduce_fadd_v3half(half %sp, <3 x half> %v) {
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
@@ -290,6 +293,7 @@ define half @test_vector_reduce_fadd_v3half(half %sp, <3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
@@ -416,6 +420,7 @@ define half @test_vector_reduce_fadd_v4half(half %sp, <4 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -478,6 +483,7 @@ define half @test_vector_reduce_fadd_v4half(half %sp, <4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -672,6 +678,7 @@ define half @test_vector_reduce_fadd_v8half(half %sp, <8 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -764,6 +771,7 @@ define half @test_vector_reduce_fadd_v8half(half %sp, <8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -1098,6 +1106,7 @@ define half @test_vector_reduce_fadd_v16half(half %sp, <16 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -1250,6 +1259,7 @@ define half @test_vector_reduce_fadd_v16half(half %sp, <16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index fe85aa746f225..78d61ab1bfedc 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -115,6 +115,7 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
@@ -153,6 +154,7 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
@@ -203,6 +205,7 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
@@ -331,6 +334,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -376,6 +380,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -433,6 +438,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -591,6 +597,7 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.h
; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -640,6 +647,7 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -701,6 +709,7 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.h
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -955,6 +964,7 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.h, v1.h, v2.l, v2.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
@@ -1031,6 +1041,7 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v1.h, v2.l, v2.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
@@ -1119,6 +1130,7 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.h, v1.h, v2.l, v2.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
@@ -1556,6 +1568,7 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v3.l, v3.h
; GFX11-GISEL-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1677,6 +1690,7 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v3.l, v3.h
; GFX1170-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1810,6 +1824,7 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v3.l, v3.h
; GFX12-GISEL-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index ba0d1686155c4..78362ffd71af4 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -115,6 +115,7 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
@@ -153,6 +154,7 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
@@ -203,6 +205,7 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
@@ -331,6 +334,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_max_f16_e32 v1.l, v1.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -376,6 +380,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -433,6 +438,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v1.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -591,6 +597,7 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v1.l, v1.h
; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -640,6 +647,7 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -701,6 +709,7 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v1.l, v1.h
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -955,6 +964,7 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.h, v1.h, v2.l, v2.h
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
@@ -1031,6 +1041,7 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v1.h, v2.l, v2.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
@@ -1119,6 +1130,7 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.h, v1.h, v2.l, v2.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
@@ -1556,6 +1568,7 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_min_f16_e32 v1.l, v3.l, v3.h
; GFX11-GISEL-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1677,6 +1690,7 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v3.l, v3.h
; GFX1170-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1810,6 +1824,7 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v3.l, v3.h
; GFX12-GISEL-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 2d9dc5bd56f24..6cf28f043e74a 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -93,6 +93,7 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
@@ -133,6 +134,7 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
@@ -261,6 +263,7 @@ define half @test_vector_reduce_fminimum_v3half(<3 x half> %v) {
; GFX1170-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX1170-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v3half:
@@ -309,6 +312,7 @@ define half @test_vector_reduce_fminimum_v3half(<3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v3half:
@@ -462,6 +466,7 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v1.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
@@ -509,6 +514,7 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v1.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
@@ -766,6 +772,7 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.h, v2.l, v2.h, v1.h
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
@@ -829,6 +836,7 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.h, v2.l, v2.h, v1.h
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
@@ -1311,6 +1319,7 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v3.l, v3.h
; GFX1170-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1170-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX1170-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
@@ -1398,6 +1407,7 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, v3.l, v3.h
; GFX12-GISEL-TRUE16-NEXT: v_minimum3_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
index 3a4c643f2e706..48ec7c398e029 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
@@ -88,6 +88,7 @@ define half @test_vector_reduce_fmul_v2half(half %sp, <2 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -135,6 +136,7 @@ define half @test_vector_reduce_fmul_v2half(half %sp, <2 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -240,6 +242,7 @@ define half @test_vector_reduce_fmul_v3half(half %sp, <3 x half> %v) {
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
@@ -290,6 +293,7 @@ define half @test_vector_reduce_fmul_v3half(half %sp, <3 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
@@ -416,6 +420,7 @@ define half @test_vector_reduce_fmul_v4half(half %sp, <4 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -478,6 +483,7 @@ define half @test_vector_reduce_fmul_v4half(half %sp, <4 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -672,6 +678,7 @@ define half @test_vector_reduce_fmul_v8half(half %sp, <8 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -764,6 +771,7 @@ define half @test_vector_reduce_fmul_v8half(half %sp, <8 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -1098,6 +1106,7 @@ define half @test_vector_reduce_fmul_v16half(half %sp, <16 x half> %v) {
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
@@ -1250,6 +1259,7 @@ define half @test_vector_reduce_fmul_v16half(half %sp, <16 x half> %v) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX12-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
index 7c2f25fa78f28..f39d35da08655 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
@@ -1009,6 +1009,7 @@ define i16 @test_vector_reduce_mul_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1037,6 +1038,7 @@ define i16 @test_vector_reduce_mul_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1255,6 +1257,7 @@ define i16 @test_vector_reduce_mul_v4i16(<4 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
@@ -1286,6 +1289,7 @@ define i16 @test_vector_reduce_mul_v4i16(<4 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
@@ -1431,6 +1435,7 @@ define i16 @test_vector_reduce_mul_v8i16(<8 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
@@ -1471,6 +1476,7 @@ define i16 @test_vector_reduce_mul_v8i16(<8 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
@@ -1683,6 +1689,7 @@ define i16 @test_vector_reduce_mul_v16i16(<16 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
@@ -1738,6 +1745,7 @@ define i16 @test_vector_reduce_mul_v16i16(<16 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
@@ -2511,6 +2519,7 @@ define i64 @test_vector_reduce_mul_v2i64(<2 x i64> %v) {
; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, v1
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], s4, v4, v3, v[1:2]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr4
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v5, v2, v[3:4]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2533,6 +2542,7 @@ define i64 @test_vector_reduce_mul_v2i64(<2 x i64> %v) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v4, v5, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[7:8], null, v4, v3, v[1:2]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr8
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v6, v5, v[7:8]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2671,8 +2681,10 @@ define i64 @test_vector_reduce_mul_v3i64(<3 x i64> %v) {
; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, v1
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[8:9], s4, v0, v3, v[8:9]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], s4, v7, v4, 0
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr9
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v6, v2, v[8:9]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], s4, v7, v5, v[1:2]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr6
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v2, v4, v[5:6]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2699,11 +2711,13 @@ define i64 @test_vector_reduce_mul_v3i64(<3 x i64> %v) {
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v0, v3, v[8:9]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v7, v4, 0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr10
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v6, v2, v[9:10]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[11:12], null, v6, v2, v[9:10]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v7, v5, v[1:2]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr9
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v10, v4, v[8:9]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v11, v4, v[8:9]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_mul_v3i64:
@@ -2879,11 +2893,14 @@ define i64 @test_vector_reduce_mul_v4i64(<4 x i64> %v) {
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[11:12], s4, v0, v4, 0
; GFX10-GISEL-NEXT: v_mov_b32_e32 v8, v1
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v2, v7, v[10:11]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr2
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[12:13], s4, v0, v5, v[12:13]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr13
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v3, v6, v[1:2]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], s4, v11, v9, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], s4, v8, v4, v[12:13]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v11, v2, v[1:2]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr2
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v3, v9, v[1:2]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2915,13 +2932,16 @@ define i64 @test_vector_reduce_mul_v4i64(<4 x i64> %v) {
; GFX11-GISEL-NEXT: v_mov_b32_e32 v8, v1
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v2, v7, v[10:11]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[14:15], null, v0, v5, v[12:13]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr14
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[15:16], null, v0, v5, v[12:13]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[17:18], null, v3, v6, v[13:14]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v11, v9, 0
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr16
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v8, v4, v[15:16]
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[15:16], null, v3, v6, v[13:14]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v8, v4, v[14:15]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v11, v15, v[1:2]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v11, v17, v[1:2]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr4
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v5, v9, v[3:4]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3220,21 +3240,28 @@ define i64 @test_vector_reduce_mul_v8i64(<8 x i64> %v) {
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[20:21], s4, v4, v12, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[22:23], s4, v0, v8, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[26:27], s4, v6, v15, v[17:18]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[27:28], s4, v2, v11, v[19:20]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[24:25], s4, v18, v16, 0
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[28:29], s4, v4, v13, v[21:22]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[28:29], s4, v2, v11, v[19:20]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[30:31], s4, v4, v13, v[21:22]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr27
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr29
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr31
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[13:14], s4, v7, v14, v[26:27]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[14:15], s4, v0, v9, v[23:24]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v3, v10, v[27:28]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], s4, v5, v12, v[28:29]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v3, v10, v[28:29]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], s4, v5, v12, v[30:31]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[6:7], s4, v22, v20, 0
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr15
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[4:5], s4, v18, v13, v[25:26]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[8:9], s4, v1, v8, v[14:15]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr5
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], s4, v6, v24, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[9:10], s4, v22, v3, v[7:8]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v2, v16, v[4:5]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr10
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], s4, v8, v20, v[9:10]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v6, v2, v[1:2]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr2
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v3, v24, v[1:2]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3287,28 +3314,35 @@ define i64 @test_vector_reduce_mul_v8i64(<8 x i64> %v) {
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[22:23], null, v0, v8, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[26:27], null, v6, v15, v[17:18]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[27:28], null, v2, v11, v[19:20]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[28:29], null, v2, v11, v[19:20]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[24:25], null, v18, v16, 0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[28:29], null, v4, v13, v[21:22]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[29:30], null, v7, v14, v[26:27]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[30:31], null, v4, v13, v[21:22]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr27
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr29
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr31
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[32:33], null, v7, v14, v[26:27]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[26:27], null, v3, v10, v[28:29]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v0, v9, v[23:24]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[14:15], null, v3, v10, v[27:28]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v22, v20, 0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v5, v12, v[28:29]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v18, v29, v[25:26]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v1, v8, v[13:14]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v5, v12, v[30:31]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr14
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v18, v32, v[25:26]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v1, v8, v[13:14]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr4
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v6, v24, 0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v22, v2, v[7:8]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v14, v16, v[3:4]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v4, v20, v[8:9]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v6, v9, v[1:2]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v10, v24, v[3:4]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v22, v2, v[7:8]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr11
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[7:8], null, v26, v16, v[3:4]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v9, v20, v[10:11]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v6, v7, v[1:2]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v3, v24, v[4:5]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: test_vector_reduce_mul_v8i64:
@@ -3916,47 +3950,62 @@ define i64 @test_vector_reduce_mul_v16i64(<16 x i64> %v) {
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[33:34], s4, v6, v22, 0
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[36:37], s4, v14, v35, v[32:33]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[37:38], s4, v6, v23, v[34:35]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[38:39], s4, v6, v23, v[34:35]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr37
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[34:35], s4, v33, v31, 0
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr39
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[14:15], s4, v15, v30, v[36:37]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[36:37], s4, v7, v22, v[37:38]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[36:37], s4, v7, v22, v[38:39]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[6:7], s4, v2, v18, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[22:23], s4, v10, v26, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[32:33], s4, v33, v14, v[35:36]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[14:15], s4, v4, v20, 0
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr33
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[48:49], s4, v10, v27, v[23:24]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr49
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[35:36], s4, v36, v31, v[32:33]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[36:37], s4, v2, v19, v[7:8]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[30:31], s4, v8, v24, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[32:33], s4, v12, v28, 0
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[36:37], s4, v2, v19, v[7:8]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[37:38], s4, v4, v21, v[15:16]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[38:39], s4, v10, v27, v[23:24]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[7:8], s4, v8, v25, v[31:32]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[48:49], s4, v12, v29, v[33:34]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[38:39], s4, v4, v21, v[15:16]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr37
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr39
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[10:11], s4, v11, v26, v[48:49]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[18:19], s4, v3, v18, v[36:37]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[19:20], s4, v5, v20, v[37:38]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v0, v16, 0
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[10:11], s4, v11, v26, v[38:39]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[7:8], s4, v8, v25, v[31:32]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[50:51], s4, v12, v29, v[33:34]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[19:20], s4, v5, v20, v[38:39]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[4:5], s4, v6, v22, 0
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr8
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr51
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[20:21], s4, v9, v24, v[7:8]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[11:12], s4, v13, v28, v[48:49]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[11:12], s4, v13, v28, v[50:51]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[7:8], s4, v14, v32, 0
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[12:13], s4, v0, v17, v[3:4]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[23:24], s4, v6, v10, v[5:6]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], s4, v2, v30, 0
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[13:14], s4, v14, v11, v[8:9]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[12:13], s4, v0, v17, v[3:4]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr13
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr24
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[14:15], s4, v14, v11, v[8:9]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[8:9], s4, v4, v34, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[10:11], s4, v5, v7, 0
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], s4, v1, v16, v[12:13]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[12:13], s4, v19, v32, v[13:14]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[12:13], s4, v18, v22, v[23:24]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v2, v20, v[6:7]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v18, v22, v[23:24]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr15
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr2
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[13:14], s4, v19, v32, v[14:15]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], s4, v4, v35, v[9:10]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[4:5], s4, v5, v12, v[11:12]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[13:14], s4, v0, v30, v[1:2]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[14:15], s4, v0, v30, v[1:2]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[0:1], s4, v10, v8, 0
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v2, v34, v[3:4]
-; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], s4, v13, v7, v[4:5]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[5:6], s4, v5, v13, v[11:12]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr6
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[2:3], s4, v12, v34, v[3:4]
+; GFX10-GISEL-NEXT: v_mad_u64_u32 v[3:4], s4, v14, v7, v[5:6]
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v10, v2, v[1:2]
+; GFX10-GISEL-NEXT: ; implicit-def: $vgpr2
; GFX10-GISEL-NEXT: v_mad_u64_u32 v[1:2], s4, v3, v8, v[1:2]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -4043,53 +4092,66 @@ define i64 @test_vector_reduce_mul_v16i64(<16 x i64> %v) {
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[33:34], null, v0, v16, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[35:36], null, v2, v18, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[37:38], null, v6, v22, 0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[48:49], null, v10, v26, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[50:51], null, v12, v28, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[52:53], null, v4, v20, 0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[48:49], null, v10, v26, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[64:65], null, v8, v24, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[68:69], null, v0, v17, v[34:35]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[69:70], null, v2, v19, v[36:37]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[66:67], null, v37, v31, 0
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[80:81], null, v12, v29, v[51:52]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr81
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[54:55], null, v14, v39, v[32:33]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[70:71], null, v6, v23, v[38:39]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[38:39], null, v10, v27, v[49:50]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[81:82], null, v15, v30, v[54:55]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[82:83], null, v8, v25, v[65:66]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[83:84], null, v7, v22, v[70:71]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr55
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr71
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr39
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[82:83], null, v15, v30, v[54:55]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[83:84], null, v8, v25, v[65:66]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[54:55], null, v4, v21, v[53:54]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[14:15], null, v35, v48, 0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[21:22], null, v11, v26, v[38:39]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[29:30], null, v52, v50, 0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v33, v64, 0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[85:86], null, v7, v22, v[70:71]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[21:22], null, v11, v26, v[38:39]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v13, v28, v[80:81]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[11:12], null, v37, v81, v[67:68]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[12:13], null, v3, v18, v[69:70]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[17:18], null, v9, v24, v[82:83]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v33, v64, 0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[11:12], null, v37, v82, v[67:68]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr70
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr84
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[22:23], null, v3, v18, v[69:70]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[17:18], null, v9, v24, v[83:84]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr55
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[2:3], null, v5, v20, v[54:55]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[18:19], null, v35, v21, v[15:16]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[3:4], null, v14, v66, 0
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[18:19], null, v35, v21, v[15:16]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[20:21], null, v52, v10, v[30:31]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[8:9], null, v6, v29, 0
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[19:20], null, v52, v10, v[30:31]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[20:21], null, v83, v31, v[11:12]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr12
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[23:24], null, v85, v31, v[11:12]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr69
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[10:11], null, v1, v16, v[68:69]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr19
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr21
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[11:12], null, v22, v48, v[18:19]
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[12:13], null, v2, v50, v[20:21]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v33, v17, v[7:8]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[15:16], null, v12, v48, v[18:19]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[11:12], null, v2, v50, v[19:20]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v14, v20, v[4:5]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[12:13], null, v6, v11, v[9:10]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[15:16], null, v14, v23, v[4:5]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr1
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr16
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[13:14], null, v6, v12, v[9:10]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[4:5], null, v10, v64, v[0:1]
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v15, v66, v[1:2]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[5:6], null, v11, v66, v[15:16]
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[0:1], null, v8, v3, 0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v4, v29, v[12:13]
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr14
+; GFX11-GISEL-NEXT: v_mad_u64_u32 v[6:7], null, v4, v29, v[13:14]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[9:10], null, v8, v5, v[1:2]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: ; implicit-def: $vgpr10
; GFX11-GISEL-NEXT: v_mad_u64_u32 v[1:2], null, v6, v3, v[9:10]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
index bf6babede48b5..2545299f129d2 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
@@ -1035,6 +1035,7 @@ define i16 @test_vector_reduce_or_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1063,6 +1064,7 @@ define i16 @test_vector_reduce_or_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index acfbc5c8be15a..bbba22b61129b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -64,6 +64,8 @@ define i8 @test_vector_reduce_smax_v2i8(<2 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v2i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
@@ -91,6 +93,8 @@ define i8 @test_vector_reduce_smax_v2i8(<2 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v2i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
@@ -207,11 +211,14 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -244,15 +251,18 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -438,9 +448,14 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v4i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -448,6 +463,7 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -502,6 +518,10 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v4i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
@@ -509,6 +529,7 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -516,6 +537,7 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -767,14 +789,22 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v8i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v8.l
; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l
@@ -784,6 +814,7 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v7, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
@@ -792,6 +823,7 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v5
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -866,18 +898,26 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v8i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v8.l
; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l
@@ -887,6 +927,7 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v7, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
@@ -895,6 +936,7 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v5
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -1252,25 +1294,41 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v16i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v4, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v9.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v17, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v4, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v15.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v13, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v3, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
@@ -1297,9 +1355,11 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.h, v2.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v12.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v7
; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v5.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.h, v0.h, v2.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8
@@ -1399,6 +1459,7 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v16i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
@@ -1407,21 +1468,36 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v4, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v9.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v17, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v4, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v15.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v13, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v3, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
@@ -1448,9 +1524,11 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.h, v2.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v12.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v7
; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v4.l
; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v5.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.h, v0.h, v2.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index a7edd4b759a99..4f63a8841be0e 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -64,6 +64,8 @@ define i8 @test_vector_reduce_smin_v2i8(<2 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v2i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
@@ -91,6 +93,8 @@ define i8 @test_vector_reduce_smin_v2i8(<2 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v2i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
@@ -207,11 +211,14 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -244,15 +251,18 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -438,9 +448,14 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v4i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -448,6 +463,7 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -502,6 +518,10 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v4i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
@@ -509,6 +529,7 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -516,6 +537,7 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v1, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -767,14 +789,22 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v8i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v8.l
; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l
@@ -784,6 +814,7 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v7, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
@@ -792,6 +823,7 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v5
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -866,18 +898,26 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v8i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v8.l
; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l
@@ -887,6 +927,7 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v7, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
@@ -895,6 +936,7 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v5
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -1252,25 +1294,41 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v16i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v4, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v9.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v17, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v4, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v15.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v13, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v3, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
@@ -1297,9 +1355,11 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.h, v2.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v12.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v7
; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v5.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.h, v0.h, v2.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8
@@ -1399,6 +1459,7 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
;
; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v16i8:
; GFX12-SDAG-TRUE16: ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_expcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
@@ -1407,21 +1468,36 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v4, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v9.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v17, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v4, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v15.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v13, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr13_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr5_hi16
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v13, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v3, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr9_hi16
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
@@ -1448,9 +1524,11 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.h, v2.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v12.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr7_hi16
; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v7
; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v4.l
; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v5.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.h, v0.h, v2.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
index ebb000198bb36..a8c8ba6d9e48e 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
@@ -981,6 +981,7 @@ define i16 @test_vector_reduce_xor_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1009,6 +1010,7 @@ define i16 @test_vector_reduce_xor_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll b/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
index 504554037c536..950ace891e073 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
@@ -1108,6 +1108,7 @@ define <3 x bfloat> @shuffle_v3bf16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
@@ -1507,6 +1508,7 @@ define <3 x half> @shuffle_v3f16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
diff --git a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
index 10c2162f5eadb..4a2ff87ae7da3 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
@@ -66,13 +66,22 @@ define <4 x half> @shuffle_v4f16_234u(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX10-NEXT: v_mov_b32_e32 v1, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: shuffle_v4f16_234u:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT: global_load_b64 v[1:2], v[2:3], off
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_234u:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v[2:3], off
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_234u:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT: global_load_b64 v[1:2], v[2:3], off
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x half>, ptr addrspace(1) %arg0
%val1 = load <4 x half>, ptr addrspace(1) %arg1
%shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 2, i32 3, i32 4, i32 poison>
@@ -213,6 +222,7 @@ define <4 x half> @shuffle_v4f16_3u6u(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -272,6 +282,7 @@ define <4 x half> @shuffle_v4f16_3uu7(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -392,6 +403,7 @@ define <4 x half> @shuffle_v4f16_357u(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4f16_357u:
@@ -3025,6 +3037,7 @@ define void @shuffle_v4i8_concat(ptr addrspace(1) %arg0, ptr addrspace(1) %arg1,
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_store_b32 v[4:5], v0, off
@@ -3356,13 +3369,22 @@ define <4 x bfloat> @shuffle_v4bf16_234u(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX10-NEXT: v_mov_b32_e32 v1, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: shuffle_v4bf16_234u:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT: global_load_b64 v[1:2], v[2:3], off
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_234u:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v[2:3], off
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_234u:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT: global_load_b64 v[1:2], v[2:3], off
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
%val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
%shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 2, i32 3, i32 4, i32 poison>
@@ -3503,6 +3525,7 @@ define <4 x bfloat> @shuffle_v4bf16_3u6u(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3562,6 +3585,7 @@ define <4 x bfloat> @shuffle_v4bf16_3uu7(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3682,6 +3706,7 @@ define <4 x bfloat> @shuffle_v4bf16_357u(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4bf16_357u:
diff --git a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
index 6c943da2f1dd7..fd57dd2ba12ae 100644
--- a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
+++ b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
@@ -266,13 +266,14 @@ bb:
}
define amdgpu_ps void @test_swmmac_f32_16x16x32_f16_negA(<8 x half> %A, <16 x half> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
-; GCN-LABEL: test_swmmac_f32_16x16x32_f16_negA:
-; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: v_swmmac_f32_16x16x32_f16 v[12:19], v[0:3], v[4:11], v20 neg_lo:[1,0,0] neg_hi:[1,0,0]
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: global_store_b128 v[21:22], v[16:19], off offset:16
-; GCN-NEXT: global_store_b128 v[21:22], v[12:15], off
-; GCN-NEXT: s_endpgm
+; GFX1170-LABEL: test_swmmac_f32_16x16x32_f16_negA:
+; GFX1170: ; %bb.0: ; %bb
+; GFX1170-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX1170-NEXT: v_swmmac_f32_16x16x32_f16 v[12:19], v[0:3], v[4:11], v20 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX1170-NEXT: s_clause 0x1
+; GFX1170-NEXT: global_store_b128 v[21:22], v[16:19], off offset:16
+; GFX1170-NEXT: global_store_b128 v[21:22], v[12:15], off
+; GFX1170-NEXT: s_endpgm
bb:
%fneg.A = fneg <8 x half> %A
%res = call <8 x float> @llvm.amdgcn.swmmac.f32.16x16x32.f16.v8f32.v8f16.v16f16.i16(<8 x half> %fneg.A, <16 x half> %B, <8 x float> %C, i16 %Index)
@@ -281,13 +282,14 @@ bb:
}
define amdgpu_ps void @test_swmmac_f32_16x16x32_f16_negB(<8 x half> %A, <16 x half> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
-; GCN-LABEL: test_swmmac_f32_16x16x32_f16_negB:
-; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: v_swmmac_f32_16x16x32_f16 v[12:19], v[0:3], v[4:11], v20 neg_lo:[0,1,0] neg_hi:[0,1,0]
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: global_store_b128 v[21:22], v[16:19], off offset:16
-; GCN-NEXT: global_store_b128 v[21:22], v[12:15], off
-; GCN-NEXT: s_endpgm
+; GFX1170-LABEL: test_swmmac_f32_16x16x32_f16_negB:
+; GFX1170: ; %bb.0: ; %bb
+; GFX1170-NEXT: ; implicit-def: $vgpr20_hi16
+; GFX1170-NEXT: v_swmmac_f32_16x16x32_f16 v[12:19], v[0:3], v[4:11], v20 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX1170-NEXT: s_clause 0x1
+; GFX1170-NEXT: global_store_b128 v[21:22], v[16:19], off offset:16
+; GFX1170-NEXT: global_store_b128 v[21:22], v[12:15], off
+; GFX1170-NEXT: s_endpgm
bb:
%fneg.B = fneg <16 x half> %B
%res = call <8 x float> @llvm.amdgcn.swmmac.f32.16x16x32.f16.v8f32.v8f16.v16f16.i16(<8 x half> %A, <16 x half> %fneg.B, <8 x float> %C, i16 %Index)
@@ -296,11 +298,12 @@ bb:
}
define amdgpu_ps void @test_swmmac_f16_16x16x32_f16_negA(<8 x half> %A, <16 x half> %B, <8 x half> %C, i16 %Index, ptr addrspace(1) %out) {
-; GCN-LABEL: test_swmmac_f16_16x16x32_f16_negA:
-; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: v_swmmac_f16_16x16x32_f16 v[12:15], v[0:3], v[4:11], v16 neg_lo:[1,0,0] neg_hi:[1,0,0]
-; GCN-NEXT: global_store_b128 v[17:18], v[12:15], off
-; GCN-NEXT: s_endpgm
+; GFX1170-LABEL: test_swmmac_f16_16x16x32_f16_negA:
+; GFX1170: ; %bb.0: ; %bb
+; GFX1170-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX1170-NEXT: v_swmmac_f16_16x16x32_f16 v[12:15], v[0:3], v[4:11], v16 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX1170-NEXT: global_store_b128 v[17:18], v[12:15], off
+; GFX1170-NEXT: s_endpgm
bb:
%fneg.A = fneg <8 x half> %A
%res = call <8 x half> @llvm.amdgcn.swmmac.f16.16x16x32.f16.v8f16.v8f16.v16f16.i16(<8 x half> %fneg.A, <16 x half> %B, <8 x half> %C, i16 %Index)
@@ -309,11 +312,12 @@ bb:
}
define amdgpu_ps void @test_swmmac_f16_16x16x32_f16_negB(<8 x half> %A, <16 x half> %B, <8 x half> %C, i16 %Index, ptr addrspace(1) %out) {
-; GCN-LABEL: test_swmmac_f16_16x16x32_f16_negB:
-; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: v_swmmac_f16_16x16x32_f16 v[12:15], v[0:3], v[4:11], v16 neg_lo:[0,1,0] neg_hi:[0,1,0]
-; GCN-NEXT: global_store_b128 v[17:18], v[12:15], off
-; GCN-NEXT: s_endpgm
+; GFX1170-LABEL: test_swmmac_f16_16x16x32_f16_negB:
+; GFX1170: ; %bb.0: ; %bb
+; GFX1170-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX1170-NEXT: v_swmmac_f16_16x16x32_f16 v[12:15], v[0:3], v[4:11], v16 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX1170-NEXT: global_store_b128 v[17:18], v[12:15], off
+; GFX1170-NEXT: s_endpgm
bb:
%fneg.B = fneg <16 x half> %B
%res = call <8 x half> @llvm.amdgcn.swmmac.f16.16x16x32.f16.v8f16.v8f16.v16f16.i16(<8 x half> %A, <16 x half> %fneg.B, <8 x half> %C, i16 %Index)
diff --git a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
index 9d8f26ea11cb8..adfea1a68227f 100644
--- a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
+++ b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
@@ -139,6 +139,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_zext_src0(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu8_zext_src0:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr14_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu8 v[6:13], v[0:1], v[2:5], v14 neg_lo:[1,0,0]
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16
@@ -153,6 +154,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_zext_src1(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu8_zext_src1:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr14_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu8 v[6:13], v[0:1], v[2:5], v14 neg_lo:[0,1,0]
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16
@@ -167,6 +169,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_clamp(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu8_clamp:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr14_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu8 v[6:13], v[0:1], v[2:5], v14 clamp
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16
@@ -183,6 +186,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_zext_src0(i32 %A, <2 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu4_zext_src0:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr11_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu4 v[3:10], v0, v[1:2], v11 neg_lo:[1,0,0]
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[12:13], v[7:10], off offset:16
@@ -197,6 +201,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_zext_src1(i32 %A, <2 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu4_zext_src1:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr11_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu4 v[3:10], v0, v[1:2], v11 neg_lo:[0,1,0]
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[12:13], v[7:10], off offset:16
@@ -211,6 +216,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_clamp(i32 %A, <2 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu4_clamp:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr11_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu4 v[3:10], v0, v[1:2], v11 clamp
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[12:13], v[7:10], off offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
index 0993c00c30415..f88a3e4eeee11 100644
--- a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
@@ -156,6 +156,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_f16(<8 x half> %A, <16 x half> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_f16:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr20_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_f16 v[12:19], v[0:3], v[4:11], v20
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[21:22], v[16:19], off offset:16
@@ -170,6 +171,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_bf16(<8 x i16> %A, <16 x i16> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_bf16:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr20_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_bf16 v[12:19], v[0:3], v[4:11], v20
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[21:22], v[16:19], off offset:16
@@ -184,6 +186,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x32_f16(<8 x half> %A, <16 x half> %B, <8 x half> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f16_16x16x32_f16:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr16_hi16
; GCN-NEXT: v_swmmac_f16_16x16x32_f16 v[12:15], v[0:3], v[4:11], v16
; GCN-NEXT: global_store_b128 v[17:18], v[12:15], off
; GCN-NEXT: s_endpgm
@@ -196,6 +199,7 @@ bb:
define amdgpu_ps void @test_swmmac_bf16_16x16x32_bf16(<8 x i16> %A, <16 x i16> %B, <8 x i16> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_bf16_16x16x32_bf16:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr16_hi16
; GCN-NEXT: v_swmmac_bf16_16x16x32_bf16 v[12:15], v[0:3], v[4:11], v16
; GCN-NEXT: global_store_b128 v[17:18], v[12:15], off
; GCN-NEXT: s_endpgm
@@ -208,6 +212,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr14_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu8 v[6:13], v[0:1], v[2:5], v14
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16
@@ -222,6 +227,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4(i32 %A, <2 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu4:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr11_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu4 v[3:10], v0, v[1:2], v11
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[12:13], v[7:10], off offset:16
@@ -250,6 +256,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_fp8_fp8(<2 x i32> %A, <4 x i32> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_fp8_fp8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr14_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_fp8_fp8 v[6:13], v[0:1], v[2:5], v14
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16
@@ -264,6 +271,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_fp8_bf8(<2 x i32> %A, <4 x i32> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_fp8_bf8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr14_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_fp8_bf8 v[6:13], v[0:1], v[2:5], v14
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16
@@ -278,6 +286,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_bf8_fp8(<2 x i32> %A, <4 x i32> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_bf8_fp8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr14_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_bf8_fp8 v[6:13], v[0:1], v[2:5], v14
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16
@@ -292,6 +301,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_bf8_bf8(<2 x i32> %A, <4 x i32> %B, <8 x float> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_bf8_bf8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr14_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_bf8_bf8 v[6:13], v[0:1], v[2:5], v14
; GCN-NEXT: s_clause 0x1
; GCN-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
index 1a2d59e969590..beab1020f8b5e 100644
--- a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
+++ b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
@@ -239,11 +239,31 @@ bb:
}
define amdgpu_ps void @test_swmmac_f32_16x16x32_f16_negA(<4 x half> %A, <8 x half> %B, <4 x float> %C, i16 %Index, ptr addrspace(1) %out) {
-; GCN-LABEL: test_swmmac_f32_16x16x32_f16_negA:
-; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[1,0,0] neg_hi:[1,0,0]
-; GCN-NEXT: global_store_b128 v[11:12], v[6:9], off
-; GCN-NEXT: s_endpgm
+; GFX1170-TRUE16-LABEL: test_swmmac_f32_16x16x32_f16_negA:
+; GFX1170-TRUE16: ; %bb.0: ; %bb
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX1170-TRUE16-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX1170-TRUE16-NEXT: global_store_b128 v[11:12], v[6:9], off
+; GFX1170-TRUE16-NEXT: s_endpgm
+;
+; GFX1170-FAKE16-LABEL: test_swmmac_f32_16x16x32_f16_negA:
+; GFX1170-FAKE16: ; %bb.0: ; %bb
+; GFX1170-FAKE16-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX1170-FAKE16-NEXT: global_store_b128 v[11:12], v[6:9], off
+; GFX1170-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_swmmac_f32_16x16x32_f16_negA:
+; GFX12-TRUE16: ; %bb.0: ; %bb
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX12-TRUE16-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX12-TRUE16-NEXT: global_store_b128 v[11:12], v[6:9], off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_swmmac_f32_16x16x32_f16_negA:
+; GFX12-FAKE16: ; %bb.0: ; %bb
+; GFX12-FAKE16-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX12-FAKE16-NEXT: global_store_b128 v[11:12], v[6:9], off
+; GFX12-FAKE16-NEXT: s_endpgm
bb:
%fneg.A = fneg <4 x half> %A
%res = call <4 x float> @llvm.amdgcn.swmmac.f32.16x16x32.f16.v4f32.v4f16.v8f16.i16(<4 x half> %fneg.A, <8 x half> %B, <4 x float> %C, i16 %Index)
@@ -252,11 +272,31 @@ bb:
}
define amdgpu_ps void @test_swmmac_f32_16x16x32_f16_negB(<4 x half> %A, <8 x half> %B, <4 x float> %C, i16 %Index, ptr addrspace(1) %out) {
-; GCN-LABEL: test_swmmac_f32_16x16x32_f16_negB:
-; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[0,1,0] neg_hi:[0,1,0]
-; GCN-NEXT: global_store_b128 v[11:12], v[6:9], off
-; GCN-NEXT: s_endpgm
+; GFX1170-TRUE16-LABEL: test_swmmac_f32_16x16x32_f16_negB:
+; GFX1170-TRUE16: ; %bb.0: ; %bb
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX1170-TRUE16-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX1170-TRUE16-NEXT: global_store_b128 v[11:12], v[6:9], off
+; GFX1170-TRUE16-NEXT: s_endpgm
+;
+; GFX1170-FAKE16-LABEL: test_swmmac_f32_16x16x32_f16_negB:
+; GFX1170-FAKE16: ; %bb.0: ; %bb
+; GFX1170-FAKE16-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX1170-FAKE16-NEXT: global_store_b128 v[11:12], v[6:9], off
+; GFX1170-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_swmmac_f32_16x16x32_f16_negB:
+; GFX12-TRUE16: ; %bb.0: ; %bb
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX12-TRUE16-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX12-TRUE16-NEXT: global_store_b128 v[11:12], v[6:9], off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_swmmac_f32_16x16x32_f16_negB:
+; GFX12-FAKE16: ; %bb.0: ; %bb
+; GFX12-FAKE16-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX12-FAKE16-NEXT: global_store_b128 v[11:12], v[6:9], off
+; GFX12-FAKE16-NEXT: s_endpgm
bb:
%fneg.B = fneg <8 x half> %B
%res = call <4 x float> @llvm.amdgcn.swmmac.f32.16x16x32.f16.v4f32.v4f16.v8f16.i16(<4 x half> %A, <8 x half> %fneg.B, <4 x float> %C, i16 %Index)
@@ -265,11 +305,31 @@ bb:
}
define amdgpu_ps void @test_swmmac_f16_16x16x32_f16_negA(<4 x half> %A, <8 x half> %B, <4 x half> %C, i16 %Index, ptr addrspace(1) %out) {
-; GCN-LABEL: test_swmmac_f16_16x16x32_f16_negA:
-; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[1,0,0] neg_hi:[1,0,0]
-; GCN-NEXT: global_store_b64 v[9:10], v[6:7], off
-; GCN-NEXT: s_endpgm
+; GFX1170-TRUE16-LABEL: test_swmmac_f16_16x16x32_f16_negA:
+; GFX1170-TRUE16: ; %bb.0: ; %bb
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX1170-TRUE16-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX1170-TRUE16-NEXT: global_store_b64 v[9:10], v[6:7], off
+; GFX1170-TRUE16-NEXT: s_endpgm
+;
+; GFX1170-FAKE16-LABEL: test_swmmac_f16_16x16x32_f16_negA:
+; GFX1170-FAKE16: ; %bb.0: ; %bb
+; GFX1170-FAKE16-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX1170-FAKE16-NEXT: global_store_b64 v[9:10], v[6:7], off
+; GFX1170-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_swmmac_f16_16x16x32_f16_negA:
+; GFX12-TRUE16: ; %bb.0: ; %bb
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX12-TRUE16-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX12-TRUE16-NEXT: global_store_b64 v[9:10], v[6:7], off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_swmmac_f16_16x16x32_f16_negA:
+; GFX12-FAKE16: ; %bb.0: ; %bb
+; GFX12-FAKE16-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[1,0,0] neg_hi:[1,0,0]
+; GFX12-FAKE16-NEXT: global_store_b64 v[9:10], v[6:7], off
+; GFX12-FAKE16-NEXT: s_endpgm
bb:
%fneg.A = fneg <4 x half> %A
%res = call <4 x half> @llvm.amdgcn.swmmac.f16.16x16x32.f16.v4f16.v4f16.v8f16.i16(<4 x half> %fneg.A, <8 x half> %B, <4 x half> %C, i16 %Index)
@@ -278,11 +338,31 @@ bb:
}
define amdgpu_ps void @test_swmmac_f16_16x16x32_f16_negB(<4 x half> %A, <8 x half> %B, <4 x half> %C, i16 %Index, ptr addrspace(1) %out) {
-; GCN-LABEL: test_swmmac_f16_16x16x32_f16_negB:
-; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[0,1,0] neg_hi:[0,1,0]
-; GCN-NEXT: global_store_b64 v[9:10], v[6:7], off
-; GCN-NEXT: s_endpgm
+; GFX1170-TRUE16-LABEL: test_swmmac_f16_16x16x32_f16_negB:
+; GFX1170-TRUE16: ; %bb.0: ; %bb
+; GFX1170-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX1170-TRUE16-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX1170-TRUE16-NEXT: global_store_b64 v[9:10], v[6:7], off
+; GFX1170-TRUE16-NEXT: s_endpgm
+;
+; GFX1170-FAKE16-LABEL: test_swmmac_f16_16x16x32_f16_negB:
+; GFX1170-FAKE16: ; %bb.0: ; %bb
+; GFX1170-FAKE16-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX1170-FAKE16-NEXT: global_store_b64 v[9:10], v[6:7], off
+; GFX1170-FAKE16-NEXT: s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_swmmac_f16_16x16x32_f16_negB:
+; GFX12-TRUE16: ; %bb.0: ; %bb
+; GFX12-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
+; GFX12-TRUE16-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX12-TRUE16-NEXT: global_store_b64 v[9:10], v[6:7], off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_swmmac_f16_16x16x32_f16_negB:
+; GFX12-FAKE16: ; %bb.0: ; %bb
+; GFX12-FAKE16-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8 neg_lo:[0,1,0] neg_hi:[0,1,0]
+; GFX12-FAKE16-NEXT: global_store_b64 v[9:10], v[6:7], off
+; GFX12-FAKE16-NEXT: s_endpgm
bb:
%fneg.B = fneg <8 x half> %B
%res = call <4 x half> @llvm.amdgcn.swmmac.f16.16x16x32.f16.v4f16.v4f16.v8f16.i16(<4 x half> %A, <8 x half> %fneg.B, <4 x half> %C, i16 %Index)
diff --git a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
index baeb81ab62957..4cea65f96522e 100644
--- a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
+++ b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
@@ -117,6 +117,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_zext_src0(i32 %A, <2 x i32> %B, <4 x i32> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu8_zext_src0:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu8 v[3:6], v0, v[1:2], v7 neg_lo:[1,0,0]
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -129,6 +130,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_zext_src1(i32 %A, <2 x i32> %B, <4 x i32> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu8_zext_src1:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu8 v[3:6], v0, v[1:2], v7 neg_lo:[0,1,0]
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -141,6 +143,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_clamp(i32 %A, <2 x i32> %B, <4 x i32> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu8_clamp:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu8 v[3:6], v0, v[1:2], v7 clamp
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -155,6 +158,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_zext_src0(i32 %A, i32 %B, <4 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu4_zext_src0:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr6_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu4 v[2:5], v0, v1, v6 neg_lo:[1,0,0]
; GCN-NEXT: global_store_b128 v[7:8], v[2:5], off
; GCN-NEXT: s_endpgm
@@ -167,6 +171,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_zext_src1(i32 %A, i32 %B, <4 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu4_zext_src1:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr6_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu4 v[2:5], v0, v1, v6 neg_lo:[0,1,0]
; GCN-NEXT: global_store_b128 v[7:8], v[2:5], off
; GCN-NEXT: s_endpgm
@@ -179,6 +184,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_clamp(i32 %A, i32 %B, <4 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu4_clamp:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr6_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu4 v[2:5], v0, v1, v6 clamp
; GCN-NEXT: global_store_b128 v[7:8], v[2:5], off
; GCN-NEXT: s_endpgm
@@ -193,6 +199,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x64_iu4_zext_src0(i32 %A, <2 x i32> %B, <4 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x64_iu4_zext_src0:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_i32_16x16x64_iu4 v[3:6], v0, v[1:2], v7 neg_lo:[1,0,0]
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -205,6 +212,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x64_iu4_zext_src1(i32 %A, <2 x i32> %B, <4 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x64_iu4_zext_src1:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_i32_16x16x64_iu4 v[3:6], v0, v[1:2], v7 neg_lo:[0,1,0]
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -217,6 +225,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x64_iu4_clamp(i32 %A, <2 x i32> %B, <4 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x64_iu4_clamp:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_i32_16x16x64_iu4 v[3:6], v0, v[1:2], v7 clamp
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
index 60dc7cc766f75..65ad094e316c7 100644
--- a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
@@ -137,6 +137,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_f16(<4 x half> %A, <8 x half> %B, <4 x float> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_f16:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr10_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_f16 v[6:9], v[0:1], v[2:5], v10
; GCN-NEXT: global_store_b128 v[11:12], v[6:9], off
; GCN-NEXT: s_endpgm
@@ -149,6 +150,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_bf16(<4 x i16> %A, <8 x i16> %B, <4 x float> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_bf16:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr10_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_bf16 v[6:9], v[0:1], v[2:5], v10
; GCN-NEXT: global_store_b128 v[11:12], v[6:9], off
; GCN-NEXT: s_endpgm
@@ -161,6 +163,7 @@ bb:
define amdgpu_ps void @test_swmmac_f16_16x16x32_f16(<4 x half> %A, <8 x half> %B, <4 x half> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f16_16x16x32_f16:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr8_hi16
; GCN-NEXT: v_swmmac_f16_16x16x32_f16 v[6:7], v[0:1], v[2:5], v8
; GCN-NEXT: global_store_b64 v[9:10], v[6:7], off
; GCN-NEXT: s_endpgm
@@ -173,6 +176,7 @@ bb:
define amdgpu_ps void @test_swmmac_bf16_16x16x32_bf16(<4 x i16> %A, <8 x i16> %B, <4 x i16> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_bf16_16x16x32_bf16:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr8_hi16
; GCN-NEXT: v_swmmac_bf16_16x16x32_bf16 v[6:7], v[0:1], v[2:5], v8
; GCN-NEXT: global_store_b64 v[9:10], v[6:7], off
; GCN-NEXT: s_endpgm
@@ -185,6 +189,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8(i32 %A, <2 x i32> %B, <4 x i32> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu8 v[3:6], v0, v[1:2], v7
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -197,6 +202,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4(i32 %A, i32 %B, <4 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x32_iu4:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr6_hi16
; GCN-NEXT: v_swmmac_i32_16x16x32_iu4 v[2:5], v0, v1, v6
; GCN-NEXT: global_store_b128 v[7:8], v[2:5], off
; GCN-NEXT: s_endpgm
@@ -209,6 +215,7 @@ bb:
define amdgpu_ps void @test_swmmac_i32_16x16x64_iu4(i32 %A, <2 x i32> %B, <4 x i32> %C, i16 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_i32_16x16x64_iu4:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_i32_16x16x64_iu4 v[3:6], v0, v[1:2], v7
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -221,6 +228,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_fp8_fp8(i32 %A, <2 x i32> %B, <4 x float> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_fp8_fp8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_fp8_fp8 v[3:6], v0, v[1:2], v7
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -233,6 +241,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_fp8_bf8(i32 %A, <2 x i32> %B, <4 x float> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_fp8_bf8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_fp8_bf8 v[3:6], v0, v[1:2], v7
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -245,6 +254,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_bf8_fp8(i32 %A, <2 x i32> %B, <4 x float> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_bf8_fp8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_bf8_fp8 v[3:6], v0, v[1:2], v7
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
@@ -257,6 +267,7 @@ bb:
define amdgpu_ps void @test_swmmac_f32_16x16x32_bf8_bf8(i32 %A, <2 x i32> %B, <4 x float> %C, i8 %Index, ptr addrspace(1) %out) {
; GCN-LABEL: test_swmmac_f32_16x16x32_bf8_bf8:
; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: ; implicit-def: $vgpr7_hi16
; GCN-NEXT: v_swmmac_f32_16x16x32_bf8_bf8 v[3:6], v0, v[1:2], v7
; GCN-NEXT: global_store_b128 v[8:9], v[3:6], off
; GCN-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
index 7b130f0007809..ddb55d74dc885 100644
--- a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
@@ -1576,6 +1576,7 @@ define { <8 x half>, <8 x half>, <8 x half> } @test_vld3q_lane_f16(ptr, <8 x hal
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ implicit-def: $q3
; CHECK-NEXT: vld3.16 {d1[3], d3[3], d5[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
@@ -1589,6 +1590,7 @@ define { <4 x half>, <4 x half>, <4 x half> } @test_vld3_lane_f16(ptr, <4 x half
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ implicit-def: $d3
; CHECK-NEXT: vld3.16 {d0[3], d1[3], d2[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
@@ -1649,6 +1651,7 @@ define void @test_vst3lane_p0i8_v8f16(ptr, <8 x half>, <8 x half>, <8 x half>) {
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ implicit-def: $q3
; CHECK-NEXT: vst3.16 {d0[0], d2[0], d4[0]}, [r0]
; CHECK-NEXT: bx lr
entry:
@@ -1661,6 +1664,7 @@ define void @test_vst3lane_p0i8_v4f16(ptr, <4 x half>, <4 x half>, <4 x half>) {
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ implicit-def: $d3
; CHECK-NEXT: vst3.16 {d0[0], d1[0], d2[0]}, [r0]
; CHECK-NEXT: bx lr
entry:
diff --git a/llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll b/llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll
index 21a6892c05fc6..71b768eef106b 100644
--- a/llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll
+++ b/llvm/test/CodeGen/ARM/bf16-intrinsics-ld-st.ll
@@ -306,6 +306,7 @@ define arm_aapcs_vfpcc [3 x <2 x i32>] @test_vld3_lane_bf16(ptr %ptr, [3 x <2 x
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ implicit-def: $d3
; CHECK-NEXT: vld3.16 {d0[1], d1[1], d2[1]}, [r0]
; CHECK-NEXT: bx lr
entry:
@@ -334,6 +335,7 @@ define arm_aapcs_vfpcc [3 x <4 x i32>] @test_vld3q_lane_bf16(ptr %ptr, [3 x <4 x
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ implicit-def: $q3
; CHECK-NEXT: vld3.16 {d1[3], d3[3], d5[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
@@ -668,6 +670,7 @@ define arm_aapcs_vfpcc void @test_vst1_bf16_x3(ptr nocapture %ptr, [3 x <2 x i32
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ implicit-def: $d3
; CHECK-NEXT: vst1.16 {d0, d1, d2}, [r0]
; CHECK-NEXT: bx lr
entry:
@@ -687,6 +690,7 @@ define arm_aapcs_vfpcc void @test_vst1q_bf16_x3(ptr nocapture %ptr, [3 x <4 x i3
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ implicit-def: $q3
; CHECK-NEXT: vst1.16 {d0, d1, d2}, [r0]!
; CHECK-NEXT: vst1.16 {d3, d4, d5}, [r0]
; CHECK-NEXT: bx lr
@@ -816,6 +820,7 @@ define arm_aapcs_vfpcc void @test_vst3_bf16(ptr %ptr, [3 x <2 x i32>] %val.coerc
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ implicit-def: $d3
; CHECK-NEXT: vst3.16 {d0, d1, d2}, [r0]
; CHECK-NEXT: bx lr
entry:
@@ -835,6 +840,7 @@ define arm_aapcs_vfpcc void @test_vst3q_bf16(ptr %ptr, [3 x <4 x i32>] %val.coer
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ implicit-def: $q3
; CHECK-NEXT: vst3.16 {d0, d2, d4}, [r0]!
; CHECK-NEXT: vst3.16 {d1, d3, d5}, [r0]
; CHECK-NEXT: bx lr
@@ -855,6 +861,7 @@ define arm_aapcs_vfpcc void @test_vst3_lane_bf16(ptr %ptr, [3 x <2 x i32>] %val.
; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ implicit-def: $d3
; CHECK-NEXT: vst3.16 {d0[1], d1[1], d2[1]}, [r0]
; CHECK-NEXT: bx lr
entry:
@@ -874,6 +881,7 @@ define arm_aapcs_vfpcc void @test_vst3q_lane_bf16(ptr %ptr, [3 x <4 x i32>] %val
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: @ implicit-def: $q3
; CHECK-NEXT: vst3.16 {d1[3], d3[3], d5[3]}, [r0]
; CHECK-NEXT: bx lr
entry:
diff --git a/llvm/test/CodeGen/ARM/llvm.exp10.ll b/llvm/test/CodeGen/ARM/llvm.exp10.ll
index 49397ca386cb4..c985675045d01 100644
--- a/llvm/test/CodeGen/ARM/llvm.exp10.ll
+++ b/llvm/test/CodeGen/ARM/llvm.exp10.ll
@@ -196,6 +196,7 @@ define <3 x float> @exp10_v3f32(<3 x float> %x) {
; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: vmov s18, r6
+; CHECK-NEXT: @ implicit-def: $s19
; CHECK-NEXT: vmov r2, r3, d9
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r6, pc}
diff --git a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
index be20eec80f400..e238b5d2d6e67 100644
--- a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
+++ b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
@@ -123,6 +123,7 @@ define void @i64_buildvector(ptr %ptr, ptr %vp) nounwind {
; CHECK-LABEL: i64_buildvector:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, [r0]
+; CHECK-NEXT: @ implicit-def: $d17
; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
; CHECK-NEXT: bx lr
%t0 = load i64, ptr %ptr, align 4
diff --git a/llvm/test/CodeGen/ARM/vldlane.ll b/llvm/test/CodeGen/ARM/vldlane.ll
index 70a1717c8b547..924672389211f 100644
--- a/llvm/test/CodeGen/ARM/vldlane.ll
+++ b/llvm/test/CodeGen/ARM/vldlane.ll
@@ -365,6 +365,7 @@ define <8 x i8> @vld3lanei8(ptr %A, ptr %B) nounwind {
; DEFAULT-NEXT: vldr d16, [r1]
; DEFAULT-NEXT: vorr d17, d16, d16
; DEFAULT-NEXT: vorr d18, d16, d16
+; DEFAULT-NEXT: @ implicit-def: $d19
; DEFAULT-NEXT: vld3.8 {d16[1], d17[1], d18[1]}, [r0]
; DEFAULT-NEXT: vadd.i8 d20, d16, d17
; DEFAULT-NEXT: vadd.i8 d16, d18, d20
@@ -376,6 +377,7 @@ define <8 x i8> @vld3lanei8(ptr %A, ptr %B) nounwind {
; BASIC-NEXT: vldr d18, [r1]
; BASIC-NEXT: vorr d19, d18, d18
; BASIC-NEXT: vorr d20, d18, d18
+; BASIC-NEXT: @ implicit-def: $d21
; BASIC-NEXT: vld3.8 {d18[1], d19[1], d20[1]}, [r0]
; BASIC-NEXT: vadd.i8 d16, d18, d19
; BASIC-NEXT: vadd.i8 d16, d20, d16
@@ -398,6 +400,7 @@ define <4 x i16> @vld3lanei16(ptr %A, ptr %B) nounwind {
; DEFAULT-NEXT: vldr d16, [r1]
; DEFAULT-NEXT: vorr d17, d16, d16
; DEFAULT-NEXT: vorr d18, d16, d16
+; DEFAULT-NEXT: @ implicit-def: $d19
; DEFAULT-NEXT: vld3.16 {d16[1], d17[1], d18[1]}, [r0]
; DEFAULT-NEXT: vadd.i16 d20, d16, d17
; DEFAULT-NEXT: vadd.i16 d16, d18, d20
@@ -409,6 +412,7 @@ define <4 x i16> @vld3lanei16(ptr %A, ptr %B) nounwind {
; BASIC-NEXT: vldr d18, [r1]
; BASIC-NEXT: vorr d19, d18, d18
; BASIC-NEXT: vorr d20, d18, d18
+; BASIC-NEXT: @ implicit-def: $d21
; BASIC-NEXT: vld3.16 {d18[1], d19[1], d20[1]}, [r0]
; BASIC-NEXT: vadd.i16 d16, d18, d19
; BASIC-NEXT: vadd.i16 d16, d20, d16
@@ -430,6 +434,7 @@ define <2 x i32> @vld3lanei32(ptr %A, ptr %B) nounwind {
; DEFAULT-NEXT: vldr d16, [r1]
; DEFAULT-NEXT: vorr d17, d16, d16
; DEFAULT-NEXT: vorr d18, d16, d16
+; DEFAULT-NEXT: @ implicit-def: $d19
; DEFAULT-NEXT: vld3.32 {d16[1], d17[1], d18[1]}, [r0]
; DEFAULT-NEXT: vadd.i32 d20, d16, d17
; DEFAULT-NEXT: vadd.i32 d16, d18, d20
@@ -441,6 +446,7 @@ define <2 x i32> @vld3lanei32(ptr %A, ptr %B) nounwind {
; BASIC-NEXT: vldr d18, [r1]
; BASIC-NEXT: vorr d19, d18, d18
; BASIC-NEXT: vorr d20, d18, d18
+; BASIC-NEXT: @ implicit-def: $d21
; BASIC-NEXT: vld3.32 {d18[1], d19[1], d20[1]}, [r0]
; BASIC-NEXT: vadd.i32 d16, d18, d19
; BASIC-NEXT: vadd.i32 d16, d20, d16
@@ -462,6 +468,7 @@ define <2 x float> @vld3lanef(ptr %A, ptr %B) nounwind {
; DEFAULT-NEXT: vldr d16, [r1]
; DEFAULT-NEXT: vorr d17, d16, d16
; DEFAULT-NEXT: vorr d18, d16, d16
+; DEFAULT-NEXT: @ implicit-def: $d19
; DEFAULT-NEXT: vld3.32 {d16[1], d17[1], d18[1]}, [r0]
; DEFAULT-NEXT: vadd.f32 d20, d16, d17
; DEFAULT-NEXT: vadd.f32 d16, d18, d20
@@ -473,6 +480,7 @@ define <2 x float> @vld3lanef(ptr %A, ptr %B) nounwind {
; BASIC-NEXT: vldr d18, [r1]
; BASIC-NEXT: vorr d19, d18, d18
; BASIC-NEXT: vorr d20, d18, d18
+; BASIC-NEXT: @ implicit-def: $d21
; BASIC-NEXT: vld3.32 {d18[1], d19[1], d20[1]}, [r0]
; BASIC-NEXT: vadd.f32 d16, d18, d19
; BASIC-NEXT: vadd.f32 d16, d20, d16
@@ -495,6 +503,7 @@ define <8 x i16> @vld3laneQi16(ptr %A, ptr %B) nounwind {
; DEFAULT-NEXT: vld1.64 {d16, d17}, [r1]
; DEFAULT-NEXT: vorr q9, q8, q8
; DEFAULT-NEXT: vorr q10, q8, q8
+; DEFAULT-NEXT: @ implicit-def: $q11
; DEFAULT-NEXT: vld3.16 {d16[1], d18[1], d20[1]}, [r0]
; DEFAULT-NEXT: vadd.i16 q12, q8, q9
; DEFAULT-NEXT: vadd.i16 q8, q10, q12
@@ -507,6 +516,7 @@ define <8 x i16> @vld3laneQi16(ptr %A, ptr %B) nounwind {
; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
; BASIC-NEXT: vorr q10, q9, q9
; BASIC-NEXT: vorr q11, q9, q9
+; BASIC-NEXT: @ implicit-def: $q12
; BASIC-NEXT: vld3.16 {d18[1], d20[1], d22[1]}, [r0]
; BASIC-NEXT: vadd.i16 q8, q9, q10
; BASIC-NEXT: vadd.i16 q8, q11, q8
@@ -534,6 +544,7 @@ define <8 x i16> @vld3laneQi16_update(ptr %ptr, ptr %B, i32 %inc) nounwind {
; DEFAULT-NEXT: vorr q9, q8, q8
; DEFAULT-NEXT: ldr lr, [r0]
; DEFAULT-NEXT: vorr q10, q8, q8
+; DEFAULT-NEXT: @ implicit-def: $q11
; DEFAULT-NEXT: vld3.16 {d16[1], d18[1], d20[1]}, [lr], r1
; DEFAULT-NEXT: vadd.i16 q12, q8, q9
; DEFAULT-NEXT: vadd.i16 q8, q10, q12
@@ -549,20 +560,20 @@ define <8 x i16> @vld3laneQi16_update(ptr %ptr, ptr %B, i32 %inc) nounwind {
; BASIC-NEXT: .save {r11, lr}
; BASIC-NEXT: push {r11, lr}
; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
-; BASIC-NEXT: mov r3, r0
+; BASIC-NEXT: mov lr, r0
; BASIC-NEXT: vorr q10, q9, q9
; BASIC-NEXT: lsl r1, r2, #1
; BASIC-NEXT: ldr r0, [r0]
; BASIC-NEXT: vorr q11, q9, q9
+; BASIC-NEXT: @ implicit-def: $q12
; BASIC-NEXT: vld3.16 {d18[1], d20[1], d22[1]}, [r0], r1
; BASIC-NEXT: vadd.i16 q8, q9, q10
; BASIC-NEXT: vadd.i16 q8, q11, q8
-; BASIC-NEXT: str r0, [r3]
-; BASIC-NEXT: vmov r1, lr, d16
-; BASIC-NEXT: vmov r2, r12, d17
+; BASIC-NEXT: str r0, [lr]
+; BASIC-NEXT: vmov r1, r12, d16
+; BASIC-NEXT: vmov r2, r3, d17
; BASIC-NEXT: mov r0, r1
-; BASIC-NEXT: mov r1, lr
-; BASIC-NEXT: mov r3, r12
+; BASIC-NEXT: mov r1, r12
; BASIC-NEXT: pop {r11, lr}
; BASIC-NEXT: mov pc, lr
%A = load ptr, ptr %ptr
@@ -584,6 +595,7 @@ define <4 x i32> @vld3laneQi32(ptr %A, ptr %B) nounwind {
; DEFAULT-NEXT: vld1.64 {d16, d17}, [r1]
; DEFAULT-NEXT: vorr q9, q8, q8
; DEFAULT-NEXT: vorr q10, q8, q8
+; DEFAULT-NEXT: @ implicit-def: $q11
; DEFAULT-NEXT: vld3.32 {d17[1], d19[1], d21[1]}, [r0]
; DEFAULT-NEXT: vadd.i32 q12, q8, q9
; DEFAULT-NEXT: vadd.i32 q8, q10, q12
@@ -596,6 +608,7 @@ define <4 x i32> @vld3laneQi32(ptr %A, ptr %B) nounwind {
; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
; BASIC-NEXT: vorr q10, q9, q9
; BASIC-NEXT: vorr q11, q9, q9
+; BASIC-NEXT: @ implicit-def: $q12
; BASIC-NEXT: vld3.32 {d19[1], d21[1], d23[1]}, [r0]
; BASIC-NEXT: vadd.i32 q8, q9, q10
; BASIC-NEXT: vadd.i32 q8, q11, q8
@@ -618,6 +631,7 @@ define <4 x float> @vld3laneQf(ptr %A, ptr %B) nounwind {
; DEFAULT-NEXT: vld1.64 {d16, d17}, [r1]
; DEFAULT-NEXT: vorr q9, q8, q8
; DEFAULT-NEXT: vorr q10, q8, q8
+; DEFAULT-NEXT: @ implicit-def: $q11
; DEFAULT-NEXT: vld3.32 {d16[1], d18[1], d20[1]}, [r0]
; DEFAULT-NEXT: vadd.f32 q12, q8, q9
; DEFAULT-NEXT: vadd.f32 q8, q10, q12
@@ -630,6 +644,7 @@ define <4 x float> @vld3laneQf(ptr %A, ptr %B) nounwind {
; BASIC-NEXT: vld1.64 {d18, d19}, [r1]
; BASIC-NEXT: vorr q10, q9, q9
; BASIC-NEXT: vorr q11, q9, q9
+; BASIC-NEXT: @ implicit-def: $q12
; BASIC-NEXT: vld3.32 {d18[1], d20[1], d22[1]}, [r0]
; BASIC-NEXT: vadd.f32 q8, q9, q10
; BASIC-NEXT: vadd.f32 q8, q11, q8
@@ -920,6 +935,7 @@ define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
; DEFAULT-NEXT: add r0, sp, #28
; DEFAULT-NEXT: vld1.32 {d21[1]}, [r0:32]
; DEFAULT-NEXT: vmov.i32 d20, #0x0
+; DEFAULT-NEXT: @ implicit-def: $q11
; DEFAULT-NEXT: vld3.16 {d16[1], d18[1], d20[1]}, [r0]
; DEFAULT-NEXT: vadd.i16 q12, q8, q9
; DEFAULT-NEXT: vadd.i16 q8, q10, q12
@@ -934,6 +950,7 @@ define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
; BASIC-NEXT: add r0, sp, #28
; BASIC-NEXT: vld1.32 {d23[1]}, [r0:32]
; BASIC-NEXT: vmov.i32 d22, #0x0
+; BASIC-NEXT: @ implicit-def: $q12
; BASIC-NEXT: vld3.16 {d18[1], d20[1], d22[1]}, [r0]
; BASIC-NEXT: vadd.i16 q8, q9, q10
; BASIC-NEXT: vadd.i16 q8, q11, q8
diff --git a/llvm/test/CodeGen/ARM/vstlane.ll b/llvm/test/CodeGen/ARM/vstlane.ll
index 32e569db6158c..5e09920bd6782 100644
--- a/llvm/test/CodeGen/ARM/vstlane.ll
+++ b/llvm/test/CodeGen/ARM/vstlane.ll
@@ -266,6 +266,7 @@ define void @vst3lanei8(ptr %A, ptr %B) nounwind {
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
+; CHECK-NEXT: @ implicit-def: $d19
; CHECK-NEXT: vst3.8 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, ptr %B
@@ -280,6 +281,7 @@ define void @vst3lanei16(ptr %A, ptr %B) nounwind {
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
+; CHECK-NEXT: @ implicit-def: $d19
; CHECK-NEXT: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, ptr %B
@@ -293,6 +295,7 @@ define void @vst3lanei32(ptr %A, ptr %B) nounwind {
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
+; CHECK-NEXT: @ implicit-def: $d19
; CHECK-NEXT: vst3.32 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x i32>, ptr %B
@@ -306,6 +309,7 @@ define void @vst3lanef(ptr %A, ptr %B) nounwind {
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vorr d18, d16, d16
+; CHECK-NEXT: @ implicit-def: $d19
; CHECK-NEXT: vst3.32 {d16[1], d17[1], d18[1]}, [r0]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x float>, ptr %B
@@ -319,6 +323,7 @@ define void @vst3laneQi16(ptr %A, ptr %B) nounwind {
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
+; CHECK-NEXT: @ implicit-def: $q11
; CHECK-NEXT: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
; CHECK-NEXT: mov pc, lr
;Check the (default) alignment value. VST3 does not support alignment.
@@ -333,6 +338,7 @@ define void @vst3laneQi32(ptr %A, ptr %B) nounwind {
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
+; CHECK-NEXT: @ implicit-def: $q11
; CHECK-NEXT: vst3.32 {d16[0], d18[0], d20[0]}, [r0]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, ptr %B
@@ -348,6 +354,7 @@ define void @vst3laneQi32_update(ptr %ptr, ptr %B) nounwind {
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: vorr q10, q8, q8
+; CHECK-NEXT: @ implicit-def: $q11
; CHECK-NEXT: vst3.32 {d16[0], d18[0], d20[0]}, [r2]!
; CHECK-NEXT: str r2, [r0]
; CHECK-NEXT: mov pc, lr
@@ -365,6 +372,7 @@ define void @vst3laneQf(ptr %A, ptr %B) nounwind {
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
+; CHECK-NEXT: @ implicit-def: $q11
; CHECK-NEXT: vst3.32 {d16[1], d18[1], d20[1]}, [r0]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x float>, ptr %B
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
index ca1f1036ea674..83f11da17eed8 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
@@ -224,6 +224,8 @@ define arm_aapcs_vfpcc float @fast_float_mac(ptr nocapture readonly %b, ptr noca
; CHECK-NEXT: le lr, .LBB1_2
; CHECK-NEXT: @ %bb.3: @ %middle.block
; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vadd.f32 q0, q0, q1
@@ -425,6 +427,8 @@ define arm_aapcs_vfpcc float @fast_float_half_mac(ptr nocapture readonly %b, ptr
; CHECK-NEXT: b .LBB2_2
; CHECK-NEXT: .LBB2_19: @ %middle.block
; CHECK-NEXT: vdup.32 q0, r12
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vcmp.u32 cs, q0, q4
; CHECK-NEXT: vpsel q0, q5, q3
; CHECK-NEXT: vmov.f32 s4, s2
diff --git a/llvm/test/CodeGen/Thumb2/mve-clmul.ll b/llvm/test/CodeGen/Thumb2/mve-clmul.ll
index aacba93e117ea..fd1be60abec23 100644
--- a/llvm/test/CodeGen/Thumb2/mve-clmul.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-clmul.ll
@@ -6250,49 +6250,53 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov q6, q1
-; CHECK-NEXT: vmov.f32 s16, s24
+; CHECK-NEXT: vmov.f32 s20, s24
+; CHECK-NEXT: @ implicit-def: $s21
+; CHECK-NEXT: @ implicit-def: $s23
+; CHECK-NEXT: @ implicit-def: $s13
+; CHECK-NEXT: @ implicit-def: $s15
+; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.f32 s22, s25
; CHECK-NEXT: mov.w lr, #0
-; CHECK-NEXT: vmov.f32 s18, s25
; CHECK-NEXT: vmov.f32 s12, s8
; CHECK-NEXT: vmov r12, s14
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: lsll r4, r5, #1
; CHECK-NEXT: mov r2, r12
; CHECK-NEXT: lsll r2, r3, #1
-; CHECK-NEXT: vmov q0[2], q0[0], r4, r2
+; CHECK-NEXT: vmov q4[2], q4[0], r4, r2
; CHECK-NEXT: adr.w r2, .LCPI22_32
-; CHECK-NEXT: vldrw.u32 q1, [r2]
-; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
+; CHECK-NEXT: vldrw.u32 q0, [r2]
+; CHECK-NEXT: vmov q4[3], q4[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
-; CHECK-NEXT: vstrw.32 q1, [sp, #480] @ 16-byte Spill
-; CHECK-NEXT: vmov r2, s20
-; CHECK-NEXT: vmov.i64 q1, #0xffffffff
-; CHECK-NEXT: vand q3, q3, q1
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vstrw.32 q0, [sp, #480] @ 16-byte Spill
+; CHECK-NEXT: vand q0, q5, q0
+; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: lsll r4, r5, #2
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s2
+; CHECK-NEXT: vmov.i64 q0, #0xffffffff
+; CHECK-NEXT: vand q0, q3, q0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
; CHECK-NEXT: adr.w r2, .LCPI22_33
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: vpsel q3, q1, q3
+; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r2]
-; CHECK-NEXT: veor q0, q3, q0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: veor q3, q0, q4
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: vstrw.32 q1, [sp, #464] @ 16-byte Spill
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6300,23 +6304,23 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: lsll r2, r3, #2
-; CHECK-NEXT: vpsel q3, q3, q0
+; CHECK-NEXT: vpsel q3, q0, q3
; CHECK-NEXT: vmov q0[2], q0[0], r4, r2
; CHECK-NEXT: adr.w r2, .LCPI22_34
; CHECK-NEXT: vldrw.u32 q1, [r2]
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #448] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #3
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6331,16 +6335,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #432] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #4
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6355,16 +6359,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #416] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #5
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6379,16 +6383,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #400] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #6
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6403,16 +6407,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #384] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #7
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6427,16 +6431,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #368] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #8
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6451,16 +6455,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #352] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #9
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6475,16 +6479,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #336] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #10
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6499,16 +6503,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #320] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #11
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6523,16 +6527,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #304] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #12
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6547,16 +6551,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #288] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #13
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6571,16 +6575,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #272] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #14
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6595,16 +6599,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #256] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #15
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6619,16 +6623,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #240] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #16
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6643,16 +6647,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #224] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #17
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6667,16 +6671,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #208] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6691,16 +6695,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #192] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #19
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6715,16 +6719,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #176] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #20
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6739,16 +6743,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #160] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #21
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6763,16 +6767,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #22
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6787,16 +6791,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #23
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6811,16 +6815,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #24
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6835,16 +6839,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #25
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6859,16 +6863,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #26
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6883,16 +6887,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #27
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6907,16 +6911,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #28
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6931,16 +6935,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #29
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6955,16 +6959,16 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vand q5, q4, q1
+; CHECK-NEXT: vand q4, q5, q1
; CHECK-NEXT: movs r5, #0
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: veor q0, q3, q0
; CHECK-NEXT: lsll r4, r5, #30
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: vmov r2, s22
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, eq
; CHECK-NEXT: bfi r3, r2, #8, #8
@@ -6979,7 +6983,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov q0[3], q0[1], r5, r3
; CHECK-NEXT: veor q1, q3, q0
; CHECK-NEXT: movs r3, #0
-; CHECK-NEXT: vand q0, q4, q7
+; CHECK-NEXT: vand q0, q5, q7
; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: lsll r0, r5, #31
@@ -6997,19 +7001,21 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vpsel q0, q3, q1
; CHECK-NEXT: vmov q1[2], q1[0], r0, r12
; CHECK-NEXT: adr.w r0, .LCPI22_31
-; CHECK-NEXT: vldrw.u32 q5, [r0]
+; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vmov q1[3], q1[1], r5, r3
; CHECK-NEXT: veor q1, q0, q1
; CHECK-NEXT: vmov.i64 q3, #0xffffffff
-; CHECK-NEXT: vand q4, q4, q5
-; CHECK-NEXT: vmov r0, s16
-; CHECK-NEXT: vmov.f32 s16, s26
+; CHECK-NEXT: vand q5, q5, q4
+; CHECK-NEXT: vmov r0, s20
+; CHECK-NEXT: @ implicit-def: $s21
+; CHECK-NEXT: @ implicit-def: $s23
+; CHECK-NEXT: vmov.f32 s20, s26
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r2, r0, #0, #8
-; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: vmov.f32 s18, s27
-; CHECK-NEXT: vand q4, q4, q3
+; CHECK-NEXT: vmov r0, s22
+; CHECK-NEXT: vmov.f32 s22, s27
+; CHECK-NEXT: vand q5, q5, q3
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r2, r0, #8, #8
@@ -7018,9 +7024,11 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s6, s11
+; CHECK-NEXT: @ implicit-def: $s5
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vand q0, q1, q3
-; CHECK-NEXT: vand q6, q4, q6
+; CHECK-NEXT: vand q6, q5, q6
; CHECK-NEXT: vmov r3, s3
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: vmov r4, s4
@@ -7058,7 +7066,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vpsel q0, q6, q0
; CHECK-NEXT: vldrw.u32 q6, [sp, #464] @ 16-byte Reload
; CHECK-NEXT: veor q2, q0, q2
-; CHECK-NEXT: vand q6, q4, q6
+; CHECK-NEXT: vand q6, q5, q6
; CHECK-NEXT: vmov r0, s24
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, eq
@@ -7072,7 +7080,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vpsel q0, q0, q2
; CHECK-NEXT: vldrw.u32 q2, [sp, #448] @ 16-byte Reload
; CHECK-NEXT: veor q1, q0, q1
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, eq
@@ -7087,7 +7095,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #3
; CHECK-NEXT: lsll r2, r7, #3
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7109,7 +7117,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #4
; CHECK-NEXT: lsll r2, r7, #4
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7131,7 +7139,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #5
; CHECK-NEXT: lsll r2, r7, #5
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7153,7 +7161,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #6
; CHECK-NEXT: lsll r2, r7, #6
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7175,7 +7183,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #7
; CHECK-NEXT: lsll r2, r7, #7
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7197,7 +7205,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #8
; CHECK-NEXT: lsll r2, r7, #8
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7219,7 +7227,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #9
; CHECK-NEXT: lsll r2, r7, #9
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7241,7 +7249,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #10
; CHECK-NEXT: lsll r2, r7, #10
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7263,7 +7271,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #11
; CHECK-NEXT: lsll r2, r7, #11
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7285,7 +7293,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #12
; CHECK-NEXT: lsll r2, r7, #12
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7307,7 +7315,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #13
; CHECK-NEXT: lsll r2, r7, #13
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7329,7 +7337,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #14
; CHECK-NEXT: lsll r2, r7, #14
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7351,7 +7359,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #15
; CHECK-NEXT: lsll r2, r7, #15
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7373,7 +7381,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #16
; CHECK-NEXT: lsll r2, r7, #16
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7395,7 +7403,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #17
; CHECK-NEXT: lsll r2, r7, #17
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7417,7 +7425,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #18
; CHECK-NEXT: lsll r2, r7, #18
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7439,7 +7447,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #19
; CHECK-NEXT: lsll r2, r7, #19
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7454,6 +7462,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, eq
+; CHECK-NEXT: bfi r2, r0, #8, #8
; CHECK-NEXT: b.w .LBB22_15
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1:
@@ -7555,14 +7564,13 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .p2align 1
; CHECK-NEXT: .LBB22_15:
-; CHECK-NEXT: bfi r2, r0, #8, #8
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: vldrw.u32 q2, [sp, #160] @ 16-byte Reload
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #20
; CHECK-NEXT: lsll r2, r7, #20
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7584,7 +7592,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #21
; CHECK-NEXT: lsll r2, r7, #21
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7606,7 +7614,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #22
; CHECK-NEXT: lsll r2, r7, #22
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7628,7 +7636,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #23
; CHECK-NEXT: lsll r2, r7, #23
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7650,7 +7658,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #24
; CHECK-NEXT: lsll r2, r7, #24
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7672,7 +7680,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #25
; CHECK-NEXT: lsll r2, r7, #25
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7694,7 +7702,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #26
; CHECK-NEXT: lsll r2, r7, #26
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7716,7 +7724,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #27
; CHECK-NEXT: lsll r2, r7, #27
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7738,7 +7746,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #28
; CHECK-NEXT: lsll r2, r7, #28
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7760,7 +7768,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: lsll r0, r5, #29
; CHECK-NEXT: lsll r2, r7, #29
-; CHECK-NEXT: vand q2, q4, q2
+; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vmov r0, s8
@@ -7773,7 +7781,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r2, r0, #0, #8
; CHECK-NEXT: vmov r0, s10
-; CHECK-NEXT: vand q2, q4, q7
+; CHECK-NEXT: vand q2, q5, q7
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r2, r0, #8, #8
@@ -7794,7 +7802,7 @@ define <4 x i64> @clmul_v4i64_zext(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r2, r0, #0, #8
; CHECK-NEXT: vmov r0, s10
-; CHECK-NEXT: vand q2, q4, q5
+; CHECK-NEXT: vand q2, q5, q4
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r2, r0, #8, #8
diff --git a/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-add.ll b/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-add.ll
index d9161ab370dd6..a65bbf4fd0ee8 100644
--- a/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-add.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-add.ll
@@ -9,6 +9,8 @@ define arm_aapcs_vfpcc <2 x float> @complex_add_v2f32(<2 x float> %a, <2 x float
; CHECK-LABEL: complex_add_v2f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f32 s5, s5, s0
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vsub.f32 s4, s4, s1
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-mul.ll b/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-mul.ll
index 8c7039f82b888..ab46bf8091022 100644
--- a/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-mul.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f32-mul.ll
@@ -8,6 +8,8 @@ define arm_aapcs_vfpcc <2 x float> @complex_mul_v2f32(<2 x float> %a, <2 x float
; CHECK-LABEL: complex_mul_v2f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f32 s9, s5, s0
+; CHECK-NEXT: @ implicit-def: $s10
+; CHECK-NEXT: @ implicit-def: $s11
; CHECK-NEXT: vmul.f32 s8, s1, s5
; CHECK-NEXT: vfma.f32 s9, s4, s1
; CHECK-NEXT: vfnms.f32 s8, s4, s0
diff --git a/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll b/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
index 16dc5a81e782b..234567f394ee4 100644
--- a/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
@@ -43,21 +43,29 @@ define arm_aapcs_vfpcc <4 x float> @add_mul(<4 x float> %a, <4 x float> %b, <4 x
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vsub.f32 q3, q1, q2
; CHECK-NEXT: vsub.f32 q0, q1, q0
-; CHECK-NEXT: vmov.f32 s4, s9
; CHECK-NEXT: vmov.f32 s13, s14
-; CHECK-NEXT: vmov.f32 s5, s11
+; CHECK-NEXT: @ implicit-def: $s14
+; CHECK-NEXT: @ implicit-def: $s15
+; CHECK-NEXT: @ implicit-def: $s18
+; CHECK-NEXT: @ implicit-def: $s19
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: vmov.f32 s16, s9
+; CHECK-NEXT: vmov.f32 s17, s11
+; CHECK-NEXT: @ implicit-def: $s11
; CHECK-NEXT: vmov.f32 s0, s1
-; CHECK-NEXT: vmul.f32 q4, q3, q1
+; CHECK-NEXT: vmul.f32 q1, q3, q4
; CHECK-NEXT: vmov.f32 s1, s3
+; CHECK-NEXT: @ implicit-def: $s3
; CHECK-NEXT: vmov.f32 s9, s10
-; CHECK-NEXT: vfma.f32 q4, q2, q0
-; CHECK-NEXT: vmul.f32 q0, q1, q0
-; CHECK-NEXT: vneg.f32 q1, q0
-; CHECK-NEXT: vmov.f32 s1, s16
-; CHECK-NEXT: vfma.f32 q1, q2, q3
-; CHECK-NEXT: vmov.f32 s3, s17
-; CHECK-NEXT: vmov.f32 s0, s4
-; CHECK-NEXT: vmov.f32 s2, s5
+; CHECK-NEXT: @ implicit-def: $s10
+; CHECK-NEXT: vfma.f32 q1, q2, q0
+; CHECK-NEXT: vmul.f32 q0, q4, q0
+; CHECK-NEXT: vneg.f32 q4, q0
+; CHECK-NEXT: vmov.f32 s1, s4
+; CHECK-NEXT: vfma.f32 q4, q2, q3
+; CHECK-NEXT: vmov.f32 s3, s5
+; CHECK-NEXT: vmov.f32 s0, s16
+; CHECK-NEXT: vmov.f32 s2, s17
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr
entry:
@@ -81,35 +89,47 @@ entry:
define arm_aapcs_vfpcc <4 x float> @mul_mul270_mul(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: mul_mul270_mul:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9, d10}
-; CHECK-NEXT: vpush {d8, d9, d10}
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.f32 s16, s8
-; CHECK-NEXT: vmov.f32 s20, s4
+; CHECK-NEXT: @ implicit-def: $s18
+; CHECK-NEXT: @ implicit-def: $s19
+; CHECK-NEXT: @ implicit-def: $s22
+; CHECK-NEXT: @ implicit-def: $s23
; CHECK-NEXT: vmov.f32 s17, s10
+; CHECK-NEXT: @ implicit-def: $s10
+; CHECK-NEXT: vmov.f32 s20, s4
; CHECK-NEXT: vmov.f32 s21, s6
+; CHECK-NEXT: @ implicit-def: $s6
; CHECK-NEXT: vmul.f32 q3, q5, q4
-; CHECK-NEXT: vmov.f32 s4, s5
-; CHECK-NEXT: vmov.f32 s5, s7
-; CHECK-NEXT: vneg.f32 q3, q3
; CHECK-NEXT: vmov.f32 s8, s9
-; CHECK-NEXT: vmul.f32 q4, q1, q4
; CHECK-NEXT: vmov.f32 s9, s11
+; CHECK-NEXT: vneg.f32 q3, q3
+; CHECK-NEXT: vmov.f32 s4, s5
+; CHECK-NEXT: @ implicit-def: $s11
+; CHECK-NEXT: vmov.f32 s5, s7
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vfma.f32 q3, q1, q2
-; CHECK-NEXT: vfma.f32 q4, q5, q2
-; CHECK-NEXT: vmov.f32 s8, s0
-; CHECK-NEXT: vmov.f32 s9, s2
+; CHECK-NEXT: vmul.f32 q1, q1, q4
+; CHECK-NEXT: vmov.f32 s16, s0
+; CHECK-NEXT: @ implicit-def: $s18
+; CHECK-NEXT: @ implicit-def: $s19
+; CHECK-NEXT: vfma.f32 q1, q5, q2
+; CHECK-NEXT: vmov.f32 s17, s2
+; CHECK-NEXT: @ implicit-def: $s2
; CHECK-NEXT: vmov.f32 s0, s1
-; CHECK-NEXT: vmul.f32 q1, q3, q2
+; CHECK-NEXT: vmul.f32 q2, q3, q4
; CHECK-NEXT: vmov.f32 s1, s3
-; CHECK-NEXT: vfma.f32 q1, q4, q0
+; CHECK-NEXT: @ implicit-def: $s3
+; CHECK-NEXT: vfma.f32 q2, q1, q0
; CHECK-NEXT: vmul.f32 q0, q3, q0
; CHECK-NEXT: vneg.f32 q3, q0
-; CHECK-NEXT: vmov.f32 s1, s4
-; CHECK-NEXT: vfma.f32 q3, q4, q2
-; CHECK-NEXT: vmov.f32 s3, s5
+; CHECK-NEXT: vmov.f32 s1, s8
+; CHECK-NEXT: vfma.f32 q3, q1, q4
+; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov.f32 s0, s12
; CHECK-NEXT: vmov.f32 s2, s13
-; CHECK-NEXT: vpop {d8, d9, d10}
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr
entry:
%strided.vec = shufflevector <4 x float> %c, <4 x float> poison, <2 x i32> <i32 0, i32 2>
@@ -269,20 +289,32 @@ define arm_aapcs_vfpcc <4 x float> @mul_triangle_addmul(<4 x float> %a, <4 x flo
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vmov.f32 s16, s0
-; CHECK-NEXT: vmov.f32 s20, s5
+; CHECK-NEXT: @ implicit-def: $s18
+; CHECK-NEXT: @ implicit-def: $s19
+; CHECK-NEXT: @ implicit-def: $s22
+; CHECK-NEXT: @ implicit-def: $s23
; CHECK-NEXT: vmov.f32 s17, s2
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: vmov.f32 s20, s5
; CHECK-NEXT: vmov.f32 s21, s7
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vmov.f32 s5, s6
+; CHECK-NEXT: @ implicit-def: $s6
; CHECK-NEXT: vmul.f32 q3, q5, q4
; CHECK-NEXT: vmul.f32 q4, q1, q4
; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s1, s3
+; CHECK-NEXT: @ implicit-def: $s3
; CHECK-NEXT: vmov q6, q4
; CHECK-NEXT: vfms.f32 q6, q5, q0
; CHECK-NEXT: vmov q7, q3
; CHECK-NEXT: vfma.f32 q3, q1, q0
; CHECK-NEXT: vmov.f32 s20, s8
; CHECK-NEXT: vmov.f32 s21, s10
+; CHECK-NEXT: @ implicit-def: $s22
+; CHECK-NEXT: @ implicit-def: $s23
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vmov.f32 s4, s9
; CHECK-NEXT: vfma.f32 q7, q5, q0
; CHECK-NEXT: vmov.f32 s5, s11
@@ -330,13 +362,21 @@ define arm_aapcs_vfpcc <4 x float> @mul_triangle_multiuses(<4 x float> %a, <4 x
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s16, s4
-; CHECK-NEXT: vmov.f32 s8, s1
+; CHECK-NEXT: @ implicit-def: $s18
+; CHECK-NEXT: @ implicit-def: $s19
+; CHECK-NEXT: @ implicit-def: $s10
+; CHECK-NEXT: @ implicit-def: $s11
; CHECK-NEXT: vmov.f32 s17, s6
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f32 s9, s3
-; CHECK-NEXT: vmov.f32 s4, s5
-; CHECK-NEXT: vmul.f32 q3, q2, q4
+; CHECK-NEXT: @ implicit-def: $s3
; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: vmul.f32 q3, q2, q4
+; CHECK-NEXT: vmov.f32 s4, s5
+; CHECK-NEXT: @ implicit-def: $s2
; CHECK-NEXT: vmov.f32 s5, s7
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vfma.f32 q3, q1, q0
; CHECK-NEXT: vmul.f32 q1, q1, q2
; CHECK-NEXT: vneg.f32 q1, q1
@@ -489,36 +529,41 @@ entry:
define <4 x float> @mul_divequal(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: mul_divequal:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d10, d11}
-; CHECK-NEXT: vpush {d10, d11}
-; CHECK-NEXT: .vsave {d8}
-; CHECK-NEXT: vpush {d8}
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov d0, r0, r1
-; CHECK-NEXT: add r0, sp, #24
-; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vmov.f32 s16, s1
-; CHECK-NEXT: add.w r12, sp, #40
-; CHECK-NEXT: vmov.f32 s12, s5
-; CHECK-NEXT: vmov.f32 s13, s7
+; CHECK-NEXT: @ implicit-def: $s14
+; CHECK-NEXT: @ implicit-def: $s15
+; CHECK-NEXT: @ implicit-def: $s18
+; CHECK-NEXT: @ implicit-def: $s19
+; CHECK-NEXT: add.w r12, sp, #48
+; CHECK-NEXT: vmov.f32 s17, s3
+; CHECK-NEXT: @ implicit-def: $s3
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vmov.f32 s1, s2
-; CHECK-NEXT: vmov.f32 s8, s4
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: vmov.f32 s12, s9
+; CHECK-NEXT: vmov.f32 s13, s11
; CHECK-NEXT: vmul.f32 q5, q3, q0
-; CHECK-NEXT: vmov.f32 s9, s6
-; CHECK-NEXT: vldrw.u32 q1, [r12]
-; CHECK-NEXT: vmov.f32 s17, s3
-; CHECK-NEXT: vfma.f32 q5, q2, q4
; CHECK-NEXT: vmul.f32 q3, q4, q3
-; CHECK-NEXT: vdiv.f32 s3, s21, s7
+; CHECK-NEXT: vmov.f32 s4, s8
; CHECK-NEXT: vneg.f32 q3, q3
-; CHECK-NEXT: vfma.f32 q3, q2, q0
-; CHECK-NEXT: vdiv.f32 s1, s20, s5
-; CHECK-NEXT: vdiv.f32 s2, s13, s6
-; CHECK-NEXT: vdiv.f32 s0, s12, s4
+; CHECK-NEXT: vmov.f32 s5, s10
+; CHECK-NEXT: vldrw.u32 q2, [r12]
+; CHECK-NEXT: vfma.f32 q3, q1, q0
+; CHECK-NEXT: vfma.f32 q5, q1, q4
+; CHECK-NEXT: vdiv.f32 s11, s21, s11
+; CHECK-NEXT: vdiv.f32 s10, s13, s10
+; CHECK-NEXT: vdiv.f32 s1, s20, s9
+; CHECK-NEXT: vdiv.f32 s0, s12, s8
; CHECK-NEXT: vmov r0, r1, d0
-; CHECK-NEXT: vmov r2, r3, d1
-; CHECK-NEXT: vpop {d8}
-; CHECK-NEXT: vpop {d10, d11}
+; CHECK-NEXT: vmov r2, r3, d5
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr
entry:
%strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
diff --git a/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll b/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
index dc67abc1be07e..b211edf9fc7cb 100644
--- a/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
@@ -33,12 +33,20 @@ define arm_aapcs_vfpcc <4 x float> @simple_mul_no_contract(<4 x float> %a, <4 x
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.f32 s8, s5
-; CHECK-NEXT: vmov.f32 s12, s1
+; CHECK-NEXT: @ implicit-def: $s10
+; CHECK-NEXT: @ implicit-def: $s11
+; CHECK-NEXT: @ implicit-def: $s14
+; CHECK-NEXT: @ implicit-def: $s15
; CHECK-NEXT: vmov.f32 s9, s7
+; CHECK-NEXT: @ implicit-def: $s7
+; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vmov.f32 s13, s3
+; CHECK-NEXT: @ implicit-def: $s3
; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: @ implicit-def: $s2
; CHECK-NEXT: vmul.f32 q4, q3, q2
; CHECK-NEXT: vmov.f32 s5, s6
+; CHECK-NEXT: @ implicit-def: $s6
; CHECK-NEXT: vmul.f32 q2, q2, q0
; CHECK-NEXT: vmul.f32 q5, q1, q0
; CHECK-NEXT: vfma.f32 q2, q1, q3
@@ -155,13 +163,21 @@ define arm_aapcs_vfpcc <4 x float> @add_external_use(<4 x float> %a, <4 x float>
; CHECK-LABEL: add_external_use:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s4
-; CHECK-NEXT: vmov.f32 s12, s1
-; CHECK-NEXT: vmov.f32 s4, s5
+; CHECK-NEXT: @ implicit-def: $s10
+; CHECK-NEXT: @ implicit-def: $s11
+; CHECK-NEXT: @ implicit-def: $s14
+; CHECK-NEXT: @ implicit-def: $s15
; CHECK-NEXT: vmov.f32 s9, s6
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vmov.f32 s13, s3
-; CHECK-NEXT: vmov.f32 s5, s7
+; CHECK-NEXT: @ implicit-def: $s3
+; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vadd.f32 q2, q3, q2
+; CHECK-NEXT: vmov.f32 s5, s7
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: @ implicit-def: $s2
; CHECK-NEXT: vsub.f32 q1, q0, q1
; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.f32 s0, s4
@@ -212,70 +228,86 @@ define arm_aapcs_vfpcc <12 x float> @abp90c12(<12 x float> %a, <12 x float> %b,
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #64
; CHECK-NEXT: sub sp, #64
-; CHECK-NEXT: vmov.f32 s21, s11
-; CHECK-NEXT: vldr s31, [sp, #140]
-; CHECK-NEXT: vmov.f32 s20, s9
-; CHECK-NEXT: vldr s30, [sp, #132]
-; CHECK-NEXT: vstrw.32 q5, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s28, s13
-; CHECK-NEXT: vmov.f32 s23, s6
+; CHECK-NEXT: vldr s23, [sp, #140]
+; CHECK-NEXT: vmov.f32 s20, s13
+; CHECK-NEXT: vldr s22, [sp, #132]
+; CHECK-NEXT: vmov.f32 s13, s11
+; CHECK-NEXT: vmov.f32 s25, s10
; CHECK-NEXT: vldr s19, [sp, #136]
-; CHECK-NEXT: vmov.f32 s6, s5
+; CHECK-NEXT: vmov.f32 s11, s6
; CHECK-NEXT: vldr s18, [sp, #128]
-; CHECK-NEXT: vmov.f32 s22, s4
-; CHECK-NEXT: vldr s27, [sp, #184]
-; CHECK-NEXT: vmov.f32 s29, s15
-; CHECK-NEXT: vldr s26, [sp, #176]
+; CHECK-NEXT: vmov.f32 s6, s5
+; CHECK-NEXT: vldr s31, [sp, #188]
+; CHECK-NEXT: vmov.f32 s10, s4
+; CHECK-NEXT: vldr s30, [sp, #180]
+; CHECK-NEXT: vmov.f32 s21, s15
+; CHECK-NEXT: vldr s29, [sp, #172]
; CHECK-NEXT: vmov.f32 s5, s3
-; CHECK-NEXT: vldr s25, [sp, #168]
+; CHECK-NEXT: vldr s28, [sp, #164]
; CHECK-NEXT: vmov.f32 s4, s1
-; CHECK-NEXT: vldr s24, [sp, #160]
+; CHECK-NEXT: vmov.f32 s24, s8
; CHECK-NEXT: vmov.f32 s16, s12
-; CHECK-NEXT: vldr s11, [sp, #188]
+; CHECK-NEXT: vstrw.32 q6, [sp, #32] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s12, s9
+; CHECK-NEXT: vldr s27, [sp, #184]
; CHECK-NEXT: vmov.f32 s17, s14
-; CHECK-NEXT: vldr s9, [sp, #172]
-; CHECK-NEXT: vmov.f32 s21, s2
-; CHECK-NEXT: vmov.f32 s20, s0
-; CHECK-NEXT: vmul.f32 q0, q7, q1
+; CHECK-NEXT: vldr s26, [sp, #176]
+; CHECK-NEXT: vmov.f32 s9, s2
+; CHECK-NEXT: vldr s25, [sp, #168]
+; CHECK-NEXT: vmov.f32 s8, s0
+; CHECK-NEXT: vmul.f32 q0, q5, q1
; CHECK-NEXT: vmul.f32 q1, q4, q1
; CHECK-NEXT: vneg.f32 q0, q0
-; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
-; CHECK-NEXT: vfma.f32 q1, q7, q5
-; CHECK-NEXT: vsub.f32 q7, q6, q1
-; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s13, s10
-; CHECK-NEXT: vldr s10, [sp, #180]
-; CHECK-NEXT: vmov.f32 s12, s8
-; CHECK-NEXT: vfma.f32 q1, q4, q5
+; CHECK-NEXT: vldr s24, [sp, #160]
; CHECK-NEXT: vstrw.32 q3, [sp, #48] @ 16-byte Spill
-; CHECK-NEXT: vldr s8, [sp, #164]
-; CHECK-NEXT: vldr s13, [sp, #156]
-; CHECK-NEXT: vldrw.u32 q5, [sp, #32] @ 16-byte Reload
-; CHECK-NEXT: vldr s12, [sp, #148]
-; CHECK-NEXT: vadd.f32 q1, q2, q1
-; CHECK-NEXT: vldr s1, [sp, #152]
-; CHECK-NEXT: vmul.f32 q2, q3, q5
-; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill
-; CHECK-NEXT: vldr s0, [sp, #144]
-; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
-; CHECK-NEXT: vneg.f32 q2, q2
-; CHECK-NEXT: vldr s25, [sp, #200]
-; CHECK-NEXT: vfma.f32 q2, q0, q3
-; CHECK-NEXT: vmul.f32 q0, q0, q5
+; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
+; CHECK-NEXT: vfma.f32 q1, q5, q2
+; CHECK-NEXT: vsub.f32 q1, q6, q1
+; CHECK-NEXT: vldrw.u32 q6, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q5, [sp] @ 16-byte Reload
-; CHECK-NEXT: vldr s24, [sp, #192]
+; CHECK-NEXT: vldr s1, [sp, #156]
+; CHECK-NEXT: vldr s0, [sp, #148]
+; CHECK-NEXT: @ implicit-def: $s26
+; CHECK-NEXT: @ implicit-def: $s27
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: @ implicit-def: $s3
+; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill
+; CHECK-NEXT: vfma.f32 q5, q4, q2
+; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload
+; CHECK-NEXT: vmul.f32 q2, q0, q6
+; CHECK-NEXT: vldr s13, [sp, #152]
+; CHECK-NEXT: vldr s12, [sp, #144]
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s7
+; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill
+; CHECK-NEXT: vneg.f32 q2, q2
+; CHECK-NEXT: @ implicit-def: $s14
+; CHECK-NEXT: @ implicit-def: $s15
+; CHECK-NEXT: vadd.f32 q5, q7, q5
+; CHECK-NEXT: vfma.f32 q2, q3, q1
+; CHECK-NEXT: vmul.f32 q0, q3, q6
+; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
+; CHECK-NEXT: vmov q7, q1
+; CHECK-NEXT: vldr s5, [sp, #200]
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s7
+; CHECK-NEXT: @ implicit-def: $s18
+; CHECK-NEXT: @ implicit-def: $s19
+; CHECK-NEXT: vldr s4, [sp, #192]
+; CHECK-NEXT: vfma.f32 q0, q3, q7
; CHECK-NEXT: vldr s17, [sp, #204]
; CHECK-NEXT: vldr s16, [sp, #196]
-; CHECK-NEXT: vfma.f32 q0, q5, q3
-; CHECK-NEXT: vsub.f32 q3, q6, q0
-; CHECK-NEXT: vmov.f32 s1, s4
+; CHECK-NEXT: vsub.f32 q3, q1, q0
+; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s1, s20
; CHECK-NEXT: vadd.f32 q4, q4, q2
-; CHECK-NEXT: vmov.f32 s3, s5
-; CHECK-NEXT: vmov.f32 s5, s6
-; CHECK-NEXT: vmov.f32 s0, s28
-; CHECK-NEXT: vmov.f32 s2, s29
-; CHECK-NEXT: vmov.f32 s4, s30
-; CHECK-NEXT: vmov.f32 s6, s31
+; CHECK-NEXT: vmov.f32 s3, s21
+; CHECK-NEXT: vmov.f32 s0, s4
+; CHECK-NEXT: vmov.f32 s2, s5
+; CHECK-NEXT: vmov.f32 s4, s6
+; CHECK-NEXT: vmov.f32 s6, s7
+; CHECK-NEXT: vmov.f32 s5, s22
+; CHECK-NEXT: vmov.f32 s7, s23
; CHECK-NEXT: vmov.f32 s8, s12
; CHECK-NEXT: vmov.f32 s9, s16
; CHECK-NEXT: vmov.f32 s10, s13
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
index 67250d5a05d4f..3b7786beb9c53 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
@@ -183,8 +183,10 @@ define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
;
; CHECK-MVEFP-LABEL: test_signed_v6f32_v6i32:
; CHECK-MVEFP: @ %bb.0:
-; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
+; CHECK-MVEFP-NEXT: @ implicit-def: $s6
+; CHECK-MVEFP-NEXT: @ implicit-def: $s7
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
+; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vmov r1, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
@@ -218,8 +220,9 @@ define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
;
; CHECK-MVEFP-LABEL: test_signed_v7f32_v7i32:
; CHECK-MVEFP: @ %bb.0:
-; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
+; CHECK-MVEFP-NEXT: @ implicit-def: $s7
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
+; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vmov r1, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r3, s6
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
index 4602a5d6dd44c..667242bcae0b2 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
@@ -170,8 +170,10 @@ define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
;
; CHECK-MVEFP-LABEL: test_unsigned_v6f32_v6i32:
; CHECK-MVEFP: @ %bb.0:
-; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
+; CHECK-MVEFP-NEXT: @ implicit-def: $s6
+; CHECK-MVEFP-NEXT: @ implicit-def: $s7
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
+; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vmov r1, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
@@ -205,8 +207,9 @@ define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
;
; CHECK-MVEFP-LABEL: test_unsigned_v7f32_v7i32:
; CHECK-MVEFP: @ %bb.0:
-; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
+; CHECK-MVEFP-NEXT: @ implicit-def: $s7
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
+; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vmov r1, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r3, s6
diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll b/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
index b45cca7e1b4c5..64932a8e9a251 100644
--- a/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
@@ -113,6 +113,8 @@ define arm_aapcs_vfpcc <2 x float> @ptr_v2f32(ptr %offptr) {
; CHECK-LABEL: ptr_v2f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r0, r1, [r0]
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: @ implicit-def: $s3
; CHECK-NEXT: vldr s1, [r1]
; CHECK-NEXT: vldr s0, [r0]
; CHECK-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
index 577c78309cd48..8e5c5d5d4debb 100644
--- a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
@@ -9,13 +9,17 @@ define arm_aapcs_vfpcc <4 x i32> @loads_i32(ptr %A, ptr %B, ptr %C) {
; CHECK-NEXT: vldrw.u32 q3, [r1]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
+; CHECK-NEXT: @ implicit-def: $s1
+; CHECK-NEXT: @ implicit-def: $s3
; CHECK-NEXT: vmov.f32 s0, s12
; CHECK-NEXT: vmov.f32 s2, s13
+; CHECK-NEXT: @ implicit-def: $s13
; CHECK-NEXT: vmov lr, r0, d2
; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov r1, r5, d1
; CHECK-NEXT: vmov.f32 s12, s14
; CHECK-NEXT: vmov.f32 s14, s15
+; CHECK-NEXT: @ implicit-def: $s15
; CHECK-NEXT: vand q2, q3, q2
; CHECK-NEXT: vmov r4, r3, d5
; CHECK-NEXT: asrs r6, r0, #31
@@ -135,8 +139,11 @@ define arm_aapcs_vfpcc void @load_store_i32(ptr %A, ptr %B, ptr %C, ptr %D) {
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vmov.i64 q0, #0xffffffff
+; CHECK-NEXT: @ implicit-def: $s9
+; CHECK-NEXT: @ implicit-def: $s11
; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s10, s7
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov r1, r12, d5
@@ -352,6 +359,8 @@ define arm_aapcs_vfpcc void @mul_i32(ptr %A, ptr %B, i64 %C, ptr %D) {
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: ldr.w lr, [sp, #20]
; CHECK-NEXT: vmov.f32 s10, s1
+; CHECK-NEXT: @ implicit-def: $s1
+; CHECK-NEXT: @ implicit-def: $s1
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov r5, s4
; CHECK-NEXT: vmov.f32 s4, s6
diff --git a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
index fe5d7f29f01ff..926f840d221c5 100644
--- a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
@@ -184,13 +184,16 @@ define arm_aapcs_vfpcc <4 x i32> @ext_add_ashr_trunc_i32(<4 x i32> %a, <4 x i32>
; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: vmov.f32 s12, s6
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
-; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov.f32 s14, s7
+; CHECK-NEXT: @ implicit-def: $s7
+; CHECK-NEXT: @ implicit-def: $s13
+; CHECK-NEXT: @ implicit-def: $s15
+; CHECK-NEXT: vmov.f32 s6, s5
+; CHECK-NEXT: vand q3, q3, q2
; CHECK-NEXT: vand q1, q1, q2
+; CHECK-NEXT: vmov r0, r1, d6
; CHECK-NEXT: vmov r3, r7, d2
-; CHECK-NEXT: vand q3, q3, q2
; CHECK-NEXT: vmov.f32 s4, s2
-; CHECK-NEXT: vmov r0, r1, d6
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov lr, r12, d7
; CHECK-NEXT: vmov r2, s4
@@ -303,6 +306,8 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: vmov.f32 s12, s2
+; CHECK-NEXT: @ implicit-def: $s9
+; CHECK-NEXT: @ implicit-def: $s11
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s8, s6
@@ -345,49 +350,49 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: rsb.w r1, r10, #0
; CHECK-NEXT: lsll r4, r5, r3
; CHECK-NEXT: lsll r0, r7, r1
+; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: lsll r0, r7, r2
-; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov q3[2], q3[0], r4, r0
-; CHECK-NEXT: vmov r0, s2
+; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov q3[3], q3[1], r5, r7
+; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vpsel q2, q3, q2
-; CHECK-NEXT: adds r4, r0, r1
-; CHECK-NEXT: asr.w r2, r0, #31
-; CHECK-NEXT: adc r3, r2, #0
-; CHECK-NEXT: asrl r4, r3, r1
-; CHECK-NEXT: subs r2, r4, r1
-; CHECK-NEXT: vmov r4, s0
-; CHECK-NEXT: sbc r8, r3, #0
-; CHECK-NEXT: vmov r3, s4
-; CHECK-NEXT: umull r2, lr, r2, r1
-; CHECK-NEXT: adds r6, r4, r3
-; CHECK-NEXT: asr.w r5, r4, #31
+; CHECK-NEXT: adds r2, r3, r1
+; CHECK-NEXT: asr.w r0, r3, #31
+; CHECK-NEXT: adc r5, r0, #0
+; CHECK-NEXT: asrl r2, r5, r1
+; CHECK-NEXT: subs r0, r2, r1
+; CHECK-NEXT: sbc r8, r5, #0
+; CHECK-NEXT: asrs r5, r4, #31
+; CHECK-NEXT: umull r2, lr, r0, r1
+; CHECK-NEXT: vmov r0, s4
+; CHECK-NEXT: adds r6, r4, r0
; CHECK-NEXT: adc r7, r5, #0
; CHECK-NEXT: mla r5, r8, r1, lr
-; CHECK-NEXT: asrl r6, r7, r3
-; CHECK-NEXT: subs.w r8, r6, r3
-; CHECK-NEXT: eor.w r6, r4, r3
+; CHECK-NEXT: asrl r6, r7, r0
+; CHECK-NEXT: subs.w r8, r6, r0
+; CHECK-NEXT: eor.w r6, r4, r0
; CHECK-NEXT: sbc lr, r7, #0
-; CHECK-NEXT: eor.w r7, r0, r1
+; CHECK-NEXT: eor.w r7, r3, r1
; CHECK-NEXT: orrs.w r6, r6, r4, asr #31
-; CHECK-NEXT: orr.w r7, r7, r0, asr #31
+; CHECK-NEXT: orr.w r7, r7, r3, asr #31
; CHECK-NEXT: csetm r6, eq
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: bfi r12, r6, #0, #8
; CHECK-NEXT: csetm r6, eq
; CHECK-NEXT: bfi r12, r6, #8, #8
-; CHECK-NEXT: umull r6, r7, r8, r3
-; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: lsll r2, r5, r0
-; CHECK-NEXT: rsbs r0, r4, #0
-; CHECK-NEXT: mla r7, lr, r3, r7
-; CHECK-NEXT: lsll r2, r5, r1
+; CHECK-NEXT: umull r6, r7, r8, r0
+; CHECK-NEXT: rsb.w r8, r3, #0
+; CHECK-NEXT: lsll r2, r5, r8
; CHECK-NEXT: vmsr p0, r12
-; CHECK-NEXT: lsll r6, r7, r0
-; CHECK-NEXT: lsll r6, r7, r3
+; CHECK-NEXT: mla r3, lr, r0, r7
+; CHECK-NEXT: lsll r2, r5, r1
+; CHECK-NEXT: rsbs r1, r4, #0
+; CHECK-NEXT: lsll r6, r3, r1
+; CHECK-NEXT: lsll r6, r3, r0
; CHECK-NEXT: vmov q0[2], q0[0], r6, r2
-; CHECK-NEXT: vmov q0[3], q0[1], r7, r5
+; CHECK-NEXT: vmov q0[3], q0[1], r3, r5
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s8
diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-load.ll b/llvm/test/CodeGen/Thumb2/mve-masked-load.ll
index b0a3a6354daa7..74cd04914072a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-masked-load.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-masked-load.ll
@@ -1240,9 +1240,14 @@ define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align1_undef(ptr %dest, <4 x i3
; CHECK-LE-NEXT: rsbs r2, r2, #0
; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: lsls r2, r1, #31
-; CHECK-LE-NEXT: itt ne
-; CHECK-LE-NEXT: ldrne r2, [r0]
-; CHECK-LE-NEXT: vmovne s0, r2
+; CHECK-LE-NEXT: beq .LBB39_2
+; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
+; CHECK-LE-NEXT: ldr r2, [r0]
+; CHECK-LE-NEXT: @ implicit-def: $s1
+; CHECK-LE-NEXT: @ implicit-def: $s2
+; CHECK-LE-NEXT: @ implicit-def: $s3
+; CHECK-LE-NEXT: vmov s0, r2
+; CHECK-LE-NEXT: .LBB39_2: @ %else
; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: ldrmi r2, [r0, #4]
@@ -1280,9 +1285,14 @@ define arm_aapcs_vfpcc <4 x float> @masked_v4f32_align1_undef(ptr %dest, <4 x i3
; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: lsls r2, r1, #28
-; CHECK-BE-NEXT: itt mi
-; CHECK-BE-NEXT: ldrmi r2, [r0]
-; CHECK-BE-NEXT: vmovmi s4, r2
+; CHECK-BE-NEXT: bpl .LBB39_2
+; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
+; CHECK-BE-NEXT: ldr r2, [r0]
+; CHECK-BE-NEXT: @ implicit-def: $s5
+; CHECK-BE-NEXT: @ implicit-def: $s6
+; CHECK-BE-NEXT: @ implicit-def: $s7
+; CHECK-BE-NEXT: vmov s4, r2
+; CHECK-BE-NEXT: .LBB39_2: @ %else
; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: ldrmi r2, [r0, #4]
diff --git a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
index 40d534a0ebfc5..32e370d137a9f 100644
--- a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
@@ -229,14 +229,16 @@ define arm_aapcs_vfpcc void @ssatmul_4_q31(ptr nocapture readonly %pSrcA, ptr no
; CHECK-NEXT: vldrw.u32 q1, [r4]
; CHECK-NEXT: .LBB1_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vldrw.u32 q3, [r5], #16
+; CHECK-NEXT: @ implicit-def: $s13
; CHECK-NEXT: vldrw.u32 q2, [r0], #16
+; CHECK-NEXT: @ implicit-def: $s17
; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: vldrw.u32 q3, [r5], #16
; CHECK-NEXT: mov.w r2, #-1
; CHECK-NEXT: vmov.f32 s16, s10
-; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: mov.w r8, #0
+; CHECK-NEXT: vmov.f32 s20, s14
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: vmov.f32 s18, s11
; CHECK-NEXT: vmov.f32 s22, s15
; CHECK-NEXT: vmullb.s32 q6, q5, q4
@@ -461,6 +463,8 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(ptr nocapture readonly %pSrcA, ptr n
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vdup.32 q4, r9
+; CHECK-NEXT: @ implicit-def: $s21
+; CHECK-NEXT: @ implicit-def: $s25
; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: add.w r9, r9, #4
; CHECK-NEXT: vorr q4, q4, q0
@@ -786,9 +790,11 @@ define arm_aapcs_vfpcc void @usatmul_4_q31(ptr nocapture readonly %pSrcA, ptr no
; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: .LBB4_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: @ implicit-def: $s9
; CHECK-NEXT: vldrw.u32 q1, [r0], #16
-; CHECK-NEXT: vldrw.u32 q2, [r1], #16
+; CHECK-NEXT: @ implicit-def: $s13
; CHECK-NEXT: movs r6, #0
+; CHECK-NEXT: vldrw.u32 q2, [r1], #16
; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: vmov.f32 s12, s6
; CHECK-NEXT: vmov.f32 s14, s7
diff --git a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
index d01734e3c1358..47e8466bb1f2c 100644
--- a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
@@ -133,25 +133,47 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @shuffle3step_i32(<16 x i32> %src) {
-; CHECK-LABEL: shuffle3step_i32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9}
-; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: vmov.f32 s13, s4
-; CHECK-NEXT: vmov.f32 s14, s7
-; CHECK-NEXT: vmov.f32 s18, s6
-; CHECK-NEXT: vmov.f32 s12, s1
-; CHECK-NEXT: vmov.f32 s15, s10
-; CHECK-NEXT: vmov.f32 s16, s0
-; CHECK-NEXT: vmov.f32 s17, s3
-; CHECK-NEXT: vmov.f32 s19, s9
-; CHECK-NEXT: vadd.i32 q3, q4, q3
-; CHECK-NEXT: vmov.f32 s4, s2
-; CHECK-NEXT: vmov.f32 s6, s8
-; CHECK-NEXT: vmov.f32 s7, s11
-; CHECK-NEXT: vadd.i32 q0, q3, q1
-; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: bx lr
+; CHECK-LV-LABEL: shuffle3step_i32:
+; CHECK-LV: @ %bb.0: @ %entry
+; CHECK-LV-NEXT: .vsave {d8, d9}
+; CHECK-LV-NEXT: vpush {d8, d9}
+; CHECK-LV-NEXT: vmov.f32 s13, s4
+; CHECK-LV-NEXT: vmov.f32 s14, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s17, s3
+; CHECK-LV-NEXT: @ implicit-def: $s3
+; CHECK-LV-NEXT: vmov.f32 s18, s6
+; CHECK-LV-NEXT: vmov.f32 s12, s1
+; CHECK-LV-NEXT: vmov.f32 s15, s10
+; CHECK-LV-NEXT: vmov.f32 s16, s0
+; CHECK-LV-NEXT: vmov.f32 s19, s9
+; CHECK-LV-NEXT: vadd.i32 q3, q4, q3
+; CHECK-LV-NEXT: vmov.f32 s4, s2
+; CHECK-LV-NEXT: vmov.f32 s6, s8
+; CHECK-LV-NEXT: vmov.f32 s7, s11
+; CHECK-LV-NEXT: vadd.i32 q0, q3, q1
+; CHECK-LV-NEXT: vpop {d8, d9}
+; CHECK-LV-NEXT: bx lr
+;
+; CHECK-LIS-LABEL: shuffle3step_i32:
+; CHECK-LIS: @ %bb.0: @ %entry
+; CHECK-LIS-NEXT: .vsave {d8, d9}
+; CHECK-LIS-NEXT: vpush {d8, d9}
+; CHECK-LIS-NEXT: vmov.f32 s13, s4
+; CHECK-LIS-NEXT: vmov.f32 s14, s7
+; CHECK-LIS-NEXT: vmov.f32 s18, s6
+; CHECK-LIS-NEXT: vmov.f32 s12, s1
+; CHECK-LIS-NEXT: vmov.f32 s15, s10
+; CHECK-LIS-NEXT: vmov.f32 s16, s0
+; CHECK-LIS-NEXT: vmov.f32 s17, s3
+; CHECK-LIS-NEXT: vmov.f32 s19, s9
+; CHECK-LIS-NEXT: vadd.i32 q3, q4, q3
+; CHECK-LIS-NEXT: vmov.f32 s4, s2
+; CHECK-LIS-NEXT: vmov.f32 s6, s8
+; CHECK-LIS-NEXT: vmov.f32 s7, s11
+; CHECK-LIS-NEXT: vadd.i32 q0, q3, q1
+; CHECK-LIS-NEXT: vpop {d8, d9}
+; CHECK-LIS-NEXT: bx lr
entry:
%s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
@@ -1100,26 +1122,6 @@ define arm_aapcs_vfpcc <4 x float> @shuffle3step_f32(<16 x float> %src) {
; CHECKFP16-NEXT: vadd.f32 s4, s0, s2
; CHECKFP16-NEXT: vmov q0, q1
; CHECKFP16-NEXT: bx lr
-;
-; CHECKFP-LABEL: shuffle3step_f32:
-; CHECKFP: @ %bb.0: @ %entry
-; CHECKFP-NEXT: .vsave {d8, d9}
-; CHECKFP-NEXT: vpush {d8, d9}
-; CHECKFP-NEXT: vmov.f32 s13, s4
-; CHECKFP-NEXT: vmov.f32 s14, s7
-; CHECKFP-NEXT: vmov.f32 s18, s6
-; CHECKFP-NEXT: vmov.f32 s12, s1
-; CHECKFP-NEXT: vmov.f32 s15, s10
-; CHECKFP-NEXT: vmov.f32 s16, s0
-; CHECKFP-NEXT: vmov.f32 s17, s3
-; CHECKFP-NEXT: vmov.f32 s19, s9
-; CHECKFP-NEXT: vadd.f32 q3, q4, q3
-; CHECKFP-NEXT: vmov.f32 s4, s2
-; CHECKFP-NEXT: vmov.f32 s6, s8
-; CHECKFP-NEXT: vmov.f32 s7, s11
-; CHECKFP-NEXT: vadd.f32 q0, q3, q1
-; CHECKFP-NEXT: vpop {d8, d9}
-; CHECKFP-NEXT: bx lr
entry:
%s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
diff --git a/llvm/test/CodeGen/Thumb2/mve-vabdus.ll b/llvm/test/CodeGen/Thumb2/mve-vabdus.ll
index dc0a33f483b36..83c2fa43fcedb 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vabdus.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vabdus.ll
@@ -533,22 +533,28 @@ define void @vabd_loop_u32(ptr nocapture readonly %x, ptr nocapture readonly %y,
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q6, [r0], #16
; CHECK-NEXT: vldrw.u32 q5, [r1], #16
-; CHECK-NEXT: vmov.f32 s12, s22
+; CHECK-NEXT: @ implicit-def: $s9
+; CHECK-NEXT: @ implicit-def: $s11
+; CHECK-NEXT: @ implicit-def: $s17
+; CHECK-NEXT: @ implicit-def: $s19
+; CHECK-NEXT: vmov.f32 s8, s22
; CHECK-NEXT: vmov.f32 s16, s26
; CHECK-NEXT: vmov r4, s24
-; CHECK-NEXT: vmov.f32 s14, s23
+; CHECK-NEXT: vmov.f32 s10, s23
+; CHECK-NEXT: @ implicit-def: $s23
; CHECK-NEXT: vmov.f32 s18, s27
+; CHECK-NEXT: @ implicit-def: $s27
; CHECK-NEXT: vmov.f32 s22, s21
; CHECK-NEXT: vmov.f32 s26, s25
-; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vmov r12, s8
; CHECK-NEXT: vmov r3, s16
; CHECK-NEXT: sub.w r12, r3, r12
; CHECK-NEXT: vmov r3, s20
; CHECK-NEXT: subs r3, r4, r3
; CHECK-NEXT: vmov r4, s18
-; CHECK-NEXT: vmov q2[2], q2[0], r3, r12
-; CHECK-NEXT: vmov r3, s14
-; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vmov q3[2], q3[0], r3, r12
+; CHECK-NEXT: vmov r3, s10
+; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vand q4, q4, q0
; CHECK-NEXT: sub.w r12, r4, r3
; CHECK-NEXT: vmov r4, s22
@@ -557,7 +563,7 @@ define void @vabd_loop_u32(ptr nocapture readonly %x, ptr nocapture readonly %y,
; CHECK-NEXT: vand q6, q6, q0
; CHECK-NEXT: subs r3, r3, r4
; CHECK-NEXT: vmov r4, r5, d12
-; CHECK-NEXT: vmov q2[3], q2[1], r3, r12
+; CHECK-NEXT: vmov q3[3], q3[1], r3, r12
; CHECK-NEXT: vmov r3, r12, d10
; CHECK-NEXT: subs r3, r4, r3
; CHECK-NEXT: vmov r4, r6, d13
@@ -571,21 +577,21 @@ define void @vabd_loop_u32(ptr nocapture readonly %x, ptr nocapture readonly %y,
; CHECK-NEXT: vmov r4, r5, d8
; CHECK-NEXT: csetm r6, lt
; CHECK-NEXT: bfi r3, r6, #4, #4
-; CHECK-NEXT: vmov r6, r12, d6
+; CHECK-NEXT: vmov r6, r12, d4
; CHECK-NEXT: subs r4, r4, r6
; CHECK-NEXT: sbcs.w r6, r5, r12
; CHECK-NEXT: vmov r4, r5, d9
; CHECK-NEXT: csetm r6, lt
; CHECK-NEXT: bfi r3, r6, #8, #4
-; CHECK-NEXT: vmov r6, r12, d7
+; CHECK-NEXT: vmov r6, r12, d5
; CHECK-NEXT: subs r4, r4, r6
; CHECK-NEXT: sbcs.w r6, r5, r12
; CHECK-NEXT: csetm r6, lt
; CHECK-NEXT: bfi r3, r6, #12, #4
; CHECK-NEXT: vmsr p0, r3
; CHECK-NEXT: vpst
-; CHECK-NEXT: vsubt.i32 q2, q1, q2
-; CHECK-NEXT: vstrb.8 q2, [r2], #16
+; CHECK-NEXT: vsubt.i32 q3, q1, q3
+; CHECK-NEXT: vstrb.8 q3, [r2], #16
; CHECK-NEXT: le lr, .LBB20_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vld2.ll b/llvm/test/CodeGen/Thumb2/mve-vld2.ll
index dca4fb3d6cfa3..7729fce03b11d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vld2.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vld2.ll
@@ -395,9 +395,13 @@ define void @vld2_v2f32(ptr %src, ptr %dst) {
; CHECK-LABEL: vld2_v2f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s7
; CHECK-NEXT: vmov.f32 s4, s1
; CHECK-NEXT: vmov.f32 s5, s3
+; CHECK-NEXT: @ implicit-def: $s3
; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: @ implicit-def: $s2
; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vstmia r1, {s0, s1}
; CHECK-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-vld3.ll b/llvm/test/CodeGen/Thumb2/mve-vld3.ll
index b919873c02bf9..e6ce1fa2ba286 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vld3.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vld3.ll
@@ -31,29 +31,55 @@ entry:
}
define void @vld3_v4i32(ptr %src, ptr %dst) {
-; CHECK-LABEL: vld3_v4i32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9}
-; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
-; CHECK-NEXT: vldrw.u32 q1, [r0]
-; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
-; CHECK-NEXT: vmov.f32 s10, s2
-; CHECK-NEXT: vmov.f32 s13, s0
-; CHECK-NEXT: vmov.f32 s14, s3
-; CHECK-NEXT: vmov.f32 s8, s4
-; CHECK-NEXT: vmov.f32 s9, s7
-; CHECK-NEXT: vmov.f32 s12, s5
-; CHECK-NEXT: vmov.f32 s15, s18
-; CHECK-NEXT: vmov.f32 s11, s17
-; CHECK-NEXT: vadd.i32 q2, q2, q3
-; CHECK-NEXT: vmov.f32 s0, s6
-; CHECK-NEXT: vmov.f32 s2, s16
-; CHECK-NEXT: vmov.f32 s3, s19
-; CHECK-NEXT: vadd.i32 q0, q2, q0
-; CHECK-NEXT: vstrw.32 q0, [r1]
-; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: bx lr
+; CHECK-LV-LABEL: vld3_v4i32:
+; CHECK-LV: @ %bb.0: @ %entry
+; CHECK-LV-NEXT: .vsave {d8, d9}
+; CHECK-LV-NEXT: vpush {d8, d9}
+; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #16]
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0]
+; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #32]
+; CHECK-LV-NEXT: vmov.f32 s9, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s10, s2
+; CHECK-LV-NEXT: vmov.f32 s13, s0
+; CHECK-LV-NEXT: vmov.f32 s14, s3
+; CHECK-LV-NEXT: @ implicit-def: $s3
+; CHECK-LV-NEXT: vmov.f32 s8, s4
+; CHECK-LV-NEXT: vmov.f32 s12, s5
+; CHECK-LV-NEXT: vmov.f32 s15, s18
+; CHECK-LV-NEXT: vmov.f32 s11, s17
+; CHECK-LV-NEXT: vadd.i32 q2, q2, q3
+; CHECK-LV-NEXT: vmov.f32 s0, s6
+; CHECK-LV-NEXT: vmov.f32 s2, s16
+; CHECK-LV-NEXT: vmov.f32 s3, s19
+; CHECK-LV-NEXT: vadd.i32 q0, q2, q0
+; CHECK-LV-NEXT: vstrw.32 q0, [r1]
+; CHECK-LV-NEXT: vpop {d8, d9}
+; CHECK-LV-NEXT: bx lr
+;
+; CHECK-LIS-LABEL: vld3_v4i32:
+; CHECK-LIS: @ %bb.0: @ %entry
+; CHECK-LIS-NEXT: .vsave {d8, d9}
+; CHECK-LIS-NEXT: vpush {d8, d9}
+; CHECK-LIS-NEXT: vldrw.u32 q0, [r0, #16]
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0]
+; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #32]
+; CHECK-LIS-NEXT: vmov.f32 s10, s2
+; CHECK-LIS-NEXT: vmov.f32 s13, s0
+; CHECK-LIS-NEXT: vmov.f32 s14, s3
+; CHECK-LIS-NEXT: vmov.f32 s8, s4
+; CHECK-LIS-NEXT: vmov.f32 s9, s7
+; CHECK-LIS-NEXT: vmov.f32 s12, s5
+; CHECK-LIS-NEXT: vmov.f32 s15, s18
+; CHECK-LIS-NEXT: vmov.f32 s11, s17
+; CHECK-LIS-NEXT: vadd.i32 q2, q2, q3
+; CHECK-LIS-NEXT: vmov.f32 s0, s6
+; CHECK-LIS-NEXT: vmov.f32 s2, s16
+; CHECK-LIS-NEXT: vmov.f32 s3, s19
+; CHECK-LIS-NEXT: vadd.i32 q0, q2, q0
+; CHECK-LIS-NEXT: vstrw.32 q0, [r1]
+; CHECK-LIS-NEXT: vpop {d8, d9}
+; CHECK-LIS-NEXT: bx lr
entry:
%l1 = load <12 x i32>, ptr %src, align 4
@@ -67,46 +93,91 @@ entry:
}
define void @vld3_v8i32(ptr %src, ptr %dst) {
-; CHECK-LABEL: vld3_v8i32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9, d10, d11}
-; CHECK-NEXT: vpush {d8, d9, d10, d11}
-; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
-; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
-; CHECK-NEXT: vmov.f32 s10, s2
-; CHECK-NEXT: vmov.f32 s13, s0
-; CHECK-NEXT: vmov.f32 s14, s3
-; CHECK-NEXT: vmov.f32 s8, s4
-; CHECK-NEXT: vmov.f32 s9, s7
-; CHECK-NEXT: vmov.f32 s12, s5
-; CHECK-NEXT: vmov.f32 s15, s18
-; CHECK-NEXT: vmov.f32 s11, s17
-; CHECK-NEXT: vadd.i32 q2, q2, q3
-; CHECK-NEXT: vmov.f32 s0, s6
-; CHECK-NEXT: vmov.f32 s2, s16
-; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
-; CHECK-NEXT: vmov.f32 s3, s19
-; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
-; CHECK-NEXT: vadd.i32 q0, q2, q0
-; CHECK-NEXT: vldrw.u32 q2, [r0]
-; CHECK-NEXT: vmov.f32 s17, s4
-; CHECK-NEXT: vstrw.32 q0, [r1, #16]
-; CHECK-NEXT: vmov.f32 s18, s7
-; CHECK-NEXT: vmov.f32 s22, s6
-; CHECK-NEXT: vmov.f32 s16, s9
-; CHECK-NEXT: vmov.f32 s19, s14
-; CHECK-NEXT: vmov.f32 s20, s8
-; CHECK-NEXT: vmov.f32 s21, s11
-; CHECK-NEXT: vmov.f32 s23, s13
-; CHECK-NEXT: vadd.i32 q4, q5, q4
-; CHECK-NEXT: vmov.f32 s4, s10
-; CHECK-NEXT: vmov.f32 s6, s12
-; CHECK-NEXT: vmov.f32 s7, s15
-; CHECK-NEXT: vadd.i32 q1, q4, q1
-; CHECK-NEXT: vstrw.32 q1, [r1]
-; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: bx lr
+; CHECK-LV-LABEL: vld3_v8i32:
+; CHECK-LV: @ %bb.0: @ %entry
+; CHECK-LV-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-LV-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #80]
+; CHECK-LV-NEXT: vmov.f32 s9, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s10, s2
+; CHECK-LV-NEXT: vmov.f32 s13, s0
+; CHECK-LV-NEXT: vmov.f32 s14, s3
+; CHECK-LV-NEXT: @ implicit-def: $s3
+; CHECK-LV-NEXT: vmov.f32 s8, s4
+; CHECK-LV-NEXT: vmov.f32 s12, s5
+; CHECK-LV-NEXT: vmov.f32 s15, s18
+; CHECK-LV-NEXT: vmov.f32 s11, s17
+; CHECK-LV-NEXT: vadd.i32 q2, q2, q3
+; CHECK-LV-NEXT: vmov.f32 s0, s6
+; CHECK-LV-NEXT: vmov.f32 s2, s16
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-LV-NEXT: vmov.f32 s3, s19
+; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-LV-NEXT: vadd.i32 q0, q2, q0
+; CHECK-LV-NEXT: vldrw.u32 q2, [r0]
+; CHECK-LV-NEXT: vmov.f32 s18, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-LV-NEXT: vmov.f32 s17, s4
+; CHECK-LV-NEXT: vmov.f32 s22, s6
+; CHECK-LV-NEXT: vmov.f32 s16, s9
+; CHECK-LV-NEXT: vmov.f32 s19, s14
+; CHECK-LV-NEXT: vmov.f32 s20, s8
+; CHECK-LV-NEXT: vmov.f32 s21, s11
+; CHECK-LV-NEXT: vmov.f32 s23, s13
+; CHECK-LV-NEXT: vadd.i32 q4, q5, q4
+; CHECK-LV-NEXT: vmov.f32 s4, s10
+; CHECK-LV-NEXT: vmov.f32 s6, s12
+; CHECK-LV-NEXT: vmov.f32 s7, s15
+; CHECK-LV-NEXT: vadd.i32 q1, q4, q1
+; CHECK-LV-NEXT: vstrw.32 q1, [r1]
+; CHECK-LV-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-LV-NEXT: bx lr
+;
+; CHECK-LIS-LABEL: vld3_v8i32:
+; CHECK-LIS: @ %bb.0: @ %entry
+; CHECK-LIS-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-LIS-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-LIS-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #80]
+; CHECK-LIS-NEXT: vmov.f32 s10, s2
+; CHECK-LIS-NEXT: vmov.f32 s13, s0
+; CHECK-LIS-NEXT: vmov.f32 s14, s3
+; CHECK-LIS-NEXT: vmov.f32 s8, s4
+; CHECK-LIS-NEXT: vmov.f32 s9, s7
+; CHECK-LIS-NEXT: vmov.f32 s12, s5
+; CHECK-LIS-NEXT: vmov.f32 s15, s18
+; CHECK-LIS-NEXT: vmov.f32 s11, s17
+; CHECK-LIS-NEXT: vadd.i32 q2, q2, q3
+; CHECK-LIS-NEXT: vmov.f32 s0, s6
+; CHECK-LIS-NEXT: vmov.f32 s2, s16
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-LIS-NEXT: vmov.f32 s3, s19
+; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-LIS-NEXT: vadd.i32 q0, q2, q0
+; CHECK-LIS-NEXT: vldrw.u32 q2, [r0]
+; CHECK-LIS-NEXT: vmov.f32 s17, s4
+; CHECK-LIS-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-LIS-NEXT: vmov.f32 s18, s7
+; CHECK-LIS-NEXT: vmov.f32 s22, s6
+; CHECK-LIS-NEXT: vmov.f32 s16, s9
+; CHECK-LIS-NEXT: vmov.f32 s19, s14
+; CHECK-LIS-NEXT: vmov.f32 s20, s8
+; CHECK-LIS-NEXT: vmov.f32 s21, s11
+; CHECK-LIS-NEXT: vmov.f32 s23, s13
+; CHECK-LIS-NEXT: vadd.i32 q4, q5, q4
+; CHECK-LIS-NEXT: vmov.f32 s4, s10
+; CHECK-LIS-NEXT: vmov.f32 s6, s12
+; CHECK-LIS-NEXT: vmov.f32 s7, s15
+; CHECK-LIS-NEXT: vadd.i32 q1, q4, q1
+; CHECK-LIS-NEXT: vstrw.32 q1, [r1]
+; CHECK-LIS-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-LIS-NEXT: bx lr
entry:
%l1 = load <24 x i32>, ptr %src, align 4
@@ -120,80 +191,163 @@ entry:
}
define void @vld3_v16i32(ptr %src, ptr %dst) {
-; CHECK-LABEL: vld3_v16i32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
-; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
-; CHECK-NEXT: vldrw.u32 q6, [r0, #176]
-; CHECK-NEXT: vmov.f32 s10, s2
-; CHECK-NEXT: vmov.f32 s13, s0
-; CHECK-NEXT: vmov.f32 s14, s3
-; CHECK-NEXT: vmov.f32 s8, s4
-; CHECK-NEXT: vmov.f32 s9, s7
-; CHECK-NEXT: vmov.f32 s12, s5
-; CHECK-NEXT: vmov.f32 s15, s18
-; CHECK-NEXT: vmov.f32 s11, s17
-; CHECK-NEXT: vadd.i32 q2, q2, q3
-; CHECK-NEXT: vmov.f32 s0, s6
-; CHECK-NEXT: vmov.f32 s2, s16
-; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
-; CHECK-NEXT: vmov.f32 s3, s19
-; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
-; CHECK-NEXT: vadd.i32 q0, q2, q0
-; CHECK-NEXT: vldrw.u32 q2, [r0]
-; CHECK-NEXT: vmov.f32 s17, s4
-; CHECK-NEXT: vmov.f32 s18, s7
-; CHECK-NEXT: vmov.f32 s22, s6
-; CHECK-NEXT: vmov.f32 s16, s9
-; CHECK-NEXT: vmov.f32 s19, s14
-; CHECK-NEXT: vmov.f32 s20, s8
-; CHECK-NEXT: vmov.f32 s21, s11
-; CHECK-NEXT: vmov.f32 s23, s13
-; CHECK-NEXT: vmov.f32 s4, s10
-; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
-; CHECK-NEXT: vmov.f32 s6, s12
-; CHECK-NEXT: vadd.i32 q4, q5, q4
-; CHECK-NEXT: vmov.f32 s7, s15
-; CHECK-NEXT: vldrw.u32 q3, [r0, #144]
-; CHECK-NEXT: vadd.i32 q1, q4, q1
-; CHECK-NEXT: vmov.f32 s18, s10
-; CHECK-NEXT: vmov.f32 s21, s8
-; CHECK-NEXT: vmov.f32 s22, s11
-; CHECK-NEXT: vmov.f32 s16, s12
-; CHECK-NEXT: vmov.f32 s17, s15
-; CHECK-NEXT: vmov.f32 s20, s13
-; CHECK-NEXT: vmov.f32 s23, s26
-; CHECK-NEXT: vmov.f32 s19, s25
-; CHECK-NEXT: vadd.i32 q4, q4, q5
-; CHECK-NEXT: vmov.f32 s8, s14
-; CHECK-NEXT: vmov.f32 s10, s24
-; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
-; CHECK-NEXT: vmov.f32 s11, s27
-; CHECK-NEXT: vldrw.u32 q5, [r0, #128]
-; CHECK-NEXT: vadd.i32 q2, q4, q2
-; CHECK-NEXT: vldrw.u32 q4, [r0, #96]
-; CHECK-NEXT: vmov.f32 s25, s12
-; CHECK-NEXT: vstrw.32 q2, [r1, #48]
-; CHECK-NEXT: vmov.f32 s26, s15
-; CHECK-NEXT: vstrw.32 q0, [r1, #16]
-; CHECK-NEXT: vmov.f32 s30, s14
-; CHECK-NEXT: vstrw.32 q1, [r1]
-; CHECK-NEXT: vmov.f32 s24, s17
-; CHECK-NEXT: vmov.f32 s27, s22
-; CHECK-NEXT: vmov.f32 s28, s16
-; CHECK-NEXT: vmov.f32 s29, s19
-; CHECK-NEXT: vmov.f32 s31, s21
-; CHECK-NEXT: vadd.i32 q6, q7, q6
-; CHECK-NEXT: vmov.f32 s12, s18
-; CHECK-NEXT: vmov.f32 s14, s20
-; CHECK-NEXT: vmov.f32 s15, s23
-; CHECK-NEXT: vadd.i32 q3, q6, q3
-; CHECK-NEXT: vstrw.32 q3, [r1, #32]
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: bx lr
+; CHECK-LV-LABEL: vld3_v16i32:
+; CHECK-LV: @ %bb.0: @ %entry
+; CHECK-LV-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LV-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #80]
+; CHECK-LV-NEXT: vldrw.u32 q6, [r0, #176]
+; CHECK-LV-NEXT: vmov.f32 s9, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s10, s2
+; CHECK-LV-NEXT: vmov.f32 s13, s0
+; CHECK-LV-NEXT: vmov.f32 s14, s3
+; CHECK-LV-NEXT: @ implicit-def: $s3
+; CHECK-LV-NEXT: vmov.f32 s8, s4
+; CHECK-LV-NEXT: vmov.f32 s12, s5
+; CHECK-LV-NEXT: vmov.f32 s15, s18
+; CHECK-LV-NEXT: vmov.f32 s11, s17
+; CHECK-LV-NEXT: vadd.i32 q2, q2, q3
+; CHECK-LV-NEXT: vmov.f32 s0, s6
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-LV-NEXT: vmov.f32 s2, s16
+; CHECK-LV-NEXT: vmov.f32 s3, s19
+; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-LV-NEXT: vadd.i32 q0, q2, q0
+; CHECK-LV-NEXT: vldrw.u32 q2, [r0]
+; CHECK-LV-NEXT: vmov.f32 s18, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s17, s4
+; CHECK-LV-NEXT: vmov.f32 s22, s6
+; CHECK-LV-NEXT: vmov.f32 s16, s9
+; CHECK-LV-NEXT: vmov.f32 s19, s14
+; CHECK-LV-NEXT: vmov.f32 s20, s8
+; CHECK-LV-NEXT: vmov.f32 s21, s11
+; CHECK-LV-NEXT: vmov.f32 s23, s13
+; CHECK-LV-NEXT: vmov.f32 s4, s10
+; CHECK-LV-NEXT: vldrw.u32 q2, [r0, #160]
+; CHECK-LV-NEXT: vmov.f32 s6, s12
+; CHECK-LV-NEXT: vadd.i32 q4, q5, q4
+; CHECK-LV-NEXT: vmov.f32 s7, s15
+; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #144]
+; CHECK-LV-NEXT: vadd.i32 q1, q4, q1
+; CHECK-LV-NEXT: vmov.f32 s18, s10
+; CHECK-LV-NEXT: vmov.f32 s17, s15
+; CHECK-LV-NEXT: @ implicit-def: $s15
+; CHECK-LV-NEXT: vmov.f32 s21, s8
+; CHECK-LV-NEXT: vmov.f32 s22, s11
+; CHECK-LV-NEXT: @ implicit-def: $s11
+; CHECK-LV-NEXT: vmov.f32 s16, s12
+; CHECK-LV-NEXT: vmov.f32 s20, s13
+; CHECK-LV-NEXT: vmov.f32 s23, s26
+; CHECK-LV-NEXT: vmov.f32 s19, s25
+; CHECK-LV-NEXT: vadd.i32 q4, q4, q5
+; CHECK-LV-NEXT: vmov.f32 s8, s14
+; CHECK-LV-NEXT: vmov.f32 s10, s24
+; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #112]
+; CHECK-LV-NEXT: vmov.f32 s11, s27
+; CHECK-LV-NEXT: vldrw.u32 q5, [r0, #128]
+; CHECK-LV-NEXT: vadd.i32 q2, q4, q2
+; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #96]
+; CHECK-LV-NEXT: vmov.f32 s26, s15
+; CHECK-LV-NEXT: @ implicit-def: $s15
+; CHECK-LV-NEXT: @ implicit-def: $s15
+; CHECK-LV-NEXT: vstrw.32 q2, [r1, #48]
+; CHECK-LV-NEXT: vmov.f32 s25, s12
+; CHECK-LV-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-LV-NEXT: vmov.f32 s30, s14
+; CHECK-LV-NEXT: vstrw.32 q1, [r1]
+; CHECK-LV-NEXT: vmov.f32 s24, s17
+; CHECK-LV-NEXT: vmov.f32 s27, s22
+; CHECK-LV-NEXT: vmov.f32 s28, s16
+; CHECK-LV-NEXT: vmov.f32 s29, s19
+; CHECK-LV-NEXT: vmov.f32 s31, s21
+; CHECK-LV-NEXT: vadd.i32 q6, q7, q6
+; CHECK-LV-NEXT: vmov.f32 s12, s18
+; CHECK-LV-NEXT: vmov.f32 s14, s20
+; CHECK-LV-NEXT: vmov.f32 s15, s23
+; CHECK-LV-NEXT: vadd.i32 q3, q6, q3
+; CHECK-LV-NEXT: vstrw.32 q3, [r1, #32]
+; CHECK-LV-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LV-NEXT: bx lr
+;
+; CHECK-LIS-LABEL: vld3_v16i32:
+; CHECK-LIS: @ %bb.0: @ %entry
+; CHECK-LIS-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LIS-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LIS-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #80]
+; CHECK-LIS-NEXT: vldrw.u32 q6, [r0, #176]
+; CHECK-LIS-NEXT: vmov.f32 s10, s2
+; CHECK-LIS-NEXT: vmov.f32 s13, s0
+; CHECK-LIS-NEXT: vmov.f32 s14, s3
+; CHECK-LIS-NEXT: vmov.f32 s8, s4
+; CHECK-LIS-NEXT: vmov.f32 s9, s7
+; CHECK-LIS-NEXT: vmov.f32 s12, s5
+; CHECK-LIS-NEXT: vmov.f32 s15, s18
+; CHECK-LIS-NEXT: vmov.f32 s11, s17
+; CHECK-LIS-NEXT: vadd.i32 q2, q2, q3
+; CHECK-LIS-NEXT: vmov.f32 s0, s6
+; CHECK-LIS-NEXT: vmov.f32 s2, s16
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-LIS-NEXT: vmov.f32 s3, s19
+; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-LIS-NEXT: vadd.i32 q0, q2, q0
+; CHECK-LIS-NEXT: vldrw.u32 q2, [r0]
+; CHECK-LIS-NEXT: vmov.f32 s17, s4
+; CHECK-LIS-NEXT: vmov.f32 s18, s7
+; CHECK-LIS-NEXT: vmov.f32 s22, s6
+; CHECK-LIS-NEXT: vmov.f32 s16, s9
+; CHECK-LIS-NEXT: vmov.f32 s19, s14
+; CHECK-LIS-NEXT: vmov.f32 s20, s8
+; CHECK-LIS-NEXT: vmov.f32 s21, s11
+; CHECK-LIS-NEXT: vmov.f32 s23, s13
+; CHECK-LIS-NEXT: vmov.f32 s4, s10
+; CHECK-LIS-NEXT: vldrw.u32 q2, [r0, #160]
+; CHECK-LIS-NEXT: vmov.f32 s6, s12
+; CHECK-LIS-NEXT: vadd.i32 q4, q5, q4
+; CHECK-LIS-NEXT: vmov.f32 s7, s15
+; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #144]
+; CHECK-LIS-NEXT: vadd.i32 q1, q4, q1
+; CHECK-LIS-NEXT: vmov.f32 s18, s10
+; CHECK-LIS-NEXT: vmov.f32 s21, s8
+; CHECK-LIS-NEXT: vmov.f32 s22, s11
+; CHECK-LIS-NEXT: vmov.f32 s16, s12
+; CHECK-LIS-NEXT: vmov.f32 s17, s15
+; CHECK-LIS-NEXT: vmov.f32 s20, s13
+; CHECK-LIS-NEXT: vmov.f32 s23, s26
+; CHECK-LIS-NEXT: vmov.f32 s19, s25
+; CHECK-LIS-NEXT: vadd.i32 q4, q4, q5
+; CHECK-LIS-NEXT: vmov.f32 s8, s14
+; CHECK-LIS-NEXT: vmov.f32 s10, s24
+; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #112]
+; CHECK-LIS-NEXT: vmov.f32 s11, s27
+; CHECK-LIS-NEXT: vldrw.u32 q5, [r0, #128]
+; CHECK-LIS-NEXT: vadd.i32 q2, q4, q2
+; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #96]
+; CHECK-LIS-NEXT: vmov.f32 s25, s12
+; CHECK-LIS-NEXT: vstrw.32 q2, [r1, #48]
+; CHECK-LIS-NEXT: vmov.f32 s26, s15
+; CHECK-LIS-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-LIS-NEXT: vmov.f32 s30, s14
+; CHECK-LIS-NEXT: vstrw.32 q1, [r1]
+; CHECK-LIS-NEXT: vmov.f32 s24, s17
+; CHECK-LIS-NEXT: vmov.f32 s27, s22
+; CHECK-LIS-NEXT: vmov.f32 s28, s16
+; CHECK-LIS-NEXT: vmov.f32 s29, s19
+; CHECK-LIS-NEXT: vmov.f32 s31, s21
+; CHECK-LIS-NEXT: vadd.i32 q6, q7, q6
+; CHECK-LIS-NEXT: vmov.f32 s12, s18
+; CHECK-LIS-NEXT: vmov.f32 s14, s20
+; CHECK-LIS-NEXT: vmov.f32 s15, s23
+; CHECK-LIS-NEXT: vadd.i32 q3, q6, q3
+; CHECK-LIS-NEXT: vstrw.32 q3, [r1, #32]
+; CHECK-LIS-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LIS-NEXT: bx lr
entry:
%l1 = load <48 x i32>, ptr %src, align 4
@@ -992,14 +1146,20 @@ define void @vld3_v2f32(ptr %src, ptr %dst) {
; CHECK-LV-LABEL: vld3_v2f32:
; CHECK-LV: @ %bb.0: @ %entry
; CHECK-LV-NEXT: vldrw.u32 q2, [r0]
-; CHECK-LV-NEXT: vldr s1, [r0, #16]
-; CHECK-LV-NEXT: vldr s5, [r0, #20]
+; CHECK-LV-NEXT: vldr s5, [r0, #16]
+; CHECK-LV-NEXT: vldr s1, [r0, #20]
+; CHECK-LV-NEXT: @ implicit-def: $s14
+; CHECK-LV-NEXT: @ implicit-def: $s15
+; CHECK-LV-NEXT: @ implicit-def: $s6
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: @ implicit-def: $s2
+; CHECK-LV-NEXT: @ implicit-def: $s3
; CHECK-LV-NEXT: vmov.f32 s12, s8
; CHECK-LV-NEXT: vmov.f32 s13, s11
-; CHECK-LV-NEXT: vmov.f32 s0, s9
-; CHECK-LV-NEXT: vadd.f32 q0, q3, q0
-; CHECK-LV-NEXT: vmov.f32 s4, s10
-; CHECK-LV-NEXT: vadd.f32 q0, q0, q1
+; CHECK-LV-NEXT: vmov.f32 s4, s9
+; CHECK-LV-NEXT: vadd.f32 q1, q3, q1
+; CHECK-LV-NEXT: vmov.f32 s0, s10
+; CHECK-LV-NEXT: vadd.f32 q0, q1, q0
; CHECK-LV-NEXT: vstmia r1, {s0, s1}
; CHECK-LV-NEXT: bx lr
;
@@ -1029,29 +1189,55 @@ entry:
}
define void @vld3_v4f32(ptr %src, ptr %dst) {
-; CHECK-LABEL: vld3_v4f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9}
-; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
-; CHECK-NEXT: vldrw.u32 q1, [r0]
-; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
-; CHECK-NEXT: vmov.f32 s10, s2
-; CHECK-NEXT: vmov.f32 s13, s0
-; CHECK-NEXT: vmov.f32 s14, s3
-; CHECK-NEXT: vmov.f32 s8, s4
-; CHECK-NEXT: vmov.f32 s9, s7
-; CHECK-NEXT: vmov.f32 s12, s5
-; CHECK-NEXT: vmov.f32 s15, s18
-; CHECK-NEXT: vmov.f32 s11, s17
-; CHECK-NEXT: vadd.f32 q2, q2, q3
-; CHECK-NEXT: vmov.f32 s0, s6
-; CHECK-NEXT: vmov.f32 s2, s16
-; CHECK-NEXT: vmov.f32 s3, s19
-; CHECK-NEXT: vadd.f32 q0, q2, q0
-; CHECK-NEXT: vstrw.32 q0, [r1]
-; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: bx lr
+; CHECK-LV-LABEL: vld3_v4f32:
+; CHECK-LV: @ %bb.0: @ %entry
+; CHECK-LV-NEXT: .vsave {d8, d9}
+; CHECK-LV-NEXT: vpush {d8, d9}
+; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #16]
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0]
+; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #32]
+; CHECK-LV-NEXT: vmov.f32 s9, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s10, s2
+; CHECK-LV-NEXT: vmov.f32 s13, s0
+; CHECK-LV-NEXT: vmov.f32 s14, s3
+; CHECK-LV-NEXT: @ implicit-def: $s3
+; CHECK-LV-NEXT: vmov.f32 s8, s4
+; CHECK-LV-NEXT: vmov.f32 s12, s5
+; CHECK-LV-NEXT: vmov.f32 s15, s18
+; CHECK-LV-NEXT: vmov.f32 s11, s17
+; CHECK-LV-NEXT: vadd.f32 q2, q2, q3
+; CHECK-LV-NEXT: vmov.f32 s0, s6
+; CHECK-LV-NEXT: vmov.f32 s2, s16
+; CHECK-LV-NEXT: vmov.f32 s3, s19
+; CHECK-LV-NEXT: vadd.f32 q0, q2, q0
+; CHECK-LV-NEXT: vstrw.32 q0, [r1]
+; CHECK-LV-NEXT: vpop {d8, d9}
+; CHECK-LV-NEXT: bx lr
+;
+; CHECK-LIS-LABEL: vld3_v4f32:
+; CHECK-LIS: @ %bb.0: @ %entry
+; CHECK-LIS-NEXT: .vsave {d8, d9}
+; CHECK-LIS-NEXT: vpush {d8, d9}
+; CHECK-LIS-NEXT: vldrw.u32 q0, [r0, #16]
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0]
+; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #32]
+; CHECK-LIS-NEXT: vmov.f32 s10, s2
+; CHECK-LIS-NEXT: vmov.f32 s13, s0
+; CHECK-LIS-NEXT: vmov.f32 s14, s3
+; CHECK-LIS-NEXT: vmov.f32 s8, s4
+; CHECK-LIS-NEXT: vmov.f32 s9, s7
+; CHECK-LIS-NEXT: vmov.f32 s12, s5
+; CHECK-LIS-NEXT: vmov.f32 s15, s18
+; CHECK-LIS-NEXT: vmov.f32 s11, s17
+; CHECK-LIS-NEXT: vadd.f32 q2, q2, q3
+; CHECK-LIS-NEXT: vmov.f32 s0, s6
+; CHECK-LIS-NEXT: vmov.f32 s2, s16
+; CHECK-LIS-NEXT: vmov.f32 s3, s19
+; CHECK-LIS-NEXT: vadd.f32 q0, q2, q0
+; CHECK-LIS-NEXT: vstrw.32 q0, [r1]
+; CHECK-LIS-NEXT: vpop {d8, d9}
+; CHECK-LIS-NEXT: bx lr
entry:
%l1 = load <12 x float>, ptr %src, align 4
@@ -1065,46 +1251,91 @@ entry:
}
define void @vld3_v8f32(ptr %src, ptr %dst) {
-; CHECK-LABEL: vld3_v8f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9, d10, d11}
-; CHECK-NEXT: vpush {d8, d9, d10, d11}
-; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
-; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
-; CHECK-NEXT: vmov.f32 s10, s2
-; CHECK-NEXT: vmov.f32 s13, s0
-; CHECK-NEXT: vmov.f32 s14, s3
-; CHECK-NEXT: vmov.f32 s8, s4
-; CHECK-NEXT: vmov.f32 s9, s7
-; CHECK-NEXT: vmov.f32 s12, s5
-; CHECK-NEXT: vmov.f32 s15, s18
-; CHECK-NEXT: vmov.f32 s11, s17
-; CHECK-NEXT: vadd.f32 q2, q2, q3
-; CHECK-NEXT: vmov.f32 s0, s6
-; CHECK-NEXT: vmov.f32 s2, s16
-; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
-; CHECK-NEXT: vmov.f32 s3, s19
-; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
-; CHECK-NEXT: vadd.f32 q0, q2, q0
-; CHECK-NEXT: vldrw.u32 q2, [r0]
-; CHECK-NEXT: vmov.f32 s17, s4
-; CHECK-NEXT: vstrw.32 q0, [r1, #16]
-; CHECK-NEXT: vmov.f32 s18, s7
-; CHECK-NEXT: vmov.f32 s22, s6
-; CHECK-NEXT: vmov.f32 s16, s9
-; CHECK-NEXT: vmov.f32 s19, s14
-; CHECK-NEXT: vmov.f32 s20, s8
-; CHECK-NEXT: vmov.f32 s21, s11
-; CHECK-NEXT: vmov.f32 s23, s13
-; CHECK-NEXT: vadd.f32 q4, q5, q4
-; CHECK-NEXT: vmov.f32 s4, s10
-; CHECK-NEXT: vmov.f32 s6, s12
-; CHECK-NEXT: vmov.f32 s7, s15
-; CHECK-NEXT: vadd.f32 q1, q4, q1
-; CHECK-NEXT: vstrw.32 q1, [r1]
-; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: bx lr
+; CHECK-LV-LABEL: vld3_v8f32:
+; CHECK-LV: @ %bb.0: @ %entry
+; CHECK-LV-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-LV-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #80]
+; CHECK-LV-NEXT: vmov.f32 s9, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s10, s2
+; CHECK-LV-NEXT: vmov.f32 s13, s0
+; CHECK-LV-NEXT: vmov.f32 s14, s3
+; CHECK-LV-NEXT: @ implicit-def: $s3
+; CHECK-LV-NEXT: vmov.f32 s8, s4
+; CHECK-LV-NEXT: vmov.f32 s12, s5
+; CHECK-LV-NEXT: vmov.f32 s15, s18
+; CHECK-LV-NEXT: vmov.f32 s11, s17
+; CHECK-LV-NEXT: vadd.f32 q2, q2, q3
+; CHECK-LV-NEXT: vmov.f32 s0, s6
+; CHECK-LV-NEXT: vmov.f32 s2, s16
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-LV-NEXT: vmov.f32 s3, s19
+; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-LV-NEXT: vadd.f32 q0, q2, q0
+; CHECK-LV-NEXT: vldrw.u32 q2, [r0]
+; CHECK-LV-NEXT: vmov.f32 s18, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-LV-NEXT: vmov.f32 s17, s4
+; CHECK-LV-NEXT: vmov.f32 s22, s6
+; CHECK-LV-NEXT: vmov.f32 s16, s9
+; CHECK-LV-NEXT: vmov.f32 s19, s14
+; CHECK-LV-NEXT: vmov.f32 s20, s8
+; CHECK-LV-NEXT: vmov.f32 s21, s11
+; CHECK-LV-NEXT: vmov.f32 s23, s13
+; CHECK-LV-NEXT: vadd.f32 q4, q5, q4
+; CHECK-LV-NEXT: vmov.f32 s4, s10
+; CHECK-LV-NEXT: vmov.f32 s6, s12
+; CHECK-LV-NEXT: vmov.f32 s7, s15
+; CHECK-LV-NEXT: vadd.f32 q1, q4, q1
+; CHECK-LV-NEXT: vstrw.32 q1, [r1]
+; CHECK-LV-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-LV-NEXT: bx lr
+;
+; CHECK-LIS-LABEL: vld3_v8f32:
+; CHECK-LIS: @ %bb.0: @ %entry
+; CHECK-LIS-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-LIS-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-LIS-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #80]
+; CHECK-LIS-NEXT: vmov.f32 s10, s2
+; CHECK-LIS-NEXT: vmov.f32 s13, s0
+; CHECK-LIS-NEXT: vmov.f32 s14, s3
+; CHECK-LIS-NEXT: vmov.f32 s8, s4
+; CHECK-LIS-NEXT: vmov.f32 s9, s7
+; CHECK-LIS-NEXT: vmov.f32 s12, s5
+; CHECK-LIS-NEXT: vmov.f32 s15, s18
+; CHECK-LIS-NEXT: vmov.f32 s11, s17
+; CHECK-LIS-NEXT: vadd.f32 q2, q2, q3
+; CHECK-LIS-NEXT: vmov.f32 s0, s6
+; CHECK-LIS-NEXT: vmov.f32 s2, s16
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-LIS-NEXT: vmov.f32 s3, s19
+; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-LIS-NEXT: vadd.f32 q0, q2, q0
+; CHECK-LIS-NEXT: vldrw.u32 q2, [r0]
+; CHECK-LIS-NEXT: vmov.f32 s17, s4
+; CHECK-LIS-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-LIS-NEXT: vmov.f32 s18, s7
+; CHECK-LIS-NEXT: vmov.f32 s22, s6
+; CHECK-LIS-NEXT: vmov.f32 s16, s9
+; CHECK-LIS-NEXT: vmov.f32 s19, s14
+; CHECK-LIS-NEXT: vmov.f32 s20, s8
+; CHECK-LIS-NEXT: vmov.f32 s21, s11
+; CHECK-LIS-NEXT: vmov.f32 s23, s13
+; CHECK-LIS-NEXT: vadd.f32 q4, q5, q4
+; CHECK-LIS-NEXT: vmov.f32 s4, s10
+; CHECK-LIS-NEXT: vmov.f32 s6, s12
+; CHECK-LIS-NEXT: vmov.f32 s7, s15
+; CHECK-LIS-NEXT: vadd.f32 q1, q4, q1
+; CHECK-LIS-NEXT: vstrw.32 q1, [r1]
+; CHECK-LIS-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-LIS-NEXT: bx lr
entry:
%l1 = load <24 x float>, ptr %src, align 4
@@ -1118,80 +1349,163 @@ entry:
}
define void @vld3_v16f32(ptr %src, ptr %dst) {
-; CHECK-LABEL: vld3_v16f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
-; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
-; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
-; CHECK-NEXT: vldrw.u32 q6, [r0, #176]
-; CHECK-NEXT: vmov.f32 s10, s2
-; CHECK-NEXT: vmov.f32 s13, s0
-; CHECK-NEXT: vmov.f32 s14, s3
-; CHECK-NEXT: vmov.f32 s8, s4
-; CHECK-NEXT: vmov.f32 s9, s7
-; CHECK-NEXT: vmov.f32 s12, s5
-; CHECK-NEXT: vmov.f32 s15, s18
-; CHECK-NEXT: vmov.f32 s11, s17
-; CHECK-NEXT: vadd.f32 q2, q2, q3
-; CHECK-NEXT: vmov.f32 s0, s6
-; CHECK-NEXT: vmov.f32 s2, s16
-; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
-; CHECK-NEXT: vmov.f32 s3, s19
-; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
-; CHECK-NEXT: vadd.f32 q0, q2, q0
-; CHECK-NEXT: vldrw.u32 q2, [r0]
-; CHECK-NEXT: vmov.f32 s17, s4
-; CHECK-NEXT: vmov.f32 s18, s7
-; CHECK-NEXT: vmov.f32 s22, s6
-; CHECK-NEXT: vmov.f32 s16, s9
-; CHECK-NEXT: vmov.f32 s19, s14
-; CHECK-NEXT: vmov.f32 s20, s8
-; CHECK-NEXT: vmov.f32 s21, s11
-; CHECK-NEXT: vmov.f32 s23, s13
-; CHECK-NEXT: vmov.f32 s4, s10
-; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
-; CHECK-NEXT: vmov.f32 s6, s12
-; CHECK-NEXT: vadd.f32 q4, q5, q4
-; CHECK-NEXT: vmov.f32 s7, s15
-; CHECK-NEXT: vldrw.u32 q3, [r0, #144]
-; CHECK-NEXT: vadd.f32 q1, q4, q1
-; CHECK-NEXT: vmov.f32 s18, s10
-; CHECK-NEXT: vmov.f32 s21, s8
-; CHECK-NEXT: vmov.f32 s22, s11
-; CHECK-NEXT: vmov.f32 s16, s12
-; CHECK-NEXT: vmov.f32 s17, s15
-; CHECK-NEXT: vmov.f32 s20, s13
-; CHECK-NEXT: vmov.f32 s23, s26
-; CHECK-NEXT: vmov.f32 s19, s25
-; CHECK-NEXT: vadd.f32 q4, q4, q5
-; CHECK-NEXT: vmov.f32 s8, s14
-; CHECK-NEXT: vmov.f32 s10, s24
-; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
-; CHECK-NEXT: vmov.f32 s11, s27
-; CHECK-NEXT: vldrw.u32 q5, [r0, #128]
-; CHECK-NEXT: vadd.f32 q2, q4, q2
-; CHECK-NEXT: vldrw.u32 q4, [r0, #96]
-; CHECK-NEXT: vmov.f32 s25, s12
-; CHECK-NEXT: vstrw.32 q2, [r1, #48]
-; CHECK-NEXT: vmov.f32 s26, s15
-; CHECK-NEXT: vstrw.32 q0, [r1, #16]
-; CHECK-NEXT: vmov.f32 s30, s14
-; CHECK-NEXT: vstrw.32 q1, [r1]
-; CHECK-NEXT: vmov.f32 s24, s17
-; CHECK-NEXT: vmov.f32 s27, s22
-; CHECK-NEXT: vmov.f32 s28, s16
-; CHECK-NEXT: vmov.f32 s29, s19
-; CHECK-NEXT: vmov.f32 s31, s21
-; CHECK-NEXT: vadd.f32 q6, q7, q6
-; CHECK-NEXT: vmov.f32 s12, s18
-; CHECK-NEXT: vmov.f32 s14, s20
-; CHECK-NEXT: vmov.f32 s15, s23
-; CHECK-NEXT: vadd.f32 q3, q6, q3
-; CHECK-NEXT: vstrw.32 q3, [r1, #32]
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: bx lr
+; CHECK-LV-LABEL: vld3_v16f32:
+; CHECK-LV: @ %bb.0: @ %entry
+; CHECK-LV-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LV-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LV-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #80]
+; CHECK-LV-NEXT: vldrw.u32 q6, [r0, #176]
+; CHECK-LV-NEXT: vmov.f32 s9, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s10, s2
+; CHECK-LV-NEXT: vmov.f32 s13, s0
+; CHECK-LV-NEXT: vmov.f32 s14, s3
+; CHECK-LV-NEXT: @ implicit-def: $s3
+; CHECK-LV-NEXT: vmov.f32 s8, s4
+; CHECK-LV-NEXT: vmov.f32 s12, s5
+; CHECK-LV-NEXT: vmov.f32 s15, s18
+; CHECK-LV-NEXT: vmov.f32 s11, s17
+; CHECK-LV-NEXT: vadd.f32 q2, q2, q3
+; CHECK-LV-NEXT: vmov.f32 s0, s6
+; CHECK-LV-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-LV-NEXT: vmov.f32 s2, s16
+; CHECK-LV-NEXT: vmov.f32 s3, s19
+; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-LV-NEXT: vadd.f32 q0, q2, q0
+; CHECK-LV-NEXT: vldrw.u32 q2, [r0]
+; CHECK-LV-NEXT: vmov.f32 s18, s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: @ implicit-def: $s7
+; CHECK-LV-NEXT: vmov.f32 s17, s4
+; CHECK-LV-NEXT: vmov.f32 s22, s6
+; CHECK-LV-NEXT: vmov.f32 s16, s9
+; CHECK-LV-NEXT: vmov.f32 s19, s14
+; CHECK-LV-NEXT: vmov.f32 s20, s8
+; CHECK-LV-NEXT: vmov.f32 s21, s11
+; CHECK-LV-NEXT: vmov.f32 s23, s13
+; CHECK-LV-NEXT: vmov.f32 s4, s10
+; CHECK-LV-NEXT: vldrw.u32 q2, [r0, #160]
+; CHECK-LV-NEXT: vmov.f32 s6, s12
+; CHECK-LV-NEXT: vadd.f32 q4, q5, q4
+; CHECK-LV-NEXT: vmov.f32 s7, s15
+; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #144]
+; CHECK-LV-NEXT: vadd.f32 q1, q4, q1
+; CHECK-LV-NEXT: vmov.f32 s18, s10
+; CHECK-LV-NEXT: vmov.f32 s17, s15
+; CHECK-LV-NEXT: @ implicit-def: $s15
+; CHECK-LV-NEXT: vmov.f32 s21, s8
+; CHECK-LV-NEXT: vmov.f32 s22, s11
+; CHECK-LV-NEXT: @ implicit-def: $s11
+; CHECK-LV-NEXT: vmov.f32 s16, s12
+; CHECK-LV-NEXT: vmov.f32 s20, s13
+; CHECK-LV-NEXT: vmov.f32 s23, s26
+; CHECK-LV-NEXT: vmov.f32 s19, s25
+; CHECK-LV-NEXT: vadd.f32 q4, q4, q5
+; CHECK-LV-NEXT: vmov.f32 s8, s14
+; CHECK-LV-NEXT: vmov.f32 s10, s24
+; CHECK-LV-NEXT: vldrw.u32 q3, [r0, #112]
+; CHECK-LV-NEXT: vmov.f32 s11, s27
+; CHECK-LV-NEXT: vldrw.u32 q5, [r0, #128]
+; CHECK-LV-NEXT: vadd.f32 q2, q4, q2
+; CHECK-LV-NEXT: vldrw.u32 q4, [r0, #96]
+; CHECK-LV-NEXT: vmov.f32 s26, s15
+; CHECK-LV-NEXT: @ implicit-def: $s15
+; CHECK-LV-NEXT: @ implicit-def: $s15
+; CHECK-LV-NEXT: vstrw.32 q2, [r1, #48]
+; CHECK-LV-NEXT: vmov.f32 s25, s12
+; CHECK-LV-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-LV-NEXT: vmov.f32 s30, s14
+; CHECK-LV-NEXT: vstrw.32 q1, [r1]
+; CHECK-LV-NEXT: vmov.f32 s24, s17
+; CHECK-LV-NEXT: vmov.f32 s27, s22
+; CHECK-LV-NEXT: vmov.f32 s28, s16
+; CHECK-LV-NEXT: vmov.f32 s29, s19
+; CHECK-LV-NEXT: vmov.f32 s31, s21
+; CHECK-LV-NEXT: vadd.f32 q6, q7, q6
+; CHECK-LV-NEXT: vmov.f32 s12, s18
+; CHECK-LV-NEXT: vmov.f32 s14, s20
+; CHECK-LV-NEXT: vmov.f32 s15, s23
+; CHECK-LV-NEXT: vadd.f32 q3, q6, q3
+; CHECK-LV-NEXT: vstrw.32 q3, [r1, #32]
+; CHECK-LV-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LV-NEXT: bx lr
+;
+; CHECK-LIS-LABEL: vld3_v16f32:
+; CHECK-LIS: @ %bb.0: @ %entry
+; CHECK-LIS-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LIS-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LIS-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #48]
+; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #80]
+; CHECK-LIS-NEXT: vldrw.u32 q6, [r0, #176]
+; CHECK-LIS-NEXT: vmov.f32 s10, s2
+; CHECK-LIS-NEXT: vmov.f32 s13, s0
+; CHECK-LIS-NEXT: vmov.f32 s14, s3
+; CHECK-LIS-NEXT: vmov.f32 s8, s4
+; CHECK-LIS-NEXT: vmov.f32 s9, s7
+; CHECK-LIS-NEXT: vmov.f32 s12, s5
+; CHECK-LIS-NEXT: vmov.f32 s15, s18
+; CHECK-LIS-NEXT: vmov.f32 s11, s17
+; CHECK-LIS-NEXT: vadd.f32 q2, q2, q3
+; CHECK-LIS-NEXT: vmov.f32 s0, s6
+; CHECK-LIS-NEXT: vmov.f32 s2, s16
+; CHECK-LIS-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-LIS-NEXT: vmov.f32 s3, s19
+; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #32]
+; CHECK-LIS-NEXT: vadd.f32 q0, q2, q0
+; CHECK-LIS-NEXT: vldrw.u32 q2, [r0]
+; CHECK-LIS-NEXT: vmov.f32 s17, s4
+; CHECK-LIS-NEXT: vmov.f32 s18, s7
+; CHECK-LIS-NEXT: vmov.f32 s22, s6
+; CHECK-LIS-NEXT: vmov.f32 s16, s9
+; CHECK-LIS-NEXT: vmov.f32 s19, s14
+; CHECK-LIS-NEXT: vmov.f32 s20, s8
+; CHECK-LIS-NEXT: vmov.f32 s21, s11
+; CHECK-LIS-NEXT: vmov.f32 s23, s13
+; CHECK-LIS-NEXT: vmov.f32 s4, s10
+; CHECK-LIS-NEXT: vldrw.u32 q2, [r0, #160]
+; CHECK-LIS-NEXT: vmov.f32 s6, s12
+; CHECK-LIS-NEXT: vadd.f32 q4, q5, q4
+; CHECK-LIS-NEXT: vmov.f32 s7, s15
+; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #144]
+; CHECK-LIS-NEXT: vadd.f32 q1, q4, q1
+; CHECK-LIS-NEXT: vmov.f32 s18, s10
+; CHECK-LIS-NEXT: vmov.f32 s21, s8
+; CHECK-LIS-NEXT: vmov.f32 s22, s11
+; CHECK-LIS-NEXT: vmov.f32 s16, s12
+; CHECK-LIS-NEXT: vmov.f32 s17, s15
+; CHECK-LIS-NEXT: vmov.f32 s20, s13
+; CHECK-LIS-NEXT: vmov.f32 s23, s26
+; CHECK-LIS-NEXT: vmov.f32 s19, s25
+; CHECK-LIS-NEXT: vadd.f32 q4, q4, q5
+; CHECK-LIS-NEXT: vmov.f32 s8, s14
+; CHECK-LIS-NEXT: vmov.f32 s10, s24
+; CHECK-LIS-NEXT: vldrw.u32 q3, [r0, #112]
+; CHECK-LIS-NEXT: vmov.f32 s11, s27
+; CHECK-LIS-NEXT: vldrw.u32 q5, [r0, #128]
+; CHECK-LIS-NEXT: vadd.f32 q2, q4, q2
+; CHECK-LIS-NEXT: vldrw.u32 q4, [r0, #96]
+; CHECK-LIS-NEXT: vmov.f32 s25, s12
+; CHECK-LIS-NEXT: vstrw.32 q2, [r1, #48]
+; CHECK-LIS-NEXT: vmov.f32 s26, s15
+; CHECK-LIS-NEXT: vstrw.32 q0, [r1, #16]
+; CHECK-LIS-NEXT: vmov.f32 s30, s14
+; CHECK-LIS-NEXT: vstrw.32 q1, [r1]
+; CHECK-LIS-NEXT: vmov.f32 s24, s17
+; CHECK-LIS-NEXT: vmov.f32 s27, s22
+; CHECK-LIS-NEXT: vmov.f32 s28, s16
+; CHECK-LIS-NEXT: vmov.f32 s29, s19
+; CHECK-LIS-NEXT: vmov.f32 s31, s21
+; CHECK-LIS-NEXT: vadd.f32 q6, q7, q6
+; CHECK-LIS-NEXT: vmov.f32 s12, s18
+; CHECK-LIS-NEXT: vmov.f32 s14, s20
+; CHECK-LIS-NEXT: vmov.f32 s15, s23
+; CHECK-LIS-NEXT: vadd.f32 q3, q6, q3
+; CHECK-LIS-NEXT: vstrw.32 q3, [r1, #32]
+; CHECK-LIS-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-LIS-NEXT: bx lr
entry:
%l1 = load <48 x float>, ptr %src, align 4
diff --git a/llvm/test/CodeGen/Thumb2/mve-vld4.ll b/llvm/test/CodeGen/Thumb2/mve-vld4.ll
index 21eee4d634986..00bfad1c01d30 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vld4.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vld4.ll
@@ -736,17 +736,25 @@ entry:
define void @vld4_v2f32(ptr %src, ptr %dst) {
; CHECK-LABEL: vld4_v2f32:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
-; CHECK-NEXT: vldrw.u32 q1, [r0]
-; CHECK-NEXT: vmov.f32 s8, s7
-; CHECK-NEXT: vmov.f32 s9, s3
-; CHECK-NEXT: vmov.f32 s12, s6
-; CHECK-NEXT: vmov.f32 s13, s2
+; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: @ implicit-def: $s10
+; CHECK-NEXT: @ implicit-def: $s11
+; CHECK-NEXT: @ implicit-def: $s14
+; CHECK-NEXT: @ implicit-def: $s15
+; CHECK-NEXT: vmov.f32 s8, s3
+; CHECK-NEXT: @ implicit-def: $s3
+; CHECK-NEXT: vmov.f32 s12, s2
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: vmov.f32 s9, s7
+; CHECK-NEXT: vmov.f32 s13, s6
; CHECK-NEXT: vadd.f32 q2, q3, q2
-; CHECK-NEXT: vmov.f32 s12, s5
-; CHECK-NEXT: vmov.f32 s13, s1
-; CHECK-NEXT: vmov.f32 s5, s0
-; CHECK-NEXT: vadd.f32 q0, q1, q3
+; CHECK-NEXT: vmov.f32 s12, s1
+; CHECK-NEXT: vmov.f32 s13, s5
+; CHECK-NEXT: @ implicit-def: $s14
+; CHECK-NEXT: @ implicit-def: $s15
+; CHECK-NEXT: vmov.f32 s1, s4
+; CHECK-NEXT: vadd.f32 q0, q0, q3
; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vstmia r1, {s0, s1}
; CHECK-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll b/llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll
index cebc0d9c0e172..a38d43c6fff11 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll
@@ -193,11 +193,12 @@ define arm_aapcs_vfpcc <4 x i64> @sext32_0213_0ext(<8 x i32> %src1, i32 %src2) {
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0
+; CHECK-NEXT: vmov.f32 s0, s1
+; CHECK-NEXT: @ implicit-def: $s1
; CHECK-NEXT: vmov q3[2], q3[0], r0, r0
; CHECK-NEXT: vmov.f32 s17, s4
-; CHECK-NEXT: vmov.f32 s0, s1
-; CHECK-NEXT: vmullb.s32 q2, q4, q3
; CHECK-NEXT: vmov.f32 s2, s3
+; CHECK-NEXT: vmullb.s32 q2, q4, q3
; CHECK-NEXT: vmullb.s32 q1, q0, q3
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
@@ -218,11 +219,12 @@ define arm_aapcs_vfpcc <4 x i64> @sext32_0ext_0213(<8 x i32> %src1, i32 %src2) {
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0
+; CHECK-NEXT: vmov.f32 s0, s1
+; CHECK-NEXT: @ implicit-def: $s1
; CHECK-NEXT: vmov q3[2], q3[0], r0, r0
; CHECK-NEXT: vmov.f32 s17, s4
-; CHECK-NEXT: vmov.f32 s0, s1
-; CHECK-NEXT: vmullb.s32 q2, q3, q4
; CHECK-NEXT: vmov.f32 s2, s3
+; CHECK-NEXT: vmullb.s32 q2, q3, q4
; CHECK-NEXT: vmullb.s32 q1, q3, q0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
@@ -479,11 +481,12 @@ define arm_aapcs_vfpcc <4 x i64> @zext32_0213_0ext(<8 x i32> %src1, i32 %src2) {
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0
+; CHECK-NEXT: vmov.f32 s0, s1
+; CHECK-NEXT: @ implicit-def: $s1
; CHECK-NEXT: vmov q3[2], q3[0], r0, r0
; CHECK-NEXT: vmov.f32 s17, s4
-; CHECK-NEXT: vmov.f32 s0, s1
-; CHECK-NEXT: vmullb.u32 q2, q4, q3
; CHECK-NEXT: vmov.f32 s2, s3
+; CHECK-NEXT: vmullb.u32 q2, q4, q3
; CHECK-NEXT: vmullb.u32 q1, q0, q3
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
@@ -504,11 +507,12 @@ define arm_aapcs_vfpcc <4 x i64> @zext32_0ext_0213(<8 x i32> %src1, i32 %src2) {
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0
+; CHECK-NEXT: vmov.f32 s0, s1
+; CHECK-NEXT: @ implicit-def: $s1
; CHECK-NEXT: vmov q3[2], q3[0], r0, r0
; CHECK-NEXT: vmov.f32 s17, s4
-; CHECK-NEXT: vmov.f32 s0, s1
-; CHECK-NEXT: vmullb.u32 q2, q3, q4
; CHECK-NEXT: vmov.f32 s2, s3
+; CHECK-NEXT: vmullb.u32 q2, q3, q4
; CHECK-NEXT: vmullb.u32 q1, q3, q0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vst3.ll b/llvm/test/CodeGen/Thumb2/mve-vst3.ll
index 8e140187c20a2..5268a7163a0ba 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vst3.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vst3.ll
@@ -42,6 +42,8 @@ define void @vst3_v4i32(ptr %src, ptr %dst) {
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s17
; CHECK-NEXT: vmov.f32 s4, s8
; CHECK-NEXT: vmov r0, r2, d0
; CHECK-NEXT: vmov.f32 s5, s12
@@ -80,40 +82,42 @@ define void @vst3_v8i32(ptr %src, ptr %dst) {
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q3, [r0]
+; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
; CHECK-NEXT: vldrw.u32 q7, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
-; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
; CHECK-NEXT: vmov.f32 s4, s12
+; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
+; CHECK-NEXT: vmov.f32 s7, s13
; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
-; CHECK-NEXT: vmov.f32 s12, s28
-; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
+; CHECK-NEXT: vmov.f64 d6, d12
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s21
; CHECK-NEXT: vmov r2, lr, d0
; CHECK-NEXT: vmov r12, r3, d4
-; CHECK-NEXT: vmov.f32 s0, s2
-; CHECK-NEXT: vmov.f32 s2, s31
-; CHECK-NEXT: vmov.f32 s20, s29
-; CHECK-NEXT: vmov.f32 s9, s15
-; CHECK-NEXT: vmov.f32 s29, s12
; CHECK-NEXT: vmov.f32 s5, s16
-; CHECK-NEXT: vmov.f32 s7, s13
-; CHECK-NEXT: vmov.f32 s22, s26
+; CHECK-NEXT: vmov.f32 s1, s27
; CHECK-NEXT: vmov.32 q1[2], r12
-; CHECK-NEXT: vmov.f32 s23, s30
+; CHECK-NEXT: vmov.f32 s22, s26
+; CHECK-NEXT: @ implicit-def: $s26
; CHECK-NEXT: vstrw.32 q1, [r1]
-; CHECK-NEXT: vmov.f32 s28, s24
+; CHECK-NEXT: vmov.f32 s9, s15
+; CHECK-NEXT: vmov.f32 s20, s29
+; CHECK-NEXT: vmov.f32 s23, s30
+; CHECK-NEXT: vmov.f32 s25, s28
; CHECK-NEXT: vmov.32 q5[1], lr
-; CHECK-NEXT: vmov.f32 s31, s25
+; CHECK-NEXT: vmov.f32 s27, s13
; CHECK-NEXT: vstrw.32 q5, [r1, #64]
; CHECK-NEXT: vmov.f32 s12, s17
-; CHECK-NEXT: vmov.32 q7[2], r2
+; CHECK-NEXT: vmov.32 q6[2], r2
; CHECK-NEXT: vmov.f32 s15, s18
-; CHECK-NEXT: vstrw.32 q7, [r1, #48]
-; CHECK-NEXT: vmov.f32 s1, s27
+; CHECK-NEXT: vstrw.32 q6, [r1, #48]
+; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vmov.32 q3[1], r3
-; CHECK-NEXT: vmov.f32 s8, s10
+; CHECK-NEXT: vmov.f32 s2, s31
; CHECK-NEXT: vstrw.32 q3, [r1, #16]
-; CHECK-NEXT: vmov.f32 s10, s19
+; CHECK-NEXT: vmov.f32 s8, s10
; CHECK-NEXT: vstrw.32 q0, [r1, #80]
+; CHECK-NEXT: vmov.f32 s10, s19
; CHECK-NEXT: vstrw.32 q2, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r7, pc}
@@ -137,108 +141,112 @@ define void @vst3_v16i32(ptr %src, ptr %dst) {
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: .pad #176
-; CHECK-NEXT: sub sp, #176
-; CHECK-NEXT: vldrw.u32 q1, [r0, #160]
-; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
-; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
+; CHECK-NEXT: .pad #160
+; CHECK-NEXT: sub sp, #160
+; CHECK-NEXT: vldrw.u32 q3, [r0, #160]
+; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vldrw.u32 q5, [r0, #128]
-; CHECK-NEXT: vstrw.32 q1, [sp, #160] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q1, [r0, #144]
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: vstrw.32 q3, [sp, #144] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q3, [r0, #144]
+; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
+; CHECK-NEXT: vmov r12, r3, d10
+; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #176]
+; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q3, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
-; CHECK-NEXT: vldrw.u32 q2, [r0]
-; CHECK-NEXT: vldrw.u32 q7, [r0, #176]
-; CHECK-NEXT: vstrw.32 q1, [sp, #80] @ 16-byte Spill
-; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
-; CHECK-NEXT: vldrw.u32 q1, [r0, #112]
-; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
-; CHECK-NEXT: vmov r12, r3, d10
; CHECK-NEXT: vmov.f32 s20, s22
-; CHECK-NEXT: vstrw.32 q4, [sp] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s22, s3
-; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
-; CHECK-NEXT: vmov.f32 s21, s11
-; CHECK-NEXT: vstrw.32 q7, [sp, #48] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q4, [r0, #112]
+; CHECK-NEXT: vstrw.32 q3, [sp, #64] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s21, s3
+; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
+; CHECK-NEXT: vmov.f32 s22, s7
+; CHECK-NEXT: vmov.f32 s26, s2
+; CHECK-NEXT: vldrw.u32 q7, [r0, #16]
; CHECK-NEXT: vstrw.32 q5, [r1, #32]
-; CHECK-NEXT: vmov.f32 s24, s1
-; CHECK-NEXT: vmov.f32 s27, s2
-; CHECK-NEXT: vstrw.32 q4, [sp, #64] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s21, s0
-; CHECK-NEXT: vmov.f32 s0, s30
-; CHECK-NEXT: vmov.f32 s3, s31
-; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s1, s15
-; CHECK-NEXT: vmov.f32 s2, s7
-; CHECK-NEXT: vstrw.32 q0, [sp, #128] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s0, s5
-; CHECK-NEXT: vmov.f32 s2, s14
-; CHECK-NEXT: vmov.f32 s3, s6
-; CHECK-NEXT: vstrw.32 q0, [sp, #112] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q0, [sp, #160] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s26, s10
-; CHECK-NEXT: vmov.f32 s20, s8
+; CHECK-NEXT: vmov.f32 s24, s5
+; CHECK-NEXT: @ implicit-def: $s25
+; CHECK-NEXT: vmov.f32 s27, s6
+; CHECK-NEXT: @ implicit-def: $s22
+; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s21, s4
+; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.32 q6[1], r3
-; CHECK-NEXT: vmov.f32 s23, s9
-; CHECK-NEXT: vldrw.u32 q2, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s16, s2
+; CHECK-NEXT: vmov.f32 s20, s0
+; CHECK-NEXT: vmov.f32 s23, s1
; CHECK-NEXT: vstrw.32 q6, [r1, #16]
-; CHECK-NEXT: vmov.f32 s19, s3
-; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s17, s31
-; CHECK-NEXT: vstrw.32 q5, [sp, #144] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s18, s11
-; CHECK-NEXT: vstrw.32 q4, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT: vmov.f64 d8, d14
-; CHECK-NEXT: vmov.f32 s19, s29
-; CHECK-NEXT: vmov.f64 d14, d0
-; CHECK-NEXT: vmov.f32 s25, s4
-; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s20, s9
-; CHECK-NEXT: vmov.f32 s23, s10
-; CHECK-NEXT: vmov.f32 s17, s8
-; CHECK-NEXT: vldrw.u32 q2, [sp, #64] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s15, s3
-; CHECK-NEXT: vmov.f32 s0, s8
-; CHECK-NEXT: vmov.f32 s1, s4
-; CHECK-NEXT: vmov.f32 s3, s9
-; CHECK-NEXT: vmov r0, r3, d14
-; CHECK-NEXT: vmov.f32 s24, s12
-; CHECK-NEXT: vmov.f32 s12, s2
-; CHECK-NEXT: vmov.32 q0[2], r0
-; CHECK-NEXT: vstrw.32 q0, [r1, #48]
+; CHECK-NEXT: vmov.f32 s1, s15
+; CHECK-NEXT: vstrw.32 q5, [sp, #128] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s0, s10
+; CHECK-NEXT: vldrw.u32 q6, [sp, #16] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s2, s19
+; CHECK-NEXT: @ implicit-def: $s22
+; CHECK-NEXT: vmov.f32 s3, s11
+; CHECK-NEXT: vstrw.32 q0, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s0, s17
+; CHECK-NEXT: vmov.f32 s2, s14
+; CHECK-NEXT: @ implicit-def: $s1
+; CHECK-NEXT: @ implicit-def: $s17
+; CHECK-NEXT: @ implicit-def: $s14
+; CHECK-NEXT: vmov.f32 s3, s18
+; CHECK-NEXT: vmov.f32 s20, s12
+; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s9, s7
+; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s18, s6
+; CHECK-NEXT: vmov.f32 s12, s4
+; CHECK-NEXT: vmov.f32 s15, s5
+; CHECK-NEXT: vldrw.u32 q1, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s21, s16
+; CHECK-NEXT: vmov.f32 s23, s13
+; CHECK-NEXT: vmov.f32 s16, s25
+; CHECK-NEXT: vmov.f32 s13, s24
+; CHECK-NEXT: vmov.f64 d12, d2
+; CHECK-NEXT: vmov.f32 s8, s2
+; CHECK-NEXT: vmov.f32 s11, s3
+; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s10, s27
+; CHECK-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s9, s31
+; CHECK-NEXT: vmov.f32 s4, s28
+; CHECK-NEXT: vmov.f32 s10, s3
+; CHECK-NEXT: vmov.f32 s5, s0
+; CHECK-NEXT: vmov.f32 s28, s1
+; CHECK-NEXT: vmov.f32 s31, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s18, s30
-; CHECK-NEXT: vmov.f32 s22, s30
-; CHECK-NEXT: vldrw.u32 q7, [sp, #48] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s19, s26
+; CHECK-NEXT: vmov r0, r3, d12
+; CHECK-NEXT: vldrw.u32 q6, [sp, #48] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vstrw.32 q0, [r1, #128]
-; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
-; CHECK-NEXT: vmov r0, lr, d14
-; CHECK-NEXT: vldrw.u32 q7, [sp, #160] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s11, s7
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s7, s29
+; CHECK-NEXT: vmov.32 q7[1], r3
+; CHECK-NEXT: vmov.32 q1[2], r0
+; CHECK-NEXT: vmov r0, lr, d12
; CHECK-NEXT: vmov.32 q0[1], lr
-; CHECK-NEXT: vmov.f32 s27, s13
+; CHECK-NEXT: vldrw.u32 q6, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1, #160]
-; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
-; CHECK-NEXT: vmov r2, r4, d14
-; CHECK-NEXT: vmov.32 q6[2], r0
+; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
+; CHECK-NEXT: vmov r2, r4, d12
+; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vstrw.32 q0, [r1, #176]
-; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s13, s11
-; CHECK-NEXT: vmov.32 q4[2], r2
-; CHECK-NEXT: vmov.f32 s8, s5
-; CHECK-NEXT: vmov.32 q5[1], r4
-; CHECK-NEXT: vmov.f32 s11, s6
+; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
+; CHECK-NEXT: vmov.32 q3[2], r2
+; CHECK-NEXT: vmov.32 q4[1], r4
; CHECK-NEXT: vmov.32 q0[2], r12
-; CHECK-NEXT: vmov.f32 s14, s7
-; CHECK-NEXT: vmov.32 q2[1], r3
-; CHECK-NEXT: vstrw.32 q2, [r1, #64]
-; CHECK-NEXT: vstrw.32 q3, [r1, #80]
-; CHECK-NEXT: vstrw.32 q4, [r1, #96]
-; CHECK-NEXT: vstrw.32 q5, [r1, #112]
-; CHECK-NEXT: vstrw.32 q6, [r1, #144]
+; CHECK-NEXT: vstrw.32 q1, [r1, #48]
+; CHECK-NEXT: vstrw.32 q7, [r1, #64]
+; CHECK-NEXT: vstrw.32 q2, [r1, #80]
+; CHECK-NEXT: vstrw.32 q3, [r1, #96]
+; CHECK-NEXT: vstrw.32 q4, [r1, #112]
+; CHECK-NEXT: vstrw.32 q5, [r1, #144]
; CHECK-NEXT: vstrw.32 q0, [r1]
-; CHECK-NEXT: add sp, #176
+; CHECK-NEXT: add sp, #160
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, pc}
entry:
@@ -301,6 +309,8 @@ define void @vst3_v4i16(ptr %src, ptr %dst) {
; CHECK-NEXT: vldrh.u32 q0, [r0, #8]
; CHECK-NEXT: vldrh.u32 q2, [r0, #16]
; CHECK-NEXT: vmov r0, r5, d2
+; CHECK-NEXT: vmov r12, s6
+; CHECK-NEXT: @ implicit-def: $s6
; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: vmov lr, r4, d1
@@ -308,11 +318,10 @@ define void @vst3_v4i16(ptr %src, ptr %dst) {
; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov.f32 s7, s11
-; CHECK-NEXT: vmov r12, s6
; CHECK-NEXT: vmov.32 q1[2], r4
; CHECK-NEXT: vmov r0, r4, d4
-; CHECK-NEXT: vstrh.32 q1, [r1, #16]
; CHECK-NEXT: vmov.16 q0[2], r0
+; CHECK-NEXT: vstrh.32 q1, [r1, #16]
; CHECK-NEXT: vmov.16 q0[3], r5
; CHECK-NEXT: vmov.16 q0[4], r3
; CHECK-NEXT: vmov.16 q0[5], r4
@@ -970,13 +979,15 @@ define void @vst3_v4f32(ptr %src, ptr %dst) {
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmov.f32 s12, s1
+; CHECK-NEXT: @ implicit-def: $s1
+; CHECK-NEXT: vmov.f32 s15, s2
+; CHECK-NEXT: @ implicit-def: $s2
; CHECK-NEXT: vmov.f32 s13, s5
+; CHECK-NEXT: vmov.f32 s14, s10
; CHECK-NEXT: vmov.f32 s18, s4
+; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vmov.f32 s4, s6
-; CHECK-NEXT: vmov.f32 s14, s10
-; CHECK-NEXT: vmov.f32 s15, s2
; CHECK-NEXT: vmov.f32 s16, s8
-; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vmov.f32 s5, s11
@@ -1011,11 +1022,13 @@ define void @vst3_v8f32(ptr %src, ptr %dst) {
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s0, s2
-; CHECK-NEXT: vldrw.u32 q6, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s1, s11
+; CHECK-NEXT: vldrw.u32 q6, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s15
; CHECK-NEXT: vldrw.u32 q7, [r0, #64]
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: @ implicit-def: $s2
; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f32 s0, s8
; CHECK-NEXT: vmov.f32 s1, s12
@@ -1065,95 +1078,104 @@ define void @vst3_v16f32(ptr %src, ptr %dst) {
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #128
; CHECK-NEXT: sub sp, #128
-; CHECK-NEXT: vldrw.u32 q3, [r0, #176]
-; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
+; CHECK-NEXT: vldrw.u32 q2, [r0, #176]
+; CHECK-NEXT: @ implicit-def: $s1
+; CHECK-NEXT: vldrw.u32 q6, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #128]
-; CHECK-NEXT: vstrw.32 q3, [sp, #112] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q3, [r0, #160]
-; CHECK-NEXT: vmov.f32 s24, s9
-; CHECK-NEXT: vldrw.u32 q5, [r0, #144]
-; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
-; CHECK-NEXT: vmov.f32 s26, s6
+; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
+; CHECK-NEXT: vmov.f32 s20, s25
; CHECK-NEXT: vldrw.u32 q7, [r0, #112]
-; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
-; CHECK-NEXT: vmov.f32 s27, s10
+; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q2, [r0, #144]
+; CHECK-NEXT: vmov.f32 s21, s1
+; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
+; CHECK-NEXT: vstrw.32 q2, [sp, #16] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
+; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
-; CHECK-NEXT: vstrw.32 q3, [sp, #48] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
-; CHECK-NEXT: vmov.f32 s25, s1
-; CHECK-NEXT: vstrw.32 q3, [sp, #16] @ 16-byte Spill
-; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
-; CHECK-NEXT: vstrw.32 q6, [r1, #16]
-; CHECK-NEXT: vmov.f32 s24, s2
-; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s27, s3
-; CHECK-NEXT: vmov.f32 s14, s0
-; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s12, s4
-; CHECK-NEXT: vmov.f32 s15, s5
-; CHECK-NEXT: vmov.f32 s13, s8
-; CHECK-NEXT: vstrw.32 q3, [sp, #64] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s25, s7
-; CHECK-NEXT: vmov.f32 s6, s0
-; CHECK-NEXT: vmov.f32 s13, s1
-; CHECK-NEXT: vmov.f32 s0, s2
-; CHECK-NEXT: vmov.f32 s4, s16
-; CHECK-NEXT: vmov.f32 s5, s28
-; CHECK-NEXT: vmov.f32 s7, s17
-; CHECK-NEXT: vmov.f32 s1, s19
-; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s2, s31
-; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s26, s11
-; CHECK-NEXT: vldrw.u32 q2, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT: vstrw.32 q0, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
+; CHECK-NEXT: vmov.f32 s23, s26
+; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill
+; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
+; CHECK-NEXT: vstrw.32 q5, [r1, #16]
+; CHECK-NEXT: vmov.f32 s21, s7
+; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s8, s4
+; CHECK-NEXT: vmov.f32 s11, s5
+; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s20, s2
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: @ implicit-def: $s2
+; CHECK-NEXT: vmov.f32 s23, s3
+; CHECK-NEXT: vmov.f32 s10, s0
+; CHECK-NEXT: vmov.f32 s0, s16
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s25, s5
+; CHECK-NEXT: vmov.f32 s4, s6
+; CHECK-NEXT: vmov.f32 s5, s19
+; CHECK-NEXT: vmov.f32 s6, s31
+; CHECK-NEXT: vmov.f32 s1, s28
+; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT: vmov.f32 s3, s17
+; CHECK-NEXT: @ implicit-def: $s5
+; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill
+; CHECK-NEXT: @ implicit-def: $s1
+; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s15, s30
-; CHECK-NEXT: vstrw.32 q6, [r1, #32]
+; CHECK-NEXT: vmov.f32 s22, s27
+; CHECK-NEXT: vmov.f32 s9, s24
+; CHECK-NEXT: vstrw.32 q5, [r1, #32]
+; CHECK-NEXT: vmov.f32 s27, s30
+; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s1
-; CHECK-NEXT: vldrw.u32 q6, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s0
; CHECK-NEXT: vmov.f32 s0, s2
-; CHECK-NEXT: vmov.f32 s1, s11
-; CHECK-NEXT: vmov.f32 s2, s7
-; CHECK-NEXT: vmov.f32 s14, s18
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmov.f32 s2, s15
+; CHECK-NEXT: vmov.f32 s24, s29
; CHECK-NEXT: vstrw.32 q0, [sp, #96] @ 16-byte Spill
-; CHECK-NEXT: vmov.f32 s18, s10
-; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s28, s8
-; CHECK-NEXT: vmov.f32 s31, s9
-; CHECK-NEXT: vldrw.u32 q2, [sp, #80] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s12, s29
-; CHECK-NEXT: vmov.f32 s29, s4
-; CHECK-NEXT: vstrw.32 q3, [r1, #160]
-; CHECK-NEXT: vmov.f32 s16, s5
-; CHECK-NEXT: vstrw.32 q7, [r1, #96]
-; CHECK-NEXT: vmov.f32 s19, s6
-; CHECK-NEXT: vmov.f32 s4, s8
-; CHECK-NEXT: vstrw.32 q4, [r1, #112]
-; CHECK-NEXT: vmov.f32 s6, s20
-; CHECK-NEXT: vmov.f32 s20, s22
-; CHECK-NEXT: vmov.f32 s5, s0
-; CHECK-NEXT: vmov.f32 s8, s1
-; CHECK-NEXT: vmov.f32 s11, s2
-; CHECK-NEXT: vmov.f32 s22, s3
+; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s16, s13
+; CHECK-NEXT: vmov.f32 s19, s14
+; CHECK-NEXT: vmov.f32 s29, s12
+; CHECK-NEXT: vldrw.u32 q3, [sp, #16] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s20, s0
+; CHECK-NEXT: vmov.f32 s23, s1
+; CHECK-NEXT: vmov.f32 s0, s9
+; CHECK-NEXT: vmov.f32 s3, s10
+; CHECK-NEXT: vmov.f32 s1, s13
+; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s7, s9
+; CHECK-NEXT: vmov.f32 s26, s18
; CHECK-NEXT: vstrw.32 q0, [r1, #128]
-; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s9, s21
-; CHECK-NEXT: vstrw.32 q1, [r1, #48]
+; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s18, s6
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: @ implicit-def: $s6
+; CHECK-NEXT: vstrw.32 q6, [r1, #160]
+; CHECK-NEXT: vmov.f64 d3, d7
; CHECK-NEXT: vstrw.32 q0, [r1, #144]
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
-; CHECK-NEXT: vmov.f32 s21, s27
-; CHECK-NEXT: vstrw.32 q2, [r1, #64]
+; CHECK-NEXT: vstrw.32 q4, [r1, #112]
; CHECK-NEXT: vstrw.32 q0, [r1, #176]
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
-; CHECK-NEXT: vstrw.32 q5, [r1, #80]
+; CHECK-NEXT: vmov.f32 s28, s4
+; CHECK-NEXT: vmov.f32 s22, s12
; CHECK-NEXT: vstrw.32 q0, [r1]
+; CHECK-NEXT: vmov.f32 s4, s14
+; CHECK-NEXT: vldrw.u32 q3, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT: vmov.f32 s31, s5
+; CHECK-NEXT: @ implicit-def: $s5
+; CHECK-NEXT: vmov.f32 s21, s8
+; CHECK-NEXT: vstrw.32 q7, [r1, #96]
+; CHECK-NEXT: vmov.f32 s5, s15
+; CHECK-NEXT: vstrw.32 q5, [r1, #48]
+; CHECK-NEXT: vmov.f32 s6, s11
+; CHECK-NEXT: vstrw.32 q1, [r1, #80]
; CHECK-NEXT: add sp, #128
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll b/llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
index 0d7354fcbbf2c..f5c48c883c5e7 100644
--- a/llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
@@ -54,19 +54,23 @@ define arm_aapcs_vfpcc <4 x double> @foo_v4i32(ptr nocapture readonly %pSrc, i32
; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
-; CHECK-NEXT: vmov.i64 q5, #0xffffffff
+; CHECK-NEXT: vmov.i64 q4, #0xffffffff
; CHECK-NEXT: vpt.s32 lt, q0, zr
-; CHECK-NEXT: vldrwt.u32 q4, [r0]
-; CHECK-NEXT: vmov.f32 s0, s16
-; CHECK-NEXT: vmov.f32 s2, s17
-; CHECK-NEXT: vand q6, q0, q5
+; CHECK-NEXT: vldrwt.u32 q5, [r0]
+; CHECK-NEXT: @ implicit-def: $s1
+; CHECK-NEXT: @ implicit-def: $s3
+; CHECK-NEXT: vmov.f32 s0, s20
+; CHECK-NEXT: vmov.f32 s2, s21
+; CHECK-NEXT: vand q6, q0, q4
; CHECK-NEXT: vmov r0, r1, d13
; CHECK-NEXT: bl __aeabi_ul2d
; CHECK-NEXT: vmov r2, r3, d12
-; CHECK-NEXT: vmov.f32 s0, s18
-; CHECK-NEXT: vmov.f32 s2, s19
+; CHECK-NEXT: @ implicit-def: $s1
+; CHECK-NEXT: @ implicit-def: $s3
+; CHECK-NEXT: vmov.f32 s0, s22
+; CHECK-NEXT: vmov.f32 s2, s23
+; CHECK-NEXT: vand q5, q0, q4
; CHECK-NEXT: vmov d9, r0, r1
-; CHECK-NEXT: vand q5, q0, q5
; CHECK-NEXT: vmov r4, r5, d11
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r3
diff --git a/llvm/test/CodeGen/Thumb2/peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll b/llvm/test/CodeGen/Thumb2/peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll
index eefa511bb5907..e6119af68fa94 100644
--- a/llvm/test/CodeGen/Thumb2/peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll
+++ b/llvm/test/CodeGen/Thumb2/peephole-opt-check-reg-sequence-compose-supports-subreg-index.ll
@@ -15,6 +15,8 @@ define <4 x float> @reg_sequence_subreg_compose_failure(<4 x float> %a, <2 x flo
; CHECK-NEXT: vldr s0, .LCPI0_0
; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f32 s9, s3
+; CHECK-NEXT: @ implicit-def: $s10
+; CHECK-NEXT: @ implicit-def: $s11
; CHECK-NEXT: vmul.f32 q1, q2, q1
; CHECK-NEXT: vmov.f32 s2, s0
; CHECK-NEXT: vmov.f32 s1, s4
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