[llvm] [CodeGen] Fix legalization of minimum/maximum (PR #206097)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 29 02:20:30 PDT 2026
https://github.com/nikic updated https://github.com/llvm/llvm-project/pull/206097
>From e27d45f8d89ab68a6c2c53e56df2c6634fdbbabc Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Fri, 26 Jun 2026 15:40:24 +0200
Subject: [PATCH 1/2] [CodeGen] Fix legalization of minimum/maximum
FMINIMUM/FMAXIMUM legalization uses IS_FPCLASS for the signed
zero fixup. However, if IS_FPCLASS needs to be expanded, this
requires the corresponding integer type to be legal, which it
often isn't.
Fix this in the same way as FMINIMUMNUM/FMAXIMUMNUM expansion
does, by rounding to float before performing the IS_FPCLASS if
necessary.
However, the way the check is performed is a bit different:
Here we use `LHS == RHS ? (isPosZero(LHS) ? LHS : RHS) : Max` for
the Max case, while FMAXIMUMNUM uses
`Max == 0.0 ? (isPosZero(LHS) ? LHS : Max) : Max`.
The reason for the difference is that the variant based on equality
is correct without any additional pre-conditions, while the one
based on the zero check requires equal values to be handled in
a specific way before reaching the zero fixup. (It might make
sense to always use the approach using equality, but that results
in a massive additional test diff, so I omitted it.)
One thing worth pointing out is that if the values are equal but
not signed zeros, picking any value is correct. As such, cases
where we only get a signed zero after rounding are handled correctly.
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 47 +-
.../CodeGen/AArch64/fmaximum-legalization.ll | 49 ++
.../CodeGen/ARM/fp-maximum-legalization.ll | 30 +
llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll | 488 +++++++-------
llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll | 488 +++++++-------
llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll | 60 +-
llvm/test/CodeGen/NVPTX/bf16-instructions.ll | 76 +--
llvm/test/CodeGen/NVPTX/math-intrins.ll | 456 ++++++-------
.../CodeGen/PowerPC/fminimum-fmaximum-f128.ll | 98 ++-
.../test/CodeGen/PowerPC/fminimum-fmaximum.ll | 312 ++++-----
.../CodeGen/X86/fminimum-fmaximum-i686.ll | 456 +++++++++++++
llvm/test/CodeGen/X86/fminimum-fmaximum.ll | 608 +++++++++++-------
12 files changed, 1785 insertions(+), 1383 deletions(-)
create mode 100644 llvm/test/CodeGen/ARM/fp-maximum-legalization.ll
create mode 100644 llvm/test/CodeGen/X86/fminimum-fmaximum-i686.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index cc3deaa83f63b..a4df2e0ddd97e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10122,6 +10122,22 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
return SDValue();
}
+static SDValue isSpecificZeroAfterMaybeRounding(SelectionDAG &DAG,
+ const TargetLowering &TLI,
+ SDLoc DL, SDValue Val,
+ FPClassTest FPClass) {
+ EVT VT = Val.getValueType();
+ EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ EVT IntVT = VT.changeTypeToInteger();
+ EVT FloatVT = VT.changeElementType(*DAG.getContext(), MVT::f32);
+ SDValue TestZero = DAG.getTargetConstant(FPClass, DL, MVT::i32);
+ if (!TLI.isTypeLegal(IntVT) &&
+ !TLI.isOperationLegalOrCustom(ISD::IS_FPCLASS, VT))
+ Val = DAG.getNode(ISD::FP_ROUND, DL, FloatVT, Val,
+ DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
+ return DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, Val, TestZero);
+}
+
SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
SelectionDAG &DAG) const {
if (SDValue Expanded = expandVectorNaryOpBySplitting(N, DAG))
@@ -10173,17 +10189,11 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
// fminimum/fmaximum requires -0.0 less than +0.0
if (!MinMaxMustRespectOrderedZero && !N->getFlags().hasNoSignedZeros() &&
!DAG.isKnownNeverLogicalZero(RHS) && !DAG.isKnownNeverLogicalZero(LHS)) {
- SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax,
- DAG.getConstantFP(0.0, DL, VT), ISD::SETOEQ);
- SDValue TestZero =
- DAG.getTargetConstant(IsMax ? fcPosZero : fcNegZero, DL, MVT::i32);
- SDValue LCmp = DAG.getSelect(
- DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHS, TestZero), LHS,
- MinMax, Flags);
- SDValue RCmp = DAG.getSelect(
- DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, RHS, TestZero), RHS,
- LCmp, Flags);
- MinMax = DAG.getSelect(DL, VT, IsZero, RCmp, MinMax, Flags);
+ SDValue IsEqual = DAG.getSetCC(DL, CCVT, LHS, RHS, ISD::SETOEQ);
+ SDValue IsSpecificZero = isSpecificZeroAfterMaybeRounding(
+ DAG, *this, DL, LHS, IsMax ? fcPosZero : fcNegZero);
+ SDValue RetZero = DAG.getSelect(DL, VT, IsSpecificZero, LHS, RHS, Flags);
+ MinMax = DAG.getSelect(DL, VT, IsEqual, RetZero, MinMax, Flags);
}
return MinMax;
@@ -10263,22 +10273,13 @@ SDValue TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *Node,
DAG.isKnownNeverLogicalZero(RHS)) {
return MinMax;
}
- SDValue TestZero =
- DAG.getTargetConstant(IsMax ? fcPosZero : fcNegZero, DL, MVT::i32);
SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax,
DAG.getConstantFP(0.0, DL, VT), ISD::SETEQ);
- EVT IntVT = VT.changeTypeToInteger();
- EVT FloatVT = VT.changeElementType(*DAG.getContext(), MVT::f32);
- SDValue LHSTrunc = LHS;
- if (!isTypeLegal(IntVT) && !isOperationLegalOrCustom(ISD::IS_FPCLASS, VT)) {
- LHSTrunc = DAG.getNode(ISD::FP_ROUND, DL, FloatVT, LHS,
- DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
- }
+ SDValue IsSpecificZero = isSpecificZeroAfterMaybeRounding(
+ DAG, *this, DL, LHS, IsMax ? fcPosZero : fcNegZero);
// It's OK to select from LHS and MinMax, with only one ISD::IS_FPCLASS, as
// we preferred RHS when generate MinMax, if the operands are equal.
- SDValue RetZero = DAG.getSelect(
- DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHSTrunc, TestZero), LHS,
- MinMax, Flags);
+ SDValue RetZero = DAG.getSelect(DL, VT, IsSpecificZero, LHS, MinMax, Flags);
return DAG.getSelect(DL, VT, IsZero, RetZero, MinMax, Flags);
}
diff --git a/llvm/test/CodeGen/AArch64/fmaximum-legalization.ll b/llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
index 86c1474068482..6569e072d5b6c 100644
--- a/llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
@@ -41,3 +41,52 @@ define <4 x half> @fmaximum_v4f16(<4 x half> %x, <4 x half> %y) {
%r = call <4 x half> @llvm.maximum.v4f16(<4 x half> %x, <4 x half> %y)
ret <4 x half> %r
}
+
+define fp128 @maximum_fp128(fp128 %x, fp128 %y) nounwind {
+; CHECK-LABEL: maximum_fp128:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #80
+; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
+; CHECK-NEXT: stp q1, q0, [sp, #32] // 32-byte Folded Spill
+; CHECK-NEXT: bl __gttf2
+; CHECK-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: mov v2.16b, v1.16b
+; CHECK-NEXT: b.le .LBB1_2
+; CHECK-NEXT: // %bb.1:
+; CHECK-NEXT: mov v2.16b, v0.16b
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: str q2, [sp, #16] // 16-byte Spill
+; CHECK-NEXT: bl __unordtf2
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: b.eq .LBB1_4
+; CHECK-NEXT: // %bb.3:
+; CHECK-NEXT: adrp x8, .LCPI1_0
+; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]
+; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
+; CHECK-NEXT: .LBB1_4:
+; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload
+; CHECK-NEXT: bl __trunctfsf2
+; CHECK-NEXT: ldp q1, q2, [sp, #32] // 32-byte Folded Reload
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: cmp w8, #0
+; CHECK-NEXT: b.ne .LBB1_6
+; CHECK-NEXT: // %bb.5:
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: .LBB1_6:
+; CHECK-NEXT: str q0, [sp] // 16-byte Spill
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: bl __eqtf2
+; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: b.ne .LBB1_8
+; CHECK-NEXT: // %bb.7:
+; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
+; CHECK-NEXT: .LBB1_8:
+; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
+; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: ret
+ %res = call fp128 @llvm.maximum.f128(fp128 %x, fp128 %y)
+ ret fp128 %res
+}
diff --git a/llvm/test/CodeGen/ARM/fp-maximum-legalization.ll b/llvm/test/CodeGen/ARM/fp-maximum-legalization.ll
new file mode 100644
index 0000000000000..fdea63a4d054e
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fp-maximum-legalization.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=armv7 | FileCheck %s
+
+define double @maximum_double(double %x, double %y) nounwind {
+; CHECK-LABEL: maximum_double:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r0, r1
+; CHECK-NEXT: vmov d17, r2, r3
+; CHECK-NEXT: vcvt.f32.f64 s0, d16
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: vcmp.f64 d16, d17
+; CHECK-NEXT: vorr d18, d17, d17
+; CHECK-NEXT: clz r0, r0
+; CHECK-NEXT: lsrs r0, r0, #5
+; CHECK-NEXT: vmovne.f64 d18, d16
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vmovgt.f64 d17, d16
+; CHECK-NEXT: vldr d16, .LCPI0_0
+; CHECK-NEXT: vmovvs.f64 d17, d16
+; CHECK-NEXT: vmoveq.f64 d17, d18
+; CHECK-NEXT: vmov r0, r1, d17
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI0_0:
+; CHECK-NEXT: .long 0 @ double NaN
+; CHECK-NEXT: .long 2146959360
+ %res = call double @llvm.maximum(double %x, double %y)
+ ret double %res
+}
diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
index 5eb508eb12e17..40927ea1f68b4 100644
--- a/llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+++ b/llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
@@ -1930,30 +1930,28 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) {
; SM60-NOFTZ-LABEL: fminimum_acq_rel_float_global_cta(
; SM60-NOFTZ: {
-; SM60-NOFTZ-NEXT: .reg .pred %p<6>;
-; SM60-NOFTZ-NEXT: .reg .b32 %r<9>;
+; SM60-NOFTZ-NEXT: .reg .pred %p<5>;
+; SM60-NOFTZ-NEXT: .reg .b32 %r<8>;
; SM60-NOFTZ-NEXT: .reg .b64 %rd<2>;
; SM60-NOFTZ-EMPTY:
; SM60-NOFTZ-NEXT: // %bb.0:
; SM60-NOFTZ-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
; SM60-NOFTZ-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
; SM60-NOFTZ-NEXT: membar.cta;
-; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r8, [%rd1];
-; SM60-NOFTZ-NEXT: setp.eq.b32 %p3, %r2, -2147483648;
+; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r7, [%rd1];
; SM60-NOFTZ-NEXT: $L__BB64_1: // %atomicrmw.start
; SM60-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-NOFTZ-NEXT: setp.nan.f32 %p1, %r8, %r2;
-; SM60-NOFTZ-NEXT: min.f32 %r3, %r8, %r2;
-; SM60-NOFTZ-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; SM60-NOFTZ-NEXT: setp.eq.b32 %p2, %r8, -2147483648;
-; SM60-NOFTZ-NEXT: selp.f32 %r5, %r8, %r4, %p2;
-; SM60-NOFTZ-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; SM60-NOFTZ-NEXT: setp.eq.f32 %p4, %r4, 0f00000000;
-; SM60-NOFTZ-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r8, %r7;
-; SM60-NOFTZ-NEXT: setp.ne.b32 %p5, %r1, %r8;
-; SM60-NOFTZ-NEXT: mov.b32 %r8, %r1;
-; SM60-NOFTZ-NEXT: @%p5 bra $L__BB64_1;
+; SM60-NOFTZ-NEXT: setp.eq.b32 %p1, %r7, -2147483648;
+; SM60-NOFTZ-NEXT: selp.f32 %r3, %r7, %r2, %p1;
+; SM60-NOFTZ-NEXT: setp.nan.f32 %p2, %r7, %r2;
+; SM60-NOFTZ-NEXT: min.f32 %r4, %r7, %r2;
+; SM60-NOFTZ-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; SM60-NOFTZ-NEXT: setp.eq.f32 %p3, %r7, %r2;
+; SM60-NOFTZ-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r7, %r6;
+; SM60-NOFTZ-NEXT: setp.ne.b32 %p4, %r1, %r7;
+; SM60-NOFTZ-NEXT: mov.b32 %r7, %r1;
+; SM60-NOFTZ-NEXT: @%p4 bra $L__BB64_1;
; SM60-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM60-NOFTZ-NEXT: membar.cta;
; SM60-NOFTZ-NEXT: st.param.b32 [func_retval0], %r1;
@@ -1961,30 +1959,28 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
;
; SM60-FTZ-LABEL: fminimum_acq_rel_float_global_cta(
; SM60-FTZ: {
-; SM60-FTZ-NEXT: .reg .pred %p<6>;
-; SM60-FTZ-NEXT: .reg .b32 %r<9>;
+; SM60-FTZ-NEXT: .reg .pred %p<5>;
+; SM60-FTZ-NEXT: .reg .b32 %r<8>;
; SM60-FTZ-NEXT: .reg .b64 %rd<2>;
; SM60-FTZ-EMPTY:
; SM60-FTZ-NEXT: // %bb.0:
; SM60-FTZ-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
; SM60-FTZ-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
; SM60-FTZ-NEXT: membar.cta;
-; SM60-FTZ-NEXT: ld.volatile.global.b32 %r8, [%rd1];
-; SM60-FTZ-NEXT: setp.eq.b32 %p3, %r2, -2147483648;
+; SM60-FTZ-NEXT: ld.volatile.global.b32 %r7, [%rd1];
; SM60-FTZ-NEXT: $L__BB64_1: // %atomicrmw.start
; SM60-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-FTZ-NEXT: setp.nan.ftz.f32 %p1, %r8, %r2;
-; SM60-FTZ-NEXT: min.ftz.f32 %r3, %r8, %r2;
-; SM60-FTZ-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; SM60-FTZ-NEXT: setp.eq.b32 %p2, %r8, -2147483648;
-; SM60-FTZ-NEXT: selp.f32 %r5, %r8, %r4, %p2;
-; SM60-FTZ-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; SM60-FTZ-NEXT: setp.eq.ftz.f32 %p4, %r4, 0f00000000;
-; SM60-FTZ-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r8, %r7;
-; SM60-FTZ-NEXT: setp.ne.b32 %p5, %r1, %r8;
-; SM60-FTZ-NEXT: mov.b32 %r8, %r1;
-; SM60-FTZ-NEXT: @%p5 bra $L__BB64_1;
+; SM60-FTZ-NEXT: setp.eq.b32 %p1, %r7, -2147483648;
+; SM60-FTZ-NEXT: selp.f32 %r3, %r7, %r2, %p1;
+; SM60-FTZ-NEXT: setp.nan.ftz.f32 %p2, %r7, %r2;
+; SM60-FTZ-NEXT: min.ftz.f32 %r4, %r7, %r2;
+; SM60-FTZ-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; SM60-FTZ-NEXT: setp.eq.ftz.f32 %p3, %r7, %r2;
+; SM60-FTZ-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r7, %r6;
+; SM60-FTZ-NEXT: setp.ne.b32 %p4, %r1, %r7;
+; SM60-FTZ-NEXT: mov.b32 %r7, %r1;
+; SM60-FTZ-NEXT: @%p4 bra $L__BB64_1;
; SM60-FTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM60-FTZ-NEXT: membar.cta;
; SM60-FTZ-NEXT: st.param.b32 [func_retval0], %r1;
@@ -1996,30 +1992,28 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) {
; SM60-NOFTZ-LABEL: fmaximum_acq_rel_float_global_cta(
; SM60-NOFTZ: {
-; SM60-NOFTZ-NEXT: .reg .pred %p<6>;
-; SM60-NOFTZ-NEXT: .reg .b32 %r<9>;
+; SM60-NOFTZ-NEXT: .reg .pred %p<5>;
+; SM60-NOFTZ-NEXT: .reg .b32 %r<8>;
; SM60-NOFTZ-NEXT: .reg .b64 %rd<2>;
; SM60-NOFTZ-EMPTY:
; SM60-NOFTZ-NEXT: // %bb.0:
; SM60-NOFTZ-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
; SM60-NOFTZ-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
; SM60-NOFTZ-NEXT: membar.cta;
-; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r8, [%rd1];
-; SM60-NOFTZ-NEXT: setp.eq.b32 %p3, %r2, 0;
+; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r7, [%rd1];
; SM60-NOFTZ-NEXT: $L__BB65_1: // %atomicrmw.start
; SM60-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-NOFTZ-NEXT: setp.nan.f32 %p1, %r8, %r2;
-; SM60-NOFTZ-NEXT: max.f32 %r3, %r8, %r2;
-; SM60-NOFTZ-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; SM60-NOFTZ-NEXT: setp.eq.b32 %p2, %r8, 0;
-; SM60-NOFTZ-NEXT: selp.f32 %r5, %r8, %r4, %p2;
-; SM60-NOFTZ-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; SM60-NOFTZ-NEXT: setp.eq.f32 %p4, %r4, 0f00000000;
-; SM60-NOFTZ-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r8, %r7;
-; SM60-NOFTZ-NEXT: setp.ne.b32 %p5, %r1, %r8;
-; SM60-NOFTZ-NEXT: mov.b32 %r8, %r1;
-; SM60-NOFTZ-NEXT: @%p5 bra $L__BB65_1;
+; SM60-NOFTZ-NEXT: setp.eq.b32 %p1, %r7, 0;
+; SM60-NOFTZ-NEXT: selp.f32 %r3, %r7, %r2, %p1;
+; SM60-NOFTZ-NEXT: setp.nan.f32 %p2, %r7, %r2;
+; SM60-NOFTZ-NEXT: max.f32 %r4, %r7, %r2;
+; SM60-NOFTZ-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; SM60-NOFTZ-NEXT: setp.eq.f32 %p3, %r7, %r2;
+; SM60-NOFTZ-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r7, %r6;
+; SM60-NOFTZ-NEXT: setp.ne.b32 %p4, %r1, %r7;
+; SM60-NOFTZ-NEXT: mov.b32 %r7, %r1;
+; SM60-NOFTZ-NEXT: @%p4 bra $L__BB65_1;
; SM60-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM60-NOFTZ-NEXT: membar.cta;
; SM60-NOFTZ-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2027,30 +2021,28 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
;
; SM60-FTZ-LABEL: fmaximum_acq_rel_float_global_cta(
; SM60-FTZ: {
-; SM60-FTZ-NEXT: .reg .pred %p<6>;
-; SM60-FTZ-NEXT: .reg .b32 %r<9>;
+; SM60-FTZ-NEXT: .reg .pred %p<5>;
+; SM60-FTZ-NEXT: .reg .b32 %r<8>;
; SM60-FTZ-NEXT: .reg .b64 %rd<2>;
; SM60-FTZ-EMPTY:
; SM60-FTZ-NEXT: // %bb.0:
; SM60-FTZ-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
; SM60-FTZ-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
; SM60-FTZ-NEXT: membar.cta;
-; SM60-FTZ-NEXT: ld.volatile.global.b32 %r8, [%rd1];
-; SM60-FTZ-NEXT: setp.eq.b32 %p3, %r2, 0;
+; SM60-FTZ-NEXT: ld.volatile.global.b32 %r7, [%rd1];
; SM60-FTZ-NEXT: $L__BB65_1: // %atomicrmw.start
; SM60-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-FTZ-NEXT: setp.nan.ftz.f32 %p1, %r8, %r2;
-; SM60-FTZ-NEXT: max.ftz.f32 %r3, %r8, %r2;
-; SM60-FTZ-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; SM60-FTZ-NEXT: setp.eq.b32 %p2, %r8, 0;
-; SM60-FTZ-NEXT: selp.f32 %r5, %r8, %r4, %p2;
-; SM60-FTZ-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; SM60-FTZ-NEXT: setp.eq.ftz.f32 %p4, %r4, 0f00000000;
-; SM60-FTZ-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r8, %r7;
-; SM60-FTZ-NEXT: setp.ne.b32 %p5, %r1, %r8;
-; SM60-FTZ-NEXT: mov.b32 %r8, %r1;
-; SM60-FTZ-NEXT: @%p5 bra $L__BB65_1;
+; SM60-FTZ-NEXT: setp.eq.b32 %p1, %r7, 0;
+; SM60-FTZ-NEXT: selp.f32 %r3, %r7, %r2, %p1;
+; SM60-FTZ-NEXT: setp.nan.ftz.f32 %p2, %r7, %r2;
+; SM60-FTZ-NEXT: max.ftz.f32 %r4, %r7, %r2;
+; SM60-FTZ-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; SM60-FTZ-NEXT: setp.eq.ftz.f32 %p3, %r7, %r2;
+; SM60-FTZ-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r7, %r6;
+; SM60-FTZ-NEXT: setp.ne.b32 %p4, %r1, %r7;
+; SM60-FTZ-NEXT: mov.b32 %r7, %r1;
+; SM60-FTZ-NEXT: @%p4 bra $L__BB65_1;
; SM60-FTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM60-FTZ-NEXT: membar.cta;
; SM60-FTZ-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2155,29 +2147,27 @@ define double @fmax_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) {
; SM60-LABEL: fminimum_acq_rel_double_global_cta(
; SM60: {
-; SM60-NEXT: .reg .pred %p<6>;
-; SM60-NEXT: .reg .b64 %rd<10>;
+; SM60-NEXT: .reg .pred %p<5>;
+; SM60-NEXT: .reg .b64 %rd<9>;
; SM60-EMPTY:
; SM60-NEXT: // %bb.0:
; SM60-NEXT: ld.param.b64 %rd3, [fminimum_acq_rel_double_global_cta_param_1];
; SM60-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_double_global_cta_param_0];
; SM60-NEXT: membar.cta;
-; SM60-NEXT: ld.volatile.global.b64 %rd9, [%rd2];
-; SM60-NEXT: setp.eq.b64 %p3, %rd3, -9223372036854775808;
+; SM60-NEXT: ld.volatile.global.b64 %rd8, [%rd2];
; SM60-NEXT: $L__BB70_1: // %atomicrmw.start
; SM60-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-NEXT: setp.nan.f64 %p1, %rd9, %rd3;
-; SM60-NEXT: min.f64 %rd4, %rd9, %rd3;
-; SM60-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1;
-; SM60-NEXT: setp.eq.b64 %p2, %rd9, -9223372036854775808;
-; SM60-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2;
-; SM60-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3;
-; SM60-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000;
-; SM60-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4;
-; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8;
-; SM60-NEXT: setp.ne.b64 %p5, %rd1, %rd9;
-; SM60-NEXT: mov.b64 %rd9, %rd1;
-; SM60-NEXT: @%p5 bra $L__BB70_1;
+; SM60-NEXT: setp.eq.b64 %p1, %rd8, -9223372036854775808;
+; SM60-NEXT: selp.f64 %rd4, %rd8, %rd3, %p1;
+; SM60-NEXT: setp.nan.f64 %p2, %rd8, %rd3;
+; SM60-NEXT: min.f64 %rd5, %rd8, %rd3;
+; SM60-NEXT: selp.f64 %rd6, 0d7FF8000000000000, %rd5, %p2;
+; SM60-NEXT: setp.eq.f64 %p3, %rd8, %rd3;
+; SM60-NEXT: selp.f64 %rd7, %rd4, %rd6, %p3;
+; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd8, %rd7;
+; SM60-NEXT: setp.ne.b64 %p4, %rd1, %rd8;
+; SM60-NEXT: mov.b64 %rd8, %rd1;
+; SM60-NEXT: @%p4 bra $L__BB70_1;
; SM60-NEXT: // %bb.2: // %atomicrmw.end
; SM60-NEXT: membar.cta;
; SM60-NEXT: st.param.b64 [func_retval0], %rd1;
@@ -2189,29 +2179,27 @@ define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double
define double @fmaximum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) {
; SM60-LABEL: fmaximum_acq_rel_double_global_cta(
; SM60: {
-; SM60-NEXT: .reg .pred %p<6>;
-; SM60-NEXT: .reg .b64 %rd<10>;
+; SM60-NEXT: .reg .pred %p<5>;
+; SM60-NEXT: .reg .b64 %rd<9>;
; SM60-EMPTY:
; SM60-NEXT: // %bb.0:
; SM60-NEXT: ld.param.b64 %rd3, [fmaximum_acq_rel_double_global_cta_param_1];
; SM60-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_double_global_cta_param_0];
; SM60-NEXT: membar.cta;
-; SM60-NEXT: ld.volatile.global.b64 %rd9, [%rd2];
-; SM60-NEXT: setp.eq.b64 %p3, %rd3, 0;
+; SM60-NEXT: ld.volatile.global.b64 %rd8, [%rd2];
; SM60-NEXT: $L__BB71_1: // %atomicrmw.start
; SM60-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-NEXT: setp.nan.f64 %p1, %rd9, %rd3;
-; SM60-NEXT: max.f64 %rd4, %rd9, %rd3;
-; SM60-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1;
-; SM60-NEXT: setp.eq.b64 %p2, %rd9, 0;
-; SM60-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2;
-; SM60-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3;
-; SM60-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000;
-; SM60-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4;
-; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8;
-; SM60-NEXT: setp.ne.b64 %p5, %rd1, %rd9;
-; SM60-NEXT: mov.b64 %rd9, %rd1;
-; SM60-NEXT: @%p5 bra $L__BB71_1;
+; SM60-NEXT: setp.eq.b64 %p1, %rd8, 0;
+; SM60-NEXT: selp.f64 %rd4, %rd8, %rd3, %p1;
+; SM60-NEXT: setp.nan.f64 %p2, %rd8, %rd3;
+; SM60-NEXT: max.f64 %rd5, %rd8, %rd3;
+; SM60-NEXT: selp.f64 %rd6, 0d7FF8000000000000, %rd5, %p2;
+; SM60-NEXT: setp.eq.f64 %p3, %rd8, %rd3;
+; SM60-NEXT: selp.f64 %rd7, %rd4, %rd6, %p3;
+; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd8, %rd7;
+; SM60-NEXT: setp.ne.b64 %p4, %rd1, %rd8;
+; SM60-NEXT: mov.b64 %rd8, %rd1;
+; SM60-NEXT: @%p4 bra $L__BB71_1;
; SM60-NEXT: // %bb.2: // %atomicrmw.end
; SM60-NEXT: membar.cta;
; SM60-NEXT: st.param.b64 [func_retval0], %rd1;
@@ -2555,8 +2543,8 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM60-NOFTZ-LABEL: fminimum_acq_rel_half_global_cta(
; SM60-NOFTZ: {
-; SM60-NOFTZ-NEXT: .reg .pred %p<7>;
-; SM60-NOFTZ-NEXT: .reg .b16 %rs<9>;
+; SM60-NOFTZ-NEXT: .reg .pred %p<6>;
+; SM60-NOFTZ-NEXT: .reg .b16 %rs<7>;
; SM60-NOFTZ-NEXT: .reg .b32 %r<15>;
; SM60-NOFTZ-NEXT: .reg .b64 %rd<3>;
; SM60-NOFTZ-EMPTY:
@@ -2572,29 +2560,26 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM60-NOFTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM60-NOFTZ-NEXT: not.b32 %r2, %r7;
; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r14, [%rd1];
-; SM60-NOFTZ-NEXT: setp.eq.b16 %p4, %rs1, -32768;
; SM60-NOFTZ-NEXT: $L__BB76_1: // %atomicrmw.start
; SM60-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
; SM60-NOFTZ-NEXT: shr.u32 %r8, %r14, %r1;
; SM60-NOFTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM60-NOFTZ-NEXT: setp.lt.f16 %p1, %rs2, %rs1;
+; SM60-NOFTZ-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; SM60-NOFTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM60-NOFTZ-NEXT: setp.nan.f16 %p2, %rs2, %rs1;
-; SM60-NOFTZ-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; SM60-NOFTZ-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; SM60-NOFTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM60-NOFTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM60-NOFTZ-NEXT: mov.b16 %rs7, 0x0000;
-; SM60-NOFTZ-NEXT: setp.eq.f16 %p5, %rs4, %rs7;
-; SM60-NOFTZ-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5;
-; SM60-NOFTZ-NEXT: cvt.u32.u16 %r9, %rs8;
+; SM60-NOFTZ-NEXT: setp.lt.f16 %p2, %rs2, %rs1;
+; SM60-NOFTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM60-NOFTZ-NEXT: setp.nan.f16 %p3, %rs2, %rs1;
+; SM60-NOFTZ-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; SM60-NOFTZ-NEXT: setp.eq.f16 %p4, %rs2, %rs1;
+; SM60-NOFTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM60-NOFTZ-NEXT: cvt.u32.u16 %r9, %rs6;
; SM60-NOFTZ-NEXT: shl.b32 %r10, %r9, %r1;
; SM60-NOFTZ-NEXT: and.b32 %r11, %r14, %r2;
; SM60-NOFTZ-NEXT: or.b32 %r12, %r11, %r10;
; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12;
-; SM60-NOFTZ-NEXT: setp.ne.b32 %p6, %r3, %r14;
+; SM60-NOFTZ-NEXT: setp.ne.b32 %p5, %r3, %r14;
; SM60-NOFTZ-NEXT: mov.b32 %r14, %r3;
-; SM60-NOFTZ-NEXT: @%p6 bra $L__BB76_1;
+; SM60-NOFTZ-NEXT: @%p5 bra $L__BB76_1;
; SM60-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM60-NOFTZ-NEXT: shr.u32 %r13, %r3, %r1;
; SM60-NOFTZ-NEXT: membar.cta;
@@ -2603,8 +2588,8 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
;
; SM60-FTZ-LABEL: fminimum_acq_rel_half_global_cta(
; SM60-FTZ: {
-; SM60-FTZ-NEXT: .reg .pred %p<7>;
-; SM60-FTZ-NEXT: .reg .b16 %rs<9>;
+; SM60-FTZ-NEXT: .reg .pred %p<6>;
+; SM60-FTZ-NEXT: .reg .b16 %rs<7>;
; SM60-FTZ-NEXT: .reg .b32 %r<15>;
; SM60-FTZ-NEXT: .reg .b64 %rd<3>;
; SM60-FTZ-EMPTY:
@@ -2620,29 +2605,26 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM60-FTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM60-FTZ-NEXT: not.b32 %r2, %r7;
; SM60-FTZ-NEXT: ld.volatile.global.b32 %r14, [%rd1];
-; SM60-FTZ-NEXT: setp.eq.b16 %p4, %rs1, -32768;
; SM60-FTZ-NEXT: $L__BB76_1: // %atomicrmw.start
; SM60-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
; SM60-FTZ-NEXT: shr.u32 %r8, %r14, %r1;
; SM60-FTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM60-FTZ-NEXT: setp.lt.ftz.f16 %p1, %rs2, %rs1;
+; SM60-FTZ-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; SM60-FTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM60-FTZ-NEXT: setp.nan.ftz.f16 %p2, %rs2, %rs1;
-; SM60-FTZ-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; SM60-FTZ-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; SM60-FTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM60-FTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM60-FTZ-NEXT: mov.b16 %rs7, 0x0000;
-; SM60-FTZ-NEXT: setp.eq.ftz.f16 %p5, %rs4, %rs7;
-; SM60-FTZ-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5;
-; SM60-FTZ-NEXT: cvt.u32.u16 %r9, %rs8;
+; SM60-FTZ-NEXT: setp.lt.ftz.f16 %p2, %rs2, %rs1;
+; SM60-FTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM60-FTZ-NEXT: setp.nan.ftz.f16 %p3, %rs2, %rs1;
+; SM60-FTZ-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; SM60-FTZ-NEXT: setp.eq.ftz.f16 %p4, %rs2, %rs1;
+; SM60-FTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM60-FTZ-NEXT: cvt.u32.u16 %r9, %rs6;
; SM60-FTZ-NEXT: shl.b32 %r10, %r9, %r1;
; SM60-FTZ-NEXT: and.b32 %r11, %r14, %r2;
; SM60-FTZ-NEXT: or.b32 %r12, %r11, %r10;
; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12;
-; SM60-FTZ-NEXT: setp.ne.b32 %p6, %r3, %r14;
+; SM60-FTZ-NEXT: setp.ne.b32 %p5, %r3, %r14;
; SM60-FTZ-NEXT: mov.b32 %r14, %r3;
-; SM60-FTZ-NEXT: @%p6 bra $L__BB76_1;
+; SM60-FTZ-NEXT: @%p5 bra $L__BB76_1;
; SM60-FTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM60-FTZ-NEXT: shr.u32 %r13, %r3, %r1;
; SM60-FTZ-NEXT: membar.cta;
@@ -2655,8 +2637,8 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM60-NOFTZ-LABEL: fmaximum_acq_rel_half_global_cta(
; SM60-NOFTZ: {
-; SM60-NOFTZ-NEXT: .reg .pred %p<7>;
-; SM60-NOFTZ-NEXT: .reg .b16 %rs<9>;
+; SM60-NOFTZ-NEXT: .reg .pred %p<6>;
+; SM60-NOFTZ-NEXT: .reg .b16 %rs<7>;
; SM60-NOFTZ-NEXT: .reg .b32 %r<15>;
; SM60-NOFTZ-NEXT: .reg .b64 %rd<3>;
; SM60-NOFTZ-EMPTY:
@@ -2672,29 +2654,26 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM60-NOFTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM60-NOFTZ-NEXT: not.b32 %r2, %r7;
; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r14, [%rd1];
-; SM60-NOFTZ-NEXT: setp.eq.b16 %p4, %rs1, 0;
; SM60-NOFTZ-NEXT: $L__BB77_1: // %atomicrmw.start
; SM60-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
; SM60-NOFTZ-NEXT: shr.u32 %r8, %r14, %r1;
; SM60-NOFTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM60-NOFTZ-NEXT: setp.gt.f16 %p1, %rs2, %rs1;
+; SM60-NOFTZ-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM60-NOFTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM60-NOFTZ-NEXT: setp.nan.f16 %p2, %rs2, %rs1;
-; SM60-NOFTZ-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; SM60-NOFTZ-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM60-NOFTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM60-NOFTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM60-NOFTZ-NEXT: mov.b16 %rs7, 0x0000;
-; SM60-NOFTZ-NEXT: setp.eq.f16 %p5, %rs4, %rs7;
-; SM60-NOFTZ-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5;
-; SM60-NOFTZ-NEXT: cvt.u32.u16 %r9, %rs8;
+; SM60-NOFTZ-NEXT: setp.gt.f16 %p2, %rs2, %rs1;
+; SM60-NOFTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM60-NOFTZ-NEXT: setp.nan.f16 %p3, %rs2, %rs1;
+; SM60-NOFTZ-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; SM60-NOFTZ-NEXT: setp.eq.f16 %p4, %rs2, %rs1;
+; SM60-NOFTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM60-NOFTZ-NEXT: cvt.u32.u16 %r9, %rs6;
; SM60-NOFTZ-NEXT: shl.b32 %r10, %r9, %r1;
; SM60-NOFTZ-NEXT: and.b32 %r11, %r14, %r2;
; SM60-NOFTZ-NEXT: or.b32 %r12, %r11, %r10;
; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12;
-; SM60-NOFTZ-NEXT: setp.ne.b32 %p6, %r3, %r14;
+; SM60-NOFTZ-NEXT: setp.ne.b32 %p5, %r3, %r14;
; SM60-NOFTZ-NEXT: mov.b32 %r14, %r3;
-; SM60-NOFTZ-NEXT: @%p6 bra $L__BB77_1;
+; SM60-NOFTZ-NEXT: @%p5 bra $L__BB77_1;
; SM60-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM60-NOFTZ-NEXT: shr.u32 %r13, %r3, %r1;
; SM60-NOFTZ-NEXT: membar.cta;
@@ -2703,8 +2682,8 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
;
; SM60-FTZ-LABEL: fmaximum_acq_rel_half_global_cta(
; SM60-FTZ: {
-; SM60-FTZ-NEXT: .reg .pred %p<7>;
-; SM60-FTZ-NEXT: .reg .b16 %rs<9>;
+; SM60-FTZ-NEXT: .reg .pred %p<6>;
+; SM60-FTZ-NEXT: .reg .b16 %rs<7>;
; SM60-FTZ-NEXT: .reg .b32 %r<15>;
; SM60-FTZ-NEXT: .reg .b64 %rd<3>;
; SM60-FTZ-EMPTY:
@@ -2720,29 +2699,26 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM60-FTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM60-FTZ-NEXT: not.b32 %r2, %r7;
; SM60-FTZ-NEXT: ld.volatile.global.b32 %r14, [%rd1];
-; SM60-FTZ-NEXT: setp.eq.b16 %p4, %rs1, 0;
; SM60-FTZ-NEXT: $L__BB77_1: // %atomicrmw.start
; SM60-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
; SM60-FTZ-NEXT: shr.u32 %r8, %r14, %r1;
; SM60-FTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM60-FTZ-NEXT: setp.gt.ftz.f16 %p1, %rs2, %rs1;
+; SM60-FTZ-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM60-FTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM60-FTZ-NEXT: setp.nan.ftz.f16 %p2, %rs2, %rs1;
-; SM60-FTZ-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; SM60-FTZ-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM60-FTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM60-FTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM60-FTZ-NEXT: mov.b16 %rs7, 0x0000;
-; SM60-FTZ-NEXT: setp.eq.ftz.f16 %p5, %rs4, %rs7;
-; SM60-FTZ-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5;
-; SM60-FTZ-NEXT: cvt.u32.u16 %r9, %rs8;
+; SM60-FTZ-NEXT: setp.gt.ftz.f16 %p2, %rs2, %rs1;
+; SM60-FTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM60-FTZ-NEXT: setp.nan.ftz.f16 %p3, %rs2, %rs1;
+; SM60-FTZ-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; SM60-FTZ-NEXT: setp.eq.ftz.f16 %p4, %rs2, %rs1;
+; SM60-FTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM60-FTZ-NEXT: cvt.u32.u16 %r9, %rs6;
; SM60-FTZ-NEXT: shl.b32 %r10, %r9, %r1;
; SM60-FTZ-NEXT: and.b32 %r11, %r14, %r2;
; SM60-FTZ-NEXT: or.b32 %r12, %r11, %r10;
; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12;
-; SM60-FTZ-NEXT: setp.ne.b32 %p6, %r3, %r14;
+; SM60-FTZ-NEXT: setp.ne.b32 %p5, %r3, %r14;
; SM60-FTZ-NEXT: mov.b32 %r14, %r3;
-; SM60-FTZ-NEXT: @%p6 bra $L__BB77_1;
+; SM60-FTZ-NEXT: @%p5 bra $L__BB77_1;
; SM60-FTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM60-FTZ-NEXT: shr.u32 %r13, %r3, %r1;
; SM60-FTZ-NEXT: membar.cta;
@@ -3139,9 +3115,9 @@ define bfloat @fmax_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) {
; SM60-NOFTZ-LABEL: fminimum_acq_rel_bfloat_global_cta(
; SM60-NOFTZ: {
-; SM60-NOFTZ-NEXT: .reg .pred %p<7>;
-; SM60-NOFTZ-NEXT: .reg .b16 %rs<8>;
-; SM60-NOFTZ-NEXT: .reg .b32 %r<20>;
+; SM60-NOFTZ-NEXT: .reg .pred %p<6>;
+; SM60-NOFTZ-NEXT: .reg .b16 %rs<7>;
+; SM60-NOFTZ-NEXT: .reg .b32 %r<18>;
; SM60-NOFTZ-NEXT: .reg .b64 %rd<3>;
; SM60-NOFTZ-EMPTY:
; SM60-NOFTZ-NEXT: // %bb.0:
@@ -3155,45 +3131,41 @@ define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM60-NOFTZ-NEXT: mov.b32 %r6, 65535;
; SM60-NOFTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM60-NOFTZ-NEXT: not.b32 %r2, %r7;
-; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r19, [%rd1];
+; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r17, [%rd1];
; SM60-NOFTZ-NEXT: cvt.u32.u16 %r10, %rs1;
; SM60-NOFTZ-NEXT: shl.b32 %r11, %r10, 16;
-; SM60-NOFTZ-NEXT: setp.eq.b16 %p4, %rs1, -32768;
; SM60-NOFTZ-NEXT: $L__BB82_1: // %atomicrmw.start
; SM60-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-NOFTZ-NEXT: shr.u32 %r8, %r19, %r1;
+; SM60-NOFTZ-NEXT: shr.u32 %r8, %r17, %r1;
; SM60-NOFTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM60-NOFTZ-NEXT: shl.b32 %r9, %r8, 16;
-; SM60-NOFTZ-NEXT: setp.lt.f32 %p1, %r9, %r11;
+; SM60-NOFTZ-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; SM60-NOFTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM60-NOFTZ-NEXT: setp.nan.f32 %p2, %r9, %r11;
-; SM60-NOFTZ-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM60-NOFTZ-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; SM60-NOFTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM60-NOFTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM60-NOFTZ-NEXT: cvt.u32.u16 %r12, %rs4;
-; SM60-NOFTZ-NEXT: shl.b32 %r13, %r12, 16;
-; SM60-NOFTZ-NEXT: setp.eq.f32 %p5, %r13, 0f00000000;
-; SM60-NOFTZ-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM60-NOFTZ-NEXT: cvt.u32.u16 %r14, %rs7;
-; SM60-NOFTZ-NEXT: shl.b32 %r15, %r14, %r1;
-; SM60-NOFTZ-NEXT: and.b32 %r16, %r19, %r2;
-; SM60-NOFTZ-NEXT: or.b32 %r17, %r16, %r15;
-; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r19, %r17;
-; SM60-NOFTZ-NEXT: setp.ne.b32 %p6, %r3, %r19;
-; SM60-NOFTZ-NEXT: mov.b32 %r19, %r3;
-; SM60-NOFTZ-NEXT: @%p6 bra $L__BB82_1;
+; SM60-NOFTZ-NEXT: shl.b32 %r9, %r8, 16;
+; SM60-NOFTZ-NEXT: setp.lt.f32 %p2, %r9, %r11;
+; SM60-NOFTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM60-NOFTZ-NEXT: setp.nan.f32 %p3, %r9, %r11;
+; SM60-NOFTZ-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM60-NOFTZ-NEXT: setp.eq.f32 %p4, %r9, %r11;
+; SM60-NOFTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM60-NOFTZ-NEXT: cvt.u32.u16 %r12, %rs6;
+; SM60-NOFTZ-NEXT: shl.b32 %r13, %r12, %r1;
+; SM60-NOFTZ-NEXT: and.b32 %r14, %r17, %r2;
+; SM60-NOFTZ-NEXT: or.b32 %r15, %r14, %r13;
+; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r17, %r15;
+; SM60-NOFTZ-NEXT: setp.ne.b32 %p5, %r3, %r17;
+; SM60-NOFTZ-NEXT: mov.b32 %r17, %r3;
+; SM60-NOFTZ-NEXT: @%p5 bra $L__BB82_1;
; SM60-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
-; SM60-NOFTZ-NEXT: shr.u32 %r18, %r3, %r1;
+; SM60-NOFTZ-NEXT: shr.u32 %r16, %r3, %r1;
; SM60-NOFTZ-NEXT: membar.cta;
-; SM60-NOFTZ-NEXT: st.param.b16 [func_retval0], %r18;
+; SM60-NOFTZ-NEXT: st.param.b16 [func_retval0], %r16;
; SM60-NOFTZ-NEXT: ret;
;
; SM60-FTZ-LABEL: fminimum_acq_rel_bfloat_global_cta(
; SM60-FTZ: {
-; SM60-FTZ-NEXT: .reg .pred %p<7>;
-; SM60-FTZ-NEXT: .reg .b16 %rs<8>;
-; SM60-FTZ-NEXT: .reg .b32 %r<20>;
+; SM60-FTZ-NEXT: .reg .pred %p<6>;
+; SM60-FTZ-NEXT: .reg .b16 %rs<7>;
+; SM60-FTZ-NEXT: .reg .b32 %r<18>;
; SM60-FTZ-NEXT: .reg .b64 %rd<3>;
; SM60-FTZ-EMPTY:
; SM60-FTZ-NEXT: // %bb.0:
@@ -3207,38 +3179,34 @@ define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM60-FTZ-NEXT: mov.b32 %r6, 65535;
; SM60-FTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM60-FTZ-NEXT: not.b32 %r2, %r7;
-; SM60-FTZ-NEXT: ld.volatile.global.b32 %r19, [%rd1];
+; SM60-FTZ-NEXT: ld.volatile.global.b32 %r17, [%rd1];
; SM60-FTZ-NEXT: cvt.u32.u16 %r10, %rs1;
; SM60-FTZ-NEXT: shl.b32 %r11, %r10, 16;
-; SM60-FTZ-NEXT: setp.eq.b16 %p4, %rs1, -32768;
; SM60-FTZ-NEXT: $L__BB82_1: // %atomicrmw.start
; SM60-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-FTZ-NEXT: shr.u32 %r8, %r19, %r1;
+; SM60-FTZ-NEXT: shr.u32 %r8, %r17, %r1;
; SM60-FTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM60-FTZ-NEXT: shl.b32 %r9, %r8, 16;
-; SM60-FTZ-NEXT: setp.lt.ftz.f32 %p1, %r9, %r11;
+; SM60-FTZ-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; SM60-FTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM60-FTZ-NEXT: setp.nan.ftz.f32 %p2, %r9, %r11;
-; SM60-FTZ-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM60-FTZ-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; SM60-FTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM60-FTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM60-FTZ-NEXT: cvt.u32.u16 %r12, %rs4;
-; SM60-FTZ-NEXT: shl.b32 %r13, %r12, 16;
-; SM60-FTZ-NEXT: setp.eq.ftz.f32 %p5, %r13, 0f00000000;
-; SM60-FTZ-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM60-FTZ-NEXT: cvt.u32.u16 %r14, %rs7;
-; SM60-FTZ-NEXT: shl.b32 %r15, %r14, %r1;
-; SM60-FTZ-NEXT: and.b32 %r16, %r19, %r2;
-; SM60-FTZ-NEXT: or.b32 %r17, %r16, %r15;
-; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r19, %r17;
-; SM60-FTZ-NEXT: setp.ne.b32 %p6, %r3, %r19;
-; SM60-FTZ-NEXT: mov.b32 %r19, %r3;
-; SM60-FTZ-NEXT: @%p6 bra $L__BB82_1;
+; SM60-FTZ-NEXT: shl.b32 %r9, %r8, 16;
+; SM60-FTZ-NEXT: setp.lt.ftz.f32 %p2, %r9, %r11;
+; SM60-FTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM60-FTZ-NEXT: setp.nan.ftz.f32 %p3, %r9, %r11;
+; SM60-FTZ-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM60-FTZ-NEXT: setp.eq.ftz.f32 %p4, %r9, %r11;
+; SM60-FTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM60-FTZ-NEXT: cvt.u32.u16 %r12, %rs6;
+; SM60-FTZ-NEXT: shl.b32 %r13, %r12, %r1;
+; SM60-FTZ-NEXT: and.b32 %r14, %r17, %r2;
+; SM60-FTZ-NEXT: or.b32 %r15, %r14, %r13;
+; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r17, %r15;
+; SM60-FTZ-NEXT: setp.ne.b32 %p5, %r3, %r17;
+; SM60-FTZ-NEXT: mov.b32 %r17, %r3;
+; SM60-FTZ-NEXT: @%p5 bra $L__BB82_1;
; SM60-FTZ-NEXT: // %bb.2: // %atomicrmw.end
-; SM60-FTZ-NEXT: shr.u32 %r18, %r3, %r1;
+; SM60-FTZ-NEXT: shr.u32 %r16, %r3, %r1;
; SM60-FTZ-NEXT: membar.cta;
-; SM60-FTZ-NEXT: st.param.b16 [func_retval0], %r18;
+; SM60-FTZ-NEXT: st.param.b16 [func_retval0], %r16;
; SM60-FTZ-NEXT: ret;
%retval = atomicrmw fminimum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
@@ -3247,9 +3215,9 @@ define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) {
; SM60-NOFTZ-LABEL: fmaximum_acq_rel_bfloat_global_cta(
; SM60-NOFTZ: {
-; SM60-NOFTZ-NEXT: .reg .pred %p<7>;
-; SM60-NOFTZ-NEXT: .reg .b16 %rs<8>;
-; SM60-NOFTZ-NEXT: .reg .b32 %r<20>;
+; SM60-NOFTZ-NEXT: .reg .pred %p<6>;
+; SM60-NOFTZ-NEXT: .reg .b16 %rs<7>;
+; SM60-NOFTZ-NEXT: .reg .b32 %r<18>;
; SM60-NOFTZ-NEXT: .reg .b64 %rd<3>;
; SM60-NOFTZ-EMPTY:
; SM60-NOFTZ-NEXT: // %bb.0:
@@ -3263,45 +3231,41 @@ define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM60-NOFTZ-NEXT: mov.b32 %r6, 65535;
; SM60-NOFTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM60-NOFTZ-NEXT: not.b32 %r2, %r7;
-; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r19, [%rd1];
+; SM60-NOFTZ-NEXT: ld.volatile.global.b32 %r17, [%rd1];
; SM60-NOFTZ-NEXT: cvt.u32.u16 %r10, %rs1;
; SM60-NOFTZ-NEXT: shl.b32 %r11, %r10, 16;
-; SM60-NOFTZ-NEXT: setp.eq.b16 %p4, %rs1, 0;
; SM60-NOFTZ-NEXT: $L__BB83_1: // %atomicrmw.start
; SM60-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-NOFTZ-NEXT: shr.u32 %r8, %r19, %r1;
+; SM60-NOFTZ-NEXT: shr.u32 %r8, %r17, %r1;
; SM60-NOFTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM60-NOFTZ-NEXT: shl.b32 %r9, %r8, 16;
-; SM60-NOFTZ-NEXT: setp.gt.f32 %p1, %r9, %r11;
+; SM60-NOFTZ-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM60-NOFTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM60-NOFTZ-NEXT: setp.nan.f32 %p2, %r9, %r11;
-; SM60-NOFTZ-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM60-NOFTZ-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM60-NOFTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM60-NOFTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM60-NOFTZ-NEXT: cvt.u32.u16 %r12, %rs4;
-; SM60-NOFTZ-NEXT: shl.b32 %r13, %r12, 16;
-; SM60-NOFTZ-NEXT: setp.eq.f32 %p5, %r13, 0f00000000;
-; SM60-NOFTZ-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM60-NOFTZ-NEXT: cvt.u32.u16 %r14, %rs7;
-; SM60-NOFTZ-NEXT: shl.b32 %r15, %r14, %r1;
-; SM60-NOFTZ-NEXT: and.b32 %r16, %r19, %r2;
-; SM60-NOFTZ-NEXT: or.b32 %r17, %r16, %r15;
-; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r19, %r17;
-; SM60-NOFTZ-NEXT: setp.ne.b32 %p6, %r3, %r19;
-; SM60-NOFTZ-NEXT: mov.b32 %r19, %r3;
-; SM60-NOFTZ-NEXT: @%p6 bra $L__BB83_1;
+; SM60-NOFTZ-NEXT: shl.b32 %r9, %r8, 16;
+; SM60-NOFTZ-NEXT: setp.gt.f32 %p2, %r9, %r11;
+; SM60-NOFTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM60-NOFTZ-NEXT: setp.nan.f32 %p3, %r9, %r11;
+; SM60-NOFTZ-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM60-NOFTZ-NEXT: setp.eq.f32 %p4, %r9, %r11;
+; SM60-NOFTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM60-NOFTZ-NEXT: cvt.u32.u16 %r12, %rs6;
+; SM60-NOFTZ-NEXT: shl.b32 %r13, %r12, %r1;
+; SM60-NOFTZ-NEXT: and.b32 %r14, %r17, %r2;
+; SM60-NOFTZ-NEXT: or.b32 %r15, %r14, %r13;
+; SM60-NOFTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r17, %r15;
+; SM60-NOFTZ-NEXT: setp.ne.b32 %p5, %r3, %r17;
+; SM60-NOFTZ-NEXT: mov.b32 %r17, %r3;
+; SM60-NOFTZ-NEXT: @%p5 bra $L__BB83_1;
; SM60-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
-; SM60-NOFTZ-NEXT: shr.u32 %r18, %r3, %r1;
+; SM60-NOFTZ-NEXT: shr.u32 %r16, %r3, %r1;
; SM60-NOFTZ-NEXT: membar.cta;
-; SM60-NOFTZ-NEXT: st.param.b16 [func_retval0], %r18;
+; SM60-NOFTZ-NEXT: st.param.b16 [func_retval0], %r16;
; SM60-NOFTZ-NEXT: ret;
;
; SM60-FTZ-LABEL: fmaximum_acq_rel_bfloat_global_cta(
; SM60-FTZ: {
-; SM60-FTZ-NEXT: .reg .pred %p<7>;
-; SM60-FTZ-NEXT: .reg .b16 %rs<8>;
-; SM60-FTZ-NEXT: .reg .b32 %r<20>;
+; SM60-FTZ-NEXT: .reg .pred %p<6>;
+; SM60-FTZ-NEXT: .reg .b16 %rs<7>;
+; SM60-FTZ-NEXT: .reg .b32 %r<18>;
; SM60-FTZ-NEXT: .reg .b64 %rd<3>;
; SM60-FTZ-EMPTY:
; SM60-FTZ-NEXT: // %bb.0:
@@ -3315,38 +3279,34 @@ define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM60-FTZ-NEXT: mov.b32 %r6, 65535;
; SM60-FTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM60-FTZ-NEXT: not.b32 %r2, %r7;
-; SM60-FTZ-NEXT: ld.volatile.global.b32 %r19, [%rd1];
+; SM60-FTZ-NEXT: ld.volatile.global.b32 %r17, [%rd1];
; SM60-FTZ-NEXT: cvt.u32.u16 %r10, %rs1;
; SM60-FTZ-NEXT: shl.b32 %r11, %r10, 16;
-; SM60-FTZ-NEXT: setp.eq.b16 %p4, %rs1, 0;
; SM60-FTZ-NEXT: $L__BB83_1: // %atomicrmw.start
; SM60-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM60-FTZ-NEXT: shr.u32 %r8, %r19, %r1;
+; SM60-FTZ-NEXT: shr.u32 %r8, %r17, %r1;
; SM60-FTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM60-FTZ-NEXT: shl.b32 %r9, %r8, 16;
-; SM60-FTZ-NEXT: setp.gt.ftz.f32 %p1, %r9, %r11;
+; SM60-FTZ-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM60-FTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM60-FTZ-NEXT: setp.nan.ftz.f32 %p2, %r9, %r11;
-; SM60-FTZ-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM60-FTZ-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM60-FTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM60-FTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM60-FTZ-NEXT: cvt.u32.u16 %r12, %rs4;
-; SM60-FTZ-NEXT: shl.b32 %r13, %r12, 16;
-; SM60-FTZ-NEXT: setp.eq.ftz.f32 %p5, %r13, 0f00000000;
-; SM60-FTZ-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM60-FTZ-NEXT: cvt.u32.u16 %r14, %rs7;
-; SM60-FTZ-NEXT: shl.b32 %r15, %r14, %r1;
-; SM60-FTZ-NEXT: and.b32 %r16, %r19, %r2;
-; SM60-FTZ-NEXT: or.b32 %r17, %r16, %r15;
-; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r19, %r17;
-; SM60-FTZ-NEXT: setp.ne.b32 %p6, %r3, %r19;
-; SM60-FTZ-NEXT: mov.b32 %r19, %r3;
-; SM60-FTZ-NEXT: @%p6 bra $L__BB83_1;
+; SM60-FTZ-NEXT: shl.b32 %r9, %r8, 16;
+; SM60-FTZ-NEXT: setp.gt.ftz.f32 %p2, %r9, %r11;
+; SM60-FTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM60-FTZ-NEXT: setp.nan.ftz.f32 %p3, %r9, %r11;
+; SM60-FTZ-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM60-FTZ-NEXT: setp.eq.ftz.f32 %p4, %r9, %r11;
+; SM60-FTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM60-FTZ-NEXT: cvt.u32.u16 %r12, %rs6;
+; SM60-FTZ-NEXT: shl.b32 %r13, %r12, %r1;
+; SM60-FTZ-NEXT: and.b32 %r14, %r17, %r2;
+; SM60-FTZ-NEXT: or.b32 %r15, %r14, %r13;
+; SM60-FTZ-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r17, %r15;
+; SM60-FTZ-NEXT: setp.ne.b32 %p5, %r3, %r17;
+; SM60-FTZ-NEXT: mov.b32 %r17, %r3;
+; SM60-FTZ-NEXT: @%p5 bra $L__BB83_1;
; SM60-FTZ-NEXT: // %bb.2: // %atomicrmw.end
-; SM60-FTZ-NEXT: shr.u32 %r18, %r3, %r1;
+; SM60-FTZ-NEXT: shr.u32 %r16, %r3, %r1;
; SM60-FTZ-NEXT: membar.cta;
-; SM60-FTZ-NEXT: st.param.b16 [func_retval0], %r18;
+; SM60-FTZ-NEXT: st.param.b16 [func_retval0], %r16;
; SM60-FTZ-NEXT: ret;
%retval = atomicrmw fmaximum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
index 10744421115b4..b0342d66c0afd 100644
--- a/llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+++ b/llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
@@ -1930,30 +1930,28 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) {
; SM70-NOFTZ-LABEL: fminimum_acq_rel_float_global_cta(
; SM70-NOFTZ: {
-; SM70-NOFTZ-NEXT: .reg .pred %p<6>;
-; SM70-NOFTZ-NEXT: .reg .b32 %r<9>;
+; SM70-NOFTZ-NEXT: .reg .pred %p<5>;
+; SM70-NOFTZ-NEXT: .reg .b32 %r<8>;
; SM70-NOFTZ-NEXT: .reg .b64 %rd<2>;
; SM70-NOFTZ-EMPTY:
; SM70-NOFTZ-NEXT: // %bb.0:
; SM70-NOFTZ-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
; SM70-NOFTZ-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
; SM70-NOFTZ-NEXT: fence.acq_rel.cta;
-; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r8, [%rd1];
-; SM70-NOFTZ-NEXT: setp.eq.b32 %p3, %r2, -2147483648;
+; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r7, [%rd1];
; SM70-NOFTZ-NEXT: $L__BB64_1: // %atomicrmw.start
; SM70-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-NOFTZ-NEXT: setp.nan.f32 %p1, %r8, %r2;
-; SM70-NOFTZ-NEXT: min.f32 %r3, %r8, %r2;
-; SM70-NOFTZ-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; SM70-NOFTZ-NEXT: setp.eq.b32 %p2, %r8, -2147483648;
-; SM70-NOFTZ-NEXT: selp.f32 %r5, %r8, %r4, %p2;
-; SM70-NOFTZ-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; SM70-NOFTZ-NEXT: setp.eq.f32 %p4, %r4, 0f00000000;
-; SM70-NOFTZ-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r8, %r7;
-; SM70-NOFTZ-NEXT: setp.ne.b32 %p5, %r1, %r8;
-; SM70-NOFTZ-NEXT: mov.b32 %r8, %r1;
-; SM70-NOFTZ-NEXT: @%p5 bra $L__BB64_1;
+; SM70-NOFTZ-NEXT: setp.eq.b32 %p1, %r7, -2147483648;
+; SM70-NOFTZ-NEXT: selp.f32 %r3, %r7, %r2, %p1;
+; SM70-NOFTZ-NEXT: setp.nan.f32 %p2, %r7, %r2;
+; SM70-NOFTZ-NEXT: min.f32 %r4, %r7, %r2;
+; SM70-NOFTZ-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; SM70-NOFTZ-NEXT: setp.eq.f32 %p3, %r7, %r2;
+; SM70-NOFTZ-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r7, %r6;
+; SM70-NOFTZ-NEXT: setp.ne.b32 %p4, %r1, %r7;
+; SM70-NOFTZ-NEXT: mov.b32 %r7, %r1;
+; SM70-NOFTZ-NEXT: @%p4 bra $L__BB64_1;
; SM70-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM70-NOFTZ-NEXT: fence.acq_rel.cta;
; SM70-NOFTZ-NEXT: st.param.b32 [func_retval0], %r1;
@@ -1961,30 +1959,28 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
;
; SM70-FTZ-LABEL: fminimum_acq_rel_float_global_cta(
; SM70-FTZ: {
-; SM70-FTZ-NEXT: .reg .pred %p<6>;
-; SM70-FTZ-NEXT: .reg .b32 %r<9>;
+; SM70-FTZ-NEXT: .reg .pred %p<5>;
+; SM70-FTZ-NEXT: .reg .b32 %r<8>;
; SM70-FTZ-NEXT: .reg .b64 %rd<2>;
; SM70-FTZ-EMPTY:
; SM70-FTZ-NEXT: // %bb.0:
; SM70-FTZ-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
; SM70-FTZ-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
; SM70-FTZ-NEXT: fence.acq_rel.cta;
-; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r8, [%rd1];
-; SM70-FTZ-NEXT: setp.eq.b32 %p3, %r2, -2147483648;
+; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r7, [%rd1];
; SM70-FTZ-NEXT: $L__BB64_1: // %atomicrmw.start
; SM70-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-FTZ-NEXT: setp.nan.ftz.f32 %p1, %r8, %r2;
-; SM70-FTZ-NEXT: min.ftz.f32 %r3, %r8, %r2;
-; SM70-FTZ-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; SM70-FTZ-NEXT: setp.eq.b32 %p2, %r8, -2147483648;
-; SM70-FTZ-NEXT: selp.f32 %r5, %r8, %r4, %p2;
-; SM70-FTZ-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; SM70-FTZ-NEXT: setp.eq.ftz.f32 %p4, %r4, 0f00000000;
-; SM70-FTZ-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r8, %r7;
-; SM70-FTZ-NEXT: setp.ne.b32 %p5, %r1, %r8;
-; SM70-FTZ-NEXT: mov.b32 %r8, %r1;
-; SM70-FTZ-NEXT: @%p5 bra $L__BB64_1;
+; SM70-FTZ-NEXT: setp.eq.b32 %p1, %r7, -2147483648;
+; SM70-FTZ-NEXT: selp.f32 %r3, %r7, %r2, %p1;
+; SM70-FTZ-NEXT: setp.nan.ftz.f32 %p2, %r7, %r2;
+; SM70-FTZ-NEXT: min.ftz.f32 %r4, %r7, %r2;
+; SM70-FTZ-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; SM70-FTZ-NEXT: setp.eq.ftz.f32 %p3, %r7, %r2;
+; SM70-FTZ-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r7, %r6;
+; SM70-FTZ-NEXT: setp.ne.b32 %p4, %r1, %r7;
+; SM70-FTZ-NEXT: mov.b32 %r7, %r1;
+; SM70-FTZ-NEXT: @%p4 bra $L__BB64_1;
; SM70-FTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM70-FTZ-NEXT: fence.acq_rel.cta;
; SM70-FTZ-NEXT: st.param.b32 [func_retval0], %r1;
@@ -1996,30 +1992,28 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) {
; SM70-NOFTZ-LABEL: fmaximum_acq_rel_float_global_cta(
; SM70-NOFTZ: {
-; SM70-NOFTZ-NEXT: .reg .pred %p<6>;
-; SM70-NOFTZ-NEXT: .reg .b32 %r<9>;
+; SM70-NOFTZ-NEXT: .reg .pred %p<5>;
+; SM70-NOFTZ-NEXT: .reg .b32 %r<8>;
; SM70-NOFTZ-NEXT: .reg .b64 %rd<2>;
; SM70-NOFTZ-EMPTY:
; SM70-NOFTZ-NEXT: // %bb.0:
; SM70-NOFTZ-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
; SM70-NOFTZ-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
; SM70-NOFTZ-NEXT: fence.acq_rel.cta;
-; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r8, [%rd1];
-; SM70-NOFTZ-NEXT: setp.eq.b32 %p3, %r2, 0;
+; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r7, [%rd1];
; SM70-NOFTZ-NEXT: $L__BB65_1: // %atomicrmw.start
; SM70-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-NOFTZ-NEXT: setp.nan.f32 %p1, %r8, %r2;
-; SM70-NOFTZ-NEXT: max.f32 %r3, %r8, %r2;
-; SM70-NOFTZ-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; SM70-NOFTZ-NEXT: setp.eq.b32 %p2, %r8, 0;
-; SM70-NOFTZ-NEXT: selp.f32 %r5, %r8, %r4, %p2;
-; SM70-NOFTZ-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; SM70-NOFTZ-NEXT: setp.eq.f32 %p4, %r4, 0f00000000;
-; SM70-NOFTZ-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r8, %r7;
-; SM70-NOFTZ-NEXT: setp.ne.b32 %p5, %r1, %r8;
-; SM70-NOFTZ-NEXT: mov.b32 %r8, %r1;
-; SM70-NOFTZ-NEXT: @%p5 bra $L__BB65_1;
+; SM70-NOFTZ-NEXT: setp.eq.b32 %p1, %r7, 0;
+; SM70-NOFTZ-NEXT: selp.f32 %r3, %r7, %r2, %p1;
+; SM70-NOFTZ-NEXT: setp.nan.f32 %p2, %r7, %r2;
+; SM70-NOFTZ-NEXT: max.f32 %r4, %r7, %r2;
+; SM70-NOFTZ-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; SM70-NOFTZ-NEXT: setp.eq.f32 %p3, %r7, %r2;
+; SM70-NOFTZ-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r7, %r6;
+; SM70-NOFTZ-NEXT: setp.ne.b32 %p4, %r1, %r7;
+; SM70-NOFTZ-NEXT: mov.b32 %r7, %r1;
+; SM70-NOFTZ-NEXT: @%p4 bra $L__BB65_1;
; SM70-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM70-NOFTZ-NEXT: fence.acq_rel.cta;
; SM70-NOFTZ-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2027,30 +2021,28 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
;
; SM70-FTZ-LABEL: fmaximum_acq_rel_float_global_cta(
; SM70-FTZ: {
-; SM70-FTZ-NEXT: .reg .pred %p<6>;
-; SM70-FTZ-NEXT: .reg .b32 %r<9>;
+; SM70-FTZ-NEXT: .reg .pred %p<5>;
+; SM70-FTZ-NEXT: .reg .b32 %r<8>;
; SM70-FTZ-NEXT: .reg .b64 %rd<2>;
; SM70-FTZ-EMPTY:
; SM70-FTZ-NEXT: // %bb.0:
; SM70-FTZ-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
; SM70-FTZ-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
; SM70-FTZ-NEXT: fence.acq_rel.cta;
-; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r8, [%rd1];
-; SM70-FTZ-NEXT: setp.eq.b32 %p3, %r2, 0;
+; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r7, [%rd1];
; SM70-FTZ-NEXT: $L__BB65_1: // %atomicrmw.start
; SM70-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-FTZ-NEXT: setp.nan.ftz.f32 %p1, %r8, %r2;
-; SM70-FTZ-NEXT: max.ftz.f32 %r3, %r8, %r2;
-; SM70-FTZ-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; SM70-FTZ-NEXT: setp.eq.b32 %p2, %r8, 0;
-; SM70-FTZ-NEXT: selp.f32 %r5, %r8, %r4, %p2;
-; SM70-FTZ-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; SM70-FTZ-NEXT: setp.eq.ftz.f32 %p4, %r4, 0f00000000;
-; SM70-FTZ-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r8, %r7;
-; SM70-FTZ-NEXT: setp.ne.b32 %p5, %r1, %r8;
-; SM70-FTZ-NEXT: mov.b32 %r8, %r1;
-; SM70-FTZ-NEXT: @%p5 bra $L__BB65_1;
+; SM70-FTZ-NEXT: setp.eq.b32 %p1, %r7, 0;
+; SM70-FTZ-NEXT: selp.f32 %r3, %r7, %r2, %p1;
+; SM70-FTZ-NEXT: setp.nan.ftz.f32 %p2, %r7, %r2;
+; SM70-FTZ-NEXT: max.ftz.f32 %r4, %r7, %r2;
+; SM70-FTZ-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; SM70-FTZ-NEXT: setp.eq.ftz.f32 %p3, %r7, %r2;
+; SM70-FTZ-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r7, %r6;
+; SM70-FTZ-NEXT: setp.ne.b32 %p4, %r1, %r7;
+; SM70-FTZ-NEXT: mov.b32 %r7, %r1;
+; SM70-FTZ-NEXT: @%p4 bra $L__BB65_1;
; SM70-FTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM70-FTZ-NEXT: fence.acq_rel.cta;
; SM70-FTZ-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2155,29 +2147,27 @@ define double @fmax_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) {
; SM70-LABEL: fminimum_acq_rel_double_global_cta(
; SM70: {
-; SM70-NEXT: .reg .pred %p<6>;
-; SM70-NEXT: .reg .b64 %rd<10>;
+; SM70-NEXT: .reg .pred %p<5>;
+; SM70-NEXT: .reg .b64 %rd<9>;
; SM70-EMPTY:
; SM70-NEXT: // %bb.0:
; SM70-NEXT: ld.param.b64 %rd3, [fminimum_acq_rel_double_global_cta_param_1];
; SM70-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_double_global_cta_param_0];
; SM70-NEXT: fence.acq_rel.cta;
-; SM70-NEXT: ld.relaxed.cta.global.b64 %rd9, [%rd2];
-; SM70-NEXT: setp.eq.b64 %p3, %rd3, -9223372036854775808;
+; SM70-NEXT: ld.relaxed.cta.global.b64 %rd8, [%rd2];
; SM70-NEXT: $L__BB70_1: // %atomicrmw.start
; SM70-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-NEXT: setp.nan.f64 %p1, %rd9, %rd3;
-; SM70-NEXT: min.f64 %rd4, %rd9, %rd3;
-; SM70-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1;
-; SM70-NEXT: setp.eq.b64 %p2, %rd9, -9223372036854775808;
-; SM70-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2;
-; SM70-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3;
-; SM70-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000;
-; SM70-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4;
-; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8;
-; SM70-NEXT: setp.ne.b64 %p5, %rd1, %rd9;
-; SM70-NEXT: mov.b64 %rd9, %rd1;
-; SM70-NEXT: @%p5 bra $L__BB70_1;
+; SM70-NEXT: setp.eq.b64 %p1, %rd8, -9223372036854775808;
+; SM70-NEXT: selp.f64 %rd4, %rd8, %rd3, %p1;
+; SM70-NEXT: setp.nan.f64 %p2, %rd8, %rd3;
+; SM70-NEXT: min.f64 %rd5, %rd8, %rd3;
+; SM70-NEXT: selp.f64 %rd6, 0d7FF8000000000000, %rd5, %p2;
+; SM70-NEXT: setp.eq.f64 %p3, %rd8, %rd3;
+; SM70-NEXT: selp.f64 %rd7, %rd4, %rd6, %p3;
+; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd8, %rd7;
+; SM70-NEXT: setp.ne.b64 %p4, %rd1, %rd8;
+; SM70-NEXT: mov.b64 %rd8, %rd1;
+; SM70-NEXT: @%p4 bra $L__BB70_1;
; SM70-NEXT: // %bb.2: // %atomicrmw.end
; SM70-NEXT: fence.acq_rel.cta;
; SM70-NEXT: st.param.b64 [func_retval0], %rd1;
@@ -2189,29 +2179,27 @@ define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double
define double @fmaximum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) {
; SM70-LABEL: fmaximum_acq_rel_double_global_cta(
; SM70: {
-; SM70-NEXT: .reg .pred %p<6>;
-; SM70-NEXT: .reg .b64 %rd<10>;
+; SM70-NEXT: .reg .pred %p<5>;
+; SM70-NEXT: .reg .b64 %rd<9>;
; SM70-EMPTY:
; SM70-NEXT: // %bb.0:
; SM70-NEXT: ld.param.b64 %rd3, [fmaximum_acq_rel_double_global_cta_param_1];
; SM70-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_double_global_cta_param_0];
; SM70-NEXT: fence.acq_rel.cta;
-; SM70-NEXT: ld.relaxed.cta.global.b64 %rd9, [%rd2];
-; SM70-NEXT: setp.eq.b64 %p3, %rd3, 0;
+; SM70-NEXT: ld.relaxed.cta.global.b64 %rd8, [%rd2];
; SM70-NEXT: $L__BB71_1: // %atomicrmw.start
; SM70-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-NEXT: setp.nan.f64 %p1, %rd9, %rd3;
-; SM70-NEXT: max.f64 %rd4, %rd9, %rd3;
-; SM70-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1;
-; SM70-NEXT: setp.eq.b64 %p2, %rd9, 0;
-; SM70-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2;
-; SM70-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3;
-; SM70-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000;
-; SM70-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4;
-; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8;
-; SM70-NEXT: setp.ne.b64 %p5, %rd1, %rd9;
-; SM70-NEXT: mov.b64 %rd9, %rd1;
-; SM70-NEXT: @%p5 bra $L__BB71_1;
+; SM70-NEXT: setp.eq.b64 %p1, %rd8, 0;
+; SM70-NEXT: selp.f64 %rd4, %rd8, %rd3, %p1;
+; SM70-NEXT: setp.nan.f64 %p2, %rd8, %rd3;
+; SM70-NEXT: max.f64 %rd5, %rd8, %rd3;
+; SM70-NEXT: selp.f64 %rd6, 0d7FF8000000000000, %rd5, %p2;
+; SM70-NEXT: setp.eq.f64 %p3, %rd8, %rd3;
+; SM70-NEXT: selp.f64 %rd7, %rd4, %rd6, %p3;
+; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd8, %rd7;
+; SM70-NEXT: setp.ne.b64 %p4, %rd1, %rd8;
+; SM70-NEXT: mov.b64 %rd8, %rd1;
+; SM70-NEXT: @%p4 bra $L__BB71_1;
; SM70-NEXT: // %bb.2: // %atomicrmw.end
; SM70-NEXT: fence.acq_rel.cta;
; SM70-NEXT: st.param.b64 [func_retval0], %rd1;
@@ -2529,8 +2517,8 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM70-NOFTZ-LABEL: fminimum_acq_rel_half_global_cta(
; SM70-NOFTZ: {
-; SM70-NOFTZ-NEXT: .reg .pred %p<7>;
-; SM70-NOFTZ-NEXT: .reg .b16 %rs<9>;
+; SM70-NOFTZ-NEXT: .reg .pred %p<6>;
+; SM70-NOFTZ-NEXT: .reg .b16 %rs<7>;
; SM70-NOFTZ-NEXT: .reg .b32 %r<15>;
; SM70-NOFTZ-NEXT: .reg .b64 %rd<3>;
; SM70-NOFTZ-EMPTY:
@@ -2546,29 +2534,26 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM70-NOFTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM70-NOFTZ-NEXT: not.b32 %r2, %r7;
; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r14, [%rd1];
-; SM70-NOFTZ-NEXT: setp.eq.b16 %p4, %rs1, -32768;
; SM70-NOFTZ-NEXT: $L__BB76_1: // %atomicrmw.start
; SM70-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
; SM70-NOFTZ-NEXT: shr.u32 %r8, %r14, %r1;
; SM70-NOFTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM70-NOFTZ-NEXT: setp.lt.f16 %p1, %rs2, %rs1;
+; SM70-NOFTZ-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; SM70-NOFTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM70-NOFTZ-NEXT: setp.nan.f16 %p2, %rs2, %rs1;
-; SM70-NOFTZ-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; SM70-NOFTZ-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; SM70-NOFTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM70-NOFTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM70-NOFTZ-NEXT: mov.b16 %rs7, 0x0000;
-; SM70-NOFTZ-NEXT: setp.eq.f16 %p5, %rs4, %rs7;
-; SM70-NOFTZ-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5;
-; SM70-NOFTZ-NEXT: cvt.u32.u16 %r9, %rs8;
+; SM70-NOFTZ-NEXT: setp.lt.f16 %p2, %rs2, %rs1;
+; SM70-NOFTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM70-NOFTZ-NEXT: setp.nan.f16 %p3, %rs2, %rs1;
+; SM70-NOFTZ-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; SM70-NOFTZ-NEXT: setp.eq.f16 %p4, %rs2, %rs1;
+; SM70-NOFTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-NOFTZ-NEXT: cvt.u32.u16 %r9, %rs6;
; SM70-NOFTZ-NEXT: shl.b32 %r10, %r9, %r1;
; SM70-NOFTZ-NEXT: and.b32 %r11, %r14, %r2;
; SM70-NOFTZ-NEXT: or.b32 %r12, %r11, %r10;
; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12;
-; SM70-NOFTZ-NEXT: setp.ne.b32 %p6, %r3, %r14;
+; SM70-NOFTZ-NEXT: setp.ne.b32 %p5, %r3, %r14;
; SM70-NOFTZ-NEXT: mov.b32 %r14, %r3;
-; SM70-NOFTZ-NEXT: @%p6 bra $L__BB76_1;
+; SM70-NOFTZ-NEXT: @%p5 bra $L__BB76_1;
; SM70-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM70-NOFTZ-NEXT: shr.u32 %r13, %r3, %r1;
; SM70-NOFTZ-NEXT: fence.acq_rel.cta;
@@ -2577,8 +2562,8 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
;
; SM70-FTZ-LABEL: fminimum_acq_rel_half_global_cta(
; SM70-FTZ: {
-; SM70-FTZ-NEXT: .reg .pred %p<7>;
-; SM70-FTZ-NEXT: .reg .b16 %rs<9>;
+; SM70-FTZ-NEXT: .reg .pred %p<6>;
+; SM70-FTZ-NEXT: .reg .b16 %rs<7>;
; SM70-FTZ-NEXT: .reg .b32 %r<15>;
; SM70-FTZ-NEXT: .reg .b64 %rd<3>;
; SM70-FTZ-EMPTY:
@@ -2594,29 +2579,26 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM70-FTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM70-FTZ-NEXT: not.b32 %r2, %r7;
; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r14, [%rd1];
-; SM70-FTZ-NEXT: setp.eq.b16 %p4, %rs1, -32768;
; SM70-FTZ-NEXT: $L__BB76_1: // %atomicrmw.start
; SM70-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
; SM70-FTZ-NEXT: shr.u32 %r8, %r14, %r1;
; SM70-FTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM70-FTZ-NEXT: setp.lt.ftz.f16 %p1, %rs2, %rs1;
+; SM70-FTZ-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; SM70-FTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM70-FTZ-NEXT: setp.nan.ftz.f16 %p2, %rs2, %rs1;
-; SM70-FTZ-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; SM70-FTZ-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; SM70-FTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM70-FTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM70-FTZ-NEXT: mov.b16 %rs7, 0x0000;
-; SM70-FTZ-NEXT: setp.eq.ftz.f16 %p5, %rs4, %rs7;
-; SM70-FTZ-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5;
-; SM70-FTZ-NEXT: cvt.u32.u16 %r9, %rs8;
+; SM70-FTZ-NEXT: setp.lt.ftz.f16 %p2, %rs2, %rs1;
+; SM70-FTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM70-FTZ-NEXT: setp.nan.ftz.f16 %p3, %rs2, %rs1;
+; SM70-FTZ-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; SM70-FTZ-NEXT: setp.eq.ftz.f16 %p4, %rs2, %rs1;
+; SM70-FTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-FTZ-NEXT: cvt.u32.u16 %r9, %rs6;
; SM70-FTZ-NEXT: shl.b32 %r10, %r9, %r1;
; SM70-FTZ-NEXT: and.b32 %r11, %r14, %r2;
; SM70-FTZ-NEXT: or.b32 %r12, %r11, %r10;
; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12;
-; SM70-FTZ-NEXT: setp.ne.b32 %p6, %r3, %r14;
+; SM70-FTZ-NEXT: setp.ne.b32 %p5, %r3, %r14;
; SM70-FTZ-NEXT: mov.b32 %r14, %r3;
-; SM70-FTZ-NEXT: @%p6 bra $L__BB76_1;
+; SM70-FTZ-NEXT: @%p5 bra $L__BB76_1;
; SM70-FTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM70-FTZ-NEXT: shr.u32 %r13, %r3, %r1;
; SM70-FTZ-NEXT: fence.acq_rel.cta;
@@ -2629,8 +2611,8 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM70-NOFTZ-LABEL: fmaximum_acq_rel_half_global_cta(
; SM70-NOFTZ: {
-; SM70-NOFTZ-NEXT: .reg .pred %p<7>;
-; SM70-NOFTZ-NEXT: .reg .b16 %rs<9>;
+; SM70-NOFTZ-NEXT: .reg .pred %p<6>;
+; SM70-NOFTZ-NEXT: .reg .b16 %rs<7>;
; SM70-NOFTZ-NEXT: .reg .b32 %r<15>;
; SM70-NOFTZ-NEXT: .reg .b64 %rd<3>;
; SM70-NOFTZ-EMPTY:
@@ -2646,29 +2628,26 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM70-NOFTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM70-NOFTZ-NEXT: not.b32 %r2, %r7;
; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r14, [%rd1];
-; SM70-NOFTZ-NEXT: setp.eq.b16 %p4, %rs1, 0;
; SM70-NOFTZ-NEXT: $L__BB77_1: // %atomicrmw.start
; SM70-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
; SM70-NOFTZ-NEXT: shr.u32 %r8, %r14, %r1;
; SM70-NOFTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM70-NOFTZ-NEXT: setp.gt.f16 %p1, %rs2, %rs1;
+; SM70-NOFTZ-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM70-NOFTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM70-NOFTZ-NEXT: setp.nan.f16 %p2, %rs2, %rs1;
-; SM70-NOFTZ-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; SM70-NOFTZ-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM70-NOFTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM70-NOFTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM70-NOFTZ-NEXT: mov.b16 %rs7, 0x0000;
-; SM70-NOFTZ-NEXT: setp.eq.f16 %p5, %rs4, %rs7;
-; SM70-NOFTZ-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5;
-; SM70-NOFTZ-NEXT: cvt.u32.u16 %r9, %rs8;
+; SM70-NOFTZ-NEXT: setp.gt.f16 %p2, %rs2, %rs1;
+; SM70-NOFTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM70-NOFTZ-NEXT: setp.nan.f16 %p3, %rs2, %rs1;
+; SM70-NOFTZ-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; SM70-NOFTZ-NEXT: setp.eq.f16 %p4, %rs2, %rs1;
+; SM70-NOFTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-NOFTZ-NEXT: cvt.u32.u16 %r9, %rs6;
; SM70-NOFTZ-NEXT: shl.b32 %r10, %r9, %r1;
; SM70-NOFTZ-NEXT: and.b32 %r11, %r14, %r2;
; SM70-NOFTZ-NEXT: or.b32 %r12, %r11, %r10;
; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12;
-; SM70-NOFTZ-NEXT: setp.ne.b32 %p6, %r3, %r14;
+; SM70-NOFTZ-NEXT: setp.ne.b32 %p5, %r3, %r14;
; SM70-NOFTZ-NEXT: mov.b32 %r14, %r3;
-; SM70-NOFTZ-NEXT: @%p6 bra $L__BB77_1;
+; SM70-NOFTZ-NEXT: @%p5 bra $L__BB77_1;
; SM70-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM70-NOFTZ-NEXT: shr.u32 %r13, %r3, %r1;
; SM70-NOFTZ-NEXT: fence.acq_rel.cta;
@@ -2677,8 +2656,8 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
;
; SM70-FTZ-LABEL: fmaximum_acq_rel_half_global_cta(
; SM70-FTZ: {
-; SM70-FTZ-NEXT: .reg .pred %p<7>;
-; SM70-FTZ-NEXT: .reg .b16 %rs<9>;
+; SM70-FTZ-NEXT: .reg .pred %p<6>;
+; SM70-FTZ-NEXT: .reg .b16 %rs<7>;
; SM70-FTZ-NEXT: .reg .b32 %r<15>;
; SM70-FTZ-NEXT: .reg .b64 %rd<3>;
; SM70-FTZ-EMPTY:
@@ -2694,29 +2673,26 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM70-FTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM70-FTZ-NEXT: not.b32 %r2, %r7;
; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r14, [%rd1];
-; SM70-FTZ-NEXT: setp.eq.b16 %p4, %rs1, 0;
; SM70-FTZ-NEXT: $L__BB77_1: // %atomicrmw.start
; SM70-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
; SM70-FTZ-NEXT: shr.u32 %r8, %r14, %r1;
; SM70-FTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM70-FTZ-NEXT: setp.gt.ftz.f16 %p1, %rs2, %rs1;
+; SM70-FTZ-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM70-FTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM70-FTZ-NEXT: setp.nan.ftz.f16 %p2, %rs2, %rs1;
-; SM70-FTZ-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; SM70-FTZ-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM70-FTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM70-FTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM70-FTZ-NEXT: mov.b16 %rs7, 0x0000;
-; SM70-FTZ-NEXT: setp.eq.ftz.f16 %p5, %rs4, %rs7;
-; SM70-FTZ-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5;
-; SM70-FTZ-NEXT: cvt.u32.u16 %r9, %rs8;
+; SM70-FTZ-NEXT: setp.gt.ftz.f16 %p2, %rs2, %rs1;
+; SM70-FTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM70-FTZ-NEXT: setp.nan.ftz.f16 %p3, %rs2, %rs1;
+; SM70-FTZ-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; SM70-FTZ-NEXT: setp.eq.ftz.f16 %p4, %rs2, %rs1;
+; SM70-FTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-FTZ-NEXT: cvt.u32.u16 %r9, %rs6;
; SM70-FTZ-NEXT: shl.b32 %r10, %r9, %r1;
; SM70-FTZ-NEXT: and.b32 %r11, %r14, %r2;
; SM70-FTZ-NEXT: or.b32 %r12, %r11, %r10;
; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12;
-; SM70-FTZ-NEXT: setp.ne.b32 %p6, %r3, %r14;
+; SM70-FTZ-NEXT: setp.ne.b32 %p5, %r3, %r14;
; SM70-FTZ-NEXT: mov.b32 %r14, %r3;
-; SM70-FTZ-NEXT: @%p6 bra $L__BB77_1;
+; SM70-FTZ-NEXT: @%p5 bra $L__BB77_1;
; SM70-FTZ-NEXT: // %bb.2: // %atomicrmw.end
; SM70-FTZ-NEXT: shr.u32 %r13, %r3, %r1;
; SM70-FTZ-NEXT: fence.acq_rel.cta;
@@ -3113,9 +3089,9 @@ define bfloat @fmax_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) {
; SM70-NOFTZ-LABEL: fminimum_acq_rel_bfloat_global_cta(
; SM70-NOFTZ: {
-; SM70-NOFTZ-NEXT: .reg .pred %p<7>;
-; SM70-NOFTZ-NEXT: .reg .b16 %rs<8>;
-; SM70-NOFTZ-NEXT: .reg .b32 %r<20>;
+; SM70-NOFTZ-NEXT: .reg .pred %p<6>;
+; SM70-NOFTZ-NEXT: .reg .b16 %rs<7>;
+; SM70-NOFTZ-NEXT: .reg .b32 %r<18>;
; SM70-NOFTZ-NEXT: .reg .b64 %rd<3>;
; SM70-NOFTZ-EMPTY:
; SM70-NOFTZ-NEXT: // %bb.0:
@@ -3129,45 +3105,41 @@ define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM70-NOFTZ-NEXT: mov.b32 %r6, 65535;
; SM70-NOFTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM70-NOFTZ-NEXT: not.b32 %r2, %r7;
-; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r19, [%rd1];
+; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r17, [%rd1];
; SM70-NOFTZ-NEXT: cvt.u32.u16 %r10, %rs1;
; SM70-NOFTZ-NEXT: shl.b32 %r11, %r10, 16;
-; SM70-NOFTZ-NEXT: setp.eq.b16 %p4, %rs1, -32768;
; SM70-NOFTZ-NEXT: $L__BB82_1: // %atomicrmw.start
; SM70-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-NOFTZ-NEXT: shr.u32 %r8, %r19, %r1;
+; SM70-NOFTZ-NEXT: shr.u32 %r8, %r17, %r1;
; SM70-NOFTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM70-NOFTZ-NEXT: shl.b32 %r9, %r8, 16;
-; SM70-NOFTZ-NEXT: setp.lt.f32 %p1, %r9, %r11;
+; SM70-NOFTZ-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; SM70-NOFTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM70-NOFTZ-NEXT: setp.nan.f32 %p2, %r9, %r11;
-; SM70-NOFTZ-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM70-NOFTZ-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; SM70-NOFTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM70-NOFTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM70-NOFTZ-NEXT: cvt.u32.u16 %r12, %rs4;
-; SM70-NOFTZ-NEXT: shl.b32 %r13, %r12, 16;
-; SM70-NOFTZ-NEXT: setp.eq.f32 %p5, %r13, 0f00000000;
-; SM70-NOFTZ-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM70-NOFTZ-NEXT: cvt.u32.u16 %r14, %rs7;
-; SM70-NOFTZ-NEXT: shl.b32 %r15, %r14, %r1;
-; SM70-NOFTZ-NEXT: and.b32 %r16, %r19, %r2;
-; SM70-NOFTZ-NEXT: or.b32 %r17, %r16, %r15;
-; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r19, %r17;
-; SM70-NOFTZ-NEXT: setp.ne.b32 %p6, %r3, %r19;
-; SM70-NOFTZ-NEXT: mov.b32 %r19, %r3;
-; SM70-NOFTZ-NEXT: @%p6 bra $L__BB82_1;
+; SM70-NOFTZ-NEXT: shl.b32 %r9, %r8, 16;
+; SM70-NOFTZ-NEXT: setp.lt.f32 %p2, %r9, %r11;
+; SM70-NOFTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM70-NOFTZ-NEXT: setp.nan.f32 %p3, %r9, %r11;
+; SM70-NOFTZ-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM70-NOFTZ-NEXT: setp.eq.f32 %p4, %r9, %r11;
+; SM70-NOFTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-NOFTZ-NEXT: cvt.u32.u16 %r12, %rs6;
+; SM70-NOFTZ-NEXT: shl.b32 %r13, %r12, %r1;
+; SM70-NOFTZ-NEXT: and.b32 %r14, %r17, %r2;
+; SM70-NOFTZ-NEXT: or.b32 %r15, %r14, %r13;
+; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r17, %r15;
+; SM70-NOFTZ-NEXT: setp.ne.b32 %p5, %r3, %r17;
+; SM70-NOFTZ-NEXT: mov.b32 %r17, %r3;
+; SM70-NOFTZ-NEXT: @%p5 bra $L__BB82_1;
; SM70-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
-; SM70-NOFTZ-NEXT: shr.u32 %r18, %r3, %r1;
+; SM70-NOFTZ-NEXT: shr.u32 %r16, %r3, %r1;
; SM70-NOFTZ-NEXT: fence.acq_rel.cta;
-; SM70-NOFTZ-NEXT: st.param.b16 [func_retval0], %r18;
+; SM70-NOFTZ-NEXT: st.param.b16 [func_retval0], %r16;
; SM70-NOFTZ-NEXT: ret;
;
; SM70-FTZ-LABEL: fminimum_acq_rel_bfloat_global_cta(
; SM70-FTZ: {
-; SM70-FTZ-NEXT: .reg .pred %p<7>;
-; SM70-FTZ-NEXT: .reg .b16 %rs<8>;
-; SM70-FTZ-NEXT: .reg .b32 %r<20>;
+; SM70-FTZ-NEXT: .reg .pred %p<6>;
+; SM70-FTZ-NEXT: .reg .b16 %rs<7>;
+; SM70-FTZ-NEXT: .reg .b32 %r<18>;
; SM70-FTZ-NEXT: .reg .b64 %rd<3>;
; SM70-FTZ-EMPTY:
; SM70-FTZ-NEXT: // %bb.0:
@@ -3181,38 +3153,34 @@ define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM70-FTZ-NEXT: mov.b32 %r6, 65535;
; SM70-FTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM70-FTZ-NEXT: not.b32 %r2, %r7;
-; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r19, [%rd1];
+; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r17, [%rd1];
; SM70-FTZ-NEXT: cvt.u32.u16 %r10, %rs1;
; SM70-FTZ-NEXT: shl.b32 %r11, %r10, 16;
-; SM70-FTZ-NEXT: setp.eq.b16 %p4, %rs1, -32768;
; SM70-FTZ-NEXT: $L__BB82_1: // %atomicrmw.start
; SM70-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-FTZ-NEXT: shr.u32 %r8, %r19, %r1;
+; SM70-FTZ-NEXT: shr.u32 %r8, %r17, %r1;
; SM70-FTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM70-FTZ-NEXT: shl.b32 %r9, %r8, 16;
-; SM70-FTZ-NEXT: setp.lt.ftz.f32 %p1, %r9, %r11;
+; SM70-FTZ-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; SM70-FTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM70-FTZ-NEXT: setp.nan.ftz.f32 %p2, %r9, %r11;
-; SM70-FTZ-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM70-FTZ-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; SM70-FTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM70-FTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM70-FTZ-NEXT: cvt.u32.u16 %r12, %rs4;
-; SM70-FTZ-NEXT: shl.b32 %r13, %r12, 16;
-; SM70-FTZ-NEXT: setp.eq.ftz.f32 %p5, %r13, 0f00000000;
-; SM70-FTZ-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM70-FTZ-NEXT: cvt.u32.u16 %r14, %rs7;
-; SM70-FTZ-NEXT: shl.b32 %r15, %r14, %r1;
-; SM70-FTZ-NEXT: and.b32 %r16, %r19, %r2;
-; SM70-FTZ-NEXT: or.b32 %r17, %r16, %r15;
-; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r19, %r17;
-; SM70-FTZ-NEXT: setp.ne.b32 %p6, %r3, %r19;
-; SM70-FTZ-NEXT: mov.b32 %r19, %r3;
-; SM70-FTZ-NEXT: @%p6 bra $L__BB82_1;
+; SM70-FTZ-NEXT: shl.b32 %r9, %r8, 16;
+; SM70-FTZ-NEXT: setp.lt.ftz.f32 %p2, %r9, %r11;
+; SM70-FTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM70-FTZ-NEXT: setp.nan.ftz.f32 %p3, %r9, %r11;
+; SM70-FTZ-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM70-FTZ-NEXT: setp.eq.ftz.f32 %p4, %r9, %r11;
+; SM70-FTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-FTZ-NEXT: cvt.u32.u16 %r12, %rs6;
+; SM70-FTZ-NEXT: shl.b32 %r13, %r12, %r1;
+; SM70-FTZ-NEXT: and.b32 %r14, %r17, %r2;
+; SM70-FTZ-NEXT: or.b32 %r15, %r14, %r13;
+; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r17, %r15;
+; SM70-FTZ-NEXT: setp.ne.b32 %p5, %r3, %r17;
+; SM70-FTZ-NEXT: mov.b32 %r17, %r3;
+; SM70-FTZ-NEXT: @%p5 bra $L__BB82_1;
; SM70-FTZ-NEXT: // %bb.2: // %atomicrmw.end
-; SM70-FTZ-NEXT: shr.u32 %r18, %r3, %r1;
+; SM70-FTZ-NEXT: shr.u32 %r16, %r3, %r1;
; SM70-FTZ-NEXT: fence.acq_rel.cta;
-; SM70-FTZ-NEXT: st.param.b16 [func_retval0], %r18;
+; SM70-FTZ-NEXT: st.param.b16 [func_retval0], %r16;
; SM70-FTZ-NEXT: ret;
%retval = atomicrmw fminimum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
@@ -3221,9 +3189,9 @@ define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) {
; SM70-NOFTZ-LABEL: fmaximum_acq_rel_bfloat_global_cta(
; SM70-NOFTZ: {
-; SM70-NOFTZ-NEXT: .reg .pred %p<7>;
-; SM70-NOFTZ-NEXT: .reg .b16 %rs<8>;
-; SM70-NOFTZ-NEXT: .reg .b32 %r<20>;
+; SM70-NOFTZ-NEXT: .reg .pred %p<6>;
+; SM70-NOFTZ-NEXT: .reg .b16 %rs<7>;
+; SM70-NOFTZ-NEXT: .reg .b32 %r<18>;
; SM70-NOFTZ-NEXT: .reg .b64 %rd<3>;
; SM70-NOFTZ-EMPTY:
; SM70-NOFTZ-NEXT: // %bb.0:
@@ -3237,45 +3205,41 @@ define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM70-NOFTZ-NEXT: mov.b32 %r6, 65535;
; SM70-NOFTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM70-NOFTZ-NEXT: not.b32 %r2, %r7;
-; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r19, [%rd1];
+; SM70-NOFTZ-NEXT: ld.relaxed.cta.global.b32 %r17, [%rd1];
; SM70-NOFTZ-NEXT: cvt.u32.u16 %r10, %rs1;
; SM70-NOFTZ-NEXT: shl.b32 %r11, %r10, 16;
-; SM70-NOFTZ-NEXT: setp.eq.b16 %p4, %rs1, 0;
; SM70-NOFTZ-NEXT: $L__BB83_1: // %atomicrmw.start
; SM70-NOFTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-NOFTZ-NEXT: shr.u32 %r8, %r19, %r1;
+; SM70-NOFTZ-NEXT: shr.u32 %r8, %r17, %r1;
; SM70-NOFTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM70-NOFTZ-NEXT: shl.b32 %r9, %r8, 16;
-; SM70-NOFTZ-NEXT: setp.gt.f32 %p1, %r9, %r11;
+; SM70-NOFTZ-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM70-NOFTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM70-NOFTZ-NEXT: setp.nan.f32 %p2, %r9, %r11;
-; SM70-NOFTZ-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM70-NOFTZ-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM70-NOFTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM70-NOFTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM70-NOFTZ-NEXT: cvt.u32.u16 %r12, %rs4;
-; SM70-NOFTZ-NEXT: shl.b32 %r13, %r12, 16;
-; SM70-NOFTZ-NEXT: setp.eq.f32 %p5, %r13, 0f00000000;
-; SM70-NOFTZ-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM70-NOFTZ-NEXT: cvt.u32.u16 %r14, %rs7;
-; SM70-NOFTZ-NEXT: shl.b32 %r15, %r14, %r1;
-; SM70-NOFTZ-NEXT: and.b32 %r16, %r19, %r2;
-; SM70-NOFTZ-NEXT: or.b32 %r17, %r16, %r15;
-; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r19, %r17;
-; SM70-NOFTZ-NEXT: setp.ne.b32 %p6, %r3, %r19;
-; SM70-NOFTZ-NEXT: mov.b32 %r19, %r3;
-; SM70-NOFTZ-NEXT: @%p6 bra $L__BB83_1;
+; SM70-NOFTZ-NEXT: shl.b32 %r9, %r8, 16;
+; SM70-NOFTZ-NEXT: setp.gt.f32 %p2, %r9, %r11;
+; SM70-NOFTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM70-NOFTZ-NEXT: setp.nan.f32 %p3, %r9, %r11;
+; SM70-NOFTZ-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM70-NOFTZ-NEXT: setp.eq.f32 %p4, %r9, %r11;
+; SM70-NOFTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-NOFTZ-NEXT: cvt.u32.u16 %r12, %rs6;
+; SM70-NOFTZ-NEXT: shl.b32 %r13, %r12, %r1;
+; SM70-NOFTZ-NEXT: and.b32 %r14, %r17, %r2;
+; SM70-NOFTZ-NEXT: or.b32 %r15, %r14, %r13;
+; SM70-NOFTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r17, %r15;
+; SM70-NOFTZ-NEXT: setp.ne.b32 %p5, %r3, %r17;
+; SM70-NOFTZ-NEXT: mov.b32 %r17, %r3;
+; SM70-NOFTZ-NEXT: @%p5 bra $L__BB83_1;
; SM70-NOFTZ-NEXT: // %bb.2: // %atomicrmw.end
-; SM70-NOFTZ-NEXT: shr.u32 %r18, %r3, %r1;
+; SM70-NOFTZ-NEXT: shr.u32 %r16, %r3, %r1;
; SM70-NOFTZ-NEXT: fence.acq_rel.cta;
-; SM70-NOFTZ-NEXT: st.param.b16 [func_retval0], %r18;
+; SM70-NOFTZ-NEXT: st.param.b16 [func_retval0], %r16;
; SM70-NOFTZ-NEXT: ret;
;
; SM70-FTZ-LABEL: fmaximum_acq_rel_bfloat_global_cta(
; SM70-FTZ: {
-; SM70-FTZ-NEXT: .reg .pred %p<7>;
-; SM70-FTZ-NEXT: .reg .b16 %rs<8>;
-; SM70-FTZ-NEXT: .reg .b32 %r<20>;
+; SM70-FTZ-NEXT: .reg .pred %p<6>;
+; SM70-FTZ-NEXT: .reg .b16 %rs<7>;
+; SM70-FTZ-NEXT: .reg .b32 %r<18>;
; SM70-FTZ-NEXT: .reg .b64 %rd<3>;
; SM70-FTZ-EMPTY:
; SM70-FTZ-NEXT: // %bb.0:
@@ -3289,38 +3253,34 @@ define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM70-FTZ-NEXT: mov.b32 %r6, 65535;
; SM70-FTZ-NEXT: shl.b32 %r7, %r6, %r1;
; SM70-FTZ-NEXT: not.b32 %r2, %r7;
-; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r19, [%rd1];
+; SM70-FTZ-NEXT: ld.relaxed.cta.global.b32 %r17, [%rd1];
; SM70-FTZ-NEXT: cvt.u32.u16 %r10, %rs1;
; SM70-FTZ-NEXT: shl.b32 %r11, %r10, 16;
-; SM70-FTZ-NEXT: setp.eq.b16 %p4, %rs1, 0;
; SM70-FTZ-NEXT: $L__BB83_1: // %atomicrmw.start
; SM70-FTZ-NEXT: // =>This Inner Loop Header: Depth=1
-; SM70-FTZ-NEXT: shr.u32 %r8, %r19, %r1;
+; SM70-FTZ-NEXT: shr.u32 %r8, %r17, %r1;
; SM70-FTZ-NEXT: cvt.u16.u32 %rs2, %r8;
-; SM70-FTZ-NEXT: shl.b32 %r9, %r8, 16;
-; SM70-FTZ-NEXT: setp.gt.ftz.f32 %p1, %r9, %r11;
+; SM70-FTZ-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM70-FTZ-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1;
-; SM70-FTZ-NEXT: setp.nan.ftz.f32 %p2, %r9, %r11;
-; SM70-FTZ-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM70-FTZ-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM70-FTZ-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3;
-; SM70-FTZ-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4;
-; SM70-FTZ-NEXT: cvt.u32.u16 %r12, %rs4;
-; SM70-FTZ-NEXT: shl.b32 %r13, %r12, 16;
-; SM70-FTZ-NEXT: setp.eq.ftz.f32 %p5, %r13, 0f00000000;
-; SM70-FTZ-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM70-FTZ-NEXT: cvt.u32.u16 %r14, %rs7;
-; SM70-FTZ-NEXT: shl.b32 %r15, %r14, %r1;
-; SM70-FTZ-NEXT: and.b32 %r16, %r19, %r2;
-; SM70-FTZ-NEXT: or.b32 %r17, %r16, %r15;
-; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r19, %r17;
-; SM70-FTZ-NEXT: setp.ne.b32 %p6, %r3, %r19;
-; SM70-FTZ-NEXT: mov.b32 %r19, %r3;
-; SM70-FTZ-NEXT: @%p6 bra $L__BB83_1;
+; SM70-FTZ-NEXT: shl.b32 %r9, %r8, 16;
+; SM70-FTZ-NEXT: setp.gt.ftz.f32 %p2, %r9, %r11;
+; SM70-FTZ-NEXT: selp.b16 %rs4, %rs2, %rs1, %p2;
+; SM70-FTZ-NEXT: setp.nan.ftz.f32 %p3, %r9, %r11;
+; SM70-FTZ-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM70-FTZ-NEXT: setp.eq.ftz.f32 %p4, %r9, %r11;
+; SM70-FTZ-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-FTZ-NEXT: cvt.u32.u16 %r12, %rs6;
+; SM70-FTZ-NEXT: shl.b32 %r13, %r12, %r1;
+; SM70-FTZ-NEXT: and.b32 %r14, %r17, %r2;
+; SM70-FTZ-NEXT: or.b32 %r15, %r14, %r13;
+; SM70-FTZ-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r17, %r15;
+; SM70-FTZ-NEXT: setp.ne.b32 %p5, %r3, %r17;
+; SM70-FTZ-NEXT: mov.b32 %r17, %r3;
+; SM70-FTZ-NEXT: @%p5 bra $L__BB83_1;
; SM70-FTZ-NEXT: // %bb.2: // %atomicrmw.end
-; SM70-FTZ-NEXT: shr.u32 %r18, %r3, %r1;
+; SM70-FTZ-NEXT: shr.u32 %r16, %r3, %r1;
; SM70-FTZ-NEXT: fence.acq_rel.cta;
-; SM70-FTZ-NEXT: st.param.b16 [func_retval0], %r18;
+; SM70-FTZ-NEXT: st.param.b16 [func_retval0], %r16;
; SM70-FTZ-NEXT: ret;
%retval = atomicrmw fmaximum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
index 46819ca53638c..7bc834674ecc7 100644
--- a/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+++ b/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
@@ -2123,29 +2123,27 @@ define double @fmax_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) {
; SM90-LABEL: fminimum_acq_rel_double_global_cta(
; SM90: {
-; SM90-NEXT: .reg .pred %p<6>;
-; SM90-NEXT: .reg .b64 %rd<10>;
+; SM90-NEXT: .reg .pred %p<5>;
+; SM90-NEXT: .reg .b64 %rd<9>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
; SM90-NEXT: ld.param.b64 %rd3, [fminimum_acq_rel_double_global_cta_param_1];
; SM90-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_double_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.relaxed.cta.global.b64 %rd9, [%rd2];
-; SM90-NEXT: setp.eq.b64 %p3, %rd3, -9223372036854775808;
+; SM90-NEXT: ld.relaxed.cta.global.b64 %rd8, [%rd2];
; SM90-NEXT: $L__BB70_1: // %atomicrmw.start
; SM90-NEXT: // =>This Inner Loop Header: Depth=1
-; SM90-NEXT: setp.nan.f64 %p1, %rd9, %rd3;
-; SM90-NEXT: min.f64 %rd4, %rd9, %rd3;
-; SM90-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1;
-; SM90-NEXT: setp.eq.b64 %p2, %rd9, -9223372036854775808;
-; SM90-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2;
-; SM90-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3;
-; SM90-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000;
-; SM90-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4;
-; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8;
-; SM90-NEXT: setp.ne.b64 %p5, %rd1, %rd9;
-; SM90-NEXT: mov.b64 %rd9, %rd1;
-; SM90-NEXT: @%p5 bra $L__BB70_1;
+; SM90-NEXT: setp.eq.b64 %p1, %rd8, -9223372036854775808;
+; SM90-NEXT: selp.f64 %rd4, %rd8, %rd3, %p1;
+; SM90-NEXT: setp.nan.f64 %p2, %rd8, %rd3;
+; SM90-NEXT: min.f64 %rd5, %rd8, %rd3;
+; SM90-NEXT: selp.f64 %rd6, 0d7FF8000000000000, %rd5, %p2;
+; SM90-NEXT: setp.eq.f64 %p3, %rd8, %rd3;
+; SM90-NEXT: selp.f64 %rd7, %rd4, %rd6, %p3;
+; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd8, %rd7;
+; SM90-NEXT: setp.ne.b64 %p4, %rd1, %rd8;
+; SM90-NEXT: mov.b64 %rd8, %rd1;
+; SM90-NEXT: @%p4 bra $L__BB70_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
@@ -2157,29 +2155,27 @@ define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double
define double @fmaximum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) {
; SM90-LABEL: fmaximum_acq_rel_double_global_cta(
; SM90: {
-; SM90-NEXT: .reg .pred %p<6>;
-; SM90-NEXT: .reg .b64 %rd<10>;
+; SM90-NEXT: .reg .pred %p<5>;
+; SM90-NEXT: .reg .b64 %rd<9>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
; SM90-NEXT: ld.param.b64 %rd3, [fmaximum_acq_rel_double_global_cta_param_1];
; SM90-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_double_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.relaxed.cta.global.b64 %rd9, [%rd2];
-; SM90-NEXT: setp.eq.b64 %p3, %rd3, 0;
+; SM90-NEXT: ld.relaxed.cta.global.b64 %rd8, [%rd2];
; SM90-NEXT: $L__BB71_1: // %atomicrmw.start
; SM90-NEXT: // =>This Inner Loop Header: Depth=1
-; SM90-NEXT: setp.nan.f64 %p1, %rd9, %rd3;
-; SM90-NEXT: max.f64 %rd4, %rd9, %rd3;
-; SM90-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1;
-; SM90-NEXT: setp.eq.b64 %p2, %rd9, 0;
-; SM90-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2;
-; SM90-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3;
-; SM90-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000;
-; SM90-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4;
-; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8;
-; SM90-NEXT: setp.ne.b64 %p5, %rd1, %rd9;
-; SM90-NEXT: mov.b64 %rd9, %rd1;
-; SM90-NEXT: @%p5 bra $L__BB71_1;
+; SM90-NEXT: setp.eq.b64 %p1, %rd8, 0;
+; SM90-NEXT: selp.f64 %rd4, %rd8, %rd3, %p1;
+; SM90-NEXT: setp.nan.f64 %p2, %rd8, %rd3;
+; SM90-NEXT: max.f64 %rd5, %rd8, %rd3;
+; SM90-NEXT: selp.f64 %rd6, 0d7FF8000000000000, %rd5, %p2;
+; SM90-NEXT: setp.eq.f64 %p3, %rd8, %rd3;
+; SM90-NEXT: selp.f64 %rd7, %rd4, %rd6, %p3;
+; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd8, %rd7;
+; SM90-NEXT: setp.ne.b64 %p4, %rd1, %rd8;
+; SM90-NEXT: mov.b64 %rd8, %rd1;
+; SM90-NEXT: @%p4 bra $L__BB71_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
diff --git a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
index 41f77b5337e6d..8548ed7ac5a45 100644
--- a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
@@ -1558,30 +1558,26 @@ define bfloat @test_roundeven(bfloat %a) {
define bfloat @test_maximum(bfloat %a, bfloat %b) {
; SM70-LABEL: test_maximum(
; SM70: {
-; SM70-NEXT: .reg .pred %p<6>;
-; SM70-NEXT: .reg .b16 %rs<8>;
-; SM70-NEXT: .reg .b32 %r<7>;
+; SM70-NEXT: .reg .pred %p<5>;
+; SM70-NEXT: .reg .b16 %rs<7>;
+; SM70-NEXT: .reg .b32 %r<5>;
; SM70-EMPTY:
; SM70-NEXT: // %bb.0:
; SM70-NEXT: ld.param.b16 %rs1, [test_maximum_param_0];
+; SM70-NEXT: setp.eq.b16 %p1, %rs1, 0;
; SM70-NEXT: ld.param.b16 %rs2, [test_maximum_param_1];
+; SM70-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
; SM70-NEXT: cvt.u32.u16 %r1, %rs2;
; SM70-NEXT: shl.b32 %r2, %r1, 16;
; SM70-NEXT: cvt.u32.u16 %r3, %rs1;
; SM70-NEXT: shl.b32 %r4, %r3, 16;
-; SM70-NEXT: setp.gt.f32 %p1, %r4, %r2;
-; SM70-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
-; SM70-NEXT: setp.nan.f32 %p2, %r4, %r2;
-; SM70-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2;
-; SM70-NEXT: setp.eq.b16 %p3, %rs1, 0;
-; SM70-NEXT: selp.b16 %rs5, %rs1, %rs4, %p3;
-; SM70-NEXT: setp.eq.b16 %p4, %rs2, 0;
-; SM70-NEXT: selp.b16 %rs6, %rs2, %rs5, %p4;
-; SM70-NEXT: cvt.u32.u16 %r5, %rs4;
-; SM70-NEXT: shl.b32 %r6, %r5, 16;
-; SM70-NEXT: setp.eq.f32 %p5, %r6, 0f00000000;
-; SM70-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; SM70-NEXT: st.param.b16 [func_retval0], %rs7;
+; SM70-NEXT: setp.gt.f32 %p2, %r4, %r2;
+; SM70-NEXT: selp.b16 %rs4, %rs1, %rs2, %p2;
+; SM70-NEXT: setp.nan.f32 %p3, %r4, %r2;
+; SM70-NEXT: selp.b16 %rs5, 0x7FC0, %rs4, %p3;
+; SM70-NEXT: setp.eq.f32 %p4, %r4, %r2;
+; SM70-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; SM70-NEXT: st.param.b16 [func_retval0], %rs6;
; SM70-NEXT: ret;
;
; SM80-LABEL: test_maximum(
@@ -1703,46 +1699,38 @@ define bfloat @test_maxnum(bfloat %a, bfloat %b) {
define <2 x bfloat> @test_maximum_v2(<2 x bfloat> %a, <2 x bfloat> %b) {
; SM70-LABEL: test_maximum_v2(
; SM70: {
-; SM70-NEXT: .reg .pred %p<11>;
-; SM70-NEXT: .reg .b16 %rs<15>;
-; SM70-NEXT: .reg .b32 %r<13>;
+; SM70-NEXT: .reg .pred %p<9>;
+; SM70-NEXT: .reg .b16 %rs<13>;
+; SM70-NEXT: .reg .b32 %r<9>;
; SM70-EMPTY:
; SM70-NEXT: // %bb.0:
; SM70-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_maximum_v2_param_0];
+; SM70-NEXT: setp.eq.b16 %p1, %rs2, 0;
; SM70-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_maximum_v2_param_1];
+; SM70-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
; SM70-NEXT: cvt.u32.u16 %r1, %rs4;
; SM70-NEXT: shl.b32 %r2, %r1, 16;
; SM70-NEXT: cvt.u32.u16 %r3, %rs2;
; SM70-NEXT: shl.b32 %r4, %r3, 16;
-; SM70-NEXT: setp.gt.f32 %p1, %r4, %r2;
-; SM70-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
-; SM70-NEXT: setp.nan.f32 %p2, %r4, %r2;
-; SM70-NEXT: selp.b16 %rs6, 0x7FC0, %rs5, %p2;
-; SM70-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; SM70-NEXT: selp.b16 %rs7, %rs2, %rs6, %p3;
-; SM70-NEXT: setp.eq.b16 %p4, %rs4, 0;
-; SM70-NEXT: selp.b16 %rs8, %rs4, %rs7, %p4;
-; SM70-NEXT: cvt.u32.u16 %r5, %rs6;
+; SM70-NEXT: setp.gt.f32 %p2, %r4, %r2;
+; SM70-NEXT: selp.b16 %rs6, %rs2, %rs4, %p2;
+; SM70-NEXT: setp.nan.f32 %p3, %r4, %r2;
+; SM70-NEXT: selp.b16 %rs7, 0x7FC0, %rs6, %p3;
+; SM70-NEXT: setp.eq.f32 %p4, %r4, %r2;
+; SM70-NEXT: selp.b16 %rs8, %rs5, %rs7, %p4;
+; SM70-NEXT: setp.eq.b16 %p5, %rs1, 0;
+; SM70-NEXT: selp.b16 %rs9, %rs1, %rs3, %p5;
+; SM70-NEXT: cvt.u32.u16 %r5, %rs3;
; SM70-NEXT: shl.b32 %r6, %r5, 16;
-; SM70-NEXT: setp.eq.f32 %p5, %r6, 0f00000000;
-; SM70-NEXT: selp.b16 %rs9, %rs8, %rs6, %p5;
-; SM70-NEXT: cvt.u32.u16 %r7, %rs3;
+; SM70-NEXT: cvt.u32.u16 %r7, %rs1;
; SM70-NEXT: shl.b32 %r8, %r7, 16;
-; SM70-NEXT: cvt.u32.u16 %r9, %rs1;
-; SM70-NEXT: shl.b32 %r10, %r9, 16;
-; SM70-NEXT: setp.gt.f32 %p6, %r10, %r8;
+; SM70-NEXT: setp.gt.f32 %p6, %r8, %r6;
; SM70-NEXT: selp.b16 %rs10, %rs1, %rs3, %p6;
-; SM70-NEXT: setp.nan.f32 %p7, %r10, %r8;
+; SM70-NEXT: setp.nan.f32 %p7, %r8, %r6;
; SM70-NEXT: selp.b16 %rs11, 0x7FC0, %rs10, %p7;
-; SM70-NEXT: setp.eq.b16 %p8, %rs1, 0;
-; SM70-NEXT: selp.b16 %rs12, %rs1, %rs11, %p8;
-; SM70-NEXT: setp.eq.b16 %p9, %rs3, 0;
-; SM70-NEXT: selp.b16 %rs13, %rs3, %rs12, %p9;
-; SM70-NEXT: cvt.u32.u16 %r11, %rs11;
-; SM70-NEXT: shl.b32 %r12, %r11, 16;
-; SM70-NEXT: setp.eq.f32 %p10, %r12, 0f00000000;
-; SM70-NEXT: selp.b16 %rs14, %rs13, %rs11, %p10;
-; SM70-NEXT: st.param.v2.b16 [func_retval0], {%rs14, %rs9};
+; SM70-NEXT: setp.eq.f32 %p8, %r8, %r6;
+; SM70-NEXT: selp.b16 %rs12, %rs9, %rs11, %p8;
+; SM70-NEXT: st.param.v2.b16 [func_retval0], {%rs12, %rs8};
; SM70-NEXT: ret;
;
; SM80-LABEL: test_maximum_v2(
diff --git a/llvm/test/CodeGen/NVPTX/math-intrins.ll b/llvm/test/CodeGen/NVPTX/math-intrins.ll
index 3bae69d76ef82..e7943dc780f6e 100644
--- a/llvm/test/CodeGen/NVPTX/math-intrins.ll
+++ b/llvm/test/CodeGen/NVPTX/math-intrins.ll
@@ -767,27 +767,24 @@ define <2 x half> @minnum_v2half(<2 x half> %a, <2 x half> %b) {
define half @minimum_half(half %a, half %b) {
; CHECK-NOF16-LABEL: minimum_half(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<6>;
-; CHECK-NOF16-NEXT: .reg .b16 %rs<8>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<4>;
+; CHECK-NOF16-NEXT: .reg .pred %p<5>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.b16 %rs1, [minimum_half_param_0];
+; CHECK-NOF16-NEXT: setp.eq.b16 %p1, %rs1, -32768;
; CHECK-NOF16-NEXT: ld.param.b16 %rs2, [minimum_half_param_1];
+; CHECK-NOF16-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs2;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs1;
-; CHECK-NOF16-NEXT: setp.lt.f32 %p1, %r2, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
-; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %r2, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p3, %rs1, -32768;
-; CHECK-NOF16-NEXT: selp.b16 %rs5, %rs1, %rs4, %p3;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p4, %rs2, -32768;
-; CHECK-NOF16-NEXT: selp.b16 %rs6, %rs2, %rs5, %p4;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs4;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p5, %r3, 0f00000000;
-; CHECK-NOF16-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; CHECK-NOF16-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-NOF16-NEXT: setp.lt.f32 %p2, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs4, %rs1, %rs2, %p2;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p3, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p4, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; CHECK-NOF16-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: minimum_half(
@@ -803,27 +800,24 @@ define half @minimum_half(half %a, half %b) {
;
; CHECK-SM80-NOF16-LABEL: minimum_half(
; CHECK-SM80-NOF16: {
-; CHECK-SM80-NOF16-NEXT: .reg .pred %p<6>;
-; CHECK-SM80-NOF16-NEXT: .reg .b16 %rs<8>;
-; CHECK-SM80-NOF16-NEXT: .reg .b32 %r<4>;
+; CHECK-SM80-NOF16-NEXT: .reg .pred %p<5>;
+; CHECK-SM80-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-SM80-NOF16-NEXT: .reg .b32 %r<3>;
; CHECK-SM80-NOF16-EMPTY:
; CHECK-SM80-NOF16-NEXT: // %bb.0:
; CHECK-SM80-NOF16-NEXT: ld.param.b16 %rs1, [minimum_half_param_0];
+; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p1, %rs1, -32768;
; CHECK-SM80-NOF16-NEXT: ld.param.b16 %rs2, [minimum_half_param_1];
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r1, %rs2;
; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r2, %rs1;
-; CHECK-SM80-NOF16-NEXT: setp.lt.f32 %p1, %r2, %r1;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
-; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p2, %r2, %r1;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p3, %rs1, -32768;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs5, %rs1, %rs4, %p3;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p4, %rs2, -32768;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs6, %rs2, %rs5, %p4;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r3, %rs4;
-; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p5, %r3, 0f00000000;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; CHECK-SM80-NOF16-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-SM80-NOF16-NEXT: setp.lt.f32 %p2, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs4, %rs1, %rs2, %p2;
+; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p3, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p4, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; CHECK-SM80-NOF16-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-SM80-NOF16-NEXT: ret;
%x = call half @llvm.minimum.f16(half %a, half %b)
ret half %x
@@ -832,22 +826,20 @@ define half @minimum_half(half %a, half %b) {
define float @minimum_float(float %a, float %b) {
; CHECK-NOF16-LABEL: minimum_float(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<8>;
+; CHECK-NOF16-NEXT: .reg .pred %p<4>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.b32 %r1, [minimum_float_param_0];
+; CHECK-NOF16-NEXT: setp.eq.b32 %p1, %r1, -2147483648;
; CHECK-NOF16-NEXT: ld.param.b32 %r2, [minimum_float_param_1];
-; CHECK-NOF16-NEXT: setp.nan.f32 %p1, %r1, %r2;
-; CHECK-NOF16-NEXT: min.f32 %r3, %r1, %r2;
-; CHECK-NOF16-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; CHECK-NOF16-NEXT: setp.eq.b32 %p2, %r1, -2147483648;
-; CHECK-NOF16-NEXT: selp.f32 %r5, %r1, %r4, %p2;
-; CHECK-NOF16-NEXT: setp.eq.b32 %p3, %r2, -2147483648;
-; CHECK-NOF16-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p4, %r4, 0f00000000;
-; CHECK-NOF16-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NOF16-NEXT: selp.f32 %r3, %r1, %r2, %p1;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %r1, %r2;
+; CHECK-NOF16-NEXT: min.f32 %r4, %r1, %r2;
+; CHECK-NOF16-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p3, %r1, %r2;
+; CHECK-NOF16-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: minimum_float(
@@ -887,8 +879,8 @@ define float @minimum_imm1(float %a) {
; CHECK-NOF16-NEXT: min.f32 %r2, %r1, 0f00000000;
; CHECK-NOF16-NEXT: selp.f32 %r3, 0f7FC00000, %r2, %p1;
; CHECK-NOF16-NEXT: setp.eq.b32 %p2, %r1, -2147483648;
-; CHECK-NOF16-NEXT: selp.f32 %r4, %r1, %r3, %p2;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p3, %r3, 0f00000000;
+; CHECK-NOF16-NEXT: selp.f32 %r4, %r1, 0f00000000, %p2;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p3, %r1, 0f00000000;
; CHECK-NOF16-NEXT: selp.f32 %r5, %r4, %r3, %p3;
; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NOF16-NEXT: ret;
@@ -928,8 +920,8 @@ define float @minimum_imm2(float %a) {
; CHECK-NOF16-NEXT: min.f32 %r2, %r1, 0f00000000;
; CHECK-NOF16-NEXT: selp.f32 %r3, 0f7FC00000, %r2, %p1;
; CHECK-NOF16-NEXT: setp.eq.b32 %p2, %r1, -2147483648;
-; CHECK-NOF16-NEXT: selp.f32 %r4, %r1, %r3, %p2;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p3, %r3, 0f00000000;
+; CHECK-NOF16-NEXT: selp.f32 %r4, %r1, 0f00000000, %p2;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p3, %r1, 0f00000000;
; CHECK-NOF16-NEXT: selp.f32 %r5, %r4, %r3, %p3;
; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NOF16-NEXT: ret;
@@ -960,22 +952,20 @@ define float @minimum_imm2(float %a) {
define float @minimum_float_ftz(float %a, float %b) #1 {
; CHECK-NOF16-LABEL: minimum_float_ftz(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<8>;
+; CHECK-NOF16-NEXT: .reg .pred %p<4>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.b32 %r1, [minimum_float_ftz_param_0];
+; CHECK-NOF16-NEXT: setp.eq.b32 %p1, %r1, -2147483648;
; CHECK-NOF16-NEXT: ld.param.b32 %r2, [minimum_float_ftz_param_1];
-; CHECK-NOF16-NEXT: setp.nan.ftz.f32 %p1, %r1, %r2;
-; CHECK-NOF16-NEXT: min.ftz.f32 %r3, %r1, %r2;
-; CHECK-NOF16-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; CHECK-NOF16-NEXT: setp.eq.b32 %p2, %r1, -2147483648;
-; CHECK-NOF16-NEXT: selp.f32 %r5, %r1, %r4, %p2;
-; CHECK-NOF16-NEXT: setp.eq.b32 %p3, %r2, -2147483648;
-; CHECK-NOF16-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; CHECK-NOF16-NEXT: setp.eq.ftz.f32 %p4, %r4, 0f00000000;
-; CHECK-NOF16-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NOF16-NEXT: selp.f32 %r3, %r1, %r2, %p1;
+; CHECK-NOF16-NEXT: setp.nan.ftz.f32 %p2, %r1, %r2;
+; CHECK-NOF16-NEXT: min.ftz.f32 %r4, %r1, %r2;
+; CHECK-NOF16-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; CHECK-NOF16-NEXT: setp.eq.ftz.f32 %p3, %r1, %r2;
+; CHECK-NOF16-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: minimum_float_ftz(
@@ -1006,22 +996,20 @@ define float @minimum_float_ftz(float %a, float %b) #1 {
define double @minimum_double(double %a, double %b) {
; CHECK-LABEL: minimum_double(
; CHECK: {
-; CHECK-NEXT: .reg .pred %p<5>;
-; CHECK-NEXT: .reg .b64 %rd<8>;
+; CHECK-NEXT: .reg .pred %p<4>;
+; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [minimum_double_param_0];
+; CHECK-NEXT: setp.eq.b64 %p1, %rd1, -9223372036854775808;
; CHECK-NEXT: ld.param.b64 %rd2, [minimum_double_param_1];
-; CHECK-NEXT: setp.nan.f64 %p1, %rd1, %rd2;
-; CHECK-NEXT: min.f64 %rd3, %rd1, %rd2;
-; CHECK-NEXT: selp.f64 %rd4, 0d7FF8000000000000, %rd3, %p1;
-; CHECK-NEXT: setp.eq.b64 %p2, %rd1, -9223372036854775808;
-; CHECK-NEXT: selp.f64 %rd5, %rd1, %rd4, %p2;
-; CHECK-NEXT: setp.eq.b64 %p3, %rd2, -9223372036854775808;
-; CHECK-NEXT: selp.f64 %rd6, %rd2, %rd5, %p3;
-; CHECK-NEXT: setp.eq.f64 %p4, %rd4, 0d0000000000000000;
-; CHECK-NEXT: selp.f64 %rd7, %rd6, %rd4, %p4;
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd7;
+; CHECK-NEXT: selp.f64 %rd3, %rd1, %rd2, %p1;
+; CHECK-NEXT: setp.nan.f64 %p2, %rd1, %rd2;
+; CHECK-NEXT: min.f64 %rd4, %rd1, %rd2;
+; CHECK-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p2;
+; CHECK-NEXT: setp.eq.f64 %p3, %rd1, %rd2;
+; CHECK-NEXT: selp.f64 %rd6, %rd3, %rd5, %p3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd6;
; CHECK-NEXT: ret;
%x = call double @llvm.minimum.f64(double %a, double %b)
ret double %x
@@ -1030,40 +1018,34 @@ define double @minimum_double(double %a, double %b) {
define <2 x half> @minimum_v2half(<2 x half> %a, <2 x half> %b) {
; CHECK-NOF16-LABEL: minimum_v2half(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<11>;
-; CHECK-NOF16-NEXT: .reg .b16 %rs<15>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .pred %p<9>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<13>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [minimum_v2half_param_0];
+; CHECK-NOF16-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [minimum_v2half_param_1];
+; CHECK-NOF16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NOF16-NEXT: setp.lt.f32 %p1, %r2, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
-; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %r2, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs6, 0x7E00, %rs5, %p2;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; CHECK-NOF16-NEXT: selp.b16 %rs7, %rs2, %rs6, %p3;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p4, %rs4, -32768;
-; CHECK-NOF16-NEXT: selp.b16 %rs8, %rs4, %rs7, %p4;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs6;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p5, %r3, 0f00000000;
-; CHECK-NOF16-NEXT: selp.b16 %rs9, %rs8, %rs6, %p5;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: setp.lt.f32 %p6, %r5, %r4;
+; CHECK-NOF16-NEXT: setp.lt.f32 %p2, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs6, %rs2, %rs4, %p2;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p3, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs7, 0x7E00, %rs6, %p3;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p4, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs8, %rs5, %rs7, %p4;
+; CHECK-NOF16-NEXT: setp.eq.b16 %p5, %rs1, -32768;
+; CHECK-NOF16-NEXT: selp.b16 %rs9, %rs1, %rs3, %p5;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.lt.f32 %p6, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs10, %rs1, %rs3, %p6;
-; CHECK-NOF16-NEXT: setp.nan.f32 %p7, %r5, %r4;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p7, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs11, 0x7E00, %rs10, %p7;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p8, %rs1, -32768;
-; CHECK-NOF16-NEXT: selp.b16 %rs12, %rs1, %rs11, %p8;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p9, %rs3, -32768;
-; CHECK-NOF16-NEXT: selp.b16 %rs13, %rs3, %rs12, %p9;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs11;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p10, %r6, 0f00000000;
-; CHECK-NOF16-NEXT: selp.b16 %rs14, %rs13, %rs11, %p10;
-; CHECK-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs14, %rs9};
+; CHECK-NOF16-NEXT: setp.eq.f32 %p8, %r4, %r3;
+; CHECK-NOF16-NEXT: selp.b16 %rs12, %rs9, %rs11, %p8;
+; CHECK-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs12, %rs8};
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: minimum_v2half(
@@ -1079,40 +1061,34 @@ define <2 x half> @minimum_v2half(<2 x half> %a, <2 x half> %b) {
;
; CHECK-SM80-NOF16-LABEL: minimum_v2half(
; CHECK-SM80-NOF16: {
-; CHECK-SM80-NOF16-NEXT: .reg .pred %p<11>;
-; CHECK-SM80-NOF16-NEXT: .reg .b16 %rs<15>;
-; CHECK-SM80-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-SM80-NOF16-NEXT: .reg .pred %p<9>;
+; CHECK-SM80-NOF16-NEXT: .reg .b16 %rs<13>;
+; CHECK-SM80-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-SM80-NOF16-EMPTY:
; CHECK-SM80-NOF16-NEXT: // %bb.0:
; CHECK-SM80-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [minimum_v2half_param_0];
+; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p1, %rs2, -32768;
; CHECK-SM80-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [minimum_v2half_param_1];
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-SM80-NOF16-NEXT: setp.lt.f32 %p1, %r2, %r1;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
-; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p2, %r2, %r1;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs6, 0x7E00, %rs5, %p2;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p3, %rs2, -32768;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs7, %rs2, %rs6, %p3;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p4, %rs4, -32768;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs8, %rs4, %rs7, %p4;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r3, %rs6;
-; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p5, %r3, 0f00000000;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs9, %rs8, %rs6, %p5;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r4, %rs3;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-SM80-NOF16-NEXT: setp.lt.f32 %p6, %r5, %r4;
+; CHECK-SM80-NOF16-NEXT: setp.lt.f32 %p2, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs6, %rs2, %rs4, %p2;
+; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p3, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs7, 0x7E00, %rs6, %p3;
+; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p4, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs8, %rs5, %rs7, %p4;
+; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p5, %rs1, -32768;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs9, %rs1, %rs3, %p5;
+; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-SM80-NOF16-NEXT: setp.lt.f32 %p6, %r4, %r3;
; CHECK-SM80-NOF16-NEXT: selp.b16 %rs10, %rs1, %rs3, %p6;
-; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p7, %r5, %r4;
+; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p7, %r4, %r3;
; CHECK-SM80-NOF16-NEXT: selp.b16 %rs11, 0x7E00, %rs10, %p7;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p8, %rs1, -32768;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs12, %rs1, %rs11, %p8;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p9, %rs3, -32768;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs13, %rs3, %rs12, %p9;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r6, %rs11;
-; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p10, %r6, 0f00000000;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs14, %rs13, %rs11, %p10;
-; CHECK-SM80-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs14, %rs9};
+; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p8, %r4, %r3;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs12, %rs9, %rs11, %p8;
+; CHECK-SM80-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs12, %rs8};
; CHECK-SM80-NOF16-NEXT: ret;
%x = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)
ret <2 x half> %x
@@ -1298,27 +1274,24 @@ define <2 x half> @maxnum_v2half(<2 x half> %a, <2 x half> %b) {
define half @maximum_half(half %a, half %b) {
; CHECK-NOF16-LABEL: maximum_half(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<6>;
-; CHECK-NOF16-NEXT: .reg .b16 %rs<8>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<4>;
+; CHECK-NOF16-NEXT: .reg .pred %p<5>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.b16 %rs1, [maximum_half_param_0];
+; CHECK-NOF16-NEXT: setp.eq.b16 %p1, %rs1, 0;
; CHECK-NOF16-NEXT: ld.param.b16 %rs2, [maximum_half_param_1];
+; CHECK-NOF16-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs2;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs1;
-; CHECK-NOF16-NEXT: setp.gt.f32 %p1, %r2, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
-; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %r2, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p3, %rs1, 0;
-; CHECK-NOF16-NEXT: selp.b16 %rs5, %rs1, %rs4, %p3;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p4, %rs2, 0;
-; CHECK-NOF16-NEXT: selp.b16 %rs6, %rs2, %rs5, %p4;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs4;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p5, %r3, 0f00000000;
-; CHECK-NOF16-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; CHECK-NOF16-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-NOF16-NEXT: setp.gt.f32 %p2, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs4, %rs1, %rs2, %p2;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p3, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p4, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; CHECK-NOF16-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: maximum_half(
@@ -1334,27 +1307,24 @@ define half @maximum_half(half %a, half %b) {
;
; CHECK-SM80-NOF16-LABEL: maximum_half(
; CHECK-SM80-NOF16: {
-; CHECK-SM80-NOF16-NEXT: .reg .pred %p<6>;
-; CHECK-SM80-NOF16-NEXT: .reg .b16 %rs<8>;
-; CHECK-SM80-NOF16-NEXT: .reg .b32 %r<4>;
+; CHECK-SM80-NOF16-NEXT: .reg .pred %p<5>;
+; CHECK-SM80-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-SM80-NOF16-NEXT: .reg .b32 %r<3>;
; CHECK-SM80-NOF16-EMPTY:
; CHECK-SM80-NOF16-NEXT: // %bb.0:
; CHECK-SM80-NOF16-NEXT: ld.param.b16 %rs1, [maximum_half_param_0];
+; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p1, %rs1, 0;
; CHECK-SM80-NOF16-NEXT: ld.param.b16 %rs2, [maximum_half_param_1];
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r1, %rs2;
; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r2, %rs1;
-; CHECK-SM80-NOF16-NEXT: setp.gt.f32 %p1, %r2, %r1;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
-; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p2, %r2, %r1;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p3, %rs1, 0;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs5, %rs1, %rs4, %p3;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p4, %rs2, 0;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs6, %rs2, %rs5, %p4;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r3, %rs4;
-; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p5, %r3, 0f00000000;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5;
-; CHECK-SM80-NOF16-NEXT: st.param.b16 [func_retval0], %rs7;
+; CHECK-SM80-NOF16-NEXT: setp.gt.f32 %p2, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs4, %rs1, %rs2, %p2;
+; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p3, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs5, 0x7E00, %rs4, %p3;
+; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p4, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs6, %rs3, %rs5, %p4;
+; CHECK-SM80-NOF16-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-SM80-NOF16-NEXT: ret;
%x = call half @llvm.maximum.f16(half %a, half %b)
ret half %x
@@ -1363,17 +1333,19 @@ define half @maximum_half(half %a, half %b) {
define float @maximum_imm1(float %a) {
; CHECK-NOF16-LABEL: maximum_imm1(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<3>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
+; CHECK-NOF16-NEXT: .reg .pred %p<4>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<6>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.b32 %r1, [maximum_imm1_param_0];
; CHECK-NOF16-NEXT: setp.nan.f32 %p1, %r1, %r1;
; CHECK-NOF16-NEXT: max.f32 %r2, %r1, 0f00000000;
; CHECK-NOF16-NEXT: selp.f32 %r3, 0f7FC00000, %r2, %p1;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p2, %r3, 0f00000000;
-; CHECK-NOF16-NEXT: selp.f32 %r4, 0f00000000, %r3, %p2;
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NOF16-NEXT: setp.eq.b32 %p2, %r1, 0;
+; CHECK-NOF16-NEXT: selp.f32 %r4, %r1, 0f00000000, %p2;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p3, %r1, 0f00000000;
+; CHECK-NOF16-NEXT: selp.f32 %r5, %r4, %r3, %p3;
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: maximum_imm1(
@@ -1402,17 +1374,19 @@ define float @maximum_imm1(float %a) {
define float @maximum_imm2(float %a) {
; CHECK-NOF16-LABEL: maximum_imm2(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<3>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
+; CHECK-NOF16-NEXT: .reg .pred %p<4>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<6>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.b32 %r1, [maximum_imm2_param_0];
; CHECK-NOF16-NEXT: setp.nan.f32 %p1, %r1, %r1;
; CHECK-NOF16-NEXT: max.f32 %r2, %r1, 0f00000000;
; CHECK-NOF16-NEXT: selp.f32 %r3, 0f7FC00000, %r2, %p1;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p2, %r3, 0f00000000;
-; CHECK-NOF16-NEXT: selp.f32 %r4, 0f00000000, %r3, %p2;
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NOF16-NEXT: setp.eq.b32 %p2, %r1, 0;
+; CHECK-NOF16-NEXT: selp.f32 %r4, %r1, 0f00000000, %p2;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p3, %r1, 0f00000000;
+; CHECK-NOF16-NEXT: selp.f32 %r5, %r4, %r3, %p3;
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: maximum_imm2(
@@ -1441,22 +1415,20 @@ define float @maximum_imm2(float %a) {
define float @maximum_float(float %a, float %b) {
; CHECK-NOF16-LABEL: maximum_float(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<8>;
+; CHECK-NOF16-NEXT: .reg .pred %p<4>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.b32 %r1, [maximum_float_param_0];
+; CHECK-NOF16-NEXT: setp.eq.b32 %p1, %r1, 0;
; CHECK-NOF16-NEXT: ld.param.b32 %r2, [maximum_float_param_1];
-; CHECK-NOF16-NEXT: setp.nan.f32 %p1, %r1, %r2;
-; CHECK-NOF16-NEXT: max.f32 %r3, %r1, %r2;
-; CHECK-NOF16-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; CHECK-NOF16-NEXT: setp.eq.b32 %p2, %r1, 0;
-; CHECK-NOF16-NEXT: selp.f32 %r5, %r1, %r4, %p2;
-; CHECK-NOF16-NEXT: setp.eq.b32 %p3, %r2, 0;
-; CHECK-NOF16-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p4, %r4, 0f00000000;
-; CHECK-NOF16-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NOF16-NEXT: selp.f32 %r3, %r1, %r2, %p1;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %r1, %r2;
+; CHECK-NOF16-NEXT: max.f32 %r4, %r1, %r2;
+; CHECK-NOF16-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p3, %r1, %r2;
+; CHECK-NOF16-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: maximum_float(
@@ -1487,22 +1459,20 @@ define float @maximum_float(float %a, float %b) {
define float @maximum_float_ftz(float %a, float %b) #1 {
; CHECK-NOF16-LABEL: maximum_float_ftz(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<8>;
+; CHECK-NOF16-NEXT: .reg .pred %p<4>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.b32 %r1, [maximum_float_ftz_param_0];
+; CHECK-NOF16-NEXT: setp.eq.b32 %p1, %r1, 0;
; CHECK-NOF16-NEXT: ld.param.b32 %r2, [maximum_float_ftz_param_1];
-; CHECK-NOF16-NEXT: setp.nan.ftz.f32 %p1, %r1, %r2;
-; CHECK-NOF16-NEXT: max.ftz.f32 %r3, %r1, %r2;
-; CHECK-NOF16-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1;
-; CHECK-NOF16-NEXT: setp.eq.b32 %p2, %r1, 0;
-; CHECK-NOF16-NEXT: selp.f32 %r5, %r1, %r4, %p2;
-; CHECK-NOF16-NEXT: setp.eq.b32 %p3, %r2, 0;
-; CHECK-NOF16-NEXT: selp.f32 %r6, %r2, %r5, %p3;
-; CHECK-NOF16-NEXT: setp.eq.ftz.f32 %p4, %r4, 0f00000000;
-; CHECK-NOF16-NEXT: selp.f32 %r7, %r6, %r4, %p4;
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NOF16-NEXT: selp.f32 %r3, %r1, %r2, %p1;
+; CHECK-NOF16-NEXT: setp.nan.ftz.f32 %p2, %r1, %r2;
+; CHECK-NOF16-NEXT: max.ftz.f32 %r4, %r1, %r2;
+; CHECK-NOF16-NEXT: selp.f32 %r5, 0f7FC00000, %r4, %p2;
+; CHECK-NOF16-NEXT: setp.eq.ftz.f32 %p3, %r1, %r2;
+; CHECK-NOF16-NEXT: selp.f32 %r6, %r3, %r5, %p3;
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: maximum_float_ftz(
@@ -1533,22 +1503,20 @@ define float @maximum_float_ftz(float %a, float %b) #1 {
define double @maximum_double(double %a, double %b) {
; CHECK-LABEL: maximum_double(
; CHECK: {
-; CHECK-NEXT: .reg .pred %p<5>;
-; CHECK-NEXT: .reg .b64 %rd<8>;
+; CHECK-NEXT: .reg .pred %p<4>;
+; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [maximum_double_param_0];
+; CHECK-NEXT: setp.eq.b64 %p1, %rd1, 0;
; CHECK-NEXT: ld.param.b64 %rd2, [maximum_double_param_1];
-; CHECK-NEXT: setp.nan.f64 %p1, %rd1, %rd2;
-; CHECK-NEXT: max.f64 %rd3, %rd1, %rd2;
-; CHECK-NEXT: selp.f64 %rd4, 0d7FF8000000000000, %rd3, %p1;
-; CHECK-NEXT: setp.eq.b64 %p2, %rd1, 0;
-; CHECK-NEXT: selp.f64 %rd5, %rd1, %rd4, %p2;
-; CHECK-NEXT: setp.eq.b64 %p3, %rd2, 0;
-; CHECK-NEXT: selp.f64 %rd6, %rd2, %rd5, %p3;
-; CHECK-NEXT: setp.eq.f64 %p4, %rd4, 0d0000000000000000;
-; CHECK-NEXT: selp.f64 %rd7, %rd6, %rd4, %p4;
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd7;
+; CHECK-NEXT: selp.f64 %rd3, %rd1, %rd2, %p1;
+; CHECK-NEXT: setp.nan.f64 %p2, %rd1, %rd2;
+; CHECK-NEXT: max.f64 %rd4, %rd1, %rd2;
+; CHECK-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p2;
+; CHECK-NEXT: setp.eq.f64 %p3, %rd1, %rd2;
+; CHECK-NEXT: selp.f64 %rd6, %rd3, %rd5, %p3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd6;
; CHECK-NEXT: ret;
%x = call double @llvm.maximum.f64(double %a, double %b)
ret double %x
@@ -1557,40 +1525,34 @@ define double @maximum_double(double %a, double %b) {
define <2 x half> @maximum_v2half(<2 x half> %a, <2 x half> %b) {
; CHECK-NOF16-LABEL: maximum_v2half(
; CHECK-NOF16: {
-; CHECK-NOF16-NEXT: .reg .pred %p<11>;
-; CHECK-NOF16-NEXT: .reg .b16 %rs<15>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .pred %p<9>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<13>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [maximum_v2half_param_0];
+; CHECK-NOF16-NEXT: setp.eq.b16 %p1, %rs2, 0;
; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [maximum_v2half_param_1];
+; CHECK-NOF16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NOF16-NEXT: setp.gt.f32 %p1, %r2, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
-; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %r2, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs6, 0x7E00, %rs5, %p2;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; CHECK-NOF16-NEXT: selp.b16 %rs7, %rs2, %rs6, %p3;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p4, %rs4, 0;
-; CHECK-NOF16-NEXT: selp.b16 %rs8, %rs4, %rs7, %p4;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs6;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p5, %r3, 0f00000000;
-; CHECK-NOF16-NEXT: selp.b16 %rs9, %rs8, %rs6, %p5;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: setp.gt.f32 %p6, %r5, %r4;
+; CHECK-NOF16-NEXT: setp.gt.f32 %p2, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs6, %rs2, %rs4, %p2;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p3, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs7, 0x7E00, %rs6, %p3;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p4, %r2, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs8, %rs5, %rs7, %p4;
+; CHECK-NOF16-NEXT: setp.eq.b16 %p5, %rs1, 0;
+; CHECK-NOF16-NEXT: selp.b16 %rs9, %rs1, %rs3, %p5;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.gt.f32 %p6, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs10, %rs1, %rs3, %p6;
-; CHECK-NOF16-NEXT: setp.nan.f32 %p7, %r5, %r4;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p7, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs11, 0x7E00, %rs10, %p7;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p8, %rs1, 0;
-; CHECK-NOF16-NEXT: selp.b16 %rs12, %rs1, %rs11, %p8;
-; CHECK-NOF16-NEXT: setp.eq.b16 %p9, %rs3, 0;
-; CHECK-NOF16-NEXT: selp.b16 %rs13, %rs3, %rs12, %p9;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs11;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p10, %r6, 0f00000000;
-; CHECK-NOF16-NEXT: selp.b16 %rs14, %rs13, %rs11, %p10;
-; CHECK-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs14, %rs9};
+; CHECK-NOF16-NEXT: setp.eq.f32 %p8, %r4, %r3;
+; CHECK-NOF16-NEXT: selp.b16 %rs12, %rs9, %rs11, %p8;
+; CHECK-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs12, %rs8};
; CHECK-NOF16-NEXT: ret;
;
; CHECK-F16-LABEL: maximum_v2half(
@@ -1606,40 +1568,34 @@ define <2 x half> @maximum_v2half(<2 x half> %a, <2 x half> %b) {
;
; CHECK-SM80-NOF16-LABEL: maximum_v2half(
; CHECK-SM80-NOF16: {
-; CHECK-SM80-NOF16-NEXT: .reg .pred %p<11>;
-; CHECK-SM80-NOF16-NEXT: .reg .b16 %rs<15>;
-; CHECK-SM80-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-SM80-NOF16-NEXT: .reg .pred %p<9>;
+; CHECK-SM80-NOF16-NEXT: .reg .b16 %rs<13>;
+; CHECK-SM80-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-SM80-NOF16-EMPTY:
; CHECK-SM80-NOF16-NEXT: // %bb.0:
; CHECK-SM80-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [maximum_v2half_param_0];
+; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p1, %rs2, 0;
; CHECK-SM80-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [maximum_v2half_param_1];
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-SM80-NOF16-NEXT: setp.gt.f32 %p1, %r2, %r1;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p1;
-; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p2, %r2, %r1;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs6, 0x7E00, %rs5, %p2;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p3, %rs2, 0;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs7, %rs2, %rs6, %p3;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p4, %rs4, 0;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs8, %rs4, %rs7, %p4;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r3, %rs6;
-; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p5, %r3, 0f00000000;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs9, %rs8, %rs6, %p5;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r4, %rs3;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-SM80-NOF16-NEXT: setp.gt.f32 %p6, %r5, %r4;
+; CHECK-SM80-NOF16-NEXT: setp.gt.f32 %p2, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs6, %rs2, %rs4, %p2;
+; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p3, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs7, 0x7E00, %rs6, %p3;
+; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p4, %r2, %r1;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs8, %rs5, %rs7, %p4;
+; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p5, %rs1, 0;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs9, %rs1, %rs3, %p5;
+; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-SM80-NOF16-NEXT: setp.gt.f32 %p6, %r4, %r3;
; CHECK-SM80-NOF16-NEXT: selp.b16 %rs10, %rs1, %rs3, %p6;
-; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p7, %r5, %r4;
+; CHECK-SM80-NOF16-NEXT: setp.nan.f32 %p7, %r4, %r3;
; CHECK-SM80-NOF16-NEXT: selp.b16 %rs11, 0x7E00, %rs10, %p7;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p8, %rs1, 0;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs12, %rs1, %rs11, %p8;
-; CHECK-SM80-NOF16-NEXT: setp.eq.b16 %p9, %rs3, 0;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs13, %rs3, %rs12, %p9;
-; CHECK-SM80-NOF16-NEXT: cvt.f32.f16 %r6, %rs11;
-; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p10, %r6, 0f00000000;
-; CHECK-SM80-NOF16-NEXT: selp.b16 %rs14, %rs13, %rs11, %p10;
-; CHECK-SM80-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs14, %rs9};
+; CHECK-SM80-NOF16-NEXT: setp.eq.f32 %p8, %r4, %r3;
+; CHECK-SM80-NOF16-NEXT: selp.b16 %rs12, %rs9, %rs11, %p8;
+; CHECK-SM80-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs12, %rs8};
; CHECK-SM80-NOF16-NEXT: ret;
%x = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
ret <2 x half> %x
diff --git a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
index 6d9eb13376827..e53c18003e2f4 100644
--- a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
@@ -4,44 +4,31 @@
define fp128 @f128_minimum(fp128 %a, fp128 %b) {
; CHECK-LABEL: f128_minimum:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscmpuqp 0, 2, 3
+; CHECK-NEXT: xststdcqp 0, 2, 4
; CHECK-NEXT: vmr 4, 2
-; CHECK-NEXT: bge 0, .LBB0_8
+; CHECK-NEXT: bc 4, 2, .LBB0_6
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: bun 0, .LBB0_9
+; CHECK-NEXT: xscmpuqp 0, 4, 3
+; CHECK-NEXT: bge 0, .LBB0_7
; CHECK-NEXT: .LBB0_2: # %entry
-; CHECK-NEXT: xststdcqp 0, 2, 4
-; CHECK-NEXT: bc 4, 2, .LBB0_10
-; CHECK-NEXT: .LBB0_3: # %entry
-; CHECK-NEXT: xststdcqp 0, 3, 4
-; CHECK-NEXT: bc 12, 2, .LBB0_5
-; CHECK-NEXT: .LBB0_4: # %entry
-; CHECK-NEXT: vmr 3, 2
-; CHECK-NEXT: .LBB0_5: # %entry
-; CHECK-NEXT: addis 3, 2, .LCPI0_1 at toc@ha
-; CHECK-NEXT: addi 3, 3, .LCPI0_1 at toc@l
-; CHECK-NEXT: lxv 34, 0(3)
-; CHECK-NEXT: xscmpuqp 0, 4, 2
-; CHECK-NEXT: beq 0, .LBB0_7
-; CHECK-NEXT: # %bb.6: # %entry
-; CHECK-NEXT: vmr 3, 4
-; CHECK-NEXT: .LBB0_7: # %entry
-; CHECK-NEXT: vmr 2, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB0_8: # %entry
-; CHECK-NEXT: vmr 4, 3
-; CHECK-NEXT: bnu 0, .LBB0_2
-; CHECK-NEXT: .LBB0_9:
+; CHECK-NEXT: bnu 0, .LBB0_4
+; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: addis 3, 2, .LCPI0_0 at toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI0_0 at toc@l
; CHECK-NEXT: lxv 36, 0(3)
-; CHECK-NEXT: xststdcqp 0, 2, 4
-; CHECK-NEXT: bc 12, 2, .LBB0_3
-; CHECK-NEXT: .LBB0_10: # %entry
+; CHECK-NEXT: .LBB0_4: # %entry
+; CHECK-NEXT: beqlr 0
+; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: vmr 2, 4
-; CHECK-NEXT: xststdcqp 0, 3, 4
-; CHECK-NEXT: bc 4, 2, .LBB0_4
-; CHECK-NEXT: b .LBB0_5
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB0_6: # %entry
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: xscmpuqp 0, 4, 3
+; CHECK-NEXT: blt 0, .LBB0_2
+; CHECK-NEXT: .LBB0_7: # %entry
+; CHECK-NEXT: vmr 4, 3
+; CHECK-NEXT: bun 0, .LBB0_3
+; CHECK-NEXT: b .LBB0_4
entry:
%m = call fp128 @llvm.minimum.f128(fp128 %a, fp128 %b)
ret fp128 %m
@@ -50,44 +37,31 @@ entry:
define fp128 @f128_maximum(fp128 %a, fp128 %b) {
; CHECK-LABEL: f128_maximum:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscmpuqp 0, 2, 3
+; CHECK-NEXT: xststdcqp 0, 2, 8
; CHECK-NEXT: vmr 4, 2
-; CHECK-NEXT: ble 0, .LBB1_8
+; CHECK-NEXT: bc 4, 2, .LBB1_6
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: bun 0, .LBB1_9
+; CHECK-NEXT: xscmpuqp 0, 4, 3
+; CHECK-NEXT: ble 0, .LBB1_7
; CHECK-NEXT: .LBB1_2: # %entry
-; CHECK-NEXT: xststdcqp 0, 2, 8
-; CHECK-NEXT: bc 4, 2, .LBB1_10
-; CHECK-NEXT: .LBB1_3: # %entry
-; CHECK-NEXT: xststdcqp 0, 3, 8
-; CHECK-NEXT: bc 12, 2, .LBB1_5
-; CHECK-NEXT: .LBB1_4: # %entry
-; CHECK-NEXT: vmr 3, 2
-; CHECK-NEXT: .LBB1_5: # %entry
-; CHECK-NEXT: addis 3, 2, .LCPI1_1 at toc@ha
-; CHECK-NEXT: addi 3, 3, .LCPI1_1 at toc@l
-; CHECK-NEXT: lxv 34, 0(3)
-; CHECK-NEXT: xscmpuqp 0, 4, 2
-; CHECK-NEXT: beq 0, .LBB1_7
-; CHECK-NEXT: # %bb.6: # %entry
-; CHECK-NEXT: vmr 3, 4
-; CHECK-NEXT: .LBB1_7: # %entry
-; CHECK-NEXT: vmr 2, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB1_8: # %entry
-; CHECK-NEXT: vmr 4, 3
-; CHECK-NEXT: bnu 0, .LBB1_2
-; CHECK-NEXT: .LBB1_9:
+; CHECK-NEXT: bnu 0, .LBB1_4
+; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: addis 3, 2, .LCPI1_0 at toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI1_0 at toc@l
; CHECK-NEXT: lxv 36, 0(3)
-; CHECK-NEXT: xststdcqp 0, 2, 8
-; CHECK-NEXT: bc 12, 2, .LBB1_3
-; CHECK-NEXT: .LBB1_10: # %entry
+; CHECK-NEXT: .LBB1_4: # %entry
+; CHECK-NEXT: beqlr 0
+; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: vmr 2, 4
-; CHECK-NEXT: xststdcqp 0, 3, 8
-; CHECK-NEXT: bc 4, 2, .LBB1_4
-; CHECK-NEXT: b .LBB1_5
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB1_6: # %entry
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: xscmpuqp 0, 4, 3
+; CHECK-NEXT: bgt 0, .LBB1_2
+; CHECK-NEXT: .LBB1_7: # %entry
+; CHECK-NEXT: vmr 4, 3
+; CHECK-NEXT: bun 0, .LBB1_3
+; CHECK-NEXT: b .LBB1_4
entry:
%m = call fp128 @llvm.maximum.f128(fp128 %a, fp128 %b)
ret fp128 %m
diff --git a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
index 6de0ee73b6f43..01e3813ea0199 100644
--- a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
+++ b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
@@ -8,7 +8,6 @@ define float @f32_minimum(float %a, float %b) {
; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: fcmpu 0, 1, 2
; NOVSX-NEXT: fmr 0, 1
-; NOVSX-NEXT: stfs 2, -8(1)
; NOVSX-NEXT: stfs 1, -4(1)
; NOVSX-NEXT: bc 12, 0, .LBB0_2
; NOVSX-NEXT: # %bb.1: # %entry
@@ -21,26 +20,14 @@ define float @f32_minimum(float %a, float %b) {
; NOVSX-NEXT: lfs 0, .LCPI0_0 at toc@l(4)
; NOVSX-NEXT: .LBB0_4: # %entry
; NOVSX-NEXT: xoris 3, 3, 32768
-; NOVSX-NEXT: lwz 4, -8(1)
-; NOVSX-NEXT: cmplwi 3, 0
-; NOVSX-NEXT: bc 12, 2, .LBB0_6
+; NOVSX-NEXT: cmplwi 1, 3, 0
+; NOVSX-NEXT: bc 12, 6, .LBB0_6
; NOVSX-NEXT: # %bb.5: # %entry
-; NOVSX-NEXT: fmr 1, 0
+; NOVSX-NEXT: fmr 1, 2
; NOVSX-NEXT: .LBB0_6: # %entry
-; NOVSX-NEXT: xoris 3, 4, 32768
-; NOVSX-NEXT: cmplwi 3, 0
-; NOVSX-NEXT: bc 12, 2, .LBB0_8
+; NOVSX-NEXT: bclr 12, 2, 0
; NOVSX-NEXT: # %bb.7: # %entry
-; NOVSX-NEXT: fmr 2, 1
-; NOVSX-NEXT: .LBB0_8: # %entry
-; NOVSX-NEXT: addis 3, 2, .LCPI0_1 at toc@ha
-; NOVSX-NEXT: lfs 1, .LCPI0_1 at toc@l(3)
-; NOVSX-NEXT: fcmpu 0, 0, 1
-; NOVSX-NEXT: bc 12, 2, .LBB0_10
-; NOVSX-NEXT: # %bb.9: # %entry
-; NOVSX-NEXT: fmr 2, 0
-; NOVSX-NEXT: .LBB0_10: # %entry
-; NOVSX-NEXT: fmr 1, 2
+; NOVSX-NEXT: fmr 1, 0
; NOVSX-NEXT: blr
;
; VSX-LABEL: f32_minimum:
@@ -76,38 +63,31 @@ define float @f32_maximum(float %a, float %b) {
; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: fcmpu 0, 1, 2
; NOVSX-NEXT: fmr 0, 1
-; NOVSX-NEXT: stfs 2, -8(1)
; NOVSX-NEXT: stfs 1, -4(1)
-; NOVSX-NEXT: bc 12, 1, .LBB1_2
+; NOVSX-NEXT: bc 4, 1, .LBB1_6
; NOVSX-NEXT: # %bb.1: # %entry
-; NOVSX-NEXT: fmr 0, 2
-; NOVSX-NEXT: .LBB1_2: # %entry
; NOVSX-NEXT: lwz 3, -4(1)
-; NOVSX-NEXT: bc 4, 3, .LBB1_4
-; NOVSX-NEXT: # %bb.3:
-; NOVSX-NEXT: addis 4, 2, .LCPI1_0 at toc@ha
-; NOVSX-NEXT: lfs 0, .LCPI1_0 at toc@l(4)
+; NOVSX-NEXT: bc 12, 3, .LBB1_7
+; NOVSX-NEXT: .LBB1_2: # %entry
+; NOVSX-NEXT: cmpwi 1, 3, 0
+; NOVSX-NEXT: bc 12, 6, .LBB1_4
+; NOVSX-NEXT: .LBB1_3: # %entry
+; NOVSX-NEXT: fmr 1, 2
; NOVSX-NEXT: .LBB1_4: # %entry
-; NOVSX-NEXT: cmpwi 3, 0
-; NOVSX-NEXT: lwz 4, -8(1)
-; NOVSX-NEXT: bc 12, 2, .LBB1_6
+; NOVSX-NEXT: bclr 12, 2, 0
; NOVSX-NEXT: # %bb.5: # %entry
; NOVSX-NEXT: fmr 1, 0
-; NOVSX-NEXT: .LBB1_6: # %entry
-; NOVSX-NEXT: cmpwi 4, 0
-; NOVSX-NEXT: bc 12, 2, .LBB1_8
-; NOVSX-NEXT: # %bb.7: # %entry
-; NOVSX-NEXT: fmr 2, 1
-; NOVSX-NEXT: .LBB1_8: # %entry
-; NOVSX-NEXT: addis 3, 2, .LCPI1_1 at toc@ha
-; NOVSX-NEXT: lfs 1, .LCPI1_1 at toc@l(3)
-; NOVSX-NEXT: fcmpu 0, 0, 1
-; NOVSX-NEXT: bc 12, 2, .LBB1_10
-; NOVSX-NEXT: # %bb.9: # %entry
-; NOVSX-NEXT: fmr 2, 0
-; NOVSX-NEXT: .LBB1_10: # %entry
-; NOVSX-NEXT: fmr 1, 2
; NOVSX-NEXT: blr
+; NOVSX-NEXT: .LBB1_6: # %entry
+; NOVSX-NEXT: fmr 0, 2
+; NOVSX-NEXT: lwz 3, -4(1)
+; NOVSX-NEXT: bc 4, 3, .LBB1_2
+; NOVSX-NEXT: .LBB1_7:
+; NOVSX-NEXT: addis 4, 2, .LCPI1_0 at toc@ha
+; NOVSX-NEXT: lfs 0, .LCPI1_0 at toc@l(4)
+; NOVSX-NEXT: cmpwi 1, 3, 0
+; NOVSX-NEXT: bc 4, 6, .LBB1_3
+; NOVSX-NEXT: b .LBB1_4
;
; VSX-LABEL: f32_maximum:
; VSX: # %bb.0: # %entry
@@ -142,7 +122,6 @@ define double @f64_minimum(double %a, double %b) {
; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: fcmpu 0, 1, 2
; NOVSX-NEXT: fmr 0, 1
-; NOVSX-NEXT: stfd 2, -16(1)
; NOVSX-NEXT: stfd 1, -8(1)
; NOVSX-NEXT: bc 12, 0, .LBB2_2
; NOVSX-NEXT: # %bb.1: # %entry
@@ -154,27 +133,16 @@ define double @f64_minimum(double %a, double %b) {
; NOVSX-NEXT: addis 4, 2, .LCPI2_0 at toc@ha
; NOVSX-NEXT: lfs 0, .LCPI2_0 at toc@l(4)
; NOVSX-NEXT: .LBB2_4: # %entry
-; NOVSX-NEXT: li 5, 1
-; NOVSX-NEXT: ld 4, -16(1)
-; NOVSX-NEXT: rldic 5, 5, 63, 0
-; NOVSX-NEXT: cmpd 3, 5
-; NOVSX-NEXT: bc 12, 2, .LBB2_6
+; NOVSX-NEXT: li 4, 1
+; NOVSX-NEXT: rldic 4, 4, 63, 0
+; NOVSX-NEXT: cmpd 1, 3, 4
+; NOVSX-NEXT: bc 12, 6, .LBB2_6
; NOVSX-NEXT: # %bb.5: # %entry
-; NOVSX-NEXT: fmr 1, 0
+; NOVSX-NEXT: fmr 1, 2
; NOVSX-NEXT: .LBB2_6: # %entry
-; NOVSX-NEXT: cmpd 4, 5
-; NOVSX-NEXT: bc 12, 2, .LBB2_8
+; NOVSX-NEXT: bclr 12, 2, 0
; NOVSX-NEXT: # %bb.7: # %entry
-; NOVSX-NEXT: fmr 2, 1
-; NOVSX-NEXT: .LBB2_8: # %entry
-; NOVSX-NEXT: addis 3, 2, .LCPI2_1 at toc@ha
-; NOVSX-NEXT: lfs 1, .LCPI2_1 at toc@l(3)
-; NOVSX-NEXT: fcmpu 0, 0, 1
-; NOVSX-NEXT: bc 12, 2, .LBB2_10
-; NOVSX-NEXT: # %bb.9: # %entry
-; NOVSX-NEXT: fmr 2, 0
-; NOVSX-NEXT: .LBB2_10: # %entry
-; NOVSX-NEXT: fmr 1, 2
+; NOVSX-NEXT: fmr 1, 0
; NOVSX-NEXT: blr
;
; VSX-LABEL: f64_minimum:
@@ -210,38 +178,31 @@ define double @f64_maximum(double %a, double %b) {
; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: fcmpu 0, 1, 2
; NOVSX-NEXT: fmr 0, 1
-; NOVSX-NEXT: stfd 2, -16(1)
; NOVSX-NEXT: stfd 1, -8(1)
-; NOVSX-NEXT: bc 12, 1, .LBB3_2
+; NOVSX-NEXT: bc 4, 1, .LBB3_6
; NOVSX-NEXT: # %bb.1: # %entry
-; NOVSX-NEXT: fmr 0, 2
-; NOVSX-NEXT: .LBB3_2: # %entry
; NOVSX-NEXT: ld 3, -8(1)
-; NOVSX-NEXT: bc 4, 3, .LBB3_4
-; NOVSX-NEXT: # %bb.3:
-; NOVSX-NEXT: addis 4, 2, .LCPI3_0 at toc@ha
-; NOVSX-NEXT: lfs 0, .LCPI3_0 at toc@l(4)
+; NOVSX-NEXT: bc 12, 3, .LBB3_7
+; NOVSX-NEXT: .LBB3_2: # %entry
+; NOVSX-NEXT: cmpdi 1, 3, 0
+; NOVSX-NEXT: bc 12, 6, .LBB3_4
+; NOVSX-NEXT: .LBB3_3: # %entry
+; NOVSX-NEXT: fmr 1, 2
; NOVSX-NEXT: .LBB3_4: # %entry
-; NOVSX-NEXT: cmpdi 3, 0
-; NOVSX-NEXT: ld 4, -16(1)
-; NOVSX-NEXT: bc 12, 2, .LBB3_6
+; NOVSX-NEXT: bclr 12, 2, 0
; NOVSX-NEXT: # %bb.5: # %entry
; NOVSX-NEXT: fmr 1, 0
-; NOVSX-NEXT: .LBB3_6: # %entry
-; NOVSX-NEXT: cmpdi 4, 0
-; NOVSX-NEXT: bc 12, 2, .LBB3_8
-; NOVSX-NEXT: # %bb.7: # %entry
-; NOVSX-NEXT: fmr 2, 1
-; NOVSX-NEXT: .LBB3_8: # %entry
-; NOVSX-NEXT: addis 3, 2, .LCPI3_1 at toc@ha
-; NOVSX-NEXT: lfs 1, .LCPI3_1 at toc@l(3)
-; NOVSX-NEXT: fcmpu 0, 0, 1
-; NOVSX-NEXT: bc 12, 2, .LBB3_10
-; NOVSX-NEXT: # %bb.9: # %entry
-; NOVSX-NEXT: fmr 2, 0
-; NOVSX-NEXT: .LBB3_10: # %entry
-; NOVSX-NEXT: fmr 1, 2
; NOVSX-NEXT: blr
+; NOVSX-NEXT: .LBB3_6: # %entry
+; NOVSX-NEXT: fmr 0, 2
+; NOVSX-NEXT: ld 3, -8(1)
+; NOVSX-NEXT: bc 4, 3, .LBB3_2
+; NOVSX-NEXT: .LBB3_7:
+; NOVSX-NEXT: addis 4, 2, .LCPI3_0 at toc@ha
+; NOVSX-NEXT: lfs 0, .LCPI3_0 at toc@l(4)
+; NOVSX-NEXT: cmpdi 1, 3, 0
+; NOVSX-NEXT: bc 4, 6, .LBB3_3
+; NOVSX-NEXT: b .LBB3_4
;
; VSX-LABEL: f64_maximum:
; VSX: # %bb.0: # %entry
@@ -285,15 +246,12 @@ define <4 x float> @v4f32_minimum(<4 x float> %a, <4 x float> %b) {
; NOVSX-NEXT: vslw 4, 4, 4
; NOVSX-NEXT: vor 0, 1, 0
; NOVSX-NEXT: lvx 1, 0, 3
+; NOVSX-NEXT: vcmpequw 4, 2, 4
; NOVSX-NEXT: vsel 5, 3, 2, 5
+; NOVSX-NEXT: vsel 4, 3, 2, 4
+; NOVSX-NEXT: vcmpeqfp 2, 2, 3
; NOVSX-NEXT: vsel 5, 5, 1, 0
-; NOVSX-NEXT: vcmpequw 0, 2, 4
-; NOVSX-NEXT: vcmpequw 4, 3, 4
-; NOVSX-NEXT: vsel 2, 5, 2, 0
-; NOVSX-NEXT: vsel 2, 2, 3, 4
-; NOVSX-NEXT: vxor 3, 3, 3
-; NOVSX-NEXT: vcmpeqfp 3, 5, 3
-; NOVSX-NEXT: vsel 2, 5, 2, 3
+; NOVSX-NEXT: vsel 2, 5, 4, 2
; NOVSX-NEXT: blr
;
; VSX-LABEL: v4f32_minimum:
@@ -342,12 +300,10 @@ define <4 x float> @v4f32_maximum(<4 x float> %a, <4 x float> %b) {
; NOVSX-NEXT: vsel 4, 3, 2, 4
; NOVSX-NEXT: vsel 4, 4, 0, 5
; NOVSX-NEXT: vxor 5, 5, 5
-; NOVSX-NEXT: vcmpequw 0, 2, 5
-; NOVSX-NEXT: vsel 2, 4, 2, 0
-; NOVSX-NEXT: vcmpequw 0, 3, 5
-; NOVSX-NEXT: vsel 2, 2, 3, 0
-; NOVSX-NEXT: vcmpeqfp 3, 4, 5
-; NOVSX-NEXT: vsel 2, 4, 2, 3
+; NOVSX-NEXT: vcmpequw 5, 2, 5
+; NOVSX-NEXT: vsel 5, 3, 2, 5
+; NOVSX-NEXT: vcmpeqfp 2, 2, 3
+; NOVSX-NEXT: vsel 2, 4, 5, 2
; NOVSX-NEXT: blr
;
; VSX-LABEL: v4f32_maximum:
@@ -386,16 +342,14 @@ define <2 x double> @v2f64_minimum(<2 x double> %a, <2 x double> %b) {
; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: fcmpu 0, 1, 3
; NOVSX-NEXT: fmr 6, 1
-; NOVSX-NEXT: stfd 4, -16(1)
; NOVSX-NEXT: stfd 2, -8(1)
-; NOVSX-NEXT: stfd 3, -32(1)
-; NOVSX-NEXT: stfd 1, -24(1)
+; NOVSX-NEXT: stfd 1, -16(1)
; NOVSX-NEXT: bc 12, 0, .LBB6_2
; NOVSX-NEXT: # %bb.1: # %entry
; NOVSX-NEXT: fmr 6, 3
; NOVSX-NEXT: .LBB6_2: # %entry
; NOVSX-NEXT: addis 3, 2, .LCPI6_0 at toc@ha
-; NOVSX-NEXT: ld 4, -24(1)
+; NOVSX-NEXT: ld 4, -16(1)
; NOVSX-NEXT: lfs 0, .LCPI6_0 at toc@l(3)
; NOVSX-NEXT: fmr 5, 0
; NOVSX-NEXT: bc 12, 3, .LBB6_4
@@ -403,60 +357,41 @@ define <2 x double> @v2f64_minimum(<2 x double> %a, <2 x double> %b) {
; NOVSX-NEXT: fmr 5, 6
; NOVSX-NEXT: .LBB6_4: # %entry
; NOVSX-NEXT: li 3, 1
-; NOVSX-NEXT: ld 5, -32(1)
; NOVSX-NEXT: rldic 3, 3, 63, 0
-; NOVSX-NEXT: cmpd 4, 3
-; NOVSX-NEXT: bc 12, 2, .LBB6_6
+; NOVSX-NEXT: cmpd 1, 4, 3
+; NOVSX-NEXT: bc 12, 6, .LBB6_6
; NOVSX-NEXT: # %bb.5: # %entry
-; NOVSX-NEXT: fmr 1, 5
+; NOVSX-NEXT: fmr 1, 3
; NOVSX-NEXT: .LBB6_6: # %entry
-; NOVSX-NEXT: cmpd 5, 3
; NOVSX-NEXT: bc 12, 2, .LBB6_8
; NOVSX-NEXT: # %bb.7: # %entry
-; NOVSX-NEXT: fmr 3, 1
+; NOVSX-NEXT: fmr 1, 5
; NOVSX-NEXT: .LBB6_8: # %entry
-; NOVSX-NEXT: addis 4, 2, .LCPI6_1 at toc@ha
-; NOVSX-NEXT: lfs 1, .LCPI6_1 at toc@l(4)
-; NOVSX-NEXT: fcmpu 0, 5, 1
-; NOVSX-NEXT: bc 12, 2, .LBB6_10
+; NOVSX-NEXT: fcmpu 0, 2, 4
+; NOVSX-NEXT: fmr 3, 2
+; NOVSX-NEXT: bc 4, 0, .LBB6_14
; NOVSX-NEXT: # %bb.9: # %entry
-; NOVSX-NEXT: fmr 3, 5
+; NOVSX-NEXT: ld 4, -8(1)
+; NOVSX-NEXT: bc 4, 3, .LBB6_15
; NOVSX-NEXT: .LBB6_10: # %entry
-; NOVSX-NEXT: fcmpu 0, 2, 4
-; NOVSX-NEXT: fmr 5, 2
-; NOVSX-NEXT: bc 12, 0, .LBB6_12
-; NOVSX-NEXT: # %bb.11: # %entry
-; NOVSX-NEXT: fmr 5, 4
+; NOVSX-NEXT: cmpd 1, 4, 3
+; NOVSX-NEXT: bc 12, 6, .LBB6_12
+; NOVSX-NEXT: .LBB6_11: # %entry
+; NOVSX-NEXT: fmr 2, 4
; NOVSX-NEXT: .LBB6_12: # %entry
-; NOVSX-NEXT: ld 5, -8(1)
-; NOVSX-NEXT: bc 12, 3, .LBB6_14
+; NOVSX-NEXT: bclr 12, 2, 0
; NOVSX-NEXT: # %bb.13: # %entry
-; NOVSX-NEXT: fmr 0, 5
-; NOVSX-NEXT: .LBB6_14: # %entry
-; NOVSX-NEXT: cmpd 5, 3
-; NOVSX-NEXT: ld 4, -16(1)
-; NOVSX-NEXT: bc 4, 2, .LBB6_19
-; NOVSX-NEXT: # %bb.15: # %entry
-; NOVSX-NEXT: cmpd 4, 3
-; NOVSX-NEXT: bc 4, 2, .LBB6_20
-; NOVSX-NEXT: .LBB6_16: # %entry
-; NOVSX-NEXT: fcmpu 0, 0, 1
-; NOVSX-NEXT: bc 12, 2, .LBB6_18
-; NOVSX-NEXT: .LBB6_17: # %entry
-; NOVSX-NEXT: fmr 4, 0
-; NOVSX-NEXT: .LBB6_18: # %entry
-; NOVSX-NEXT: fmr 1, 3
-; NOVSX-NEXT: fmr 2, 4
-; NOVSX-NEXT: blr
-; NOVSX-NEXT: .LBB6_19: # %entry
; NOVSX-NEXT: fmr 2, 0
-; NOVSX-NEXT: cmpd 4, 3
-; NOVSX-NEXT: bc 12, 2, .LBB6_16
-; NOVSX-NEXT: .LBB6_20: # %entry
-; NOVSX-NEXT: fmr 4, 2
-; NOVSX-NEXT: fcmpu 0, 0, 1
-; NOVSX-NEXT: bc 4, 2, .LBB6_17
-; NOVSX-NEXT: b .LBB6_18
+; NOVSX-NEXT: blr
+; NOVSX-NEXT: .LBB6_14: # %entry
+; NOVSX-NEXT: fmr 3, 4
+; NOVSX-NEXT: ld 4, -8(1)
+; NOVSX-NEXT: bc 12, 3, .LBB6_10
+; NOVSX-NEXT: .LBB6_15: # %entry
+; NOVSX-NEXT: fmr 0, 3
+; NOVSX-NEXT: cmpd 1, 4, 3
+; NOVSX-NEXT: bc 4, 6, .LBB6_11
+; NOVSX-NEXT: b .LBB6_12
;
; VSX-LABEL: v2f64_minimum:
; VSX: # %bb.0: # %entry
@@ -494,75 +429,58 @@ define <2 x double> @v2f64_maximum(<2 x double> %a, <2 x double> %b) {
; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: fcmpu 0, 1, 3
; NOVSX-NEXT: fmr 6, 1
-; NOVSX-NEXT: stfd 4, -16(1)
; NOVSX-NEXT: stfd 2, -8(1)
-; NOVSX-NEXT: stfd 3, -32(1)
-; NOVSX-NEXT: stfd 1, -24(1)
+; NOVSX-NEXT: stfd 1, -16(1)
; NOVSX-NEXT: bc 12, 1, .LBB7_2
; NOVSX-NEXT: # %bb.1: # %entry
; NOVSX-NEXT: fmr 6, 3
; NOVSX-NEXT: .LBB7_2: # %entry
; NOVSX-NEXT: addis 4, 2, .LCPI7_0 at toc@ha
-; NOVSX-NEXT: ld 3, -24(1)
+; NOVSX-NEXT: ld 3, -16(1)
; NOVSX-NEXT: lfs 0, .LCPI7_0 at toc@l(4)
; NOVSX-NEXT: fmr 5, 0
-; NOVSX-NEXT: bc 12, 3, .LBB7_4
+; NOVSX-NEXT: bc 4, 3, .LBB7_12
; NOVSX-NEXT: # %bb.3: # %entry
-; NOVSX-NEXT: fmr 5, 6
+; NOVSX-NEXT: cmpdi 1, 3, 0
+; NOVSX-NEXT: bc 4, 6, .LBB7_13
; NOVSX-NEXT: .LBB7_4: # %entry
-; NOVSX-NEXT: cmpdi 3, 0
-; NOVSX-NEXT: ld 4, -32(1)
; NOVSX-NEXT: bc 12, 2, .LBB7_6
-; NOVSX-NEXT: # %bb.5: # %entry
+; NOVSX-NEXT: .LBB7_5: # %entry
; NOVSX-NEXT: fmr 1, 5
; NOVSX-NEXT: .LBB7_6: # %entry
-; NOVSX-NEXT: cmpdi 4, 0
-; NOVSX-NEXT: bc 12, 2, .LBB7_8
+; NOVSX-NEXT: fcmpu 0, 2, 4
+; NOVSX-NEXT: fmr 3, 2
+; NOVSX-NEXT: bc 4, 1, .LBB7_14
; NOVSX-NEXT: # %bb.7: # %entry
-; NOVSX-NEXT: fmr 3, 1
+; NOVSX-NEXT: ld 3, -8(1)
+; NOVSX-NEXT: bc 4, 3, .LBB7_15
; NOVSX-NEXT: .LBB7_8: # %entry
-; NOVSX-NEXT: addis 3, 2, .LCPI7_1 at toc@ha
-; NOVSX-NEXT: lfs 1, .LCPI7_1 at toc@l(3)
-; NOVSX-NEXT: fcmpu 0, 5, 1
-; NOVSX-NEXT: bc 12, 2, .LBB7_10
-; NOVSX-NEXT: # %bb.9: # %entry
-; NOVSX-NEXT: fmr 3, 5
+; NOVSX-NEXT: cmpdi 1, 3, 0
+; NOVSX-NEXT: bc 12, 6, .LBB7_10
+; NOVSX-NEXT: .LBB7_9: # %entry
+; NOVSX-NEXT: fmr 2, 4
; NOVSX-NEXT: .LBB7_10: # %entry
-; NOVSX-NEXT: fcmpu 0, 2, 4
-; NOVSX-NEXT: fmr 5, 2
-; NOVSX-NEXT: bc 12, 1, .LBB7_12
+; NOVSX-NEXT: bclr 12, 2, 0
; NOVSX-NEXT: # %bb.11: # %entry
-; NOVSX-NEXT: fmr 5, 4
+; NOVSX-NEXT: fmr 2, 0
+; NOVSX-NEXT: blr
; NOVSX-NEXT: .LBB7_12: # %entry
-; NOVSX-NEXT: ld 4, -8(1)
-; NOVSX-NEXT: bc 12, 3, .LBB7_14
-; NOVSX-NEXT: # %bb.13: # %entry
-; NOVSX-NEXT: fmr 0, 5
-; NOVSX-NEXT: .LBB7_14: # %entry
-; NOVSX-NEXT: cmpdi 4, 0
-; NOVSX-NEXT: ld 3, -16(1)
-; NOVSX-NEXT: bc 4, 2, .LBB7_19
-; NOVSX-NEXT: # %bb.15: # %entry
-; NOVSX-NEXT: cmpdi 3, 0
-; NOVSX-NEXT: bc 4, 2, .LBB7_20
-; NOVSX-NEXT: .LBB7_16: # %entry
-; NOVSX-NEXT: fcmpu 0, 0, 1
-; NOVSX-NEXT: bc 12, 2, .LBB7_18
-; NOVSX-NEXT: .LBB7_17: # %entry
-; NOVSX-NEXT: fmr 4, 0
-; NOVSX-NEXT: .LBB7_18: # %entry
+; NOVSX-NEXT: fmr 5, 6
+; NOVSX-NEXT: cmpdi 1, 3, 0
+; NOVSX-NEXT: bc 12, 6, .LBB7_4
+; NOVSX-NEXT: .LBB7_13: # %entry
; NOVSX-NEXT: fmr 1, 3
-; NOVSX-NEXT: fmr 2, 4
-; NOVSX-NEXT: blr
-; NOVSX-NEXT: .LBB7_19: # %entry
-; NOVSX-NEXT: fmr 2, 0
-; NOVSX-NEXT: cmpdi 3, 0
-; NOVSX-NEXT: bc 12, 2, .LBB7_16
-; NOVSX-NEXT: .LBB7_20: # %entry
-; NOVSX-NEXT: fmr 4, 2
-; NOVSX-NEXT: fcmpu 0, 0, 1
-; NOVSX-NEXT: bc 4, 2, .LBB7_17
-; NOVSX-NEXT: b .LBB7_18
+; NOVSX-NEXT: bc 4, 2, .LBB7_5
+; NOVSX-NEXT: b .LBB7_6
+; NOVSX-NEXT: .LBB7_14: # %entry
+; NOVSX-NEXT: fmr 3, 4
+; NOVSX-NEXT: ld 3, -8(1)
+; NOVSX-NEXT: bc 12, 3, .LBB7_8
+; NOVSX-NEXT: .LBB7_15: # %entry
+; NOVSX-NEXT: fmr 0, 3
+; NOVSX-NEXT: cmpdi 1, 3, 0
+; NOVSX-NEXT: bc 4, 6, .LBB7_9
+; NOVSX-NEXT: b .LBB7_10
;
; VSX-LABEL: v2f64_maximum:
; VSX: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/X86/fminimum-fmaximum-i686.ll b/llvm/test/CodeGen/X86/fminimum-fmaximum-i686.ll
new file mode 100644
index 0000000000000..fd28605c6522b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fminimum-fmaximum-i686.ll
@@ -0,0 +1,456 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
+
+define half @maximum_half(half %x, half %y) nounwind {
+; CHECK-LABEL: maximum_half:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushl %esi
+; CHECK-NEXT: subl $12, %esp
+; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl %eax, (%esp)
+; CHECK-NEXT: calll __extendhfsf2
+; CHECK-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: movl %esi, (%esp)
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: calll __extendhfsf2
+; CHECK-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; CHECK-NEXT: cmpl $0, {{[0-9]+}}(%esp)
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: je .LBB0_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(1)
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: fucom %st(2)
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: ja .LBB0_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: .LBB0_4:
+; CHECK-NEXT: fstp %st(2)
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: jp .LBB0_6
+; CHECK-NEXT: # %bb.5:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: .LBB0_6:
+; CHECK-NEXT: fstp %st(2)
+; CHECK-NEXT: jne .LBB0_7
+; CHECK-NEXT: # %bb.8:
+; CHECK-NEXT: jp .LBB0_11
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: jmp .LBB0_10
+; CHECK-NEXT: .LBB0_7:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: .LBB0_10:
+; CHECK-NEXT: fldz
+; CHECK-NEXT: .LBB0_11:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fstps (%esp)
+; CHECK-NEXT: calll __truncsfhf2
+; CHECK-NEXT: addl $12, %esp
+; CHECK-NEXT: popl %esi
+; CHECK-NEXT: retl
+ %res = call half @llvm.maximum.f16(half %x, half %y)
+ ret half %res
+}
+
+define float @maximum_float(float %x, float %y) nounwind {
+; CHECK-LABEL: maximum_float:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushl %eax
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: fsts (%esp)
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: cmpl $0, (%esp)
+; CHECK-NEXT: fld %st(1)
+; CHECK-NEXT: je .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: fucom %st(1)
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: ja .LBB1_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: .LBB1_4:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: jp .LBB1_6
+; CHECK-NEXT: # %bb.5:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: .LBB1_6:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: jne .LBB1_7
+; CHECK-NEXT: # %bb.8:
+; CHECK-NEXT: jp .LBB1_11
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: jmp .LBB1_10
+; CHECK-NEXT: .LBB1_7:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: .LBB1_10:
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: .LBB1_11:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: popl %eax
+; CHECK-NEXT: retl
+ %res = call float @llvm.maximum.f32(float %x, float %y)
+ ret float %res
+}
+
+define double @maximum_double(double %x, double %y) nounwind {
+; CHECK-LABEL: maximum_double:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subl $8, %esp
+; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT: fsts (%esp)
+; CHECK-NEXT: flds (%esp)
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: cmpl $0, {{[0-9]+}}(%esp)
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: je .LBB2_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(1)
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: fucom %st(2)
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: ja .LBB2_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: .LBB2_4:
+; CHECK-NEXT: fstp %st(2)
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: jp .LBB2_6
+; CHECK-NEXT: # %bb.5:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: .LBB2_6:
+; CHECK-NEXT: fstp %st(2)
+; CHECK-NEXT: jne .LBB2_7
+; CHECK-NEXT: # %bb.8:
+; CHECK-NEXT: jp .LBB2_11
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: jmp .LBB2_10
+; CHECK-NEXT: .LBB2_7:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: .LBB2_10:
+; CHECK-NEXT: fldz
+; CHECK-NEXT: .LBB2_11:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: addl $8, %esp
+; CHECK-NEXT: retl
+ %res = call double @llvm.maximum.f64(double %x, double %y)
+ ret double %res
+}
+
+define fp128 @maximum_fp128(fp128 %x, fp128 %y) nounwind {
+; CHECK-LABEL: maximum_fp128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushl %ebp
+; CHECK-NEXT: movl %esp, %ebp
+; CHECK-NEXT: pushl %ebx
+; CHECK-NEXT: pushl %edi
+; CHECK-NEXT: pushl %esi
+; CHECK-NEXT: andl $-16, %esp
+; CHECK-NEXT: subl $80, %esp
+; CHECK-NEXT: movl 8(%ebp), %esi
+; CHECK-NEXT: movl 36(%ebp), %edi
+; CHECK-NEXT: movl 40(%ebp), %ebx
+; CHECK-NEXT: movl 44(%ebp), %edx
+; CHECK-NEXT: movl 48(%ebp), %ecx
+; CHECK-NEXT: movl 52(%ebp), %eax
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %ebx, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %edi, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl 32(%ebp), %eax
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl 28(%ebp), %eax
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl 24(%ebp), %eax
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl %eax, (%esp)
+; CHECK-NEXT: calll fmaximuml
+; CHECK-NEXT: subl $4, %esp
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
+; CHECK-NEXT: movl %edi, 12(%esi)
+; CHECK-NEXT: movl %edx, 8(%esi)
+; CHECK-NEXT: movl %ecx, 4(%esi)
+; CHECK-NEXT: movl %eax, (%esi)
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: leal -12(%ebp), %esp
+; CHECK-NEXT: popl %esi
+; CHECK-NEXT: popl %edi
+; CHECK-NEXT: popl %ebx
+; CHECK-NEXT: popl %ebp
+; CHECK-NEXT: retl $4
+ %res = call fp128 @llvm.maximum.f128(fp128 %x, fp128 %y)
+ ret fp128 %res
+}
+
+define half @minimum_half(half %x, half %y) nounwind {
+; CHECK-LABEL: minimum_half:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushl %esi
+; CHECK-NEXT: subl $12, %esp
+; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl %eax, (%esp)
+; CHECK-NEXT: calll __extendhfsf2
+; CHECK-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
+; CHECK-NEXT: movl %esi, (%esp)
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: calll __extendhfsf2
+; CHECK-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: jo .LBB4_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(1)
+; CHECK-NEXT: .LBB4_2:
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: fucom %st(1)
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: fld %st(1)
+; CHECK-NEXT: ja .LBB4_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: .LBB4_4:
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: fucompp
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: jp .LBB4_6
+; CHECK-NEXT: # %bb.5:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: .LBB4_6:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: jne .LBB4_7
+; CHECK-NEXT: # %bb.8:
+; CHECK-NEXT: jp .LBB4_11
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: jmp .LBB4_10
+; CHECK-NEXT: .LBB4_7:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: .LBB4_10:
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: .LBB4_11:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: fstps (%esp)
+; CHECK-NEXT: calll __truncsfhf2
+; CHECK-NEXT: addl $12, %esp
+; CHECK-NEXT: popl %esi
+; CHECK-NEXT: retl
+ %res = call half @llvm.minimum.f16(half %x, half %y)
+ ret half %res
+}
+
+define float @minimum_float(float %x, float %y) nounwind {
+; CHECK-LABEL: minimum_float:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushl %eax
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: fsts (%esp)
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpl (%esp), %eax
+; CHECK-NEXT: fld %st(1)
+; CHECK-NEXT: jo .LBB5_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: .LBB5_2:
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: fucom %st(2)
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: fld %st(2)
+; CHECK-NEXT: ja .LBB5_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: .LBB5_4:
+; CHECK-NEXT: fxch %st(3)
+; CHECK-NEXT: fucompp
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: jp .LBB5_6
+; CHECK-NEXT: # %bb.5:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: .LBB5_6:
+; CHECK-NEXT: fstp %st(2)
+; CHECK-NEXT: jne .LBB5_7
+; CHECK-NEXT: # %bb.8:
+; CHECK-NEXT: jp .LBB5_11
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: jmp .LBB5_10
+; CHECK-NEXT: .LBB5_7:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: .LBB5_10:
+; CHECK-NEXT: fldz
+; CHECK-NEXT: .LBB5_11:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: popl %eax
+; CHECK-NEXT: retl
+ %res = call float @llvm.minimum.f32(float %x, float %y)
+ ret float %res
+}
+
+define double @minimum_double(double %x, double %y) nounwind {
+; CHECK-LABEL: minimum_double:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subl $8, %esp
+; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT: fsts (%esp)
+; CHECK-NEXT: flds (%esp)
+; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: jo .LBB6_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(1)
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: fucom %st(1)
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: fld %st(1)
+; CHECK-NEXT: ja .LBB6_4
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: .LBB6_4:
+; CHECK-NEXT: fxch %st(2)
+; CHECK-NEXT: fucompp
+; CHECK-NEXT: fnstsw %ax
+; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT: sahf
+; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: jp .LBB6_6
+; CHECK-NEXT: # %bb.5:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: .LBB6_6:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: jne .LBB6_7
+; CHECK-NEXT: # %bb.8:
+; CHECK-NEXT: jp .LBB6_11
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: fstp %st(0)
+; CHECK-NEXT: jmp .LBB6_10
+; CHECK-NEXT: .LBB6_7:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: .LBB6_10:
+; CHECK-NEXT: fldz
+; CHECK-NEXT: fxch %st(1)
+; CHECK-NEXT: .LBB6_11:
+; CHECK-NEXT: fstp %st(1)
+; CHECK-NEXT: addl $8, %esp
+; CHECK-NEXT: retl
+ %res = call double @llvm.minimum.f64(double %x, double %y)
+ ret double %res
+}
+
+define fp128 @minimum_fp128(fp128 %x, fp128 %y) nounwind {
+; CHECK-LABEL: minimum_fp128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushl %ebp
+; CHECK-NEXT: movl %esp, %ebp
+; CHECK-NEXT: pushl %ebx
+; CHECK-NEXT: pushl %edi
+; CHECK-NEXT: pushl %esi
+; CHECK-NEXT: andl $-16, %esp
+; CHECK-NEXT: subl $80, %esp
+; CHECK-NEXT: movl 8(%ebp), %esi
+; CHECK-NEXT: movl 36(%ebp), %edi
+; CHECK-NEXT: movl 40(%ebp), %ebx
+; CHECK-NEXT: movl 44(%ebp), %edx
+; CHECK-NEXT: movl 48(%ebp), %ecx
+; CHECK-NEXT: movl 52(%ebp), %eax
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %ebx, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl %edi, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl 32(%ebp), %eax
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl 28(%ebp), %eax
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl 24(%ebp), %eax
+; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl %eax, (%esp)
+; CHECK-NEXT: calll fminimuml
+; CHECK-NEXT: subl $4, %esp
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
+; CHECK-NEXT: movl %edi, 12(%esi)
+; CHECK-NEXT: movl %edx, 8(%esi)
+; CHECK-NEXT: movl %ecx, 4(%esi)
+; CHECK-NEXT: movl %eax, (%esi)
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: leal -12(%ebp), %esp
+; CHECK-NEXT: popl %esi
+; CHECK-NEXT: popl %edi
+; CHECK-NEXT: popl %ebx
+; CHECK-NEXT: popl %ebp
+; CHECK-NEXT: retl $4
+ %res = call fp128 @llvm.minimum.f128(fp128 %x, fp128 %y)
+ ret fp128 %res
+}
diff --git a/llvm/test/CodeGen/X86/fminimum-fmaximum.ll b/llvm/test/CodeGen/X86/fminimum-fmaximum.ll
index 7f0c138654d09..e9af7fff00db6 100644
--- a/llvm/test/CodeGen/X86/fminimum-fmaximum.ll
+++ b/llvm/test/CodeGen/X86/fminimum-fmaximum.ll
@@ -1796,154 +1796,134 @@ define <4 x half> @test_fmaximum_v4f16(<4 x half> %x, <4 x half> %y) nounwind {
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
-; AVX512F-NEXT: xorl %eax, %eax
+; AVX512F-NEXT: xorl %r8d, %r8d
; AVX512F-NEXT: vucomiss %xmm2, %xmm3
; AVX512F-NEXT: movl $65535, %ecx # imm = 0xFFFF
-; AVX512F-NEXT: movl $0, %edx
-; AVX512F-NEXT: cmovpl %ecx, %edx
-; AVX512F-NEXT: movl $0, %edi
-; AVX512F-NEXT: cmoval %ecx, %edi
+; AVX512F-NEXT: movl $65535, %eax # imm = 0xFFFF
+; AVX512F-NEXT: cmovnel %r8d, %eax
+; AVX512F-NEXT: cmovpl %r8d, %eax
+; AVX512F-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512F-NEXT: movl $0, %eax
+; AVX512F-NEXT: cmovpl %ecx, %eax
+; AVX512F-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512F-NEXT: movl $0, %eax
+; AVX512F-NEXT: cmoval %ecx, %eax
+; AVX512F-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; AVX512F-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vpsrldq {{.*#+}} xmm3 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vucomiss %xmm2, %xmm3
-; AVX512F-NEXT: movl $0, %esi
-; AVX512F-NEXT: cmovpl %ecx, %esi
-; AVX512F-NEXT: movl $0, %r9d
-; AVX512F-NEXT: cmoval %ecx, %r9d
+; AVX512F-NEXT: movl $65535, %ebx # imm = 0xFFFF
+; AVX512F-NEXT: cmovnel %r8d, %ebx
+; AVX512F-NEXT: cmovpl %r8d, %ebx
+; AVX512F-NEXT: movl $0, %eax
+; AVX512F-NEXT: cmovpl %ecx, %eax
+; AVX512F-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512F-NEXT: movl $0, %eax
+; AVX512F-NEXT: cmoval %ecx, %eax
+; AVX512F-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; AVX512F-NEXT: vshufpd {{.*#+}} xmm2 = xmm1[1,0]
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vucomiss %xmm2, %xmm3
-; AVX512F-NEXT: movl $0, %r8d
-; AVX512F-NEXT: cmovpl %ecx, %r8d
-; AVX512F-NEXT: movl $0, %r11d
-; AVX512F-NEXT: cmoval %ecx, %r11d
+; AVX512F-NEXT: movl $65535, %r10d # imm = 0xFFFF
+; AVX512F-NEXT: cmovnel %r8d, %r10d
+; AVX512F-NEXT: cmovpl %r8d, %r10d
+; AVX512F-NEXT: movl $0, %eax
+; AVX512F-NEXT: cmovpl %ecx, %eax
+; AVX512F-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512F-NEXT: movl $0, %r12d
+; AVX512F-NEXT: cmoval %ecx, %r12d
; AVX512F-NEXT: vpsrlq $48, %xmm1, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vpsrlq $48, %xmm0, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vucomiss %xmm2, %xmm3
-; AVX512F-NEXT: movl $0, %r10d
-; AVX512F-NEXT: cmovpl %ecx, %r10d
-; AVX512F-NEXT: movl $0, %ebp
-; AVX512F-NEXT: cmoval %ecx, %ebp
+; AVX512F-NEXT: movl $65535, %r11d # imm = 0xFFFF
+; AVX512F-NEXT: cmovnel %r8d, %r11d
+; AVX512F-NEXT: cmovpl %r8d, %r11d
+; AVX512F-NEXT: movl $0, %r15d
+; AVX512F-NEXT: cmovpl %ecx, %r15d
+; AVX512F-NEXT: movl $0, %edi
+; AVX512F-NEXT: cmoval %ecx, %edi
; AVX512F-NEXT: vmovshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vucomiss %xmm2, %xmm3
-; AVX512F-NEXT: movl $0, %ebx
-; AVX512F-NEXT: cmovpl %ecx, %ebx
-; AVX512F-NEXT: movl $0, %r14d
-; AVX512F-NEXT: cmoval %ecx, %r14d
+; AVX512F-NEXT: movl $65535, %r14d # imm = 0xFFFF
+; AVX512F-NEXT: cmovnel %r8d, %r14d
+; AVX512F-NEXT: cmovpl %r8d, %r14d
+; AVX512F-NEXT: movl $0, %r9d
+; AVX512F-NEXT: cmovpl %ecx, %r9d
+; AVX512F-NEXT: movl $0, %edx
+; AVX512F-NEXT: cmoval %ecx, %edx
; AVX512F-NEXT: vpsrld $16, %xmm1, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vpsrld $16, %xmm0, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vucomiss %xmm2, %xmm3
-; AVX512F-NEXT: movl $0, %r15d
-; AVX512F-NEXT: cmovpl %ecx, %r15d
-; AVX512F-NEXT: movl $0, %r12d
-; AVX512F-NEXT: cmoval %ecx, %r12d
+; AVX512F-NEXT: movl $65535, %r13d # imm = 0xFFFF
+; AVX512F-NEXT: cmovnel %r8d, %r13d
+; AVX512F-NEXT: cmovpl %r8d, %r13d
+; AVX512F-NEXT: movl $0, %esi
+; AVX512F-NEXT: cmovpl %ecx, %esi
+; AVX512F-NEXT: movl $0, %eax
+; AVX512F-NEXT: cmoval %ecx, %eax
; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm3
; AVX512F-NEXT: vucomiss %xmm2, %xmm3
-; AVX512F-NEXT: movl $0, %r13d
-; AVX512F-NEXT: cmoval %ecx, %r13d
-; AVX512F-NEXT: vmovd %r13d, %xmm2
-; AVX512F-NEXT: vpinsrw $1, %r12d, %xmm2, %xmm2
-; AVX512F-NEXT: vpinsrw $2, %r14d, %xmm2, %xmm2
-; AVX512F-NEXT: vpinsrw $3, %ebp, %xmm2, %xmm2
-; AVX512F-NEXT: vpinsrw $4, %r11d, %xmm2, %xmm2
-; AVX512F-NEXT: vpinsrw $5, %r9d, %xmm2, %xmm2
-; AVX512F-NEXT: vpinsrw $6, %edi, %xmm2, %xmm2
-; AVX512F-NEXT: movl $0, %edi
-; AVX512F-NEXT: cmovpl %ecx, %edi
+; AVX512F-NEXT: movl $0, %ebp
+; AVX512F-NEXT: cmoval %ecx, %ebp
+; AVX512F-NEXT: vmovd %ebp, %xmm2
+; AVX512F-NEXT: vpinsrw $1, %eax, %xmm2, %xmm2
+; AVX512F-NEXT: vpinsrw $2, %edx, %xmm2, %xmm2
+; AVX512F-NEXT: vpinsrw $3, %edi, %xmm2, %xmm2
+; AVX512F-NEXT: vpinsrw $4, %r12d, %xmm2, %xmm2
+; AVX512F-NEXT: vpinsrw $5, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 4-byte Folded Reload
+; AVX512F-NEXT: vpinsrw $6, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 4-byte Folded Reload
+; AVX512F-NEXT: movl $65535, %eax # imm = 0xFFFF
+; AVX512F-NEXT: cmovnel %r8d, %eax
+; AVX512F-NEXT: cmovpl %r8d, %eax
+; AVX512F-NEXT: movl $0, %edx
+; AVX512F-NEXT: cmovpl %ecx, %edx
; AVX512F-NEXT: vpsrldq {{.*#+}} xmm3 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vpsrldq {{.*#+}} xmm4 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512F-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX512F-NEXT: vucomiss %xmm3, %xmm4
-; AVX512F-NEXT: movl $0, %r9d
-; AVX512F-NEXT: cmoval %ecx, %r9d
-; AVX512F-NEXT: vpinsrw $7, %r9d, %xmm2, %xmm2
-; AVX512F-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm2
-; AVX512F-NEXT: vmovd %edi, %xmm3
-; AVX512F-NEXT: vpinsrw $1, %r15d, %xmm3, %xmm3
-; AVX512F-NEXT: vpinsrw $2, %ebx, %xmm3, %xmm3
-; AVX512F-NEXT: vpinsrw $3, %r10d, %xmm3, %xmm3
-; AVX512F-NEXT: vpinsrw $4, %r8d, %xmm3, %xmm3
-; AVX512F-NEXT: vpinsrw $5, %esi, %xmm3, %xmm3
-; AVX512F-NEXT: vpinsrw $6, %edx, %xmm3, %xmm3
+; AVX512F-NEXT: movl $0, %edi
+; AVX512F-NEXT: cmoval %ecx, %edi
+; AVX512F-NEXT: vpinsrw $7, %edi, %xmm2, %xmm2
+; AVX512F-NEXT: vmovd %edx, %xmm3
+; AVX512F-NEXT: vpinsrw $1, %esi, %xmm3, %xmm3
+; AVX512F-NEXT: vpinsrw $2, %r9d, %xmm3, %xmm3
+; AVX512F-NEXT: vpinsrw $3, %r15d, %xmm3, %xmm3
+; AVX512F-NEXT: vpinsrw $4, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3, %xmm3 # 4-byte Folded Reload
+; AVX512F-NEXT: vpinsrw $5, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3, %xmm3 # 4-byte Folded Reload
+; AVX512F-NEXT: vpinsrw $6, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3, %xmm3 # 4-byte Folded Reload
; AVX512F-NEXT: movl $0, %edx
; AVX512F-NEXT: cmovpl %ecx, %edx
; AVX512F-NEXT: vpinsrw $7, %edx, %xmm3, %xmm3
-; AVX512F-NEXT: vpbroadcastw {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
-; AVX512F-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2
-; AVX512F-NEXT: vpsrld $16, %xmm2, %xmm3
-; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
-; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX512F-NEXT: vucomiss %xmm4, %xmm3
-; AVX512F-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512F-NEXT: cmovnel %eax, %edx
-; AVX512F-NEXT: cmovpl %eax, %edx
-; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm3
-; AVX512F-NEXT: vucomiss %xmm4, %xmm3
-; AVX512F-NEXT: movl $65535, %esi # imm = 0xFFFF
-; AVX512F-NEXT: cmovnel %eax, %esi
-; AVX512F-NEXT: cmovpl %eax, %esi
-; AVX512F-NEXT: vmovd %esi, %xmm3
-; AVX512F-NEXT: vpinsrw $1, %edx, %xmm3, %xmm3
-; AVX512F-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
-; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512F-NEXT: vucomiss %xmm4, %xmm5
-; AVX512F-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512F-NEXT: cmovnel %eax, %edx
-; AVX512F-NEXT: cmovpl %eax, %edx
-; AVX512F-NEXT: vpinsrw $2, %edx, %xmm3, %xmm3
-; AVX512F-NEXT: vpsrlq $48, %xmm2, %xmm5
-; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512F-NEXT: vucomiss %xmm4, %xmm5
-; AVX512F-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512F-NEXT: cmovnel %eax, %edx
-; AVX512F-NEXT: cmovpl %eax, %edx
-; AVX512F-NEXT: vpinsrw $3, %edx, %xmm3, %xmm3
-; AVX512F-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[2,3,0,1]
-; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512F-NEXT: vucomiss %xmm4, %xmm5
-; AVX512F-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512F-NEXT: cmovnel %eax, %edx
-; AVX512F-NEXT: cmovpl %eax, %edx
-; AVX512F-NEXT: vpinsrw $4, %edx, %xmm3, %xmm3
-; AVX512F-NEXT: vpsrldq {{.*#+}} xmm5 = xmm2[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512F-NEXT: vucomiss %xmm4, %xmm5
-; AVX512F-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512F-NEXT: cmovnel %eax, %edx
-; AVX512F-NEXT: cmovpl %eax, %edx
-; AVX512F-NEXT: vpinsrw $5, %edx, %xmm3, %xmm3
-; AVX512F-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[3,3,3,3]
-; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512F-NEXT: vucomiss %xmm4, %xmm5
-; AVX512F-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512F-NEXT: cmovnel %eax, %edx
-; AVX512F-NEXT: cmovpl %eax, %edx
-; AVX512F-NEXT: vpinsrw $6, %edx, %xmm3, %xmm3
-; AVX512F-NEXT: vpsrldq {{.*#+}} xmm5 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512F-NEXT: vucomiss %xmm4, %xmm5
-; AVX512F-NEXT: cmovnel %eax, %ecx
-; AVX512F-NEXT: cmovpl %eax, %ecx
-; AVX512F-NEXT: vpinsrw $7, %ecx, %xmm3, %xmm3
-; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX512F-NEXT: vpcmpeqw %xmm4, %xmm0, %xmm5
-; AVX512F-NEXT: vpblendvb %xmm5, %xmm0, %xmm2, %xmm0
-; AVX512F-NEXT: vpcmpeqw %xmm4, %xmm1, %xmm4
-; AVX512F-NEXT: vpblendvb %xmm4, %xmm1, %xmm0, %xmm0
-; AVX512F-NEXT: vpblendvb %xmm3, %xmm0, %xmm2, %xmm0
+; AVX512F-NEXT: vmovd %eax, %xmm4
+; AVX512F-NEXT: vpinsrw $1, %r13d, %xmm4, %xmm4
+; AVX512F-NEXT: vpinsrw $2, %r14d, %xmm4, %xmm4
+; AVX512F-NEXT: vpinsrw $3, %r11d, %xmm4, %xmm4
+; AVX512F-NEXT: vpinsrw $4, %r10d, %xmm4, %xmm4
+; AVX512F-NEXT: vpinsrw $5, %ebx, %xmm4, %xmm4
+; AVX512F-NEXT: vpinsrw $6, {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 4-byte Folded Reload
+; AVX512F-NEXT: cmovnel %r8d, %ecx
+; AVX512F-NEXT: cmovpl %r8d, %ecx
+; AVX512F-NEXT: vpinsrw $7, %ecx, %xmm4, %xmm4
+; AVX512F-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm2
+; AVX512F-NEXT: vpbroadcastw {{.*#+}} xmm5 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512F-NEXT: vpblendvb %xmm3, %xmm5, %xmm2, %xmm2
+; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX512F-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm3
+; AVX512F-NEXT: vpblendvb %xmm3, %xmm0, %xmm1, %xmm0
+; AVX512F-NEXT: vpblendvb %xmm4, %xmm0, %xmm2, %xmm0
; AVX512F-NEXT: popq %rbx
; AVX512F-NEXT: popq %r12
; AVX512F-NEXT: popq %r13
@@ -1964,154 +1944,134 @@ define <4 x half> @test_fmaximum_v4f16(<4 x half> %x, <4 x half> %y) nounwind {
; AVX512DQ-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[3,3,3,3]
; AVX512DQ-NEXT: vcvtph2ps %xmm3, %xmm3
-; AVX512DQ-NEXT: xorl %eax, %eax
+; AVX512DQ-NEXT: xorl %r8d, %r8d
; AVX512DQ-NEXT: vucomiss %xmm2, %xmm3
; AVX512DQ-NEXT: movl $65535, %ecx # imm = 0xFFFF
-; AVX512DQ-NEXT: movl $0, %edx
-; AVX512DQ-NEXT: cmovpl %ecx, %edx
-; AVX512DQ-NEXT: movl $0, %edi
-; AVX512DQ-NEXT: cmoval %ecx, %edi
+; AVX512DQ-NEXT: movl $65535, %eax # imm = 0xFFFF
+; AVX512DQ-NEXT: cmovnel %r8d, %eax
+; AVX512DQ-NEXT: cmovpl %r8d, %eax
+; AVX512DQ-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512DQ-NEXT: movl $0, %eax
+; AVX512DQ-NEXT: cmovpl %ecx, %eax
+; AVX512DQ-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512DQ-NEXT: movl $0, %eax
+; AVX512DQ-NEXT: cmoval %ecx, %eax
+; AVX512DQ-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; AVX512DQ-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512DQ-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512DQ-NEXT: vpsrldq {{.*#+}} xmm3 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512DQ-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512DQ-NEXT: vucomiss %xmm2, %xmm3
-; AVX512DQ-NEXT: movl $0, %esi
-; AVX512DQ-NEXT: cmovpl %ecx, %esi
-; AVX512DQ-NEXT: movl $0, %r9d
-; AVX512DQ-NEXT: cmoval %ecx, %r9d
+; AVX512DQ-NEXT: movl $65535, %ebx # imm = 0xFFFF
+; AVX512DQ-NEXT: cmovnel %r8d, %ebx
+; AVX512DQ-NEXT: cmovpl %r8d, %ebx
+; AVX512DQ-NEXT: movl $0, %eax
+; AVX512DQ-NEXT: cmovpl %ecx, %eax
+; AVX512DQ-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512DQ-NEXT: movl $0, %eax
+; AVX512DQ-NEXT: cmoval %ecx, %eax
+; AVX512DQ-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; AVX512DQ-NEXT: vshufpd {{.*#+}} xmm2 = xmm1[1,0]
; AVX512DQ-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512DQ-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
; AVX512DQ-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512DQ-NEXT: vucomiss %xmm2, %xmm3
-; AVX512DQ-NEXT: movl $0, %r8d
-; AVX512DQ-NEXT: cmovpl %ecx, %r8d
-; AVX512DQ-NEXT: movl $0, %r11d
-; AVX512DQ-NEXT: cmoval %ecx, %r11d
+; AVX512DQ-NEXT: movl $65535, %r10d # imm = 0xFFFF
+; AVX512DQ-NEXT: cmovnel %r8d, %r10d
+; AVX512DQ-NEXT: cmovpl %r8d, %r10d
+; AVX512DQ-NEXT: movl $0, %eax
+; AVX512DQ-NEXT: cmovpl %ecx, %eax
+; AVX512DQ-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; AVX512DQ-NEXT: movl $0, %r12d
+; AVX512DQ-NEXT: cmoval %ecx, %r12d
; AVX512DQ-NEXT: vpsrlq $48, %xmm1, %xmm2
; AVX512DQ-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512DQ-NEXT: vpsrlq $48, %xmm0, %xmm3
; AVX512DQ-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512DQ-NEXT: vucomiss %xmm2, %xmm3
-; AVX512DQ-NEXT: movl $0, %r10d
-; AVX512DQ-NEXT: cmovpl %ecx, %r10d
-; AVX512DQ-NEXT: movl $0, %ebp
-; AVX512DQ-NEXT: cmoval %ecx, %ebp
+; AVX512DQ-NEXT: movl $65535, %r11d # imm = 0xFFFF
+; AVX512DQ-NEXT: cmovnel %r8d, %r11d
+; AVX512DQ-NEXT: cmovpl %r8d, %r11d
+; AVX512DQ-NEXT: movl $0, %r15d
+; AVX512DQ-NEXT: cmovpl %ecx, %r15d
+; AVX512DQ-NEXT: movl $0, %edi
+; AVX512DQ-NEXT: cmoval %ecx, %edi
; AVX512DQ-NEXT: vmovshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
; AVX512DQ-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512DQ-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
; AVX512DQ-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512DQ-NEXT: vucomiss %xmm2, %xmm3
-; AVX512DQ-NEXT: movl $0, %ebx
-; AVX512DQ-NEXT: cmovpl %ecx, %ebx
-; AVX512DQ-NEXT: movl $0, %r14d
-; AVX512DQ-NEXT: cmoval %ecx, %r14d
+; AVX512DQ-NEXT: movl $65535, %r14d # imm = 0xFFFF
+; AVX512DQ-NEXT: cmovnel %r8d, %r14d
+; AVX512DQ-NEXT: cmovpl %r8d, %r14d
+; AVX512DQ-NEXT: movl $0, %r9d
+; AVX512DQ-NEXT: cmovpl %ecx, %r9d
+; AVX512DQ-NEXT: movl $0, %edx
+; AVX512DQ-NEXT: cmoval %ecx, %edx
; AVX512DQ-NEXT: vpsrld $16, %xmm1, %xmm2
; AVX512DQ-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512DQ-NEXT: vpsrld $16, %xmm0, %xmm3
; AVX512DQ-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512DQ-NEXT: vucomiss %xmm2, %xmm3
-; AVX512DQ-NEXT: movl $0, %r15d
-; AVX512DQ-NEXT: cmovpl %ecx, %r15d
-; AVX512DQ-NEXT: movl $0, %r12d
-; AVX512DQ-NEXT: cmoval %ecx, %r12d
+; AVX512DQ-NEXT: movl $65535, %r13d # imm = 0xFFFF
+; AVX512DQ-NEXT: cmovnel %r8d, %r13d
+; AVX512DQ-NEXT: cmovpl %r8d, %r13d
+; AVX512DQ-NEXT: movl $0, %esi
+; AVX512DQ-NEXT: cmovpl %ecx, %esi
+; AVX512DQ-NEXT: movl $0, %eax
+; AVX512DQ-NEXT: cmoval %ecx, %eax
; AVX512DQ-NEXT: vcvtph2ps %xmm1, %xmm2
; AVX512DQ-NEXT: vcvtph2ps %xmm0, %xmm3
; AVX512DQ-NEXT: vucomiss %xmm2, %xmm3
-; AVX512DQ-NEXT: movl $0, %r13d
-; AVX512DQ-NEXT: cmoval %ecx, %r13d
-; AVX512DQ-NEXT: vmovd %r13d, %xmm2
-; AVX512DQ-NEXT: vpinsrw $1, %r12d, %xmm2, %xmm2
-; AVX512DQ-NEXT: vpinsrw $2, %r14d, %xmm2, %xmm2
-; AVX512DQ-NEXT: vpinsrw $3, %ebp, %xmm2, %xmm2
-; AVX512DQ-NEXT: vpinsrw $4, %r11d, %xmm2, %xmm2
-; AVX512DQ-NEXT: vpinsrw $5, %r9d, %xmm2, %xmm2
-; AVX512DQ-NEXT: vpinsrw $6, %edi, %xmm2, %xmm2
-; AVX512DQ-NEXT: movl $0, %edi
-; AVX512DQ-NEXT: cmovpl %ecx, %edi
+; AVX512DQ-NEXT: movl $0, %ebp
+; AVX512DQ-NEXT: cmoval %ecx, %ebp
+; AVX512DQ-NEXT: vmovd %ebp, %xmm2
+; AVX512DQ-NEXT: vpinsrw $1, %eax, %xmm2, %xmm2
+; AVX512DQ-NEXT: vpinsrw $2, %edx, %xmm2, %xmm2
+; AVX512DQ-NEXT: vpinsrw $3, %edi, %xmm2, %xmm2
+; AVX512DQ-NEXT: vpinsrw $4, %r12d, %xmm2, %xmm2
+; AVX512DQ-NEXT: vpinsrw $5, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 4-byte Folded Reload
+; AVX512DQ-NEXT: vpinsrw $6, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 4-byte Folded Reload
+; AVX512DQ-NEXT: movl $65535, %eax # imm = 0xFFFF
+; AVX512DQ-NEXT: cmovnel %r8d, %eax
+; AVX512DQ-NEXT: cmovpl %r8d, %eax
+; AVX512DQ-NEXT: movl $0, %edx
+; AVX512DQ-NEXT: cmovpl %ecx, %edx
; AVX512DQ-NEXT: vpsrldq {{.*#+}} xmm3 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512DQ-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512DQ-NEXT: vpsrldq {{.*#+}} xmm4 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512DQ-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX512DQ-NEXT: vucomiss %xmm3, %xmm4
-; AVX512DQ-NEXT: movl $0, %r9d
-; AVX512DQ-NEXT: cmoval %ecx, %r9d
-; AVX512DQ-NEXT: vpinsrw $7, %r9d, %xmm2, %xmm2
-; AVX512DQ-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm2
-; AVX512DQ-NEXT: vmovd %edi, %xmm3
-; AVX512DQ-NEXT: vpinsrw $1, %r15d, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpinsrw $2, %ebx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpinsrw $3, %r10d, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpinsrw $4, %r8d, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpinsrw $5, %esi, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpinsrw $6, %edx, %xmm3, %xmm3
+; AVX512DQ-NEXT: movl $0, %edi
+; AVX512DQ-NEXT: cmoval %ecx, %edi
+; AVX512DQ-NEXT: vpinsrw $7, %edi, %xmm2, %xmm2
+; AVX512DQ-NEXT: vmovd %edx, %xmm3
+; AVX512DQ-NEXT: vpinsrw $1, %esi, %xmm3, %xmm3
+; AVX512DQ-NEXT: vpinsrw $2, %r9d, %xmm3, %xmm3
+; AVX512DQ-NEXT: vpinsrw $3, %r15d, %xmm3, %xmm3
+; AVX512DQ-NEXT: vpinsrw $4, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3, %xmm3 # 4-byte Folded Reload
+; AVX512DQ-NEXT: vpinsrw $5, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3, %xmm3 # 4-byte Folded Reload
+; AVX512DQ-NEXT: vpinsrw $6, {{[-0-9]+}}(%r{{[sb]}}p), %xmm3, %xmm3 # 4-byte Folded Reload
; AVX512DQ-NEXT: movl $0, %edx
; AVX512DQ-NEXT: cmovpl %ecx, %edx
; AVX512DQ-NEXT: vpinsrw $7, %edx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpbroadcastw {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
-; AVX512DQ-NEXT: vpblendvb %xmm3, %xmm4, %xmm2, %xmm2
-; AVX512DQ-NEXT: vpsrld $16, %xmm2, %xmm3
-; AVX512DQ-NEXT: vcvtph2ps %xmm3, %xmm3
-; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX512DQ-NEXT: vucomiss %xmm4, %xmm3
-; AVX512DQ-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512DQ-NEXT: cmovnel %eax, %edx
-; AVX512DQ-NEXT: cmovpl %eax, %edx
-; AVX512DQ-NEXT: vcvtph2ps %xmm2, %xmm3
-; AVX512DQ-NEXT: vucomiss %xmm4, %xmm3
-; AVX512DQ-NEXT: movl $65535, %esi # imm = 0xFFFF
-; AVX512DQ-NEXT: cmovnel %eax, %esi
-; AVX512DQ-NEXT: cmovpl %eax, %esi
-; AVX512DQ-NEXT: vmovd %esi, %xmm3
-; AVX512DQ-NEXT: vpinsrw $1, %edx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
-; AVX512DQ-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512DQ-NEXT: vucomiss %xmm4, %xmm5
-; AVX512DQ-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512DQ-NEXT: cmovnel %eax, %edx
-; AVX512DQ-NEXT: cmovpl %eax, %edx
-; AVX512DQ-NEXT: vpinsrw $2, %edx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpsrlq $48, %xmm2, %xmm5
-; AVX512DQ-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512DQ-NEXT: vucomiss %xmm4, %xmm5
-; AVX512DQ-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512DQ-NEXT: cmovnel %eax, %edx
-; AVX512DQ-NEXT: cmovpl %eax, %edx
-; AVX512DQ-NEXT: vpinsrw $3, %edx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[2,3,0,1]
-; AVX512DQ-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512DQ-NEXT: vucomiss %xmm4, %xmm5
-; AVX512DQ-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512DQ-NEXT: cmovnel %eax, %edx
-; AVX512DQ-NEXT: cmovpl %eax, %edx
-; AVX512DQ-NEXT: vpinsrw $4, %edx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpsrldq {{.*#+}} xmm5 = xmm2[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX512DQ-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512DQ-NEXT: vucomiss %xmm4, %xmm5
-; AVX512DQ-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512DQ-NEXT: cmovnel %eax, %edx
-; AVX512DQ-NEXT: cmovpl %eax, %edx
-; AVX512DQ-NEXT: vpinsrw $5, %edx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[3,3,3,3]
-; AVX512DQ-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512DQ-NEXT: vucomiss %xmm4, %xmm5
-; AVX512DQ-NEXT: movl $65535, %edx # imm = 0xFFFF
-; AVX512DQ-NEXT: cmovnel %eax, %edx
-; AVX512DQ-NEXT: cmovpl %eax, %edx
-; AVX512DQ-NEXT: vpinsrw $6, %edx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpsrldq {{.*#+}} xmm5 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; AVX512DQ-NEXT: vcvtph2ps %xmm5, %xmm5
-; AVX512DQ-NEXT: vucomiss %xmm4, %xmm5
-; AVX512DQ-NEXT: cmovnel %eax, %ecx
-; AVX512DQ-NEXT: cmovpl %eax, %ecx
-; AVX512DQ-NEXT: vpinsrw $7, %ecx, %xmm3, %xmm3
-; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
-; AVX512DQ-NEXT: vpcmpeqw %xmm4, %xmm0, %xmm5
-; AVX512DQ-NEXT: vpblendvb %xmm5, %xmm0, %xmm2, %xmm0
-; AVX512DQ-NEXT: vpcmpeqw %xmm4, %xmm1, %xmm4
-; AVX512DQ-NEXT: vpblendvb %xmm4, %xmm1, %xmm0, %xmm0
-; AVX512DQ-NEXT: vpblendvb %xmm3, %xmm0, %xmm2, %xmm0
+; AVX512DQ-NEXT: vmovd %eax, %xmm4
+; AVX512DQ-NEXT: vpinsrw $1, %r13d, %xmm4, %xmm4
+; AVX512DQ-NEXT: vpinsrw $2, %r14d, %xmm4, %xmm4
+; AVX512DQ-NEXT: vpinsrw $3, %r11d, %xmm4, %xmm4
+; AVX512DQ-NEXT: vpinsrw $4, %r10d, %xmm4, %xmm4
+; AVX512DQ-NEXT: vpinsrw $5, %ebx, %xmm4, %xmm4
+; AVX512DQ-NEXT: vpinsrw $6, {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 4-byte Folded Reload
+; AVX512DQ-NEXT: cmovnel %r8d, %ecx
+; AVX512DQ-NEXT: cmovpl %r8d, %ecx
+; AVX512DQ-NEXT: vpinsrw $7, %ecx, %xmm4, %xmm4
+; AVX512DQ-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm2
+; AVX512DQ-NEXT: vpbroadcastw {{.*#+}} xmm5 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; AVX512DQ-NEXT: vpblendvb %xmm3, %xmm5, %xmm2, %xmm2
+; AVX512DQ-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX512DQ-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm3
+; AVX512DQ-NEXT: vpblendvb %xmm3, %xmm0, %xmm1, %xmm0
+; AVX512DQ-NEXT: vpblendvb %xmm4, %xmm0, %xmm2, %xmm0
; AVX512DQ-NEXT: popq %rbx
; AVX512DQ-NEXT: popq %r12
; AVX512DQ-NEXT: popq %r13
@@ -2122,22 +2082,17 @@ define <4 x half> @test_fmaximum_v4f16(<4 x half> %x, <4 x half> %y) nounwind {
;
; AVX512BF16-LABEL: test_fmaximum_v4f16:
; AVX512BF16: # %bb.0:
+; AVX512BF16-NEXT: vptestnmw %xmm0, %xmm0, %k1
+; AVX512BF16-NEXT: vpblendmw %xmm0, %xmm1, %xmm2 {%k1}
; AVX512BF16-NEXT: vcvtph2ps %xmm0, %ymm3
; AVX512BF16-NEXT: vcvtph2ps %xmm1, %ymm4
; AVX512BF16-NEXT: vcmpltps %ymm3, %ymm4, %k1
-; AVX512BF16-NEXT: vpblendmw %xmm0, %xmm1, %xmm2 {%k1}
+; AVX512BF16-NEXT: vpblendmw %xmm0, %xmm1, %xmm0 {%k1}
; AVX512BF16-NEXT: vcmpunordps %ymm4, %ymm3, %k1
-; AVX512BF16-NEXT: vpbroadcastw {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
-; AVX512BF16-NEXT: vmovdqu16 %xmm3, %xmm2 {%k1}
-; AVX512BF16-NEXT: vptestnmw %xmm0, %xmm0, %k1
-; AVX512BF16-NEXT: vpblendmw %xmm0, %xmm2, %xmm0 {%k1}
-; AVX512BF16-NEXT: vptestnmw %xmm1, %xmm1, %k1
+; AVX512BF16-NEXT: vpbroadcastw {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
; AVX512BF16-NEXT: vmovdqu16 %xmm1, %xmm0 {%k1}
-; AVX512BF16-NEXT: vcvtph2ps %xmm2, %ymm1
-; AVX512BF16-NEXT: vpxor %xmm3, %xmm3, %xmm3
-; AVX512BF16-NEXT: vcmpeqps %ymm3, %ymm1, %k1
-; AVX512BF16-NEXT: vmovdqu16 %xmm0, %xmm2 {%k1}
-; AVX512BF16-NEXT: vmovdqa %xmm2, %xmm0
+; AVX512BF16-NEXT: vcmpeqps %ymm4, %ymm3, %k1
+; AVX512BF16-NEXT: vmovdqu16 %xmm2, %xmm0 {%k1}
; AVX512BF16-NEXT: vzeroupper
; AVX512BF16-NEXT: retq
;
@@ -2813,24 +2768,18 @@ define <4 x bfloat> @test_fmaximum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
;
; AVX512BF16-LABEL: test_fmaximum_v4bf16:
; AVX512BF16: # %bb.0:
-; AVX512BF16-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX512BF16-NEXT: vpslld $16, %ymm2, %ymm3
-; AVX512BF16-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
-; AVX512BF16-NEXT: vpslld $16, %ymm2, %ymm4
-; AVX512BF16-NEXT: vcmpltps %ymm3, %ymm4, %k1
+; AVX512BF16-NEXT: vptestnmw %xmm0, %xmm0, %k1
; AVX512BF16-NEXT: vpblendmw %xmm0, %xmm1, %xmm2 {%k1}
+; AVX512BF16-NEXT: vpmovzxwd {{.*#+}} ymm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX512BF16-NEXT: vpslld $16, %ymm3, %ymm3
+; AVX512BF16-NEXT: vpmovzxwd {{.*#+}} ymm4 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX512BF16-NEXT: vpslld $16, %ymm4, %ymm4
+; AVX512BF16-NEXT: vcmpltps %ymm3, %ymm4, %k1
+; AVX512BF16-NEXT: vpblendmw %xmm0, %xmm1, %xmm0 {%k1}
; AVX512BF16-NEXT: vcmpunordps %ymm4, %ymm3, %k1
-; AVX512BF16-NEXT: vmovdqu16 {{.*#+}} xmm2 {%k1} = [32704,32704,32704,32704,32704,32704,32704,32704]
-; AVX512BF16-NEXT: vptestnmw %xmm0, %xmm0, %k1
-; AVX512BF16-NEXT: vpblendmw %xmm0, %xmm2, %xmm0 {%k1}
-; AVX512BF16-NEXT: vptestnmw %xmm1, %xmm1, %k1
-; AVX512BF16-NEXT: vmovdqu16 %xmm1, %xmm0 {%k1}
-; AVX512BF16-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
-; AVX512BF16-NEXT: vpslld $16, %ymm1, %ymm1
-; AVX512BF16-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; AVX512BF16-NEXT: vcmpeqps %ymm3, %ymm1, %k1
-; AVX512BF16-NEXT: vmovdqu16 %xmm0, %xmm2 {%k1}
-; AVX512BF16-NEXT: vmovdqa %xmm2, %xmm0
+; AVX512BF16-NEXT: vmovdqu16 {{.*#+}} xmm0 {%k1} = [32704,32704,32704,32704,32704,32704,32704,32704]
+; AVX512BF16-NEXT: vcmpeqps %ymm4, %ymm3, %k1
+; AVX512BF16-NEXT: vmovdqu16 %xmm2, %xmm0 {%k1}
; AVX512BF16-NEXT: vzeroupper
; AVX512BF16-NEXT: retq
;
@@ -3356,4 +3305,169 @@ define float @test_fminimum_daz(float %x) #0 {
ret float %1
}
+define fp128 @maximum_fp128(fp128 %x, fp128 %y) nounwind {
+; SSE2-LABEL: maximum_fp128:
+; SSE2: # %bb.0:
+; SSE2-NEXT: subq $72, %rsp
+; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE2-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
+; SSE2-NEXT: callq __trunctfsf2 at PLT
+; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE2-NEXT: movd %xmm0, %eax
+; SSE2-NEXT: testl %eax, %eax
+; SSE2-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE2-NEXT: je .LBB45_2
+; SSE2-NEXT: # %bb.1:
+; SSE2-NEXT: movaps %xmm1, %xmm0
+; SSE2-NEXT: .LBB45_2:
+; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE2-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE2-NEXT: callq __gttf2 at PLT
+; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE2-NEXT: testl %eax, %eax
+; SSE2-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE2-NEXT: jg .LBB45_4
+; SSE2-NEXT: # %bb.3:
+; SSE2-NEXT: movaps %xmm1, %xmm0
+; SSE2-NEXT: .LBB45_4:
+; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE2-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE2-NEXT: callq __unordtf2 at PLT
+; SSE2-NEXT: testl %eax, %eax
+; SSE2-NEXT: je .LBB45_6
+; SSE2-NEXT: # %bb.5:
+; SSE2-NEXT: movaps {{.*#+}} xmm0 = [NaN]
+; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE2-NEXT: .LBB45_6:
+; SSE2-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE2-NEXT: callq __eqtf2 at PLT
+; SSE2-NEXT: testl %eax, %eax
+; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE2-NEXT: je .LBB45_8
+; SSE2-NEXT: # %bb.7:
+; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; SSE2-NEXT: .LBB45_8:
+; SSE2-NEXT: addq $72, %rsp
+; SSE2-NEXT: retq
+;
+; AVX-LABEL: maximum_fp128:
+; AVX: # %bb.0:
+; AVX-NEXT: subq $72, %rsp
+; AVX-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; AVX-NEXT: callq __trunctfsf2 at PLT
+; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; AVX-NEXT: vmovd %xmm0, %eax
+; AVX-NEXT: testl %eax, %eax
+; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX-NEXT: je .LBB45_2
+; AVX-NEXT: # %bb.1:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: .LBB45_2:
+; AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; AVX-NEXT: callq __gttf2 at PLT
+; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; AVX-NEXT: testl %eax, %eax
+; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX-NEXT: jg .LBB45_4
+; AVX-NEXT: # %bb.3:
+; AVX-NEXT: vmovaps %xmm1, %xmm0
+; AVX-NEXT: .LBB45_4:
+; AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX-NEXT: callq __unordtf2 at PLT
+; AVX-NEXT: testl %eax, %eax
+; AVX-NEXT: je .LBB45_6
+; AVX-NEXT: # %bb.5:
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [NaN]
+; AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX-NEXT: .LBB45_6:
+; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; AVX-NEXT: callq __eqtf2 at PLT
+; AVX-NEXT: testl %eax, %eax
+; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX-NEXT: je .LBB45_8
+; AVX-NEXT: # %bb.7:
+; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX-NEXT: .LBB45_8:
+; AVX-NEXT: addq $72, %rsp
+; AVX-NEXT: retq
+;
+; AVX10_2-LABEL: maximum_fp128:
+; AVX10_2: # %bb.0:
+; AVX10_2-NEXT: subq $72, %rsp
+; AVX10_2-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX10_2-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
+; AVX10_2-NEXT: callq __trunctfsf2 at PLT
+; AVX10_2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; AVX10_2-NEXT: vmovd %xmm0, %eax
+; AVX10_2-NEXT: testl %eax, %eax
+; AVX10_2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX10_2-NEXT: je .LBB45_2
+; AVX10_2-NEXT: # %bb.1:
+; AVX10_2-NEXT: vmovaps %xmm1, %xmm0
+; AVX10_2-NEXT: .LBB45_2:
+; AVX10_2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX10_2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX10_2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; AVX10_2-NEXT: callq __gttf2 at PLT
+; AVX10_2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; AVX10_2-NEXT: testl %eax, %eax
+; AVX10_2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX10_2-NEXT: jg .LBB45_4
+; AVX10_2-NEXT: # %bb.3:
+; AVX10_2-NEXT: vmovaps %xmm1, %xmm0
+; AVX10_2-NEXT: .LBB45_4:
+; AVX10_2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX10_2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX10_2-NEXT: callq __unordtf2 at PLT
+; AVX10_2-NEXT: testl %eax, %eax
+; AVX10_2-NEXT: je .LBB45_6
+; AVX10_2-NEXT: # %bb.5:
+; AVX10_2-NEXT: vmovaps {{.*#+}} xmm0 = [NaN]
+; AVX10_2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; AVX10_2-NEXT: .LBB45_6:
+; AVX10_2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX10_2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; AVX10_2-NEXT: callq __eqtf2 at PLT
+; AVX10_2-NEXT: testl %eax, %eax
+; AVX10_2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX10_2-NEXT: je .LBB45_8
+; AVX10_2-NEXT: # %bb.7:
+; AVX10_2-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX10_2-NEXT: .LBB45_8:
+; AVX10_2-NEXT: addq $72, %rsp
+; AVX10_2-NEXT: retq
+;
+; X86-LABEL: maximum_fp128:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: movl %esp, %ebp
+; X86-NEXT: pushl %esi
+; X86-NEXT: andl $-16, %esp
+; X86-NEXT: subl $80, %esp
+; X86-NEXT: movl 8(%ebp), %esi
+; X86-NEXT: vmovups 24(%ebp), %ymm0
+; X86-NEXT: vmovups %ymm0, {{[0-9]+}}(%esp)
+; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %eax, (%esp)
+; X86-NEXT: vzeroupper
+; X86-NEXT: calll fmaximuml
+; X86-NEXT: subl $4, %esp
+; X86-NEXT: vmovaps {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT: vmovaps %xmm0, (%esi)
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: leal -4(%ebp), %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %res = call fp128 @llvm.maximum.f128(fp128 %x, fp128 %y)
+ ret fp128 %res
+}
+
attributes #0 = { nounwind denormal_fpenv(preservesign) }
>From 9c97d2d36f3f37bc2c5caaa843308f9eb4f9a8d8 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Mon, 29 Jun 2026 11:18:32 +0200
Subject: [PATCH 2/2] pass by const ref
---
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a4df2e0ddd97e..00153ef66cf2c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10124,7 +10124,7 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
static SDValue isSpecificZeroAfterMaybeRounding(SelectionDAG &DAG,
const TargetLowering &TLI,
- SDLoc DL, SDValue Val,
+ const SDLoc &DL, SDValue Val,
FPClassTest FPClass) {
EVT VT = Val.getValueType();
EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
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