[llvm] [RISCV] Don't run insertVSETMTK if +xsfmmbase isn't present (PR #206426)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Luke Lau (lukel97)

<details>
<summary>Changes</summary>

I'm not familiar with xsfmmbase but IIUC we don't need to run those passes if the extension isn't present, so this saves some compile time when the feature isn't enabled.

Some tests were missing the sifive-O0-ATM-ATK.ll extension so I've added the feature, which caused one of the vsetvlis to turn into a sf.vsettnt


---
Full diff: https://github.com/llvm/llvm-project/pull/206426.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp (+5-3) 
- (modified) llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index f964979baa412..0455c28774a8e 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1094,9 +1094,11 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
   for (MachineBasicBlock &MBB : MF)
     insertReadVL(MBB);
 
-  for (MachineBasicBlock &MBB : MF) {
-    insertVSETMTK(MBB, VSETTM);
-    insertVSETMTK(MBB, VSETTK);
+  if (ST->hasVendorXSfmmbase()) {
+    for (MachineBasicBlock &MBB : MF) {
+      insertVSETMTK(MBB, VSETTM);
+      insertVSETMTK(MBB, VSETTK);
+    }
   }
 
   BlockInfo.clear();
diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll b/llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll
index 1bd966ef7e481..2fe64c71fe5f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -O0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV64
+; RUN: llc -mtriple=riscv64 -mattr=+v,+xsfmmbase -O0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV64
 
 define void @matmul() {
 ; CHECK-RV64-LABEL: matmul:
 ; CHECK-RV64:       # %bb.0: # %entry
 ; CHECK-RV64-NEXT:    li a0, 0
-; CHECK-RV64-NEXT:    vsetvli zero, a0, 512
+; CHECK-RV64-NEXT:    sf.vsettnt zero, a0, e8, w1
 ; CHECK-RV64-NEXT:    sf.vsettm zero, a0
 ; CHECK-RV64-NEXT:    sf.vtzero.t mt0
 ; CHECK-RV64-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir b/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir
index 3faf5f51b6b84..202b051114649 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v \
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v,+xsfmmbase \
 # RUN:     -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s
 
 --- |

``````````

</details>


https://github.com/llvm/llvm-project/pull/206426