[llvm] [AArch64] Remove FeatureMaxInterleaveFactor4 from neoverse-v3ae (PR #190166)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 29 00:56:01 PDT 2026
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/190166
>From 49eeb8af62ce7a2515f5bc0f8fa5bf9fbb4b61c7 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 29 Jun 2026 08:55:45 +0100
Subject: [PATCH] [AArch64] Remove FeatureMaxInterleaveFactor4 from
neoverse-v3ae
This CPU has 2 vector pipelines, and even though unrolling can sometimes be
beneficial on its own, we usually set the interleaving factor to the number of
vector pipelines. Remove FeatureMaxInterleaveFactor4 so that the default of 2
is used.
---
llvm/lib/Target/AArch64/AArch64Processors.td | 5 ++---
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 +
.../LoopVectorize/AArch64/interleaving-load-store.ll | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index dfa2bd46c8e56..8c8dc2ac80309 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -602,7 +602,7 @@ def TuneNeoverseV3 : SubtargetFeature<"neoversev3", "ARMProcFamily", "NeoverseV3
FeaturePredictableSelectIsExpensive,
FeatureMaxInterleaveFactor4]>;
-def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "NeoverseV3",
+def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "NeoverseV3AE",
"Neoverse V3AE ARM processors", [
FeatureFuseAES,
FeatureALULSLFast,
@@ -613,8 +613,7 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover
FeatureEnableSelectOptimize,
FeatureUseFixedOverScalableIfEqualCost,
FeatureAvoidLDAPUR,
- FeaturePredictableSelectIsExpensive,
- FeatureMaxInterleaveFactor4]>;
+ FeaturePredictableSelectIsExpensive]>;
def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
"Qualcomm Saphira processors", [
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index f4b0af0333f4e..9ee3d0cc9e0ea 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -261,6 +261,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
[[fallthrough]];
case NeoverseN2:
case NeoverseN3:
+ case NeoverseV3AE:
PrefFunctionAlignment = Align(16);
PrefLoopAlignment = Align(32);
MaxBytesForLoopAlignment = 16;
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
index d9c3ae2e3b533..a371f3e4fe262 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
@@ -11,7 +11,7 @@
; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a18 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v2 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
-; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3ae -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
+; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3ae -S %s | FileCheck --check-prefix=INTERLEAVE-2 %s
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=exynos-m5 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=cortex-x1 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=cortex-x2 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s
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