[llvm] [VPlan] Fix miscompile when widening induction with loop-variant step (PR #206010)

[Florian Hahn via llvm-commits]

https://github.com/fhahn commented:

@clarence1121 please make sure to carefully read the message posted earlier: https://github.com/llvm/llvm-project/pull/206010#issuecomment-4808147981

Note in particular the AI policy. It looks like you used Claude for your changes. This should be made clear in the PR description.

The PR description/comments should also be written by yourself, not AI.

https://github.com/llvm/llvm-project/pull/206010