[llvm] [RISCV][NFC] Use true/false for boolean fields in RISCV.td (PR #206399)

Mark Zhuang via llvm-commits llvm-commits at lists.llvm.org
Sun Jun 28 21:46:18 PDT 2026


https://github.com/zqb-all created https://github.com/llvm/llvm-project/pull/206399

None

>From 1efbb6ede73aa0b260a46332716087dffdb2d60d Mon Sep 17 00:00:00 2001
From: Mark Zhuang <mark.zhuang at spacemit.com>
Date: Mon, 29 Jun 2026 12:44:37 +0800
Subject: [PATCH] [RISCV][NFC] Use true/false for boolean fields in RISCV.td

---
 llvm/lib/Target/RISCV/RISCV.td | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 7a4d8a6fd55d5..9de000eb1772a 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -85,12 +85,12 @@ include "RISCVPfmCounters.td"
 //===----------------------------------------------------------------------===//
 
 def RISCVInstrInfo : InstrInfo {
-  let guessInstructionProperties = 0;
+  let guessInstructionProperties = false;
 }
 
 def RISCVAsmParser : AsmParser {
-  let ShouldEmitMatchRegisterAltName = 1;
-  let AllowDuplicateRegisterNames = 1;
+  let ShouldEmitMatchRegisterAltName = true;
+  let AllowDuplicateRegisterNames = true;
 }
 
 def RISCVAsmWriter : AsmWriter {
@@ -103,5 +103,5 @@ def RISCV : Target {
   let InstructionSet = RISCVInstrInfo;
   let AssemblyParsers = [RISCVAsmParser];
   let AssemblyWriters = [RISCVAsmWriter];
-  let AllowRegisterRenaming = 1;
+  let AllowRegisterRenaming = true;
 }



More information about the llvm-commits mailing list