[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[Jonathan Thackray via llvm-commits]

jthackray wrote:

> @jthackray I think we can implement the ZPR3_3b as we implemented ZPRMul2_Lo and ZPRMul2_Hi in this PR:

Thanks, your suggestion works. Code updated.

https://github.com/llvm/llvm-project/pull/200751