[llvm] [AArch64][llvm] Implement HINT instructions as aliases (NFCI) (PR #206383)
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Sun Jun 28 18:02:37 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
<details>
<summary>Changes</summary>
Implement some `HINT`-space encodings as aliases of `HINT`
instead of dedicated instructions. Re-implement these isns:
* bti
* psb
* stshh
* stcph
* shuh
* tsb
Parse aliases explicitly in `AArch64AsmParser::parseHintAlias()` as they
have custom operands. Remove the (now unused) `PSB`, `BTI`, `CMH`, `PHint`
and `TSB` tablegen defs, operand classes, parser hooks and printer helpers.
Also, tighten the BTI check in the parser. The old bitmask matched non-BTI
`HINT` immediates such as `shuh/stcph`; use an exact BTI HINT encoding
check instead (`isHintSpaceBTI()`)
Add additional MC coverage for HINT aliases. The only intended functional
change is a diagnostic tweak for invalid `tsb csync` operands, which now
uses the common `HINT` alias error message codepath:
```
-//CHECK-ERROR: error: 'csync' operand expected
+//CHECK-ERROR: error: invalid operand for instruction
```
Apart from this, no other test code was modified; only new tests added.
---
Patch is 52.07 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206383.diff
19 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (-103)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+21-24)
- (modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (-152)
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+184-281)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp (+3-52)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h (-11)
- (modified) llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp (-35)
- (modified) llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h (+6-51)
- (modified) llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s (+3)
- (modified) llvm/test/MC/AArch64/armv8.4a-trace-error.s (+3-3)
- (modified) llvm/test/MC/AArch64/armv8.4a-trace.s (+2)
- (modified) llvm/test/MC/AArch64/armv8.5a-bti.s (+3)
- (added) llvm/test/MC/AArch64/armv9.6a-pcdphint-diagnostics.s (+19)
- (modified) llvm/test/MC/AArch64/armv9.6a-pcdphint.s (+9-1)
- (modified) llvm/test/MC/AArch64/armv9.7a-memsys.s (+13-1)
- (modified) llvm/test/MC/AArch64/basic-a64-instructions.s (+13-1)
- (modified) llvm/test/MC/AArch64/ras-extension.s (+3)
- (modified) llvm/test/MC/AArch64/speculation-barriers.s (+2)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 156c12c5ab8dd..6468f047532a5 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -3202,8 +3202,7 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
if (CurrentPatchableFunctionEntrySym &&
CurrentPatchableFunctionEntrySym == CurrentFnBegin &&
MI == &MF->front().front()) {
- int64_t Imm = MI->getOperand(0).getImm();
- if ((Imm & 32) && (Imm & 6)) {
+ if (AArch64BTIHint::isHintSpaceBTI(MI->getOperand(0).getImm())) {
MCInst Inst;
MCInstLowering.Lower(MI, Inst);
EmitToStreamer(*OutStreamer, Inst);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index daf53c99988b0..c84f1c4a66ac3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1861,29 +1861,6 @@ let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
let Inst{11-5} = imm;
}
-def PHintInstOperand : AsmOperandClass {
- let Name = "PHint";
- let ParserMethod = "tryParsePHintInstOperand";
-}
-
-def phint_op : Operand<i32> {
- let ParserMatchClass = PHintInstOperand;
- let PrintMethod = "printPHintOp";
- let OperandType = "OPERAND_IMMEDIATE";
- let MIOperandInfo = (ops i32imm: $policy);
- let DecoderMethod = "DecodeUImm<3>";
-}
-
-class STSHHI
- : SimpleSystemI<0, (ins phint_op:$policy), "stshh", "\t$policy", []>,
- Sched<[WriteHint]> {
- bits<1> policy;
- let Inst{20-12} = 0b000110010;
- let Inst{11-8} = 0b0110;
- let Inst{7-6} = 0b00;
- let Inst{5} = policy;
-}
-
// System instructions taking a single literal operand which encodes into
// CRm. op2 differentiates the opcodes.
def BarrierAsmOperand : AsmOperandClass {
@@ -1952,55 +1929,6 @@ def msr_sysreg_op : Operand<i32> {
let OperandType = "OPERAND_IMMEDIATE";
}
-def PSBHintOperand : AsmOperandClass {
- let Name = "PSBHint";
- let ParserMethod = "tryParsePSBHint";
-}
-def psbhint_op : Operand<i32> {
- let ParserMatchClass = PSBHintOperand;
- let PrintMethod = "printPSBHintOp";
- let MCOperandPredicate = [{
- // Check, if operand is valid, to fix exhaustive aliasing in disassembly.
- // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
- if (!MCOp.isImm())
- return false;
- return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr;
- }];
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
-def BTIHintOperand : AsmOperandClass {
- let Name = "BTIHint";
- let ParserMethod = "tryParseBTIHint";
-}
-def btihint_op : Operand<i32> {
- let ParserMatchClass = BTIHintOperand;
- let PrintMethod = "printBTIHintOp";
- let MCOperandPredicate = [{
- // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
- if (!MCOp.isImm())
- return false;
- return AArch64BTIHint::lookupBTIByEncoding(MCOp.getImm() ^ 32) != nullptr;
- }];
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
-def CMHPriorityHintOperand : AsmOperandClass {
- let Name = "CMHPriorityHint";
- let ParserMethod = "tryParseCMHPriorityHint";
-}
-
-def CMHPriorityHint_op : Operand<i32> {
- let ParserMatchClass = CMHPriorityHintOperand;
- let PrintMethod = "printCMHPriorityHintOp";
- let MCOperandPredicate = [{
- if (!MCOp.isImm())
- return false;
- return AArch64CMHPriorityHint::lookupCMHPriorityHintByEncoding(MCOp.getImm()) != nullptr;
- }];
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
def TIndexHintOperand : AsmOperandClass {
let Name = "TIndexHint";
let ParserMethod = "tryParseTIndexHint";
@@ -13600,37 +13528,6 @@ multiclass SIMDThreeSameVectorFP8MatrixMul<string asm, SDPatternOperator OpNode>
}
}
-//----------------------------------------------------------------------------
-// Contention Management Hints - FEAT_CMH
-//----------------------------------------------------------------------------
-
-class SHUHInst<string asm> : I<
- (outs),
- (ins CMHPriorityHint_op:$priority),
- asm, "\t$priority", "", []>, Sched<[]> {
- bits<1> priority;
- let Inst{31-12} = 0b11010101000000110010;
- let Inst{11-8} = 0b0110;
- let Inst{7-6} = 0b01;
- let Inst{5} = priority;
- let Inst{4-0} = 0b11111;
-}
-
-multiclass SHUH<string asm> {
- def NAME : SHUHInst<asm>;
- def : InstAlias<asm, (!cast<Instruction>(NAME) 0), 1>;
-}
-
-class STCPHInst<string asm> : I<
- (outs),
- (ins),
- asm, "", "", []>, Sched<[]> {
- let Inst{31-12} = 0b11010101000000110010;
- let Inst{11-8} = 0b0110;
- let Inst{7-5} = 0b100;
- let Inst{4-0} = 0b11111;
-}
-
//---
// Permission Overlays Extension 2 (FEAT_S1POE2)
//---
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index fc7aea5a4d5f5..e3bc8da02f153 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1552,13 +1552,13 @@ let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in {
//===----------------------------------------------------------------------===//
def HINT : HintI<"hint">;
-def : InstAlias<"yield",(HINT 0b001)>;
-def : InstAlias<"wfe", (HINT 0b010)>;
-def : InstAlias<"wfi", (HINT 0b011)>;
-def : InstAlias<"sev", (HINT 0b100)>;
-def : InstAlias<"sevl", (HINT 0b101)>;
-def : InstAlias<"dgh", (HINT 0b110)>;
-def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;
+def : InstAlias<"yield",(HINT 1)>;
+def : InstAlias<"wfe", (HINT 2)>;
+def : InstAlias<"wfi", (HINT 3)>;
+def : InstAlias<"sev", (HINT 4)>;
+def : InstAlias<"sevl", (HINT 5)>;
+def : InstAlias<"dgh", (HINT 6)>;
+def : InstAlias<"esb", (HINT 16)>, Requires<[HasRAS]>;
def : InstAlias<"csdb", (HINT 20)>;
let CRm = 0b0000, hasSideEffects = 0 in
@@ -1566,20 +1566,30 @@ def NOP : SystemNoOperands<0b000, "hint\t#0">;
def : InstAlias<"nop", (NOP)>;
-def STSHH: STSHHI;
+def : InstAlias<"stshh keep", (HINT 48), 1>;
+def : InstAlias<"stshh strm", (HINT 49), 1>;
+def : InstAlias<"shuh", (HINT 50), 1>;
+def : InstAlias<"shuh ph", (HINT 51), 1>;
+def : InstAlias<"stcph", (HINT 52), 1>;
// In order to be able to write readable assembly, LLVM should accept assembly
// inputs that use Branch Target Identification mnemonics, even with BTI disabled.
// However, in order to be compatible with other assemblers (e.g. GAS), LLVM
// should not emit these mnemonics unless BTI is enabled.
def : InstAlias<"bti", (HINT 32), 0>;
-def : InstAlias<"bti $op", (HINT btihint_op:$op), 0>;
+def : InstAlias<"bti r", (HINT 32), 0>;
+def : InstAlias<"bti c", (HINT 34), 0>;
+def : InstAlias<"bti j", (HINT 36), 0>;
+def : InstAlias<"bti jc", (HINT 38), 0>;
def : InstAlias<"bti r", (HINT 32)>, Requires<[HasBTIE]>;
def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>;
-def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>;
+def : InstAlias<"bti c", (HINT 34)>, Requires<[HasBTI]>;
+def : InstAlias<"bti j", (HINT 36)>, Requires<[HasBTI]>;
+def : InstAlias<"bti jc", (HINT 38)>, Requires<[HasBTI]>;
// v8.2a Statistical Profiling extension
-def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
+def : InstAlias<"psb csync", (HINT 17), 1>, Requires<[HasSPE]>;
+def : InstAlias<"tsb csync", (HINT 18), 1>, Requires<[HasTRACEV8_4]>;
// As far as LLVM is concerned this writes to the system's exclusive monitors.
let mayLoad = 1, mayStore = 1 in
@@ -1597,12 +1607,6 @@ def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
def ISB : CRmSystemI<barrier_op, 0b110, "isb",
[(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
-def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> {
- let CRm = 0b0010;
- let Inst{12} = 0;
- let Predicates = [HasTRACEV8_4];
-}
-
def DSBnXS : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> {
let CRm{1-0} = 0b11;
let Inst{9-8} = 0b10;
@@ -11931,13 +11935,6 @@ let Predicates = [HasF16F32MM] in
let Uses = [FPMR, FPCR] in
defm FMMLA : SIMDThreeSameVectorFP8MatrixMul<"fmmla", int_aarch64_neon_fmmla>;
-//===----------------------------------------------------------------------===//
-// Contention Management Hints (FEAT_CMH)
-//===----------------------------------------------------------------------===//
-
-defm SHUH : SHUH<"shuh">; // Shared Update Hint instruction
-def STCPH : STCPHInst<"stcph">; // Store Concurrent Priority Hint instruction
-
//===----------------------------------------------------------------------===//
// Permission Overlays Extension 2 (FEAT_S1POE2)
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index bcd1786a0e9ea..971b57fb490f7 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -337,39 +337,6 @@ def lookupISBByName : SearchIndex {
def : ISB<"sy", 0xf>;
-//===----------------------------------------------------------------------===//
-// TSB (Trace synchronization barrier) instruction options.
-//===----------------------------------------------------------------------===//
-
-class TSB<string name, bits<4> encoding> {
- string Name = name;
- bits<4> Encoding;
- let Encoding = encoding;
-
- code Requires = [{ {AArch64::FeatureTRACEV8_4} }];
-}
-
-def TSBValues : GenericEnum {
- let FilterClass = "TSB";
- let NameField = "Name";
- let ValueField = "Encoding";
-}
-
-def TSBsList : GenericTable {
- let FilterClass = "TSB";
- let Fields = ["Name", "Encoding", "Requires"];
-
- let PrimaryKey = ["Encoding"];
- let PrimaryKeyName = "lookupTSBByEncoding";
-}
-
-def lookupTSBByName : SearchIndex {
- let Table = TSBsList;
- let Key = ["Name"];
-}
-
-def : TSB<"csync", 2>;
-
//===----------------------------------------------------------------------===//
// PRFM (prefetch) instruction options.
//===----------------------------------------------------------------------===//
@@ -749,87 +716,6 @@ def : SVCR<"SVCRZA", 0b010>;
def : SVCR<"SVCRSMZA", 0b011>;
}
-//===----------------------------------------------------------------------===//
-// PSB instruction options.
-//===----------------------------------------------------------------------===//
-
-class PSB<string name, bits<5> encoding> {
- string Name = name;
- bits<5> Encoding;
- let Encoding = encoding;
-}
-
-def PSBValues : GenericEnum {
- let FilterClass = "PSB";
- let NameField = "Name";
- let ValueField = "Encoding";
-}
-
-def PSBsList : GenericTable {
- let FilterClass = "PSB";
- let Fields = ["Name", "Encoding"];
-
- let PrimaryKey = ["Encoding"];
- let PrimaryKeyName = "lookupPSBByEncoding";
-}
-
-def lookupPSBByName : SearchIndex {
- let Table = PSBsList;
- let Key = ["Name"];
-}
-
-def : PSB<"csync", 0x11>;
-
-//===----------------------------------------------------------------------===//
-// BTI instruction options.
-//===----------------------------------------------------------------------===//
-
-class BTI<string name, bits<3> encoding> {
- string Name = name;
- bits<3> Encoding;
- let Encoding = encoding;
-}
-
-def BTIValues : GenericEnum {
- let FilterClass = "BTI";
- let NameField = "Name";
- let ValueField = "Encoding";
-}
-
-def BTIsList : GenericTable {
- let FilterClass = "BTI";
- let Fields = ["Name", "Encoding"];
-
- let PrimaryKey = ["Encoding"];
- let PrimaryKeyName = "lookupBTIByEncoding";
-}
-
-def lookupBTIByName : SearchIndex {
- let Table = BTIsList;
- let Key = ["Name"];
-}
-
-def : BTI<"r", 0b000>;
-def : BTI<"c", 0b010>;
-def : BTI<"j", 0b100>;
-def : BTI<"jc", 0b110>;
-
-//===----------------------------------------------------------------------===//
-// CMHPriority instruction options.
-//===----------------------------------------------------------------------===//
-
-class CMHPriorityHint<string name, bits<1> encoding> : SearchableTable {
- let SearchableFields = ["Name", "Encoding"];
- let EnumValueField = "Encoding";
-
- string Name = name;
- bits<1> Encoding;
- let Encoding = encoding;
-}
-
-def : CMHPriorityHint<"ph", 0b1>;
-
-
//===----------------------------------------------------------------------===//
// TIndex instruction options.
//===----------------------------------------------------------------------===//
@@ -2446,44 +2332,6 @@ def : RWSysReg<"ACTLRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b001>;
def : RWSysReg<"ACTLRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b001>;
def : RWSysReg<"ACTLRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b101>;
-//===----------------------------------------------------------------------===//
-// v9.6a PCDPHINT instruction options.
-//===----------------------------------------------------------------------===//
-
-class PHint<bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
- bits<3> op2, string name> {
- string Name = name;
- bits<16> Encoding;
- let Encoding{15-14} = op0;
- let Encoding{13-11} = op1;
- let Encoding{10-7} = crn;
- let Encoding{6-3} = crm;
- let Encoding{2-0} = op2;
- code Requires = [{ {} }];
-}
-
-def PHintValues : GenericEnum {
- let FilterClass = "PHint";
- let NameField = "Name";
- let ValueField = "Encoding";
-}
-
-def PHintsList : GenericTable {
- let FilterClass = "PHint";
- let Fields = ["Name", "Encoding", "Requires"];
-
- let PrimaryKey = ["Encoding"];
- let PrimaryKeyName = "lookupPHintByEncoding";
-}
-
-def lookupPHintByName : SearchIndex {
- let Table = PHintsList;
- let Key = ["Name"];
-}
-
-def KEEP : PHint<0b00, 0b000, 0b0000, 0b0000, 0b000, "keep">;
-def STRM : PHint<0b00, 0b000, 0b0000, 0b0000, 0b001, "strm">;
-
// v9.6a Realm management extension enhancements
def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index b3fda2fe849fa..d9107f031d52f 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -162,6 +162,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
bool parseSyslAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
bool parseSyspAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
+ bool parseHintAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S);
AArch64CC::CondCode parseCondCodeString(StringRef Cond,
std::string &Suggestion);
@@ -267,9 +268,6 @@ class AArch64AsmParser : public MCTargetAsmParser {
template <bool IsSVEPrefetch = false>
ParseStatus tryParsePrefetch(OperandVector &Operands);
ParseStatus tryParseRPRFMOperand(OperandVector &Operands);
- ParseStatus tryParsePSBHint(OperandVector &Operands);
- ParseStatus tryParseBTIHint(OperandVector &Operands);
- ParseStatus tryParseCMHPriorityHint(OperandVector &Operands);
ParseStatus tryParseTIndexHint(OperandVector &Operands);
ParseStatus tryParseAdrpLabel(OperandVector &Operands);
ParseStatus tryParseAdrLabel(OperandVector &Operands);
@@ -300,7 +298,24 @@ class AArch64AsmParser : public MCTargetAsmParser {
ParseStatus tryParseGPR64x8(OperandVector &Operands);
ParseStatus tryParseImmRange(OperandVector &Operands);
template <int> ParseStatus tryParseAdjImm0_63(OperandVector &Operands);
- ParseStatus tryParsePHintInstOperand(OperandVector &Operands);
+ template <typename LookupFn, typename CreateFn>
+ ParseStatus tryParseNamedHintOperand(OperandVector &Operands,
+ LookupFn LookupByName,
+ CreateFn CreateOperand) {
+ SMLoc S = getLoc();
+ const AsmToken &Tok = getTok();
+ if (Tok.isNot(AsmToken::Identifier))
+ return TokError("invalid operand for instruction");
+
+ auto Entry = LookupByName(Tok.getString());
+ if (!Entry)
+ return TokError("invalid operand for instruction");
+
+ Operands.push_back(
+ CreateOperand(Entry->Encoding, Tok.getString(), S, getContext()));
+ Lex(); // Eat identifier token.
+ return ParseStatus::Success;
+ }
public:
enum AArch64MatchResultTy {
@@ -372,10 +387,6 @@ class AArch64Operand : public MCParsedAsmOperand {
k_ShiftExtend,
k_FPImm,
k_Barrier,
- k_PSBHint,
- k_PHint,
- k_BTIHint,
- k_CMHPriorityHint,
k_TIndexHint,
} Kind;
@@ -491,31 +502,12 @@ class AArch64Operand : public MCParsedAsmOperand {
unsigned Val;
};
- struct PSBHintOp {
- const char *Data;
- unsigned Length;
- unsigned Val;
- };
- struct PHintOp {
- const char *Data;
- unsigned Length;
- unsigned Val;
- };
- struct BTIHintOp {
- const char *Data;
- unsigned Length;
- unsigned Val;
- };
- struct CMHPriorityHintOp {
- const char *Data;
- unsigned Length;
- unsigned Val;
- };
- struct TIndexHintOp {
+ struct NamedHintOp {
const char *Data;
unsigned Length;
unsigned Val;
};
+ using TIndexHintOp = NamedHintOp;
struct SVCROp {
const char *Data;
@@ -524,28 +516,24 @@ class AArch64Operand : public MCParsedAsmOperand {
};
union {
- struct TokOp Tok;
- struct RegOp Reg;
- struct MatrixRegOp MatrixReg;
- struct MatrixTileListOp MatrixTileList;
- struct VectorListOp VectorList;
- struct VectorIndexOp VectorIndex;
- struct ImmOp Imm;
- struct ShiftedImmOp ShiftedImm;
- struct ImmRangeOp ImmRange;
- struct CondCodeOp CondCode;
- struct FPImmOp FPImm;
- struct BarrierOp Barrier;
- struct SysRegOp SysReg;
- struct SysCRImmOp SysCRImm;
- struct PrefetchOp Prefetch;
- struct PSBHintOp PSBHint;
- struct PHintOp PHint;
- struct BTIHintOp BTIHint;
- struct CMHPriorityHintOp CMHPriorityHint;
- struct TIndexHintOp TIndexHint;
- struct ShiftExtendOp ShiftExtend;
- struct SVCROp SVCR;
+ TokOp Tok;
+ RegOp Reg;
+ MatrixRegOp MatrixReg;
+ MatrixTileListOp MatrixTileList;
+ VectorListOp VectorList;
+ VectorIndexOp VectorIndex;
+ ImmOp Imm;
+ ShiftedImmOp ShiftedImm;
+ ImmRangeOp ImmRange;
+ CondCodeOp CondCode;
+ FPImmOp FPImm;
+ BarrierOp Barrier;
+ SysRegOp SysReg;
+ SysCRImmOp SysCRImm;
+ PrefetchOp Prefetch;
+ TIndexHintOp TIndexHint;
+ ShiftExtendOp ShiftExtend;
+ SVCROp SVCR;
};
// Keep the MCContext around as the MCExprs may need manipulated during
@@ -605,18 +593,6 @@ class AArch64Operand : public MCParsedAsmOperand {
case k_Prefetch:
Prefetch = o.Prefetch;
break;
- case k_PSBHint:
- PSBHint = o.PSBHint;
- break;
- case k_PHint:
- PHint = o.PHint;
- break;
- case k_BTIHint:
- BTIHint = o.BTIHint;
- break;
- case k_CMHPriorityHint:
- CMHPriorityHint = o.CMHPriorityHint;
- break;
case k_TIndexHint:
TIndexHint = o.TIndexHint;
break;
@@ -764,46 +740,6 @@ class AArch64Operand : public MCParsedAsmOperand {
return Prefetch.Val;
}
- unsigned getPSBHint() const {
- assert(Kind == k_PSBHint && "Invalid access!");
- return PSBHint.Val;
- }
-
- unsigned getPHint() const {
- assert(Kind == k_PHint && "Invalid access!");
- return PHint.Val;
- }
-
- StringRef getPSBHintName() const {
- assert(Kind == k_PSBHint && "Invalid access!");
- return StringRef(PSBHint.Data, PSBHint.Length);
- }
-
- StringRef getPHintName() const {
- assert(Kind == k_PHint && "Invalid access!");
- return StringRef(PHint.Data, PHint.Length);
- }
-
- unsigned getBTIHint() const {
- assert(Kind == k_BTIHint && "Invalid access!");
- return BTIHint.Val;
- }
-
- StringRef getBTIHintName() const {
- assert(Kind == k_BTIHint && "Invalid access!");
- return StringRef(BTIHint.Data, BTIHint.Length);
- }
-
- unsigned getCMHPriorityHint() const {
- assert(Kind == k_CMHPriorityHint && "Invalid access!");
- return CMHPriorityHint.Val;
- }
-
- StringRef getCMHPriorityHintName() const {
- assert(Kind == k_CMHPriorityHint && "Invalid access!");
- return StringRef(CMHPriorityHint.Data, CMHPriorityHint.Length);
- }
-
unsigned getTIndexHint() const {
assert(K...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206383
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