[llvm] [TableGen][SchedModel] Add repeat rate to block buffered resources (PR #202775)

Min-Yih Hsu via llvm-commits llvm-commits at lists.llvm.org
Sun Jun 28 14:41:30 PDT 2026


mshockwave wrote:

Sorry I was occupied by something else. 

> when we schedule an instruction, we update some state `ReservedCycles`, and future instructions query this state to understand the conditions.

okay this (potential) approach sounds reasonable.

> We would either need to change the semantics of Acquire/ReleaseAtCycle for BufferSize=1 ProcReources, or intoduce a new SchedModel property (which is what this PR does). The former would need agreement with SystemZ, Mips, PowerPC, ARM, X86, and RISCV backends as well as AMDGPU, as these all use BufferSize=1 ProcResources. As groundwork for possible extension into SchedModel, I thought it better to introduce new property to express the new semantic that we want, rather than changing the semantics of well established property.

Generally speaking, I also don't want to change the semantics of BufferSize = 1 just yet, and thus agree adding a new scheduling model property is a better approach.

That being said, given how similar `RepeatRate` and `AcquireAtCycle` / `ReleaseAtCycle` are (semantics-wise), could we instead reuse `AcquireAtCycle` / `ReleaseAtCycle` and add another flag for those `WriteRes`?
For instance, instead of writing
```
let RepeatRate = [4, 1] in
def : WriteRes<SC1, [Res0, Res1]>;
```
we do
```
let ReleaseAtCycles = [4, 1], ForceReserved = true in
def : WriteRes<SC1, [Res0, Res1]>;
```
where `ForceReserved` is the new property I was talking about here. The name could also be something like `AlwaysReserved` or even `AlwaysUnbuffered`.

what do you think?

https://github.com/llvm/llvm-project/pull/202775


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