[llvm] 2959bfa - [LV] Add test with pointer based on SRem expression (NFC). (#206344)
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Sun Jun 28 09:45:51 PDT 2026
Author: Florian Hahn
Date: 2026-06-28T16:45:46Z
New Revision: 2959bfa4665a8b63ac079f756cd4cc2fe73f4d49
URL: https://github.com/llvm/llvm-project/commit/2959bfa4665a8b63ac079f756cd4cc2fe73f4d49
DIFF: https://github.com/llvm/llvm-project/commit/2959bfa4665a8b63ac079f756cd4cc2fe73f4d49.diff
LOG: [LV] Add test with pointer based on SRem expression (NFC). (#206344)
Add a test with loads and stores with pointers based on a signed
remainder (srem) of a non-negative induction variable, mirroring the
existing urem test.
Added:
Modified:
llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll b/llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
index 9fbd9526a0cf7..57762b77cb09c 100644
--- a/llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
+++ b/llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
@@ -1485,3 +1485,126 @@ loop.latch:
exit:
ret void
}
+
+; Same as @sink_multiple_store_groups_noalias_via_scev_urem, but the pointers
+; %gep.dst1.then / %gep.dst1.else are derived from a srem of the IV. As the IV
+; is non-negative, the signed remainder matches the unsigned one.
+define void @sink_multiple_store_groups_noalias_via_scev_srem(ptr %dst, ptr %src) {
+; CHECK-LABEL: define void @sink_multiple_store_groups_noalias_via_scev_srem(
+; CHECK-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
+; CHECK: [[VECTOR_SCEVCHECK]]:
+; CHECK-NEXT: [[MUL:%.*]] = call { i7, i1 } @llvm.umul.with.overflow.i7(i7 16, i7 -29)
+; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i7, i1 } [[MUL]], 1
+; CHECK-NEXT: br i1 [[MUL_OVERFLOW]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 12828
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[DST]], i64 12696
+; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP1]]
+; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP]]
+; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE7:.*]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 16>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE7]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 16
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP2]], i64 152
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP3]], i64 152
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP4]], align 4, !alias.scope [[META126:![0-9]+]], !noalias [[META129:![0-9]+]]
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP5]], align 4, !alias.scope [[META126]], !noalias [[META129]]
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq <2 x i32> [[TMP9]], zeroinitializer
+; CHECK-NEXT: [[TMP11:%.*]] = load double, ptr [[TMP2]], align 8, !alias.scope [[META126]], !noalias [[META129]]
+; CHECK-NEXT: [[TMP12:%.*]] = load double, ptr [[TMP3]], align 8, !alias.scope [[META126]], !noalias [[META129]]
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x double> poison, double [[TMP11]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x double> [[TMP13]], double [[TMP12]], i32 1
+; CHECK-NEXT: [[TMP15:%.*]] = srem <2 x i64> [[VEC_IND]], splat (i64 128)
+; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i1> [[TMP10]], splat (i1 true)
+; CHECK-NEXT: [[TMP17:%.*]] = fadd <2 x double> [[TMP14]], splat (double 8.000000e+00)
+; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i1> [[TMP16]], i64 0
+; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
+; CHECK: [[PRED_STORE_IF]]:
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i64> [[TMP15]], i64 0
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x double> [[TMP17]], i64 0
+; CHECK-NEXT: store double [[TMP21]], ptr [[TMP20]], align 8, !alias.scope [[META129]]
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
+; CHECK: [[PRED_STORE_CONTINUE]]:
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i1> [[TMP16]], i64 1
+; CHECK-NEXT: br i1 [[TMP22]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3:.*]]
+; CHECK: [[PRED_STORE_IF2]]:
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i64> [[TMP15]], i64 1
+; CHECK-NEXT: [[TMP24:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP23]]
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <2 x double> [[TMP17]], i64 1
+; CHECK-NEXT: store double [[TMP25]], ptr [[TMP24]], align 8, !alias.scope [[META129]]
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE3]]
+; CHECK: [[PRED_STORE_CONTINUE3]]:
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <2 x i1> [[TMP10]], i64 0
+; CHECK-NEXT: br i1 [[TMP26]], label %[[PRED_STORE_IF4:.*]], label %[[PRED_STORE_CONTINUE5:.*]]
+; CHECK: [[PRED_STORE_IF4]]:
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <2 x i64> [[TMP15]], i64 0
+; CHECK-NEXT: [[TMP28:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP27]]
+; CHECK-NEXT: store double [[TMP11]], ptr [[TMP28]], align 8, !alias.scope [[META129]]
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP28]], i64 16
+; CHECK-NEXT: store double 1.000000e+01, ptr [[TMP29]], align 8, !alias.scope [[META129]]
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE5]]
+; CHECK: [[PRED_STORE_CONTINUE5]]:
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <2 x i1> [[TMP10]], i64 1
+; CHECK-NEXT: br i1 [[TMP30]], label %[[PRED_STORE_IF6:.*]], label %[[PRED_STORE_CONTINUE7]]
+; CHECK: [[PRED_STORE_IF6]]:
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <2 x i64> [[TMP15]], i64 1
+; CHECK-NEXT: [[TMP32:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP31]]
+; CHECK-NEXT: store double [[TMP12]], ptr [[TMP32]], align 8, !alias.scope [[META129]]
+; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[TMP32]], i64 16
+; CHECK-NEXT: store double 1.000000e+01, ptr [[TMP33]], align 8, !alias.scope [[META129]]
+; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE7]]
+; CHECK: [[PRED_STORE_CONTINUE7]]:
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 32)
+; CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
+; CHECK-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP131:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br [[EXIT:label %.*]]
+; CHECK: [[SCALAR_PH]]:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
+ %gep.src = getelementptr double, ptr %src, i64 %iv
+ %gep.flag = getelementptr i8, ptr %gep.src, i64 152
+ %c = load i32, ptr %gep.flag, align 4
+ %cmp = icmp eq i32 %c, 0
+ %v.1 = load double, ptr %gep.src, align 8
+ %clamped = srem i64 %iv, 128
+ br i1 %cmp, label %then, label %else
+
+then:
+ %gep.dst1.then = getelementptr double, ptr %dst, i64 %clamped
+ store double %v.1, ptr %gep.dst1.then, align 8
+ %gep.dst2.then = getelementptr i8, ptr %gep.dst1.then, i64 16
+ store double 10.0, ptr %gep.dst2.then, align 8
+ br label %loop.latch
+
+else:
+ %r.1 = fadd double %v.1, 8.0
+ %gep.dst1.else = getelementptr double, ptr %dst, i64 %clamped
+ store double %r.1, ptr %gep.dst1.else, align 8
+ br label %loop.latch
+
+loop.latch:
+ %iv.next = add i64 %iv, 16
+ %exit.cond = icmp eq i64 %iv.next, 1600
+ br i1 %exit.cond, label %exit, label %loop
+
+exit:
+ ret void
+}
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