[llvm] [AMDGPU][GlobalISel] Improve odd size s16 vector store legalization (PR #206342)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 28 08:44:52 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Jiaqi He (heturing)
<details>
<summary>Changes</summary>
Fixes https://github.com/llvm/llvm-project/issues/205569.
Odd s16 vector stores, such as `<3 x s16>`, currently fall through to `lower` during legalization and are split into multiple s16 stores.
This patch adds a predicate to route odd s16 vector stores through the existing `fewerElements` path, allowing them to be split into wider stores if possible. For example, `<3 x s16>` is split into a `<2 x s16>` store and a `s16` store.
This changes the expected output of a few existing tests, which have been updated with the test update script. A new legalizer regression test is also added to verify the behaviour.
---
Patch is 58.67 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206342.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+12-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll (+66-96)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir (+172-54)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll (+9-13)
- (modified) llvm/test/CodeGen/AMDGPU/freeze.ll (+27-60)
- (modified) llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll (+31-53)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 3909c5b964fa5..2ebb01351aa09 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1575,6 +1575,16 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
return false;
};
+ const auto isOddS16VectorStore = [=](const LegalityQuery &Query,
+ bool IsStore) -> bool {
+ const LLT DstTy = Query.Types[0];
+ const LLT MemTy = Query.MMODescrs[0].MemoryTy;
+
+ return IsStore && DstTy == MemTy &&
+ DstTy.getElementType().getSizeInBits() == 16 &&
+ DstTy.getNumElements() % 2 != 0;
+ };
+
unsigned GlobalAlign32 = ST.hasUnalignedBufferAccessEnabled() ? 0 : 32;
unsigned GlobalAlign16 = ST.hasUnalignedBufferAccessEnabled() ? 0 : 16;
unsigned GlobalAlign8 = ST.hasUnalignedBufferAccessEnabled() ? 0 : 8;
@@ -1699,7 +1709,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.fewerElementsIf(
[=](const LegalityQuery &Query) -> bool {
return Query.Types[0].isVector() &&
- needToSplitMemOp(Query, Op == G_LOAD);
+ (needToSplitMemOp(Query, Op == G_LOAD) ||
+ isOddS16VectorStore(Query, IsStore));
},
[=](const LegalityQuery &Query) -> std::pair<unsigned, LLT> {
const LLT DstTy = Query.Types[0];
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
index 18f96acb268fa..0a2a8e363632f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
@@ -21,22 +21,20 @@ define void @add_v3i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addrs
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 4, v2
; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
-; GFX8-NEXT: flat_load_ushort v11, v[2:3]
-; GFX8-NEXT: flat_load_ushort v12, v[0:1]
-; GFX8-NEXT: flat_load_ushort v6, v[6:7]
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v4
+; GFX8-NEXT: flat_load_ushort v2, v[2:3]
+; GFX8-NEXT: flat_load_ushort v3, v[6:7]
+; GFX8-NEXT: flat_load_ushort v6, v[0:1]
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v4
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_add_u16_e32 v7, v8, v11
+; GFX8-NEXT: v_add_u16_e32 v2, v8, v2
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_add_u16_e32 v8, v9, v12
+; GFX8-NEXT: v_add_u16_e32 v3, v10, v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_add_u16_e32 v6, v10, v6
-; GFX8-NEXT: flat_store_short v[4:5], v7
-; GFX8-NEXT: flat_store_short v[0:1], v8
-; GFX8-NEXT: flat_store_short v[2:3], v6
+; GFX8-NEXT: v_add_u16_sdwa v6, v9, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX8-NEXT: flat_store_dword v[4:5], v2
+; GFX8-NEXT: flat_store_short v[0:1], v3
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -65,8 +63,7 @@ define void @add_v3i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addrs
; GFX9-NEXT: v_lshl_or_b32 v3, s4, 16, v3
; GFX9-NEXT: v_pk_add_u16 v0, v0, v2
; GFX9-NEXT: v_pk_add_u16 v1, v1, v3
-; GFX9-NEXT: global_store_short v[4:5], v0, off
-; GFX9-NEXT: global_store_short_d16_hi v[4:5], v0, off offset:2
+; GFX9-NEXT: global_store_dword v[4:5], v0, off
; GFX9-NEXT: global_store_short v[4:5], v1, off offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -179,34 +176,27 @@ define void @add_v5i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addrs
; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v10, vcc, 8, v2
; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v3, vcc
-; GFX8-NEXT: flat_load_ushort v17, v[2:3]
-; GFX8-NEXT: flat_load_ushort v18, v[0:1]
-; GFX8-NEXT: flat_load_ushort v19, v[6:7]
-; GFX8-NEXT: flat_load_ushort v20, v[8:9]
-; GFX8-NEXT: flat_load_ushort v10, v[10:11]
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v4
+; GFX8-NEXT: flat_load_ushort v2, v[2:3]
+; GFX8-NEXT: flat_load_ushort v3, v[10:11]
+; GFX8-NEXT: flat_load_ushort v10, v[0:1]
+; GFX8-NEXT: flat_load_ushort v6, v[6:7]
+; GFX8-NEXT: flat_load_ushort v7, v[8:9]
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v4
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 6, v4
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
-; GFX8-NEXT: v_add_u32_e32 v8, vcc, 8, v4
-; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GFX8-NEXT: s_waitcnt vmcnt(4)
-; GFX8-NEXT: v_add_u16_e32 v11, v12, v17
+; GFX8-NEXT: v_add_u16_e32 v2, v12, v2
; GFX8-NEXT: s_waitcnt vmcnt(3)
-; GFX8-NEXT: v_add_u16_e32 v12, v13, v18
+; GFX8-NEXT: v_add_u16_e32 v8, v16, v3
; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_add_u16_e32 v13, v14, v19
+; GFX8-NEXT: v_add_u16_sdwa v3, v13, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_add_u16_e32 v14, v15, v20
+; GFX8-NEXT: v_add_u16_e32 v6, v14, v6
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_add_u16_e32 v10, v16, v10
-; GFX8-NEXT: flat_store_short v[4:5], v11
-; GFX8-NEXT: flat_store_short v[0:1], v12
-; GFX8-NEXT: flat_store_short v[2:3], v13
-; GFX8-NEXT: flat_store_short v[6:7], v14
-; GFX8-NEXT: flat_store_short v[8:9], v10
+; GFX8-NEXT: v_add_u16_sdwa v7, v15, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[2:3]
+; GFX8-NEXT: flat_store_short v[0:1], v8
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -241,17 +231,14 @@ define void @add_v5i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addrs
; GFX9-NEXT: v_lshl_or_b32 v1, v13, 16, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshl_or_b32 v3, v14, 16, v3
-; GFX9-NEXT: v_lshl_or_b32 v2, s4, 16, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshl_or_b32 v6, v15, 16, v6
+; GFX9-NEXT: v_lshl_or_b32 v2, s4, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v7, s4, 16, v7
; GFX9-NEXT: v_pk_add_u16 v0, v0, v3
; GFX9-NEXT: v_pk_add_u16 v1, v1, v6
; GFX9-NEXT: v_pk_add_u16 v2, v2, v7
-; GFX9-NEXT: global_store_short v[4:5], v0, off
-; GFX9-NEXT: global_store_short_d16_hi v[4:5], v0, off offset:2
-; GFX9-NEXT: global_store_short v[4:5], v1, off offset:4
-; GFX9-NEXT: global_store_short_d16_hi v[4:5], v1, off offset:6
+; GFX9-NEXT: global_store_dwordx2 v[4:5], v[0:1], off
; GFX9-NEXT: global_store_short v[4:5], v2, off offset:8
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -387,43 +374,34 @@ define void @addv_7i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addrs
; GFX8-NEXT: v_add_u32_e32 v14, vcc, 12, v2
; GFX8-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc
; GFX8-NEXT: flat_load_ushort v2, v[2:3]
-; GFX8-NEXT: flat_load_ushort v3, v[0:1]
+; GFX8-NEXT: flat_load_ushort v3, v[14:15]
+; GFX8-NEXT: flat_load_ushort v14, v[0:1]
; GFX8-NEXT: flat_load_ushort v6, v[6:7]
; GFX8-NEXT: flat_load_ushort v7, v[8:9]
; GFX8-NEXT: flat_load_ushort v8, v[10:11]
; GFX8-NEXT: flat_load_ushort v9, v[12:13]
-; GFX8-NEXT: flat_load_ushort v10, v[14:15]
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v4
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-NEXT: s_waitcnt vmcnt(6)
; GFX8-NEXT: v_add_u16_e32 v2, v16, v2
; GFX8-NEXT: s_waitcnt vmcnt(5)
-; GFX8-NEXT: v_add_u16_e32 v3, v17, v3
-; GFX8-NEXT: flat_store_short v[4:5], v2
-; GFX8-NEXT: flat_store_short v[0:1], v3
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v4
-; GFX8-NEXT: s_waitcnt vmcnt(6)
+; GFX8-NEXT: v_add_u16_e32 v10, v22, v3
+; GFX8-NEXT: s_waitcnt vmcnt(4)
+; GFX8-NEXT: v_add_u16_sdwa v3, v17, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: s_waitcnt vmcnt(3)
; GFX8-NEXT: v_add_u16_e32 v6, v18, v6
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
-; GFX8-NEXT: flat_store_short v[0:1], v6
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 6, v4
-; GFX8-NEXT: s_waitcnt vmcnt(6)
-; GFX8-NEXT: v_add_u16_e32 v7, v19, v7
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
-; GFX8-NEXT: flat_store_short v[0:1], v7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4
-; GFX8-NEXT: s_waitcnt vmcnt(6)
+; GFX8-NEXT: s_waitcnt vmcnt(2)
+; GFX8-NEXT: v_add_u16_sdwa v7, v19, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_add_u16_e32 v8, v20, v8
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
-; GFX8-NEXT: flat_store_short v[0:1], v8
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 10, v4
-; GFX8-NEXT: s_waitcnt vmcnt(6)
-; GFX8-NEXT: v_add_u16_e32 v9, v21, v9
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
-; GFX8-NEXT: flat_store_short v[0:1], v9
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_add_u16_sdwa v9, v21, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX8-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[2:3]
+; GFX8-NEXT: flat_store_dword v[0:1], v6
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 12, v4
-; GFX8-NEXT: s_waitcnt vmcnt(6)
-; GFX8-NEXT: v_add_u16_e32 v10, v22, v10
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-NEXT: flat_store_short v[0:1], v10
; GFX8-NEXT: s_waitcnt vmcnt(0)
@@ -470,22 +448,17 @@ define void @addv_7i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addrs
; GFX9-NEXT: v_lshl_or_b32 v2, v16, 16, v2
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_lshl_or_b32 v6, v17, 16, v6
-; GFX9-NEXT: v_lshl_or_b32 v3, s4, 16, v3
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshl_or_b32 v7, v18, 16, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshl_or_b32 v8, v19, 16, v8
+; GFX9-NEXT: v_lshl_or_b32 v3, s4, 16, v3
; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v9
; GFX9-NEXT: v_pk_add_u16 v0, v0, v6
; GFX9-NEXT: v_pk_add_u16 v1, v1, v7
; GFX9-NEXT: v_pk_add_u16 v2, v2, v8
; GFX9-NEXT: v_pk_add_u16 v3, v3, v9
-; GFX9-NEXT: global_store_short v[4:5], v0, off
-; GFX9-NEXT: global_store_short_d16_hi v[4:5], v0, off offset:2
-; GFX9-NEXT: global_store_short v[4:5], v1, off offset:4
-; GFX9-NEXT: global_store_short_d16_hi v[4:5], v1, off offset:6
-; GFX9-NEXT: global_store_short v[4:5], v2, off offset:8
-; GFX9-NEXT: global_store_short_d16_hi v[4:5], v2, off offset:10
+; GFX9-NEXT: global_store_dwordx3 v[4:5], v[0:2], off
; GFX9-NEXT: global_store_short v[4:5], v3, off offset:12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -701,39 +674,37 @@ define void @add_v11i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addr
; GFX8-NEXT: s_waitcnt vmcnt(3)
; GFX8-NEXT: v_add_u16_e32 v17, v6, v10
; GFX8-NEXT: v_add_u16_sdwa v10, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 18, v0
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 20, v0
; GFX8-NEXT: v_add_u16_e32 v18, v7, v11
; GFX8-NEXT: v_add_u16_sdwa v11, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 20, v0
-; GFX8-NEXT: flat_load_ushort v2, v[2:3]
-; GFX8-NEXT: flat_load_ushort v3, v[6:7]
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, 18, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: flat_load_ushort v21, v[0:1]
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, 16, v4
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
+; GFX8-NEXT: flat_load_ushort v22, v[2:3]
+; GFX8-NEXT: flat_load_ushort v23, v[0:1]
+; GFX8-NEXT: flat_load_ushort v21, v[6:7]
; GFX8-NEXT: v_add_u16_e32 v19, v8, v12
; GFX8-NEXT: v_add_u16_sdwa v12, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_add_u32_e32 v8, vcc, 18, v4
; GFX8-NEXT: v_add_u16_e32 v20, v9, v13
; GFX8-NEXT: v_add_u16_sdwa v13, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 16, v4
+; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
; GFX8-NEXT: v_or_b32_e32 v0, v17, v10
; GFX8-NEXT: v_or_b32_e32 v1, v18, v11
-; GFX8-NEXT: v_add_u32_e32 v10, vcc, 20, v4
-; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_add_u16_e32 v14, v2, v14
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_add_u16_e32 v15, v3, v15
; GFX8-NEXT: v_or_b32_e32 v2, v19, v12
; GFX8-NEXT: v_or_b32_e32 v3, v20, v13
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_add_u16_e32 v16, v21, v16
+; GFX8-NEXT: v_add_u32_e32 v8, vcc, 20, v4
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: flat_store_short v[6:7], v14
-; GFX8-NEXT: flat_store_short v[8:9], v15
-; GFX8-NEXT: flat_store_short v[10:11], v16
+; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GFX8-NEXT: s_waitcnt vmcnt(3)
+; GFX8-NEXT: v_add_u16_e32 v11, v22, v14
+; GFX8-NEXT: s_waitcnt vmcnt(2)
+; GFX8-NEXT: v_add_u16_sdwa v12, v23, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v11, v12
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_add_u16_e32 v10, v21, v16
+; GFX8-NEXT: flat_store_dword v[6:7], v0
+; GFX8-NEXT: flat_store_short v[8:9], v10
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -771,8 +742,7 @@ define void @add_v11i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb, ptr addr
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_pk_add_u16 v0, v6, v8
; GFX9-NEXT: v_pk_add_u16 v1, v7, v9
-; GFX9-NEXT: global_store_short v[4:5], v0, off offset:16
-; GFX9-NEXT: global_store_short_d16_hi v[4:5], v0, off offset:18
+; GFX9-NEXT: global_store_dword v[4:5], v0, off offset:16
; GFX9-NEXT: global_store_short v[4:5], v1, off offset:20
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
index 0a009e702dea4..0aed2903e1d61 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
@@ -8443,14 +8443,14 @@ body: |
; SI-NEXT: G_STORE [[BITCAST4]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
; SI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; SI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
- ; SI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; SI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32)
+ ; SI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL4]]
+ ; SI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
+ ; SI-NEXT: G_STORE [[BITCAST5]](<2 x s16>), [[PTR_ADD]](p1) :: (store (<2 x s16>) into unknown-address + 16, align 16, addrspace 1)
+ ; SI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
- ; SI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ; SI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; SI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
- ; SI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
+ ; SI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; SI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
;
; CI-LABEL: name: test_store_global_v11s16_align4
; CI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -8475,14 +8475,14 @@ body: |
; CI-NEXT: G_STORE [[BITCAST4]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
; CI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
- ; CI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32)
+ ; CI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL4]]
+ ; CI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
+ ; CI-NEXT: G_STORE [[BITCAST5]](<2 x s16>), [[PTR_ADD]](p1) :: (store (<2 x s16>) into unknown-address + 16, align 16, addrspace 1)
+ ; CI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
- ; CI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ; CI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
- ; CI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
+ ; CI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
;
; VI-LABEL: name: test_store_global_v11s16_align4
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -8507,14 +8507,14 @@ body: |
; VI-NEXT: G_STORE [[BITCAST4]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), addrspace 1)
; VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; VI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
- ; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; VI-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32)
+ ; VI-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[C]], [[SHL4]]
+ ; VI-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
+ ; VI-NEXT: G_STORE [[BITCAST5]](<2 x s16>), [[PTR_ADD]](p1) :: (store (<2 x s16>) into unknown-address + 16, align 16, addrspace 1)
+ ; VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
- ; VI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
- ; VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[PTR_ADD]], [[C4]](s64)
- ; VI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
+ ; VI-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; VI-NEXT: G_STORE [[DEF]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
;
; GFX9-LABEL: name: test_store_global_v11s16_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -8530,14 +8530,12 @@ body: |
; GFX9-NEXT: G_STORE [[BITCAST]](<4 x s32>), [[COPY]](p1) :: (store (<4 x s32>), a...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206342
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