[llvm] [GlobalISel] Legalize wide-memory extending loads via load + extension (PR #206276)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 27 11:42:06 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-mips
Author: Ilpo Ruotsalainen (lonemeow)
<details>
<summary>Changes</summary>
Legalize an aligned G_ZEXTLOAD/G_SEXTLOAD whose memory type is register-width or wider in `lowerLoad()` by emitting a memory-width G_LOAD followed by a separate extension to the destination type and route the previously unimplemented path of `narrowScalar()` through `lowerLoad()` to reuse the logic.
Fixes a legalization failure reachable from portable C on RV32 and MIPS at `-O2`: https://godbolt.org/z/63aWeaarx
Assisted-by: Claude Opus 4.8
---
Patch is 21.87 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206276.diff
5 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+29-8)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir (+53)
- (modified) llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir (+118-45)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir (+61)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/wide-extload.ll (+57)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 8c38d8ce79d59..359cac50f710e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1701,8 +1701,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
} else if (MemSize < NarrowSize) {
MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), TmpReg, PtrReg, MMO);
} else if (MemSize > NarrowSize) {
- // FIXME: Need to split the load.
- return UnableToLegalize;
+ // Decompose into a memory-width load + extension, narrowed separately.
+ return lowerLoad(LoadMI);
}
if (isa<GZExtLoad>(LoadMI))
@@ -4259,17 +4259,38 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerLoad(GAnyLoad &LoadMI) {
LargeSplitSize = llvm::bit_floor(MemSizeInBits);
SmallSplitSize = MemSizeInBits - LargeSplitSize;
} else {
- // This is already a power of 2, but we still need to split this in half.
- //
- // Assume we're being asked to decompose an unaligned load.
- // TODO: If this requires multiple splits, handle them all at once.
auto &Ctx = MF.getFunction().getContext();
- if (TLI.allowsMemoryAccess(Ctx, MIRBuilder.getDataLayout(), MemTy, MMO))
- return UnableToLegalize;
+ if (TLI.allowsMemoryAccess(Ctx, MIRBuilder.getDataLayout(), MemTy, MMO)) {
+ // Only an extending scalar load has anything to lower here: a
+ // memory-width load plus a separate extension. Non-extending loads
+ // have nothing to lower and vector extloads aren't handled, so
+ // decline both.
+ if (MemTy.isVector() || DstTy.getSizeInBits() <= MemSizeInBits)
+ return UnableToLegalize;
+
+ auto NewLoad = MIRBuilder.buildLoad(MemTy, PtrReg, MMO);
+ if (isa<GSExtLoad>(LoadMI))
+ MIRBuilder.buildSExt(DstReg, NewLoad);
+ else if (isa<GZExtLoad>(LoadMI))
+ MIRBuilder.buildZExt(DstReg, NewLoad);
+ else if (isa<GFPExtLoad>(LoadMI))
+ MIRBuilder.buildFPExt(DstReg, NewLoad);
+ else
+ MIRBuilder.buildAnyExt(DstReg, NewLoad);
+ LoadMI.eraseFromParent();
+ return Legalized;
+ }
+ // The access isn't allowed as-is (presumably underaligned). The size is
+ // already a power of 2, so split it into two half-width accesses.
+ // TODO: If this requires multiple splits, handle them all at once.
SmallSplitSize = LargeSplitSize = MemSizeInBits / 2;
}
+ // The integer split logic below cannot reassemble an FP extension.
+ if (isa<GFPExtLoad>(LoadMI))
+ return UnableToLegalize;
+
if (MemTy.isVector()) {
// TODO: Handle vector extloads
if (MemTy != DstTy)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
index bf10e5c3b8ad6..cbce35202cfd6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
@@ -167,3 +167,56 @@ body: |
$x0 = COPY %trunc(s64)
RET_ReallyLR implicit $x0
...
+---
+name: zext_i128_i256
+body: |
+ bb.1:
+ liveins: $x0
+ ; CHECK-LABEL: name: zext_i128_i256
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD %ptr(p0) :: (load (s128))
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[C]](s64)
+ ; CHECK-NEXT: $x3 = COPY [[C]](s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3
+ %ptr:_(p0) = COPY $x0
+ %load:_(s256) = G_ZEXTLOAD %ptr(p0) :: (load (s128))
+ %v0:_(s64), %v1:_(s64), %v2:_(s64), %v3:_(s64) = G_UNMERGE_VALUES %load(s256)
+ $x0 = COPY %v0(s64)
+ $x1 = COPY %v1(s64)
+ $x2 = COPY %v2(s64)
+ $x3 = COPY %v3(s64)
+ RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3
+...
+---
+name: sext_i128_i256
+body: |
+ bb.1:
+ liveins: $x0
+ ; CHECK-LABEL: name: sext_i128_i256
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD %ptr(p0) :: (load (s128))
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](s128)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(i64) = G_ASHR [[UV1]], [[C]](i64)
+ ; CHECK-NEXT: $x0 = COPY [[UV]](i64)
+ ; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
+ ; CHECK-NEXT: $x2 = COPY [[ASHR]](i64)
+ ; CHECK-NEXT: $x3 = COPY [[ASHR]](i64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3
+ %ptr:_(p0) = COPY $x0
+ %load:_(s256) = G_SEXTLOAD %ptr(p0) :: (load (s128))
+ %v0:_(s64), %v1:_(s64), %v2:_(s64), %v3:_(s64) = G_UNMERGE_VALUES %load(s256)
+ $x0 = COPY %v0(s64)
+ $x1 = COPY %v1(s64)
+ $x2 = COPY %v2(s64)
+ $x3 = COPY %v3(s64)
+ RET_ReallyLR implicit $x0, implicit $x1, implicit $x2, implicit $x3
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
index 2e1c82c879f51..f8e39d067ae5b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
@@ -7,11 +7,13 @@
define void @load1_s8_to_zextLoad1_s16(ptr %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(ptr %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(ptr %px) {entry: ret void}
+ define void @load8_s64_to_zextLoad8_s128(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(ptr %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(ptr %px) {entry: ret void}
+ define void @load8_s64_to_sextLoad8_s128(ptr %px) {entry: ret void}
...
---
@@ -24,10 +26,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$v0 = COPY %2(s32)
@@ -44,10 +47,11 @@ body: |
; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$v0 = COPY %2(s32)
@@ -64,10 +68,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
%3:_(s32) = G_ANYEXT %2(s16)
@@ -85,10 +90,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$v0 = COPY %3(s32)
@@ -105,12 +111,13 @@ body: |
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
- ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: $v1 = COPY [[C]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
+ ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: $v1 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
@@ -118,6 +125,36 @@ body: |
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
+...
+---
+name: load8_s64_to_zextLoad8_s128
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load8_s64_to_zextLoad8_s128
+ ; MIPS32: liveins: $a0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.px)
+ ; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
+ ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32-NEXT: $v0 = COPY [[UV]](s32)
+ ; MIPS32-NEXT: $v1 = COPY [[UV1]](s32)
+ ; MIPS32-NEXT: $a0 = COPY [[C]](s32)
+ ; MIPS32-NEXT: $a1 = COPY [[C]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ %0:_(p0) = COPY $a0
+ %2:_(s128) = G_ZEXTLOAD %0(p0) :: (load (s64) from %ir.px)
+ %3:_(s32), %4:_(s32), %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %2(s128)
+ $v0 = COPY %3(s32)
+ $v1 = COPY %4(s32)
+ $a0 = COPY %5(s32)
+ $a1 = COPY %6(s32)
+ RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+
...
---
name: load1_s8_to_sextLoad1_s32
@@ -129,10 +166,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$v0 = COPY %2(s32)
@@ -149,10 +187,11 @@ body: |
; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)
$v0 = COPY %2(s32)
@@ -169,10 +208,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
%3:_(s32) = G_ANYEXT %2(s16)
@@ -190,10 +230,11 @@ body: |
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
+ ; MIPS32-NEXT: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
%3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
$v0 = COPY %3(s32)
@@ -210,13 +251,14 @@ body: |
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
- ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: $v1 = COPY [[ASHR]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)
+ ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
+ ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: $v1 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32) from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
@@ -225,3 +267,34 @@ body: |
RetRA implicit $v0, implicit $v1
...
+---
+name: load8_s64_to_sextLoad8_s128
+alignment: 4
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load8_s64_to_sextLoad8_s128
+ ; MIPS32: liveins: $a0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.px)
+ ; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
+ ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; MIPS32-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
+ ; MIPS32-NEXT: $v0 = COPY [[UV]](s32)
+ ; MIPS32-NEXT: $v1 = COPY [[UV1]](s32)
+ ; MIPS32-NEXT: $a0 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: $a1 = COPY [[ASHR]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+ %0:_(p0) = COPY $a0
+ %2:_(s128) = G_SEXTLOAD %0(p0) :: (load (s64) from %ir.px)
+ %3:_(s32), %4:_(s32), %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %2(s128)
+ $v0 = COPY %3(s32)
+ $v1 = COPY %4(s32)
+ $a0 = COPY %5(s32)
+ $a1 = COPY %6(s32)
+ RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir
index a36ed5345790b..6e2b379d513ef 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv32.mir
@@ -128,6 +128,36 @@ body: |
$x11 = COPY %4(s32)
PseudoRET implicit $x10, implicit $x11
+...
+---
+name: zextload_i64_i128
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i64_i128
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[LOAD1]](s32)
+ ; CHECK-NEXT: $x12 = COPY [[C1]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[C1]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13
+ %0:_(p0) = COPY $x10
+ %2:_(s128) = G_ZEXTLOAD %0(p0) :: (load (s64))
+ %3:_(s32), %4:_(s32), %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %2(s128)
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ $x12 = COPY %5(s32)
+ $x13 = COPY %6(s32)
+ PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13
+
...
---
name: sextload_i8_i16
@@ -259,3 +289,34 @@ body: |
PseudoRET implicit $x10, implicit $x11
...
+---
+name: sextload_i64_i128
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i64_i128
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32), align 8)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from unknown-address + 4)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD1]], [[C1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[LOAD1]](s32)
+ ; CHECK-NEXT: $x12 = COPY [[ASHR]](s32)
+ ; CHECK-NEXT: $x13 = COPY [[ASHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13
+ %0:_(p0) = COPY $x10
+ %2:_(s128) = G_SEXTLOAD %0(p0) :: (load (s64))
+ %3:_(s32), %4:_(s32), %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %2(s128)
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ $x12 = COPY %5(s32)
+ $x13 = COPY %6(s32)
+ PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/wide-extload.ll b/llvm/test/CodeGen/RISCV/GlobalISel/wide-extload.ll
new file mode 100644
index 0000000000000..c9fcbed39df91
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206276
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